[U-Boot] [PATCH V2 0/3] Support for Marvell Orion5x SoC and LaCie ED Mini V2 board
This series of patches is the second attempt at introducing support for the Marvell Orion5x SoC and the LaCie ED Mini V2 board. Initial support includes only serial port and Flash. Additional support will be added as Marvell devices (e.g. egiga) are made common to kirkwood and orion5x.
All comments to the first attempt have been taken into account.
The Linux checkpatch.pl script has been run on all three patches. The first patch has six errors and zero warnings, and all errors are false positives triggered by colons in 'asm volatile' statements. The second and third patches have zero errors and zero warnings.
Albert Aribaud (3): Initial support for Marvell Orion5x SoC Add Orion5x support to 16550 serial device driver Add support for the LaCie ED Mini V2 board
MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/LaCie/edminiv2/Makefile | 54 +++++ board/LaCie/edminiv2/config.mk | 27 +++ board/LaCie/edminiv2/edminiv2.c | 134 +++++++++++++ board/LaCie/edminiv2/edminiv2.h | 43 ++++ cpu/arm926ejs/orion5x/Makefile | 52 +++++ cpu/arm926ejs/orion5x/cpu.c | 332 ++++++++++++++++++++++++++++++++ cpu/arm926ejs/orion5x/dram.c | 61 ++++++ cpu/arm926ejs/orion5x/mpp.c | 89 +++++++++ cpu/arm926ejs/orion5x/timer.c | 175 +++++++++++++++++ drivers/serial/serial.c | 3 + include/asm-arm/arch-orion5x/88f5182.h | 40 ++++ include/asm-arm/arch-orion5x/cpu.h | 213 ++++++++++++++++++++ include/asm-arm/arch-orion5x/gpio.h | 52 +++++ include/asm-arm/arch-orion5x/mpp.h | 122 ++++++++++++ include/asm-arm/arch-orion5x/orion5x.h | 67 +++++++ include/configs/edminiv2.h | 143 ++++++++++++++ 19 files changed, 1615 insertions(+), 0 deletions(-) create mode 100644 board/LaCie/edminiv2/Makefile create mode 100644 board/LaCie/edminiv2/config.mk create mode 100644 board/LaCie/edminiv2/edminiv2.c create mode 100644 board/LaCie/edminiv2/edminiv2.h create mode 100644 cpu/arm926ejs/orion5x/Makefile create mode 100644 cpu/arm926ejs/orion5x/cpu.c create mode 100644 cpu/arm926ejs/orion5x/dram.c create mode 100644 cpu/arm926ejs/orion5x/mpp.c create mode 100644 cpu/arm926ejs/orion5x/timer.c create mode 100644 include/asm-arm/arch-orion5x/88f5182.h create mode 100644 include/asm-arm/arch-orion5x/cpu.h create mode 100644 include/asm-arm/arch-orion5x/gpio.h create mode 100644 include/asm-arm/arch-orion5x/mpp.h create mode 100644 include/asm-arm/arch-orion5x/orion5x.h create mode 100644 include/configs/edminiv2.h
This patch adds support for the Marvell Orion5x SoC. It has no use alone, and must be followed by a patch to add Orion5x support for serial, then support for the ED Mini V2, an Orion5x-based board from LaCie.
Signed-off-by: Albert Aribaud albert.aribaud@free.fr --- cpu/arm926ejs/orion5x/Makefile | 52 +++++ cpu/arm926ejs/orion5x/cpu.c | 332 ++++++++++++++++++++++++++++++++ cpu/arm926ejs/orion5x/dram.c | 61 ++++++ cpu/arm926ejs/orion5x/mpp.c | 89 +++++++++ cpu/arm926ejs/orion5x/timer.c | 175 +++++++++++++++++ include/asm-arm/arch-orion5x/88f5182.h | 40 ++++ include/asm-arm/arch-orion5x/cpu.h | 213 ++++++++++++++++++++ include/asm-arm/arch-orion5x/gpio.h | 52 +++++ include/asm-arm/arch-orion5x/mpp.h | 122 ++++++++++++ include/asm-arm/arch-orion5x/orion5x.h | 67 +++++++ 10 files changed, 1203 insertions(+), 0 deletions(-) create mode 100644 cpu/arm926ejs/orion5x/Makefile create mode 100644 cpu/arm926ejs/orion5x/cpu.c create mode 100644 cpu/arm926ejs/orion5x/dram.c create mode 100644 cpu/arm926ejs/orion5x/mpp.c create mode 100644 cpu/arm926ejs/orion5x/timer.c create mode 100644 include/asm-arm/arch-orion5x/88f5182.h create mode 100644 include/asm-arm/arch-orion5x/cpu.h create mode 100644 include/asm-arm/arch-orion5x/gpio.h create mode 100644 include/asm-arm/arch-orion5x/mpp.h create mode 100644 include/asm-arm/arch-orion5x/orion5x.h
diff --git a/cpu/arm926ejs/orion5x/Makefile b/cpu/arm926ejs/orion5x/Makefile new file mode 100644 index 0000000..3343124 --- /dev/null +++ b/cpu/arm926ejs/orion5x/Makefile @@ -0,0 +1,52 @@ +# +# Copyright (C) 2009 Albert ARIBAUD albrt.aribaud@free.fr +# +# Based on original Kirkwood support which is +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS-y = cpu.o +COBJS-y += dram.o +COBJS-y += mpp.o +COBJS-y += timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/orion5x/cpu.c b/cpu/arm926ejs/orion5x/cpu.c new file mode 100644 index 0000000..8f1806e --- /dev/null +++ b/cpu/arm926ejs/orion5x/cpu.c @@ -0,0 +1,332 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/cache.h> +#include <u-boot/md5.h> +#include <asm/arch/orion5x.h> +#include <hush.h> + +#define BUFLEN 16 + +void reset_cpu(unsigned long ignored) +{ + struct orion5x_cpu_registers *cpureg = + (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE; + + writel(readl(&cpureg->rstoutn_mask) | (1 << 2), + &cpureg->rstoutn_mask); + writel(readl(&cpureg->sys_soft_rst) | 1, + &cpureg->sys_soft_rst); + while (1) + ; +} + +/* + * Window Size + * Used with the Base register to set the address window size and location. + * Must be programmed from LSB to MSB as sequence of ones followed by + * sequence of zeros. The number of ones specifies the size of the window in + * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte). + * NOTE: A value of 0x0 specifies 64-KByte size. + */ +unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) +{ + int i; + unsigned int j = 0; + u32 val = sizeval >> 1; + + for (i = 0; val > 0x10000; i++) { + j |= (1 << i); + val = val >> 1; + } + return 0x0000ffff & j; +} + +/* + * orion5x_config_adr_windows - Configure address Windows + * + * There are 8 address windows supported by Orion5x Soc to addess different + * devices. Each window can be configured for size, BAR and remap addr + * Below configuration is standard for most of the cases + * + * If remap function not used, remap_lo must be set as base + * + * Reference Documentation: + * Mbus-L to Mbus Bridge Registers Configuration. + * (Sec 25.1 and 25.3 of Datasheet) + */ +int orion5x_config_adr_windows(void) +{ + struct orion5x_win_registers *winregs = + (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE; + + /* Window 0: PCIE MEM address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM, + ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM, + ORION5X_WIN_ENABLE), &winregs[0].ctrl); + writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base); + writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo); + writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi); + + /* Window 1: PCIE IO address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO, + ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO, + ORION5X_WIN_ENABLE), &winregs[1].ctrl); + writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base); + writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo); + writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi); + + /* Window 2: PCI MEM address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM, + ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM, + ORION5X_WIN_ENABLE), &winregs[2].ctrl); + writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base); + + /* Window 3: PCI IO address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO, + ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO, + ORION5X_WIN_ENABLE), &winregs[3].ctrl); + writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base); + + /* Window 4: DEV_CS0 address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0, + ORION5X_WIN_ENABLE), &winregs[4].ctrl); + writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base); + + /* Window 5: DEV_CS1 address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1, + ORION5X_WIN_ENABLE), &winregs[5].ctrl); + writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base); + + /* Window 6: DEV_CS2 address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2, + ORION5X_WIN_ENABLE), &winregs[6].ctrl); + writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base); + + /* Window 7: BOOT Memory address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM, + ORION5X_WIN_ENABLE), &winregs[7].ctrl); + writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base); + + return 0; +} + +/* + * orion5x_config_gpio - GPIO configuration + */ +void orion5x_config_gpio(u32 gpp_oe_val, u32 gpp_oe) +{ + struct orion5x_gpio_registers *gpioreg = + (struct orion5x_gpio_registers *)ORION5X_GPIO_BASE; + + /* Init GPIOS to default values as per board requirement */ + writel(gpp_oe_val, &gpioreg->dout); + writel(gpp_oe, &gpioreg->oe); +} + +/* + * orion5x_config_mpp - Multi-Purpose Pins Functionality configuration + * + * Each MPP can be configured to different functionality through + * MPP control register, ref (sec 6.1 of Orion5x h/w specification) + * + * There are maximum 20 Multi-Pourpose Pins on Orion5x + * Each MPP functionality can be configured by a 4bit value + * in the MPP control registers, the value and associated functionality + * depends upon used SoC variant + */ +int orion5x_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23) +{ + u32 *mppreg = (u32 *) ORION5X_MPP_BASE; + + /* program mpp registers */ + writel(mpp0_7, &mppreg[0]); + writel(mpp8_15, &mppreg[1]); + writel(mpp16_23, &mppreg[2]); + return 0; +} + +/* + * Orion5x identification is done through PCIE space. + */ +#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000) +#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008) +u32 orion5x_device_id(void) +{ + return readl(PCIE_DEV_ID_OFF) >> 16; +} + +u32 orion5x_device_rev(void) +{ + return readl(PCIE_DEV_REV_OFF) & 0xff; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) + +int print_cpuinfo(void) +{ + char dev_str[] = "0x0000"; + char rev_str[] = "0x00"; + char *dev_name = NULL; + char *rev_name = NULL; + + u32 dev = orion5x_device_id(); + u32 rev = orion5x_device_rev(); + + if (dev == MV88F5181_DEV_ID) { + dev_name = "MV88F5181"; + if (rev == MV88F5181_REV_B1) + rev_name = "B1"; + else if (rev == MV88F5181L_REV_A1) { + dev_name = "MV88F5181L"; + rev_name = "A1"; + } else if (rev == MV88F5181L_REV_A0) { + dev_name = "MV88F5181L"; + rev_name = "A0"; + } + } else if (dev == MV88F5182_DEV_ID) { + dev_name = "MV88F5182"; + if (rev == MV88F5182_REV_A2) + rev_name = "A2"; + } else if (dev == MV88F5281_DEV_ID) { + dev_name = "MV88F5281"; + if (rev == MV88F5281_REV_D2) + rev_name = "D2"; + else if (rev == MV88F5281_REV_D1) + rev_name = "D1"; + else if (rev == MV88F5281_REV_D0) + rev_name = "D0"; + } else if (dev == MV88F6183_DEV_ID) { + dev_name = "MV88F6183"; + if (rev == MV88F6183_REV_B0) + rev_name = "B0"; + } + if (dev_name == NULL) { + sprintf(dev_str, "0x%04x", dev); + dev_name = dev_str; + } + if (rev_name == NULL) { + sprintf(rev_str, "0x%02x", rev); + rev_name = rev_str; + } + + printf("SoC: Orion5x %s-%s\n", dev_name, rev_name); + + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + struct orion5x_cpu_registers *cpureg = + (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE; + + /* Linux expects` the internal registers to be at 0xf1000000 */ + writel(ORION5X_REGS_PHY_BASE, ORION5X_OFFSET_REG); + + /* Enable and invalidate L2 cache in write through mode */ + invalidate_l2_cache(); + + orion5x_config_adr_windows(); + +#ifdef CONFIG_ORION5X_RGMII_PAD_1V8 + /* + * Configures the I/O voltage of the pads connected to Egigabit + * Ethernet interface to 1.8V + * By defult it is set to 3.3V + */ + reg = readl(ORION5X_REG_MPP_OUT_DRV_REG); + reg |= (1 << 7); + writel(reg, ORION5X_REG_MPP_OUT_DRV_REG); +#endif +#ifdef CONFIG_ORION5X_EGIGA_INIT + /* + * Set egiga port0/1 in normal functional mode. + * This is required because on Orion5x by default ports are in + * reset mode and OS-level egiga driver may not have provision + * to set them in normal mode, thus if u-boot is build without + * network support, network may fail at OS level + */ + reg = readl(ORION5XGBE_PORT_SERIAL_CONTROL1_REG(0)); + reg &= ~(1 << 4); /* Clear PortReset Bit */ + writel(reg, (ORION5XGBE_PORT_SERIAL_CONTROL1_REG(0))); + reg = readl(ORION5XGBE_PORT_SERIAL_CONTROL1_REG(1)); + reg &= ~(1 << 4); /* Clear PortReset Bit */ + writel(reg, (ORION5XGBE_PORT_SERIAL_CONTROL1_REG(1))); +#endif +#ifdef CONFIG_ORION5X_PCIE_INIT + /* + * Enable PCI Express Port0 + */ + reg = readl(&cpureg->ctrl_stat); + reg |= (1 << 0); /* Set PEX0En Bit */ + writel(reg, &cpureg->ctrl_stat); +#endif + return 0; +} +#endif /* CONFIG_ARCH_CPU_INIT */ + +/* + * SOC specific misc init + */ +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + u32 temp; + + /*CPU streaming & write allocate */ + temp = readfr_extra_feature_reg(); + temp &= ~(1 << 28); /* disable wr alloc */ + writefr_extra_feature_reg(temp); + + temp = readfr_extra_feature_reg(); + temp &= ~(1 << 29); /* streaming disabled */ + writefr_extra_feature_reg(temp); + + /* L2Cache settings */ + temp = readfr_extra_feature_reg(); + /* Disable L2C pre fetch - Set bit 24 */ + temp |= (1 << 24); + /* enable L2C - Set bit 22 */ + temp |= (1 << 22); + writefr_extra_feature_reg(temp); + + icache_enable(); + /* Change reset vector to address 0x0 */ + temp = get_cr(); + set_cr(temp & ~CR_V); + + return 0; +} +#endif /* CONFIG_ARCH_MISC_INIT */ diff --git a/cpu/arm926ejs/orion5x/dram.c b/cpu/arm926ejs/orion5x/dram.c new file mode 100644 index 0000000..ba6dd91 --- /dev/null +++ b/cpu/arm926ejs/orion5x/dram.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <config.h> +#include <asm/arch/orion5x.h> + +#define ORION5X_REG_CPUCS_WIN_BAR(x) (ORION5X_REGISTER(0x1500) + (x * 0x08)) +#define ORION5X_REG_CPUCS_WIN_SZ(x) (ORION5X_REGISTER(0x1504) + (x * 0x08)) +/* + * orion5x_sdram_bar - reads SDRAM Base Address Register + */ +u32 orion5x_sdram_bar(enum memory_bank bank) +{ + u32 result = 0; + u32 enable = 0x01 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank)); + + if ((!enable) || (bank > BANK3)) + return 0; + + result = readl(ORION5X_REG_CPUCS_WIN_BAR(bank)); + return result; +} + +/* + * orion5x_sdram_bs - reads SDRAM Bank size + */ +u32 orion5x_sdram_bs(enum memory_bank bank) +{ + u32 result = 0; + u32 enable = 0x01 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank)); + + if ((!enable) || (bank > BANK3)) + return 0; + result = 0xff000000 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank)); + result += 0x01000000; + return result; +} diff --git a/cpu/arm926ejs/orion5x/mpp.c b/cpu/arm926ejs/orion5x/mpp.c new file mode 100644 index 0000000..f341747 --- /dev/null +++ b/cpu/arm926ejs/orion5x/mpp.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood support + * + * arch/arm/mach-orion5x/mpp.c + * + * MPP functions for Marvell Kirorion5xood SoCs + * Referenced from Linux kernel source + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <common.h> +#include <asm/arch/orion5x.h> +#include <asm/arch/mpp.h> + +static u32 orion5x_variant(void) +{ + switch (orion5x_device_id()) { + case MV88F5181_DEV_ID: + return 0; + case MV88F5182_DEV_ID: + return MPP_F5182_MASK; + case MV88F5281_DEV_ID: + return MPP_F5281_MASK; + case MV88F6183_DEV_ID: + return 0; + default: + debug("MPP setup: unknown Orion5x variant\n"); + return 0; + } +} + +#define MPP_CTRL(i) (ORION5X_MPP_BASE + (i*4)) +#define MPP_NR_REGS (1 + MPP_MAX/8) + +void orion5x_mpp_conf(u32 *mpp_list) +{ + u32 mpp_ctrl[MPP_NR_REGS]; + unsigned int variant_mask; + int i; + + variant_mask = orion5x_variant(); + if (!variant_mask) + return; + + debug("initial MPP regs:"); + + for (i = 0; i < MPP_NR_REGS; i++) { + mpp_ctrl[i] = readl(MPP_CTRL(i)); + debug(" %08x", mpp_ctrl[i]); + } + debug("\n"); + + + while (*mpp_list) { + unsigned int num = MPP_NUM(*mpp_list); + unsigned int sel = MPP_SEL(*mpp_list); + int shift; + + if (num > MPP_MAX) { + debug("orion5x_mpp_conf: invalid MPP " + "number (%u)\n", num); + continue; + } + if (!(*mpp_list & variant_mask)) { + debug("orion5x_mpp_conf: requested MPP%u config " + "unavailable on this hardware\n", num); + continue; + } + + shift = (num & 7) << 2; + mpp_ctrl[num / 8] &= ~(0xf << shift); + mpp_ctrl[num / 8] |= sel << shift; + + mpp_list++; + } + + debug(" final MPP regs:"); + for (i = 0; i < MPP_NR_REGS; i++) { + writel(mpp_ctrl[i], MPP_CTRL(i)); + debug(" %08x", mpp_ctrl[i]); + } + debug("\n"); + +} diff --git a/cpu/arm926ejs/orion5x/timer.c b/cpu/arm926ejs/orion5x/timer.c new file mode 100644 index 0000000..9944916 --- /dev/null +++ b/cpu/arm926ejs/orion5x/timer.c @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood support which is + * Copyright (C) Marvell International Ltd. and its affiliates + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/arch/orion5x.h> + +#define UBOOT_CNTR 0 /* counter to use for uboot timer */ + +/* Timer reload and current value registers */ +struct orion5x_tmr_val { + u32 reload; /* Timer reload reg */ + u32 val; /* Timer value reg */ +}; + +/* Timer registers */ +struct orion5x_tmr_registers { + u32 ctrl; /* Timer control reg */ + u32 pad[3]; + struct orion5x_tmr_val tmr[2]; + u32 wdt_reload; + u32 wdt_val; +}; + +struct orion5x_tmr_registers *orion5x_tmr_regs = + (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE; + +/* + * ARM Timers Registers Map + */ +#define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl) +#define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload) +#define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val) + +/* + * ARM Timers Control Register + * CPU_TIMERS_CTRL_REG (CTCR) + */ +#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) +#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) +#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) +#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) + +#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) +#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) +#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) +#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) + +/* + * ARM Timer\Watchdog Reload Register + * CNTMR_RELOAD_REG (TRR) + */ +#define TRG_ARM_TIMER_REL_OFFS 0 +#define TRG_ARM_TIMER_REL_MASK 0xffffffff + +/* + * ARM Timer\Watchdog Register + * CNTMR_VAL_REG (TVRG) + */ +#define TVR_ARM_TIMER_OFFS 0 +#define TVR_ARM_TIMER_MASK 0xffffffff +#define TVR_ARM_TIMER_MAX 0xffffffff +#define TIMER_LOAD_VAL 0xffffffff + +#define READ_TIMER \ + (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000)) + +static ulong timestamp; +static ulong lastdec; + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER; + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER; + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + + (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; + } + lastdec = now; + + return timestamp; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +#define UBOOT_CNTR_VAL readl(CNTMR_VAL_REG(UBOOT_CNTR)) + +void udelay(unsigned long usec) +{ + uint current; + ulong delayticks; + + current = readl(CNTMR_VAL_REG(UBOOT_CNTR)); + delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); + + if (current < delayticks) { + delayticks -= current; + while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) + ; + while ((TIMER_LOAD_VAL - delayticks) < UBOOT_CNTR_VAL) + ; + } else { + while (UBOOT_CNTR_VAL > (current - delayticks)) + ; + } +} + +/* + * init the counter + */ +int timer_init(void) +{ + unsigned int cntmrctrl; + + /* load value into timer */ + writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); + writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); + + /* enable timer in auto reload mode */ + cntmrctrl = readl(CNTMR_CTRL_REG); + cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); + cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); + writel(cntmrctrl, CNTMR_CTRL_REG); + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} diff --git a/include/asm-arm/arch-orion5x/88f5182.h b/include/asm-arm/arch-orion5x/88f5182.h new file mode 100644 index 0000000..b16b23f --- /dev/null +++ b/include/asm-arm/arch-orion5x/88f5182.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood 88F6182 support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * Header file for Feroceon CPU core 88F5182 SOC. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_88F5182_H +#define _CONFIG_88F5182_H + +/* SOC specific definations */ +#define F88F5182_REGS_PHYS_BASE 0xf1000000 +#define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE + +/* TCLK Core Clock defination */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +#endif /* _CONFIG_88F5182_H */ diff --git a/include/asm-arm/arch-orion5x/cpu.h b/include/asm-arm/arch-orion5x/cpu.h new file mode 100644 index 0000000..b9c4054 --- /dev/null +++ b/include/asm-arm/arch-orion5x/cpu.h @@ -0,0 +1,213 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirorion5x_ood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ORION5X_CPU_H +#define _ORION5X_CPU_H + +#include <asm/system.h> + +#ifndef __ASSEMBLY__ + +#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ + | (attr << 8) | (orion5x_winctrl_calcsize(size) << 16)) + +#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \ + ((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c) + +#define ORION5X_REG_DEVICE_ID (ORION5X_MPP_BASE + 0x34) +#define ORION5X_REG_SYSRST_CNT (ORION5X_MPP_BASE + 0x50) +#define SYSRST_CNT_1SEC_VAL (25*1000000) +#define ORION5X_REG_MPP_OUT_DRV_REG (ORION5X_MPP_BASE + 0xE0) + +enum memory_bank { + BANK0, + BANK1, + BANK2, + BANK3 +}; + +enum orion5x_cpu_winen { + ORION5X_WIN_DISABLE, + ORION5X_WIN_ENABLE +}; + +enum orion5x_cpu_target { + ORION5X_TARGET_DRAM = 0, + ORION5X_TARGET_DEVICE = 1, + ORION5X_TARGET_PCI = 3, + ORION5X_TARGET_PCIE = 4, + ORION5X_TARGET_SASRAM = 9 +}; + +enum orion5x_cpu_attrib { + ORION5X_ATTR_DRAM_CS0 = 0x0e, + ORION5X_ATTR_DRAM_CS1 = 0x0d, + ORION5X_ATTR_DRAM_CS2 = 0x0b, + ORION5X_ATTR_DRAM_CS3 = 0x07, + ORION5X_ATTR_PCI_MEM = 0x59, + ORION5X_ATTR_PCI_IO = 0x51, + ORION5X_ATTR_PCIE_MEM = 0x59, + ORION5X_ATTR_PCIE_IO = 0x51, + ORION5X_ATTR_SASRAM = 0x00, + ORION5X_ATTR_DEV_CS0 = 0x1e, + ORION5X_ATTR_DEV_CS1 = 0x1d, + ORION5X_ATTR_DEV_CS2 = 0x1b, + ORION5X_ATTR_BOOTROM = 0x0f +}; + +/* + * Default Device Address MAP BAR values + */ +#define ORION5X_DEFADR_PCIE_MEM 0x90000000 +#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO 0x90000000 +#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI 0 +#define ORION5X_DEFSZ_PCIE_MEM (128*1024*1024) + +#define ORION5X_DEFADR_PCIE_IO 0xf0000000 +#define ORION5X_DEFADR_PCIE_IO_REMAP_LO 0x90000000 +#define ORION5X_DEFADR_PCIE_IO_REMAP_HI 0 +#define ORION5X_DEFSZ_PCIE_IO (64*1024) + +#define ORION5X_DEFADR_PCI_MEM 0x98000000 +#define ORION5X_DEFSZ_PCI_MEM (128*1024*1024) + +#define ORION5X_DEFADR_PCI_IO 0xf0100000 +#define ORION5X_DEFSZ_PCI_IO (64*1024) + +#define ORION5X_DEFADR_DEV_CS0 0xfa000000 +#define ORION5X_DEFSZ_DEV_CS0 (2*1024*1024) + +#define ORION5X_DEFADR_DEV_CS1 0xf8000000 +#define ORION5X_DEFSZ_DEV_CS1 (32*1024*1024) + +#define ORION5X_DEFADR_DEV_CS2 0xfa800000 +#define ORION5X_DEFSZ_DEV_CS2 (1*1024*1024) + +#define ORION5X_DEFADR_BOOTROM 0xFFF80000 +#define ORION5X_DEFSZ_BOOTROM (512*1024) + +/* + * PCIE registers are used for SoC device ID and revision + */ +#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000) +#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008) + +/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ +#define MV88F5181_DEV_ID 0x5181 +#define MV88F5181_REV_B1 3 +#define MV88F5181L_REV_A0 8 +#define MV88F5181L_REV_A1 9 +/* Orion-NAS (88F5182) */ +#define MV88F5182_DEV_ID 0x5182 +#define MV88F5182_REV_A2 2 +/* Orion-2 (88F5281) */ +#define MV88F5281_DEV_ID 0x5281 +#define MV88F5281_REV_D0 4 +#define MV88F5281_REV_D1 5 +#define MV88F5281_REV_D2 6 +/* Orion-1-90 (88F6183) */ +#define MV88F6183_DEV_ID 0x6183 +#define MV88F6183_REV_B0 3 + +/* + * read feroceon core extra feature register + * using co-proc instruction + */ +static inline unsigned int readfr_extra_feature_reg(void) +{ + unsigned int val; + asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r" + (val)::"cc"); + return val; +} + +/* + * write feroceon core extra feature register + * using co-proc instruction + */ +static inline void writefr_extra_feature_reg(unsigned int val) +{ + asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r" + (val):"cc"); + isb(); +} + +/* + * AHB to Mbus Bridge Registers + * Source: 88F5182 User Manual, Appendix A, section A.4 + * Note: only windows 0 and 1 have remap capability. + */ +struct orion5x_win_registers { + u32 ctrl; + u32 base; + u32 remap_lo; + u32 remap_hi; +}; + +/* + * CPU control and status Registers + * Source: 88F5182 User Manual, Appendix A, section A.4 + */ +struct orion5x_cpu_registers { + u32 config; /*0x20100 */ + u32 ctrl_stat; /*0x20104 */ + u32 rstoutn_mask; /* 0x20108 */ + u32 sys_soft_rst; /* 0x2010C */ + u32 ahb_mbus_cause_irq; /* 0x20110 */ + u32 ahb_mbus_mask_irq; /* 0x20114 */ +}; + +/* + * GPIO Registers + * Source: 88F5182 User Manual, Appendix A, section A.17 + */ +struct orion5x_gpio_registers { + u32 dout; + u32 oe; + u32 blink_en; + u32 din_pol; + u32 din; + u32 int_cause; + u32 int_mask; + u32 int_level_mask; +}; + +/* + * functions + */ +void reset_cpu(unsigned long ignored); +u32 orion5x_device_id(void); +u32 orion5x_device_rev(void); +unsigned int orion5x_sdram_bar(enum memory_bank bank); +unsigned int orion5x_sdram_bs(enum memory_bank bank); +int orion5x_config_adr_windows(void); +void orion5x_config_gpio(unsigned int gpp_oe_val, unsigned int gpp_oe); +int orion5x_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, + unsigned int mpp16_23); +unsigned int orion5x_winctrl_calcsize(unsigned int sizeval); +#endif /* __ASSEMBLY__ */ +#endif /* _ORION5X_CPU_H */ diff --git a/include/asm-arm/arch-orion5x/gpio.h b/include/asm-arm/arch-orion5x/gpio.h new file mode 100644 index 0000000..58592ad --- /dev/null +++ b/include/asm-arm/arch-orion5x/gpio.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on arch/asm-arm/mach-kirkwood/include/mach/gpio.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/* + * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver. + * Removed kernel level irq handling. Took some macros from kernel to + * allow build. + * + * Dieter Kiermaier dk-arm-linux@gmx.de + */ + +#ifndef __ORION5X_GPIO_H +#define __ORION5X_GPIO_H + +/* got from kernel include/linux/bitops.h */ +#define BITS_PER_BYTE 8 +#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) + +#define GPIO_MAX 26 +#define GPIO_OUT(pin) (ORION5X_GPIO0_BASE + 0x00) +#define GPIO_IO_CONF(pin) (ORION5X_GPIO0_BASE + 0x04) +#define GPIO_BLINK_EN(pin) (ORION5X_GPIO0_BASE + 0x08) +#define GPIO_IN_POL(pin) (ORION5X_GPIO0_BASE + 0x0c) +#define GPIO_DATA_IN(pin) (ORION5X_GPIO0_BASE + 0x10) +#define GPIO_EDGE_CAUSE(pin) (ORION5X_GPIO0_BASE + 0x14) +#define GPIO_EDGE_MASK(pin) (ORION5X_GPIO0_BASE + 0x18) +#define GPIO_LEVEL_MASK(pin) (ORION5X_GPIO0_BASE + 0x1c) + +/* + * Orion5x-specific GPIO API + */ + +void orion5x_gpio_set_valid(unsigned pin, int mode); +int orion5x_gpio_is_valid(unsigned pin, int mode); +int orion5x_gpio_direction_input(unsigned pin); +int orion5x_gpio_direction_output(unsigned pin, int value); +int orion5x_gpio_get_value(unsigned pin); +void orion5x_gpio_set_value(unsigned pin, int value); +void orion5x_gpio_set_blink(unsigned pin, int blink); +void orion5x_gpio_set_unused(unsigned pin); + +#define GPIO_INPUT_OK (1 << 0) +#define GPIO_OUTPUT_OK (1 << 1) + +#endif diff --git a/include/asm-arm/arch-orion5x/mpp.h b/include/asm-arm/arch-orion5x/mpp.h new file mode 100644 index 0000000..31fade7 --- /dev/null +++ b/include/asm-arm/arch-orion5x/mpp.h @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood support which is + * Copyright 2009: Marvell Technology Group Ltd. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ORION5X_MPP_H +#define __ORION5X_MPP_H + +#define MPP(_num, _sel, _in, _out, _F5182, _F5281) ( \ + /* MPP number */ ((_num) & 0xff) | \ + /* MPP select value */ (((_sel) & 0xf) << 8) | \ + /* may be input signal */ ((!!(_in)) << 12) | \ + /* may be output signal */ ((!!(_out)) << 13) | \ + /* available on F5182 */ ((!!(_F5182)) << 14) | \ + /* available on F5281 */ ((!!(_F5182)) << 15)) + +#define MPP_NUM(x) ((x) & 0xff) +#define MPP_SEL(x) (((x) >> 8) & 0xf) + + /* num sel i o 5182 5281 */ + +#define MPP_INPUT_MASK MPP(0, 0x0, 1, 0, 0, 0) +#define MPP_OUTPUT_MASK MPP(0, 0x0, 0, 1, 0, 0) + +#define MPP_F5182_MASK MPP(0, 0x0, 0, 0, 1, 0) +#define MPP_F5281_MASK MPP(0, 0x0, 0, 0, 0, 1) + +#define MPP0_PEX_RST_OUTn MPP(0, 0x0, 0, 1, 1, 1) +#define MPP0_PCI_REQ2n MPP(0, 0x2, 1, 0, 1, 1) +#define MPP0_GPIO MPP(0, 0x3, 1, 1, 1, 1) + +#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1, 1) +#define MPP1_PCI_GNT2n MPP(1, 0x2, 0, 1, 1, 1) + +#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1, 1) +#define MPP2_PCI_REQ3n MPP(2, 0x2, 1, 0, 1, 1) +#define MPP2_PMEn MPP(2, 0x3, 0, 1, 1, 1) + +#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1, 1) +#define MPP3_PCI_GNT3nO MPP(3, 0x2, 0, 1, 1, 1) + +#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1, 1) +#define MPP4_PCI_REQ4n MPP(4, 0x2, 1, 0, 1, 1) +#define MPP4_BOOT_NAND_FLASH_REn MPP(4, 0x4, 0, 0, 1, 1) +#define MPP4_SATA0_PRESENTn MPP(4, 0x5, 0, 1, 1, 0) + +#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1, 1) +#define MPP5_PCI_GNT4n MPP(5, 0x2, 0, 1, 1, 1) +#define MPP5_BOOT_NAND_FLASH_WEn MPP(5, 0x4, 0, 0, 1, 1) +#define MPP5_SATA1_PRESENTn MPP(5, 0x5, 0, 1, 1, 0) + +#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1, 1) +#define MPP6_PCI_REQ5n MPP(6, 0x2, 1, 0, 1, 1) +#define MPP6_NAND_FLASH_RE0n MPP(6, 0x4, 0, 0, 1, 1) +#define MPP6_SATA0_ACTn MPP(6, 0x5, 0, 1, 1, 0) + +#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1, 1) +#define MPP7_PCI_GNT5n MPP(7, 0x2, 0, 1, 1, 1) +#define MPP7_NAND_FLASH_WE0n MPP(7, 0x4, 0, 0, 1, 1) +#define MPP7_SATA1_ACTn MPP(7, 0x5, 0, 1, 1, 0) + +#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1, 1) +#define MPP8_GE_COL MPP(8, 0x1, 1, 0, 1, 1) + +#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1, 1) +#define MPP9_GE_RXERR MPP(9, 0x1, 1, 0, 1, 1) + +#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1, 1) +#define MPP10_GE_CRS MPP(10, 0x1, 1, 0, 1, 1) + +#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1, 1) +#define MPP11_GE_TXERR MPP(11, 0x1, 0, 1, 1, 1) + +#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1, 1) +#define MPP12_GE_TXD4 MPP(12, 0x1, 0, 1, 1, 1) +#define MPP12_NAND_FLASH_RE1n MPP(12, 0x4, 1, 1, 1, 1) +#define MPP12_SATA0_PRESENTn MPP(12, 0x5, 0, 1, 1, 0) + +#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1, 1) +#define MPP13_GE_TXD5 MPP(13, 0x1, 0, 1, 1, 1) +#define MPP13_NAND_FLASH_WE1n MPP(13, 0x4, 0, 1, 1, 1) +#define MPP13_SATA1_PRESENTn MPP(13, 0x5, 0, 1, 1, 0) + +#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1, 1) +#define MPP14_GE_TXD6 MPP(14, 0x1, 0, 1, 1, 1) +#define MPP14_NAND_FLASH_RE2n MPP(14, 0x4, 1, 1, 1, 1) +#define MPP14_SATA0_ACTn MPP(14, 0x5, 0, 1, 1, 0) + +#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1, 1) +#define MPP15_GE_TXD7 MPP(15, 0x1, 0, 1, 1, 1) +#define MPP15_NAND_FLASH_WE2n MPP(15, 0x4, 0, 1, 1, 1) +#define MPP15_SATA1_ACTn MPP(15, 0x5, 0, 1, 1, 0) + +#define MPP16_UART1_RXD MPP(16, 0x0, 1, 0, 1, 1) +#define MPP16_GE_RXD4 MPP(16, 0x1, 1, 0, 1, 1) +#define MPP16_BOOT_NAND_FLASH_REn MPP(16, 0x4, 0, 0, 1, 1) +#define MPP16_GPIO MPP(16, 0x5, 1, 1, 1, 0) + +#define MPP17_UART1_TXD MPP(17, 0x0, 0, 1, 1, 1) +#define MPP17_GE_RXD5 MPP(17, 0x1, 1, 0, 1, 1) +#define MPP17_BOOT_NAND_FLASH_WEn MPP(17, 0x4, 0, 0, 1, 1) +#define MPP17_GPIO MPP(17, 0x5, 1, 1, 1, 0) + +#define MPP18_UART1_CTSn MPP(18, 0x0, 1, 0, 1, 1) +#define MPP18_GE_RXD6 MPP(18, 0x1, 1, 0, 1, 1) +#define MPP18_GPIO MPP(18, 0x5, 1, 1, 1, 0) + +#define MPP19_UART1_RTSn MPP(19, 0x0, 0, 1, 1, 1) +#define MPP19_GE_RXD7 MPP(19, 0x1, 1, 0, 1, 1) +#define MPP19_GPIO MPP(19, 0x5, 1, 1, 1, 0) + +#define MPP_MAX 19 + +void orion5x_mpp_conf(unsigned int *mpp_list); + +#endif diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h new file mode 100644 index 0000000..850bca2 --- /dev/null +++ b/include/asm-arm/arch-orion5x/orion5x.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * Header file for Marvell's Orion SoC with Feroceon CPU core. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ASM_ARCH_ORION5X_H +#define _ASM_ARCH_ORION5X_H + +#ifndef __ASSEMBLY__ +#include <asm/types.h> +#include <asm/io.h> +#endif /* __ASSEMBLY__ */ + +#if defined(CONFIG_FEROCEON) +#include <asm/arch/cpu.h> + +/* SOC specific definations */ +#define INTREG_BASE 0xd0000000 +#define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x) +#define ORION5X_OFFSET_REG (INTREG_BASE + 0x20080) + +/* Documented registers */ +#define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000)) +#define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000)) +#define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100)) +#define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000)) +#define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100)) +#define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000)) +#define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100)) +#define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300)) +#define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000)) +#define ORION5X_REG_PCIE_BASE (ORION5X_REGISTER(0x40000)) +#define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000)) +#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000)) +#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000)) + +#if defined(CONFIG_88F5182) +#include <asm/arch/88f5182.h> +#else +#error "SOC Name not defined" +#endif +#endif /* CONFIG_FEROCEON */ +#endif /* _ASM_ARCH_ORION5X_H */
This patch provides access to the 16550-compatible serial device of the Orion5x SoC.
Signed-off-by: Albert Aribaud albert.aribaud@free.fr --- drivers/serial/serial.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index dd5f332..18686a2 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -30,6 +30,9 @@ #ifdef CONFIG_KIRKWOOD #include <asm/arch/kirkwood.h> #endif +#ifdef CONFIG_ORION5X +#include <asm/arch/orion5x.h> +#endif
#if defined (CONFIG_SERIAL_MULTI) #include <serial.h>
This board is based on the Marvell Orion5x SoC. Current support is limited to console and Flash. Flash support uses LEGACY as the Macronix 29LV400 used on ED Mini V2 is not 100% CFI compliant.
Signed-off-by: Albert Aribaud albert.aribaud@free.fr --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/LaCie/edminiv2/Makefile | 54 +++++++++++++++ board/LaCie/edminiv2/config.mk | 27 +++++++ board/LaCie/edminiv2/edminiv2.c | 134 ++++++++++++++++++++++++++++++++++++ board/LaCie/edminiv2/edminiv2.h | 43 ++++++++++++ include/configs/edminiv2.h | 143 +++++++++++++++++++++++++++++++++++++++ 8 files changed, 409 insertions(+), 0 deletions(-) create mode 100644 board/LaCie/edminiv2/Makefile create mode 100644 board/LaCie/edminiv2/config.mk create mode 100644 board/LaCie/edminiv2/edminiv2.c create mode 100644 board/LaCie/edminiv2/edminiv2.h create mode 100644 include/configs/edminiv2.h
diff --git a/MAINTAINERS b/MAINTAINERS index d70a9d2..93e57f5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -512,6 +512,10 @@ Unknown / orphaned boards: # Board CPU # #########################################################################
+Albert ARIBAUD albert.aribaud@free.fr + + edminiv2 ARM926EJS (Orion5x SoC) + Rowel Atienza rowel@diwalabs.com
armadillo ARM720T diff --git a/MAKEALL b/MAKEALL index d63c5c2..f7b2a24 100755 --- a/MAKEALL +++ b/MAKEALL @@ -548,6 +548,7 @@ LIST_ARM9=" \ cp926ejs \ cp946es \ cp966 \ + edminiv2 \ imx27lite \ lpd7a400 \ mv88f6281gtw_ge \ diff --git a/Makefile b/Makefile index bcb3fe9..83b35b5 100644 --- a/Makefile +++ b/Makefile @@ -2951,6 +2951,9 @@ davinci_dm365evm_config : unconfig davinci_dm6467evm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci
+edminiv2_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) LaCie orion5x + imx27lite_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27
diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile new file mode 100644 index 0000000..6543da0 --- /dev/null +++ b/board/LaCie/edminiv2/Makefile @@ -0,0 +1,54 @@ +# +# Copyright (C) 2009 Albert ARIBAUD albrt.aribaud@free.fr +# +# Based on original Kirkwood support which is +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := edminiv2.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/LaCie/edminiv2/config.mk b/board/LaCie/edminiv2/config.mk new file mode 100644 index 0000000..9c725d3 --- /dev/null +++ b/board/LaCie/edminiv2/config.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2009 Albert ARIBAUD albrt.aribaud@free.fr +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +TEXT_BASE = 0x00100000 diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c new file mode 100644 index 0000000..2832860 --- /dev/null +++ b/board/LaCie/edminiv2/edminiv2.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albrt.aribaud@free.fr + * + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/orion5x.h> +#include <asm/arch/mpp.h> +#include "edminiv2.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH + * which CFI does not properly detect, hence the LEGACY config. + */ +#if defined(CONFIG_FLASH_CFI_LEGACY) +#include <flash.h> +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + int sectsz[] = CONFIG_SYS_FLASH_SECTSZ; + int sect; + + if (base != CONFIG_SYS_FLASH_BASE) + return 0; + + info->size = 0; + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; + for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) { + info->start[sect] = base+info->size; + info->size += sectsz[sect]; + } + info->flash_id = 0x01000000; + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->buffer_size = 32; + info->erase_blk_tout = 1000; + info->write_tout = 10; + info->buffer_write_tout = 300; + info->vendor = CFI_CMDSET_AMD_LEGACY; + info->cmd_reset = 0xF0; + info->interface = FLASH_CFI_X8; + info->legacy_unlock = 0; + info->manufacturer_id = 0xC2; + info->device_id = 0xBA; + info->device_id2 = 0; + info->ext_addr = 0; + info->cfi_version = 0x3133; + info->cfi_offset = 0x0000; + info->addr_unlock1 = 0x00000aaa; + info->addr_unlock2 = 0x00000555; + info->name = "MX29LV400CB"; + + return 1; +} +#endif /* CONFIG_SYS_FLASH_CFI */ + +int board_init(void) +{ + /* + * default gpio configuration + * There are maximum 26 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + orion5x_config_gpio(EDMINIV2_OE_VAL, EDMINIV2_OE); + + /* Multi-Purpose Pins Functionality configuration */ + u32 edminiv2_mpp_config[] = { + MPP0_GPIO, + MPP1_GPIO, + MPP2_GPIO, + MPP3_GPIO, + MPP4_GPIO, + MPP5_GPIO, + MPP6_GPIO, + MPP7_GPIO, + MPP8_GPIO, + MPP9_GPIO, + MPP10_GPIO, + MPP11_GPIO, + MPP12_SATA0_PRESENTn, + MPP13_SATA1_PRESENTn, + MPP14_SATA0_ACTn, + MPP15_SATA1_ACTn, + MPP16_GPIO, + MPP17_GPIO, + MPP18_GPIO, + MPP19_GPIO, + 0 + }; + orion5x_mpp_conf(edminiv2_mpp_config); + + /* arch number of board */ + gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = orion5x_sdram_bar(0) + 0x100; + + return 0; +} + +int dram_init(void) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = orion5x_sdram_bar(i); + gd->bd->bi_dram[i].size = orion5x_sdram_bs(i); + } + return 0; +} + diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/edminiv2/edminiv2.h new file mode 100644 index 0000000..c725037 --- /dev/null +++ b/board/LaCie/edminiv2/edminiv2.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albrt.aribaud@free.fr + * + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __EDMINIV2_H +#define __EDMINIV2_H + +/* + * GPIOs for LaCie ED Mini: + * GPIO3 is input (RTC interrupt) + * GPIO16 is Power LED control (0 = on, 1 = off) + * GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) + * GPIO18 is Power Button status (0 = Released, 1 = Pressed) + * + * Default is LED ON + */ + +#define EDMINIV2_OE 0xfffcffff +#define EDMINIV2_OE_VAL 0x00020000 + +#endif /* __EDMINIV2_H */ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h new file mode 100644 index 0000000..31de164 --- /dev/null +++ b/include/configs/edminiv2.h @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_EDMINIV2_H +#define _CONFIG_EDMINIV2_H + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING " EDMiniV2" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_FEROCEON 1 /* CPU Core subversion */ +#define CONFIG_ORION5X 1 /* SOC Family Name */ +#define CONFIG_88F5182 1 /* SOC Name */ +#define CONFIG_MACH_EDMINIV2 1 /* Machine type */ + +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * CLKs configurations + */ +#define CONFIG_SYS_HZ 1000 + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ +{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } +/* + * FLASH configuration + */ + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BASE 0xfff80000 +#define CONFIG_SYS_FLASH_SECTSZ \ +{16384, 8192, 8192, 32768, 65536, 65536, 65536, 65536, 65536, 65536, 65536} + +/* auto boot */ +#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_PROMPT "EDMiniV2> " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ +/* + * Commands configuration - using default command set for now + */ +#include <config_cmd_default.h> +/* + * Disabling some default commands for staggered bring-up + */ +#undef CONFIG_CMD_BOOTD /* no bootd since no net */ +#undef CONFIG_CMD_NET /* no net since no eth */ +#undef CONFIG_CMD_NFS /* no NFS since no net */ + +/* + * Environment variables configurations + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required minimal configurations + */ +#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +#endif /* _CONFIG_EDMINIV2_H */
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Albert Aribaud Sent: Sunday, November 15, 2009 4:33 AM To: U-Boot@lists.denx.de Subject: [U-Boot] [PATCH V2 3/3] Add support for the LaCie ED Mini V2 board
This board is based on the Marvell Orion5x SoC. Current support is limited to console and Flash. Flash support uses LEGACY as the Macronix 29LV400 used on ED Mini V2 is not 100% CFI compliant.
Signed-off-by: Albert Aribaud albert.aribaud@free.fr
MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/LaCie/edminiv2/Makefile | 54 +++++++++++++++ board/LaCie/edminiv2/config.mk | 27 +++++++ board/LaCie/edminiv2/edminiv2.c | 134 ++++++++++++++++++++++++++++++++++++ board/LaCie/edminiv2/edminiv2.h | 43 ++++++++++++ include/configs/edminiv2.h | 143 +++++++++++++++++++++++++++++++++++++++ 8 files changed, 409 insertions(+), 0 deletions(-) create mode 100644 board/LaCie/edminiv2/Makefile create mode 100644 board/LaCie/edminiv2/config.mk create mode 100644 board/LaCie/edminiv2/edminiv2.c create mode 100644 board/LaCie/edminiv2/edminiv2.h create mode 100644 include/configs/edminiv2.h
diff --git a/MAINTAINERS b/MAINTAINERS index d70a9d2..93e57f5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -512,6 +512,10 @@ Unknown / orphaned boards: # Board CPU #
############################################################## ###########
+Albert ARIBAUD albert.aribaud@free.fr
- edminiv2 ARM926EJS (Orion5x SoC)
That's good if you can move this entry above Albin Tonnerre's entry
...snip...
MPP17_GPIO,MPP18_GPIO,MPP19_GPIO,
Why not configured rest 6 gpios ?
...snip...
+/*
- GPIOs for LaCie ED Mini:
- GPIO3 is input (RTC interrupt)
- GPIO16 is Power LED control (0 = on, 1 = off)
- GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
- GPIO18 is Power Button status (0 = Released, 1 = Pressed)
- Default is LED ON
- */
+#define EDMINIV2_OE 0xfffcffff +#define EDMINIV2_OE_VAL 0x00020000
How about adding GPIO_OE? This settings are referred to GPIOs register
...snip...
+#define CONFIG_IDENT_STRING " EDMiniV2"
+/*
- High Level Configuration Options (easy to change)
- */
+#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_FEROCEON 1 /* CPU Core subversion */ +#define CONFIG_ORION5X 1 /* SOC Family Name */ +#define CONFIG_88F5182 1 /* SOC Name */ +#define CONFIG_MACH_EDMINIV2 1 /* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
How you are addressing DRAM configuration? I think you need lowlevel_init.
...snip...
+/*
- Environment variables configurations
- */
+#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */
I don't know how this is going to work, how much flash do you have? I hope it is mapped in the end since your reset address is 0xffff0000.
Where is the code to fetch flashed image from flash to DRAM at TEXT_BASE?
I suggest you provide some more details about your board in the commit log
+/*
- Size of malloc() pool
- */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128
+/*
- Other required minimal configurations
- */
+#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
Same comment applies here
Regards.. Prafulla . .
Prafulla Wadaskar a écrit :
diff --git a/MAINTAINERS b/MAINTAINERS index d70a9d2..93e57f5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -512,6 +512,10 @@ Unknown / orphaned boards: # Board CPU #
############################################################## ###########
+Albert ARIBAUD albert.aribaud@free.fr
- edminiv2 ARM926EJS (Orion5x SoC)
That's good if you can move this entry above Albin Tonnerre's entry
Are you sure? Seems to me like this list is ordered by last, not first, name.
How you are addressing DRAM configuration? I think you need lowlevel_init.
Yes. That will be in patch V3.
...snip...
+/*
- Environment variables configurations
- */
+#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */
I don't know how this is going to work, how much flash do you have?
51KB NOR located at fff88000 in the final mapping, and mirrored throughout f8000000-ffffffff at power-up. That's an MX29LV400CB, with a 1x16kb,2x8kb,1x32kb,7x64kb region layout, of which U-boot utilizes the 7 64K banks for code and the lowest 8K bank for environment.
I hope it is mapped in the end since your reset address is 0xffff0000.
This *does* work, I step-debugged through the Orion init sequence. The fact is, there's ROM code in the Orion SoC apparently, at 0xffff0000, and which takes precedence over the boot CS. This ROM code checks the SoC device type and, if 5182, branches to 0xfff90000 (at this point a mirror of the boot CS).
Where is the code to fetch flashed image from flash to DRAM at TEXT_BASE?
That's done by the start.S relocation code, subject to not defining CONFIG_SKIP_RELOCATION of course. Note that Orion has NOR flash, not NAND.
I suggest you provide some more details about your board in the commit log
I will.
Amicalement,
Dear Albert Aribaud,
In message 1258239796-21528-4-git-send-email-albert.aribaud@free.fr you wrote:
This board is based on the Marvell Orion5x SoC. Current support is limited to console and Flash. Flash support uses LEGACY as the Macronix 29LV400 used on ED Mini V2 is not 100% CFI compliant.
And the differences are really so big that we cannot tweak the CFI driver?
+int dram_init(void) +{
- int i;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);gd->bd->bi_dram[i].size = orion5x_sdram_bs(i);- }
- return 0;
+}
Cannot you use get_ram_size() for auto-sizing and checking?
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h new file mode 100644 index 0000000..31de164 --- /dev/null +++ b/include/configs/edminiv2.h
...
+#define CONFIG_SYS_BAUDRATE_TABLE \ +{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
Indentation by a TAB, please.
+#define CONFIG_SYS_FLASH_SECTSZ \ +{16384, 8192, 8192, 32768, 65536, 65536, 65536, 65536, 65536, 65536, 65536}
Ditto. And be careful about the line length.
Best regards,
Wolfgang Denk
Hi Albert,
On Wednesday 18 November 2009 23:21:58 Wolfgang Denk wrote:
This board is based on the Marvell Orion5x SoC. Current support is limited to console and Flash. Flash support uses LEGACY as the Macronix 29LV400 used on ED Mini V2 is not 100% CFI compliant.
And the differences are really so big that we cannot tweak the CFI driver?
It's not CFI compliant. But you can use the legacy infrastructure in this driver, which meant to support such chips. Please take a look at the following driver:
drivers/mtd/jedec_flash.c
Your board config header would need something like this:
/* Use common CFI driver */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER /* board provides its own flash_init code */ #define CONFIG_FLASH_CFI_LEGACY 1 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #define CONFIG_SYS_FLASH_LEGACY_512Kx8 1 ...
Taken from include/configs/hcu4.h. This should give you an idea...
Cheers, Stefan
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office@denx.de
Stefan Roese a écrit :
Hi Albert,
On Wednesday 18 November 2009 23:21:58 Wolfgang Denk wrote:
This board is based on the Marvell Orion5x SoC. Current support is limited to console and Flash. Flash support uses LEGACY as the Macronix 29LV400 used on ED Mini V2 is not 100% CFI compliant.
And the differences are really so big that we cannot tweak the CFI driver?
It's not CFI compliant. But you can use the legacy infrastructure in this driver, which meant to support such chips. Please take a look at the following driver:
drivers/mtd/jedec_flash.c
Your board config header would need something like this:
/* Use common CFI driver */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER /* board provides its own flash_init code */ #define CONFIG_FLASH_CFI_LEGACY 1 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #define CONFIG_SYS_FLASH_LEGACY_512Kx8 1 ...
Taken from include/configs/hcu4.h. This should give you an idea...
Cheers, Stefan
Er... Precisely, I am using [CONFIG_FLASH_CFI_]LEGACY, as the patch comment says, though obviously not clearly enough.
Amicalement,
On Thursday 19 November 2009 13:48:15 Albert ARIBAUD wrote:
Your board config header would need something like this:
/* Use common CFI driver */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER /* board provides its own flash_init code */ #define CONFIG_FLASH_CFI_LEGACY 1 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #define CONFIG_SYS_FLASH_LEGACY_512Kx8 1 ...
Taken from include/configs/hcu4.h. This should give you an idea...
Cheers, Stefan
Er... Precisely, I am using [CONFIG_FLASH_CFI_]LEGACY, as the patch comment says, though obviously not clearly enough.
Ahh, sorry I missed this.
Cheers, Stefan
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office@denx.de
Wolfgang Denk a écrit :
Dear Albert Aribaud,
In message 1258239796-21528-4-git-send-email-albert.aribaud@free.fr you wrote:
This board is based on the Marvell Orion5x SoC. Current support is limited to console and Flash. Flash support uses LEGACY as the Macronix 29LV400 used on ED Mini V2 is not 100% CFI compliant.
And the differences are really so big that we cannot tweak the CFI driver?
Apparently not.
The MX29LV400CB is 8-bit/16-bit and it configured on the ED Mini as 8-bit, but presents a pure 16-bit QRY (with zeroes between qry bytes) which causes cfi_flash to mistakenly detect it as 16-bit wide, and thus use 16-bit accesses at 16-bit addresses to read IDs and write instructions, which of course does not work.
+int dram_init(void) +{
- int i;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);gd->bd->bi_dram[i].size = orion5x_sdram_bs(i);- }
- return 0;
+}
Cannot you use get_ram_size() for auto-sizing and checking?
As this is SoC code, not board code, and as the SoC allows to have up to four non-contiguous DRAM banks, I prefer to read the four DRAM base/size registers.
Amicalement,
Wolfgang Denk a écrit :
+int dram_init(void) +{
- int i;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);gd->bd->bi_dram[i].size = orion5x_sdram_bs(i);- }
- return 0;
+}
Cannot you use get_ram_size() for auto-sizing and checking?
The SoC allows for up to 4 banks of DRAM, not necessarily contiguous. Granted, this is not a frequent configuration, however I'd like to support it correctly, and the heuristics of get_ram_size() are based on the assumption that all DRAM is contiguous.
However I realize that this code is actually SoC-specific, not board-specific. It could be moved in cpu/arm926ejs/orion5x/dram.c, and then orion5x_sdram_{bar,bs} could be made static (or inlined).
What do you think?
Amicalement,
Dear Albert ARIBAUD,
In message 4B126F68.9020005@free.fr you wrote:
Cannot you use get_ram_size() for auto-sizing and checking?
The SoC allows for up to 4 banks of DRAM, not necessarily contiguous. Granted, this is not a frequent configuration, however I'd like to support it correctly, and the heuristics of get_ram_size() are based on the assumption that all DRAM is contiguous.
No, this is not correct. get_ram_size() is used always on a single bank of memory only.
However I realize that this code is actually SoC-specific, not board-specific. It could be moved in cpu/arm926ejs/orion5x/dram.c, and then orion5x_sdram_{bar,bs} could be made static (or inlined).
What do you think?
Seems to make sense.
Best regards,
Wolfgang Denk
Wolfgang Denk a écrit :
Dear Albert ARIBAUD,
In message 4B126F68.9020005@free.fr you wrote:
Cannot you use get_ram_size() for auto-sizing and checking?
The SoC allows for up to 4 banks of DRAM, not necessarily contiguous. Granted, this is not a frequent configuration, however I'd like to support it correctly, and the heuristics of get_ram_size() are based on the assumption that all DRAM is contiguous.
No, this is not correct. get_ram_size() is used always on a single bank of memory only.
Do you mean calling get_ram_size() four up to times based on the configured number of banks and configured sizes? I then fail to see the added value of get_ram_size() wrt using the configured sizes directly.
However I realize that this code is actually SoC-specific, not board-specific. It could be moved in cpu/arm926ejs/orion5x/dram.c, and then orion5x_sdram_{bar,bs} could be made static (or inlined).
What do you think?
Seems to make sense.
All right. Does doing that lift the requirement to use get_ram_size()?
Best regards,
Wolfgang Denk
Amicalement,
Dear Albert ARIBAUD,
In message 4B1A05A9.4040104@free.fr you wrote:
No, this is not correct. get_ram_size() is used always on a single bank of memory only.
Do you mean calling get_ram_size() four up to times based on the configured number of banks and configured sizes? I then fail to see the
Yes, exactly.
added value of get_ram_size() wrt using the configured sizes directly.
The added value is that get_ram_size() will detect (1) a lot of common error situations and (2) will detect the actual size of the respective memory banks.
Assume you have a system where differentt types of memory chips can be fit, or where you can insert memory modules. Then you configure for the largest possible type, and get_ram_size() will detect what's really present, so you can adjust the configuration. See the README for details.
However I realize that this code is actually SoC-specific, not board-specific. It could be moved in cpu/arm926ejs/orion5x/dram.c, and then orion5x_sdram_{bar,bs} could be made static (or inlined).
What do you think?
Seems to make sense.
All right. Does doing that lift the requirement to use get_ram_size()?
I see no reason yet why you would not want to use get_ram_size() - the memory test feature alone is useful enough, even if you never intend to use different RAM sizes.
Best regards,
Wolfgang Denk
Wolfgang Denk a écrit :
Dear Albert ARIBAUD,
In message 4B1A05A9.4040104@free.fr you wrote:
No, this is not correct. get_ram_size() is used always on a single bank of memory only.
Do you mean calling get_ram_size() four up to times based on the configured number of banks and configured sizes? I then fail to see the
Yes, exactly.
added value of get_ram_size() wrt using the configured sizes directly.
The added value is that get_ram_size() will detect (1) a lot of common error situations and (2) will detect the actual size of the respective memory banks.
Assume you have a system where differentt types of memory chips can be fit, or where you can insert memory modules. Then you configure for the largest possible type, and get_ram_size() will detect what's really present, so you can adjust the configuration. See the README for details.
However I realize that this code is actually SoC-specific, not board-specific. It could be moved in cpu/arm926ejs/orion5x/dram.c, and then orion5x_sdram_{bar,bs} could be made static (or inlined).
What do you think?
Seems to make sense.
All right. Does doing that lift the requirement to use get_ram_size()?
I see no reason yet why you would not want to use get_ram_size() - the memory test feature alone is useful enough, even if you never intend to use different RAM sizes.
Ok. Considering the machine would have had fixed sized banks but the SoC would not, get_ram_size() indeed makes sense especially if I move the code to cpu/arm926ejs/orion5x/dram.c. I'll do that in V4 of the patch, once I get complete feedback for V3.
Amicalement,
(starting a new subject as this goes beyond simply adding support for any platform/SoC/whetever, and touches on MTD/Flash, thus also adding Stefan as To:)
Hi Wolfgang and others,
Wolfgang Denk a écrit :
Dear Albert Aribaud,
In message 1258239796-21528-4-git-send-email-albert.aribaud@free.fr you wrote:
This board is based on the Marvell Orion5x SoC. Current support is limited to console and Flash. Flash support uses LEGACY as the Macronix 29LV400 used on ED Mini V2 is not 100% CFI compliant.
And the differences are really so big that we cannot tweak the CFI driver?
After deeper analysis, there are two issues:
1) there is an already known quirk in that the MX29LV400CB, reputedly compliant with the 1.0 CFI spec, has the 7th bit set in the Mfg ID byte although it should not. That can cause a mistaken region list inversion, however this kind of issue is known for other parts and can be handled in the current U-boot architecture.
2) The MX29LV400 QRY bytes appear at byte offsets 0x20, 0x22, 0x24 etc, which is normal for mixed 8/16 bit chips: the spec says they should output their QRY bytes at the same offset and with the same spacing as pure 16-bit chips. However, they also should duplicate these QRY bytes at odd addresses (0x21, 0x23, 0x25 etc) so that reading bytes from 0x20 onward would yield 'Q', 'Q', 'R', 'R', 'Y', 'Y' etc. However, the MX29LV400CB output odd bytes as zeroes, just like a pure 16-bit device, thus producing (LSB first) 'Q', #0, 'R', #0, 'Y', #0 etc.
To add insult to injury, for other JEDEC commands such as READ ID, the MX29LV400CB does behave correctly, that is, duplicates its even bytes to its odd bytes. A READ ID gives 0xC2, 0xC2, 0xBA, 0xBA which is correct as far as mixed 8/16 chip behavior is concerned.
The consequence of all this is that even a perfectly CFI-compliant code will recognize the MX29LV400CB as a 16-bit device even though it is a mixed device and could, or worse, should (as in my own unfortunate case) be used in BYTE mode.
In the case of U-boot's CFI detection code, it detects the MX29LV400CB as 16-bit because of its QRY block offset (0x20) and null upper bytes. Then it wants to talk to it using 16-bit wide writes at 16-bit mode offsets, which, in my case, fails.
U-Boot 2009.11-rc1-00069-g93fb3c4-dirty (dec. 02 2009 - 09:00:04) EDMiniV2
SoC: Orion5x MV88F5182-A2 DRAM: 64 MB flash detect cfi fwc addr fff80000 cmd f0 f0 8bit x 8 bit fwc addr fff80000 cmd ff ff 8bit x 8 bit fwc addr fff80055 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr fff80010 is= ff 51 fwc addr fff80555 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr fff80010 is= ff 51 fwc addr fff80000 cmd f0 f0f0 16bit x 8 bit fwc addr fff80000 cmd ff ffff 16bit x 8 bit fwc addr fff800aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr fff80020 is= 0051 5151 fwc addr fff80aaa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr fff80020 is= 0051 5151 fwc addr fff80000 cmd f0 00f0 16bit x 16 bit fwc addr fff80000 cmd ff 00ff 16bit x 16 bit fwc addr fff800aa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr fff80020 is= 0051 0051 is= cmd 52(R) addr fff80022 is= 0052 0052 is= cmd 59(Y) addr fff80024 is= 0059 0059 device interface is 2 found port 2 chip 2 port 16 bits chip 16 bits 00 : 51 52 59 02 00 40 00 00 00 00 00 27 36 00 00 04 QRY..@.....'6... 10 : 00 0a 00 05 00 04 00 13 02 00 00 00 04 00 00 40 ...............@ 20 : 00 01 00 20 00 00 00 80 00 06 00 00 01 d0 43 61 ... ..........Ca fwc addr fff80000 cmd f0 00f0 16bit x 16 bit fwc addr fff80aaa cmd aa 00aa 16bit x 16 bit fwc addr fff80554 cmd 55 0055 16bit x 16 bit fwc addr fff80aaa cmd 90 0090 16bit x 16 bit fwc addr fff80000 cmd f0 00f0 16bit x 16 bit fwc addr fff800aa cmd 98 0098 16bit x 16 bit manufacturer is 2 manufacturer id is 0xff device id is 0xffff device id2 is 0x0
Looking at the commands and addresses displayed above and at the source code of cfi_flash.c), I think the CFI detection code never tries the 'mixed 8/16-bit chip in 8-bit mode only' case. It does try a '16bit x 8 bit' case but as it doubles the write bytes (e.g. 0xF0F0), I suspect this is meant for pairs of interleaved chips, not for a mixed-mode chip, for which commands need not be duplicated.
Actually, the U-boot code seems to assume that if QRY bytes start at 0x20 and are at even offsets, then the chip is 16-bit, period -- see how portwidth is used both to calculate offsets in QRY and other JEDEC data *and* in computing the width of writes to the flash.
If so, then this would have to be amended for mixed-mode chips in byte mode only.
Only, before I go on with proposing a fix, I'd like to be sure I'm right so far; thus comments are heartily welcome.
Amicalement,
Hi Albert,
On Wednesday 02 December 2009 09:31:43 Albert ARIBAUD wrote:
This board is based on the Marvell Orion5x SoC. Current support is limited to console and Flash. Flash support uses LEGACY as the Macronix 29LV400 used on ED Mini V2 is not 100% CFI compliant.
And the differences are really so big that we cannot tweak the CFI driver?
After deeper analysis, there are two issues:
- there is an already known quirk in that the MX29LV400CB, reputedly
compliant with the 1.0 CFI spec, has the 7th bit set in the Mfg ID byte although it should not. That can cause a mistaken region list inversion, however this kind of issue is known for other parts and can be handled in the current U-boot architecture.
Yes, this should be easy to fix.
- The MX29LV400 QRY bytes appear at byte offsets 0x20, 0x22, 0x24 etc,
which is normal for mixed 8/16 bit chips: the spec says they should output their QRY bytes at the same offset and with the same spacing as pure 16-bit chips. However, they also should duplicate these QRY bytes at odd addresses (0x21, 0x23, 0x25 etc) so that reading bytes from 0x20 onward would yield 'Q', 'Q', 'R', 'R', 'Y', 'Y' etc. However, the MX29LV400CB output odd bytes as zeroes, just like a pure 16-bit device, thus producing (LSB first) 'Q', #0, 'R', #0, 'Y', #0 etc.
To add insult to injury, for other JEDEC commands such as READ ID, the MX29LV400CB does behave correctly, that is, duplicates its even bytes to its odd bytes. A READ ID gives 0xC2, 0xC2, 0xBA, 0xBA which is correct as far as mixed 8/16 chip behavior is concerned.
The consequence of all this is that even a perfectly CFI-compliant code will recognize the MX29LV400CB as a 16-bit device even though it is a mixed device and could, or worse, should (as in my own unfortunate case) be used in BYTE mode.
In the case of U-boot's CFI detection code, it detects the MX29LV400CB as 16-bit because of its QRY block offset (0x20) and null upper bytes. Then it wants to talk to it using 16-bit wide writes at 16-bit mode offsets, which, in my case, fails.
Since the CFI driver starts detection in 8bit mode and only switches to 16bit mode (32bit etc.) if this fails, we seem to have a problem with 8bit mode detection of this chip.
U-Boot 2009.11-rc1-00069-g93fb3c4-dirty (dec. 02 2009 - 09:00:04) EDMiniV2
SoC: Orion5x MV88F5182-A2 DRAM: 64 MB flash detect cfi fwc addr fff80000 cmd f0 f0 8bit x 8 bit fwc addr fff80000 cmd ff ff 8bit x 8 bit fwc addr fff80055 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr fff80010 is= ff 51 fwc addr fff80555 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr fff80010 is= ff 51 fwc addr fff80000 cmd f0 f0f0 16bit x 8 bit fwc addr fff80000 cmd ff ffff 16bit x 8 bit fwc addr fff800aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr fff80020 is= 0051 5151 fwc addr fff80aaa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr fff80020 is= 0051 5151 fwc addr fff80000 cmd f0 00f0 16bit x 16 bit fwc addr fff80000 cmd ff 00ff 16bit x 16 bit fwc addr fff800aa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr fff80020 is= 0051 0051 is= cmd 52(R) addr fff80022 is= 0052 0052 is= cmd 59(Y) addr fff80024 is= 0059 0059 device interface is 2 found port 2 chip 2 port 16 bits chip 16 bits 00 : 51 52 59 02 00 40 00 00 00 00 00 27 36 00 00 04 QRY..@.....'6... 10 : 00 0a 00 05 00 04 00 13 02 00 00 00 04 00 00 40 ...............@ 20 : 00 01 00 20 00 00 00 80 00 06 00 00 01 d0 43 61 ... ..........Ca fwc addr fff80000 cmd f0 00f0 16bit x 16 bit fwc addr fff80aaa cmd aa 00aa 16bit x 16 bit fwc addr fff80554 cmd 55 0055 16bit x 16 bit fwc addr fff80aaa cmd 90 0090 16bit x 16 bit fwc addr fff80000 cmd f0 00f0 16bit x 16 bit fwc addr fff800aa cmd 98 0098 16bit x 16 bit manufacturer is 2 manufacturer id is 0xff device id is 0xffff device id2 is 0x0
Looking at the commands and addresses displayed above and at the source code of cfi_flash.c), I think the CFI detection code never tries the 'mixed 8/16-bit chip in 8-bit mode only' case. It does try a '16bit x 8 bit' case but as it doubles the write bytes (e.g. 0xF0F0), I suspect this is meant for pairs of interleaved chips, not for a mixed-mode chip, for which commands need not be duplicated.
Maybe. I don't remember ever using an mixed-mode chip (8 & 16bit interface) in 8bit mode.
Actually, the U-boot code seems to assume that if QRY bytes start at 0x20 and are at even offsets, then the chip is 16-bit, period -- see how portwidth is used both to calculate offsets in QRY and other JEDEC data *and* in computing the width of writes to the flash.
If so, then this would have to be amended for mixed-mode chips in byte mode only.
Only, before I go on with proposing a fix, I'd like to be sure I'm right so far; thus comments are heartily welcome.
I have to admit, that I'm not totally sure about this problem. Perhaps it would be best, if you would try to "fix" to the CFI code. To verify, if your theory is correct. And then post the resulting fix to the list, so that we can discuss it here.
Thanks.
Cheers, Stefan
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office@denx.de
Dear Stefan Roese,
In message 200912021015.34183.sr@denx.de you wrote:
Maybe. I don't remember ever using an mixed-mode chip (8 & 16bit interface) in 8bit mode.
Indeed. I wonder which arguments the hardware designer has to defend such an implementation.
I have to admit, that I'm not totally sure about this problem. Perhaps it would be best, if you would try to "fix" to the CFI code. To verify, if your theory is correct. And then post the resulting fix to the list, so that we can discuss it here.
Agreed. Eventually the READ ID could / should be combined with the 8/16 bit test, at least for this specific device ID.
Um... what does the Linux kernel code do in this case?
Best regards,
Wolfgang Denk
Wolfgang Denk a écrit :
Dear Stefan Roese,
I have to admit, that I'm not totally sure about this problem. Perhaps it would be best, if you would try to "fix" to the CFI code. To verify, if your theory is correct. And then post the resulting fix to the list, so that we can discuss it here.
Agreed. Eventually the READ ID could / should be combined with the 8/16 bit test, at least for this specific device ID.
That is 'should', really, because the only way to tell apart a real pure word mode QRY from this faulty miwed-mode QRY is to try the READ ID, because i) it *is* correclty mixed-mode and ii) the Mfg and device ID are needed for verifying that we indeed had a faulty part.
Um... what does the Linux kernel code do in this case?
Not entierly sure yet. I'll look.
Amicalement,
Stefan Roese a écrit :
Hi Albert,
In the case of U-boot's CFI detection code, it detects the MX29LV400CB as 16-bit because of its QRY block offset (0x20) and null upper bytes. Then it wants to talk to it using 16-bit wide writes at 16-bit mode offsets, which, in my case, fails.
Since the CFI driver starts detection in 8bit mode and only switches to 16bit mode (32bit etc.) if this fails, we seem to have a problem with 8bit mode detection of this chip.
All 8-bit mode checks assume the QRY bytes are at addresses 0x10, 0x11, 0x12 etc. So they fail too, since a mixed-mode chip outputs a word-mode QRY always, at addresses 0xx20, 0x22, 0x24 etc.
Amicalement,
Dear Albert Aribaud,
In message 1258239796-21528-2-git-send-email-albert.aribaud@free.fr you wrote:
This patch adds support for the Marvell Orion5x SoC. It has no use alone, and must be followed by a patch to add Orion5x support for serial, then support for the ED Mini V2, an Orion5x-based board from LaCie.
...
diff --git a/cpu/arm926ejs/orion5x/timer.c b/cpu/arm926ejs/orion5x/timer.c new file mode 100644
...
+#define READ_TIMER \
- (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000))
...
- /* reset time */
- lastdec = READ_TIMER;
Macros resembling functions should look like functions, i. e. have parens. Also please note that generally, inline functions are preferable to macros resembling functions.
...
+#define UBOOT_CNTR_VAL readl(CNTMR_VAL_REG(UBOOT_CNTR))
Ditto.
+void udelay(unsigned long usec) +{
- uint current;
- ulong delayticks;
- current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
Why do you add the #define above when you then don't use it?
- delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
- if (current < delayticks) {
delayticks -= current;while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current)
Ditto.
diff --git a/cpu/arm926ejs/orion5x/mpp.c b/cpu/arm926ejs/orion5x/mpp.c new file mode 100644 index 0000000..f341747 --- /dev/null +++ b/cpu/arm926ejs/orion5x/mpp.c ... + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied.
NAK. License must be "v2 or any later version". Ditto for some other files.
diff --git a/include/asm-arm/arch-orion5x/88f5182.h b/include/asm-arm/arch-orion5x/88f5182.h new file mode 100644 index 0000000..b16b23f --- /dev/null +++ b/include/asm-arm/arch-orion5x/88f5182.h
88f5182 is a terrible file name. Can you not come up with something more descriptive, please?
diff --git a/include/asm-arm/arch-orion5x/gpio.h b/include/asm-arm/arch-orion5x/gpio.h new file mode 100644 index 0000000..58592ad --- /dev/null +++ b/include/asm-arm/arch-orion5x/gpio.h
...
- This file is licensed under the terms of the GNU General Public
- License version 2. This program is licensed "as is" without any
- warranty of any kind, whether express or implied.
NAK. See above.
+#define GPIO_MAX 26 +#define GPIO_OUT(pin) (ORION5X_GPIO0_BASE + 0x00) +#define GPIO_IO_CONF(pin) (ORION5X_GPIO0_BASE + 0x04) +#define GPIO_BLINK_EN(pin) (ORION5X_GPIO0_BASE + 0x08) +#define GPIO_IN_POL(pin) (ORION5X_GPIO0_BASE + 0x0c) +#define GPIO_DATA_IN(pin) (ORION5X_GPIO0_BASE + 0x10) +#define GPIO_EDGE_CAUSE(pin) (ORION5X_GPIO0_BASE + 0x14) +#define GPIO_EDGE_MASK(pin) (ORION5X_GPIO0_BASE + 0x18) +#define GPIO_LEVEL_MASK(pin) (ORION5X_GPIO0_BASE + 0x1c)
NAK. Please make this a C struct.
+/*
- Orion5x-specific GPIO API
- */
Why do we need an Orion5x-specific GPIO API? Can't we use something that is more general?
diff --git a/include/asm-arm/arch-orion5x/mpp.h b/include/asm-arm/arch-orion5x/mpp.h new file mode 100644 index 0000000..31fade7 --- /dev/null +++ b/include/asm-arm/arch-orion5x/mpp.h
...
- This file is licensed under the terms of the GNU General Public
- License version 2. This program is licensed "as is" without any
- warranty of any kind, whether express or implied.
NAK. See above.
+#define MPP(_num, _sel, _in, _out, _F5182, _F5281) ( \
- /* MPP number */ ((_num) & 0xff) | \
- /* MPP select value */ (((_sel) & 0xf) << 8) | \
- /* may be input signal */ ((!!(_in)) << 12) | \
- /* may be output signal */ ((!!(_out)) << 13) | \
- /* available on F5182 */ ((!!(_F5182)) << 14) | \
- /* available on F5281 */ ((!!(_F5182)) << 15))
Comments follow the code, not vice versa.
Best regards,
Wolfgang Denk
Hi Wolfgang,
Wolfgang Denk a écrit :
88f5182 is a terrible file name. Can you not come up with something more descriptive, please?
Actually, the name is based on the actual name of the Marvell SoC variant.
Why do we need an Orion5x-specific GPIO API? Can't we use something that is more general?
If there is such a general API, I'm willing to use it.
Amicalement,
Wolfgang Denk a écrit :
Dear Albert Aribaud,
diff --git a/cpu/arm926ejs/orion5x/mpp.c b/cpu/arm926ejs/orion5x/mpp.c new file mode 100644 index 0000000..f341747 --- /dev/null +++ b/cpu/arm926ejs/orion5x/mpp.c ...
- This file is licensed under the terms of the GNU General Public
- License version 2. This program is licensed "as is" without any
- warranty of any kind, whether express or implied.
NAK. License must be "v2 or any later version". Ditto for some other files.
diff --git a/include/asm-arm/arch-orion5x/gpio.h b/include/asm-arm/arch-orion5x/gpio.h new file mode 100644 index 0000000..58592ad --- /dev/null +++ b/include/asm-arm/arch-orion5x/gpio.h
...
- This file is licensed under the terms of the GNU General Public
- License version 2. This program is licensed "as is" without any
- warranty of any kind, whether express or implied.
NAK. See above.
diff --git a/include/asm-arm/arch-orion5x/mpp.h b/include/asm-arm/arch-orion5x/mpp.h new file mode 100644 index 0000000..31fade7 --- /dev/null +++ b/include/asm-arm/arch-orion5x/mpp.h
...
- This file is licensed under the terms of the GNU General Public
- License version 2. This program is licensed "as is" without any
- warranty of any kind, whether express or implied.
NAK. See above.
Best regards,
Wolfgang Denk
These files are derived from their kirkwood counterparts, which are GPL v2 only, so I don't have the right to simply change that to "v2 or any later version", I believe, unless the originals' copyright owner allows it (and possibly even fixes the originals). Prafulla, would you ACK this?
Amicalement,
Dear Albert ARIBAUD,
In message 4B1236F3.4010605@free.fr you wrote:
These files are derived from their kirkwood counterparts, which are GPL v2 only, so I don't have the right to simply change that to "v2 or any later version", I believe, unless the originals' copyright owner allows it (and possibly even fixes the originals). Prafulla, would you ACK this?
Indeed. These files need to be fixed ASAP, too:
drivers/gpio/kw_gpio.c drivers/i2c/kirkwood_i2c.c include/asm-arm/arch-kirkwood/gpio.h include/asm-arm/arch-kirkwood/mpp.h include/usb/omap1510_udc.h
Best regards,
Wolfgang Denk
-----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Saturday, December 05, 2009 6:08 AM To: Albert ARIBAUD Cc: U-Boot@lists.denx.de; Prafulla Wadaskar Subject: Re: [U-Boot] [PATCH V2 1/3] Initial support for Marvell Orion5x SoC
Dear Albert ARIBAUD,
In message 4B1236F3.4010605@free.fr you wrote:
These files are derived from their kirkwood counterparts,
which are GPL
v2 only, so I don't have the right to simply change that to
"v2 or any
later version", I believe, unless the originals' copyright
owner allows
it (and possibly even fixes the originals). Prafulla, would
you ACK this?
Ack
Indeed. These files need to be fixed ASAP, too:
drivers/gpio/kw_gpio.c drivers/i2c/kirkwood_i2c.c include/asm-arm/arch-kirkwood/gpio.h include/asm-arm/arch-kirkwood/mpp.h
In the kirkwood port these files are Imported from Linux kernel source, I will request the respective writers to update to latest GPL license.
Regards.. Prafulla . .
Wolfgang Denk a écrit :
Dear Albert Aribaud,
diff --git a/include/asm-arm/arch-orion5x/88f5182.h b/include/asm-arm/arch-orion5x/88f5182.h new file mode 100644 index 0000000..b16b23f --- /dev/null +++ b/include/asm-arm/arch-orion5x/88f5182.h
88f5182 is a terrible file name. Can you not come up with something more descriptive, please?
(Pre)fixed: file is now mv88f5182.h. That's the best I can do since 88F5182 is actually the SoC variant 'name'. Expect 'mv88f5181.h', 'mv88f5281.h' in the future.
diff --git a/include/asm-arm/arch-orion5x/gpio.h b/include/asm-arm/arch-orion5x/gpio.h new file mode 100644 index 0000000..58592ad --- /dev/null +++ b/include/asm-arm/arch-orion5x/gpio.h
...
+/*
- Orion5x-specific GPIO API
- */
Why do we need an Orion5x-specific GPIO API? Can't we use something that is more general?
I've looked at the current u-boot code and have found no generic GPIO API -- and six different, specific ones. Is there an effort going on to generalize this?
Amicalement,
participants (5)
-
Albert ARIBAUD -
Albert Aribaud
-
Prafulla Wadaskar -
Stefan Roese -
Wolfgang Denk