It seems two entries were merged in one when this file has been created. The GPSLXAU entries is obviously a mix of GPU and SLXA which are next to each other according to the datasheet. Moreover it can be noticed because the APB_MISC_PP_PULLUPDOWN_REG_B_0 register only have 15 entries instead of 16.

Also fix the pin group descriptions that were using these buggy entries. In particular SLXA that needed to used CRTP to actually write the SLXA register.

Signed-off-by: Alban Bedel alban.bedel@avionic-design.de --- arch/arm/cpu/tegra20-common/pinmux.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c index a65e991..5c80ed9 100644 --- a/arch/arm/cpu/tegra20-common/pinmux.c +++ b/arch/arm/cpu/tegra20-common/pinmux.c @@ -190,7 +190,8 @@ enum pmux_pullid {

PUCTL_SPDI, PUCTL_SPDO, - PUCTL_GPSLXAU, + PUCTL_GPU, + PUCTL_SLXA, PUCTL_CRTP, PUCTL_SLXC, PUCTL_SLXD, @@ -333,8 +334,7 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1), PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1),

- PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4, - GPSLXAU), + PIN(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4), PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE), PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4), PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB), @@ -356,7 +356,7 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC), PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM), PIN_RESERVED, - PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP), + PIN(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE), PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4), PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4), PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE),