[U-Boot] [PATCH 1/5] powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdb
From: Priyanka Jain Priyanka.Jain@freescale.com
Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash boot loaders because: - P1_P2_RDB boards have soldered DDR so no need for SPD - Also P102x has 256K L2 cache size so becomes a limiting factor for size of image that could be loaded in SRAM mode and would require three stage boot loader (TPL).
Changes done: 1. CONFIG_SYS_TEXT_BASE to 0x11000000 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc
Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com Signed-off-by: Poonam Aggrwal Poonam.Aggrwal@freescale.com Signed-off-by: Dipen Dudhat Dipen.Dudhat@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/p1_p2_rdb/ddr.c | 15 +++++++++++---- board/freescale/p1_p2_rdb/tlb.c | 13 ++++--------- include/configs/P1_P2_RDB.h | 8 ++++---- 3 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 44faec3..853044e 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -202,6 +202,17 @@ phys_size_t fixed_sdram (void) struct cpu_type *cpu; ulong ddr_freq, ddr_freq_mhz;
+ cpu = gd->cpu; + /* P1020 and it's derivatives support max 32bit DDR width */ + if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || + cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { + ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); + } else { + ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + } +#if defined(CONFIG_SYS_RAMBOOT) + return ddr_size; +#endif ddr_freq = get_ddr_freq(0); ddr_freq_mhz = ddr_freq / 1000000;
@@ -220,16 +231,12 @@ phys_size_t fixed_sdram (void) panic("Unsupported DDR data rate %s MT/s data rate\n", strmhz(buf, ddr_freq));
- cpu = gd->cpu; /* P1020 and it's derivatives support max 32bit DDR width */ if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE; ddr_cfg_regs.cs[0].bnds = 0x0000001F; - ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); } - else - ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index b85c268..e54defb 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -80,15 +80,10 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1),
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256K, 1), +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_1G, 1) #endif };
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 651dc76..23b8afa 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -57,14 +57,14 @@
#ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD 1 -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif
#ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH 1 -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif
#ifndef CONFIG_SYS_TEXT_BASE
From: Priyanka Jain Priyanka.Jain@freescale.com
PCA9557 is parallel I/O expansion device on I2C bus which stores various board switch settings like NOR Flash-Bank selection, SD Data width.
On board: switch SW5[6] is to select width for eSDHC ON - 4-bit [Enable eSPI] OFF - 8-bit [Disable eSPI]
switch SW4[8] is to select NOR Flash Bank for Booting OFF - Primary Bank ON - Secondary Bank
Read board switch settings on p1_p2_rdb and configure corresponding eSDHC width.
Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com Signed-off-by: Dipen Dudhat dipen.dudhat@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/p1_p2_rdb/p1_p2_rdb.c | 25 +++++++++++++++++++++++++ include/configs/P1_P2_RDB.h | 2 ++ 2 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 806d90e..9f57a21 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -35,6 +35,7 @@ #include <vsc7385.h> #include <netdev.h> #include <rtc.h> +#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -142,6 +143,30 @@ int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + unsigned int orig_bus = i2c_get_bus_num(); + u8 i2c_data; + + i2c_set_bus_num(1); + if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, + 1, &i2c_data, sizeof(i2c_data)) == 0) { + if (i2c_data & 0x2) + puts("NOR Flash Bank : Secondary\n"); + else + puts("NOR Flash Bank : Primary\n"); + + if (i2c_data & 0x1) { + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); + puts("SD/MMC : 8-bit Mode\n"); + puts("eSPI : Disabled\n"); + } else { + puts("SD/MMC : 4-bit Mode\n"); + puts("eSPI : Enabled\n"); + } + } else { + puts("Failed reading I2C Chip 0x18 on bus 1\n"); + } + i2c_set_bus_num(orig_bus);
/* * Remap Boot flash region to caching-inhibited diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 23b8afa..d601fcd 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -362,6 +362,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_BUS_NUM 1
+#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 + #define CONFIG_RTC_DS1337 #define CONFIG_SYS_RTC_DS1337_NOOSC #define CONFIG_SYS_I2C_RTC_ADDR 0x68
From: Poonam Aggrwal poonam.aggrwal@freescale.com
RevB boards never really made it outside of Freescale and have been replaced with RevC & RevD which had various board bug fixes.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/p1_p2_rdb/p1_p2_rdb.c | 29 +++++++---------------------- 1 files changed, 7 insertions(+), 22 deletions(-)
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 9f57a21..d4b4b68 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -55,38 +55,25 @@ DECLARE_GLOBAL_DATA_PTR;
#define SYSCLK_MASK 0x00200000 #define BOARDREV_MASK 0x10100000 -#define BOARDREV_B 0x10100000 #define BOARDREV_C 0x00100000 #define BOARDREV_D 0x00000000
#define SYSCLK_66 66666666 -#define SYSCLK_50 50000000 #define SYSCLK_100 100000000
unsigned long get_board_sys_clk(ulong dummy) { volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - u32 val_gpdat, sysclk_gpio, board_rev_gpio; + u32 val_gpdat, sysclk_gpio;
val_gpdat = in_be32(&pgpio->gpdat); sysclk_gpio = val_gpdat & SYSCLK_MASK; - board_rev_gpio = val_gpdat & BOARDREV_MASK; - if (board_rev_gpio == BOARDREV_C) { - if(sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_100; - } else if (board_rev_gpio == BOARDREV_B) { - if(sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_50; - } else if (board_rev_gpio == BOARDREV_D) { - if(sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_100; - } + + if(sysclk_gpio == 0) + return SYSCLK_66; + else + return SYSCLK_100; + return 0; }
@@ -113,8 +100,6 @@ int checkboard (void) board_rev_gpio = val_gpdat & BOARDREV_MASK; if (board_rev_gpio == BOARDREV_C) board_rev = 'C'; - else if (board_rev_gpio == BOARDREV_B) - board_rev = 'B'; else if (board_rev_gpio == BOARDREV_D) board_rev = 'D'; else
From: Poonam Aggrwal poonam.aggrwal@freescale.com
Changed the following DDR timing parameters for 800Mt/s: tRRT BL/2+1 to BL/2 tWWT BL/2+1 to BL/2 tWRT BL/2+1 to BL/2 tRWT BL/2+1 to BL/2 REFINT 6500ns to 7800ns
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/p1_p2_rdb/ddr.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 853044e..71c6088 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -74,13 +74,13 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
#define CONFIG_SYS_DDR_TIMING_3_800 0x00040000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x55770802 +#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 #define CONFIG_SYS_DDR_MODE_1_800 0x00040852 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = { .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
From: Poonam Aggrwal poonam.aggrwal@freescale.com
Add support for 36-bit address map for NOR, SD, and SPI boot cfgs.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Priyanka Jain priyanka.jain@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/p1_p2_rdb/p1_p2_rdb.c | 3 + board/freescale/p1_p2_rdb/tlb.c | 9 ++-- boards.cfg | 12 +++++ include/configs/P1_P2_RDB.h | 75 +++++++++++++++++++++++++++++--- 4 files changed, 88 insertions(+), 11 deletions(-)
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index d4b4b68..307c3e2 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -107,6 +107,9 @@ int checkboard (void)
cpu = gd->cpu; printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev); +#ifdef CONFIG_PHYS_64BIT + puts ("(36-bit addrmap) \n"); +#endif setbits_be32(&pgpio->gpdir, GPIO_DIR);
/* diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index e54defb..5b88b68 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -25,19 +25,20 @@
struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
diff --git a/boards.cfg b/boards.cfg index 45c3102..263c1e6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -509,15 +509,24 @@ MPC8572DS powerpc mpc85xx mpc8572ds freesca MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB +P1011RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT +P1011RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SDCARD +P1011RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SPIFLASH P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,NAND P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SDCARD P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SPIFLASH P1020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB +P1020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT +P1020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SDCARD +P1020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SPIFLASH P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH P1022DS powerpc mpc85xx p1022ds freescale P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB +P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT +P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD +P2010RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SPIFLASH P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,NAND P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SDCARD P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SPIFLASH @@ -525,6 +534,9 @@ P2020DS powerpc mpc85xx p2020ds freesca P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2 P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB +P2020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT +P2020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SDCARD +P2020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SPIFLASH P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index d601fcd..9eed1c8 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -30,6 +30,10 @@ #ifndef __CONFIG_H #define __CONFIG_H
+#ifdef CONFIG_36BIT +#define CONFIG_PHYS_64BIT +#endif + #ifdef CONFIG_P1011RDB #define CONFIG_P1011 #endif @@ -123,6 +127,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_ENABLE_36BIT_PHYS 1
+#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x1fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ @@ -144,7 +153,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * actual resources get mapped (not physical addresses) */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#endif /* CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ /* CONFIG_SYS_IMMR */ @@ -197,13 +210,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
+#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull +#else #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif
#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xff000ff7
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
@@ -231,6 +248,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ @@ -242,10 +271,20 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull #else -#define CONFIG_SYS_NAND_BASE 0xfff00000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif +#else +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull +#else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#endif + #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 @@ -292,7 +331,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_VSC7385_BASE 0xffb00000
+#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull +#else #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE +#endif
#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \ | BR_PS_8 | BR_V) @@ -376,24 +419,42 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_PCI) #define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 +#endif
/* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_NAME "Slot 2" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#else #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 +#endif
#define CONFIG_PCI_PNP /* do pci plug-and-play */
On Mar 6, 2011, at 10:17 PM, Kumar Gala wrote:
From: Poonam Aggrwal poonam.aggrwal@freescale.com
Changed the following DDR timing parameters for 800Mt/s: tRRT BL/2+1 to BL/2 tWWT BL/2+1 to BL/2 tWRT BL/2+1 to BL/2 tRWT BL/2+1 to BL/2 REFINT 6500ns to 7800ns
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
board/freescale/p1_p2_rdb/ddr.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
applied to 85xx next
- k
On Mar 6, 2011, at 10:17 PM, Kumar Gala wrote:
From: Poonam Aggrwal poonam.aggrwal@freescale.com
RevB boards never really made it outside of Freescale and have been replaced with RevC & RevD which had various board bug fixes.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
board/freescale/p1_p2_rdb/p1_p2_rdb.c | 29 +++++++---------------------- 1 files changed, 7 insertions(+), 22 deletions(-)
applied to 85xx next
- k
On Sun, Mar 6, 2011 at 10:17 PM, Kumar Gala galak@kernel.crashing.org wrote:
- if (i2c_data & 0x1) {
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
- puts("SD/MMC : 8-bit Mode\n");
- puts("eSPI : Disabled\n");
- } else {
- puts("SD/MMC : 4-bit Mode\n");
- puts("eSPI : Enabled\n");
I think this bit is actually important for the p1_p2_rdb_pc boards also? Is this handled by the CPLD somehow or do we need to do the same thing?
'IO0 - "read-only" CFG_SDWIDTH SW2[1].
-M
On Mar 9, 2011, at 12:38 AM, McClintock Matthew-B29882 wrote:
On Sun, Mar 6, 2011 at 10:17 PM, Kumar Gala galak@kernel.crashing.org wrote:
if (i2c_data & 0x1) {setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);puts("SD/MMC : 8-bit Mode\n");puts("eSPI : Disabled\n");} else {puts("SD/MMC : 4-bit Mode\n");puts("eSPI : Enabled\n");I think this bit is actually important for the p1_p2_rdb_pc boards also? Is this handled by the CPLD somehow or do we need to do the same thing?
'IO0 - "read-only" CFG_SDWIDTH SW2[1].
the setting of pmuxcr? SW has to do that.
- k
On Wed, Mar 9, 2011 at 9:36 AM, Kumar Gala galak@kernel.crashing.org wrote:
the setting of pmuxcr? SW has to do that.
But we don't do this based off the switch value currently on p1_p2_rdb_pc boards.
-M
On Mar 6, 2011, at 10:17 PM, Kumar Gala wrote:
From: Priyanka Jain Priyanka.Jain@freescale.com
PCA9557 is parallel I/O expansion device on I2C bus which stores various board switch settings like NOR Flash-Bank selection, SD Data width.
On board: switch SW5[6] is to select width for eSDHC ON - 4-bit [Enable eSPI] OFF - 8-bit [Disable eSPI]
switch SW4[8] is to select NOR Flash Bank for Booting OFF - Primary Bank ON - Secondary Bank
Read board switch settings on p1_p2_rdb and configure corresponding eSDHC width.
Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com Signed-off-by: Dipen Dudhat dipen.dudhat@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
board/freescale/p1_p2_rdb/p1_p2_rdb.c | 25 +++++++++++++++++++++++++ include/configs/P1_P2_RDB.h | 2 ++ 2 files changed, 27 insertions(+), 0 deletions(-)
applied to 85xx next
- k
On Mar 6, 2011, at 10:17 PM, Kumar Gala wrote:
From: Priyanka Jain Priyanka.Jain@freescale.com
Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash boot loaders because:
- P1_P2_RDB boards have soldered DDR so no need for SPD
- Also P102x has 256K L2 cache size so becomes a limiting factor for
size of image that could be loaded in SRAM mode and would require three stage boot loader (TPL).
Changes done:
- CONFIG_SYS_TEXT_BASE to 0x11000000
- CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc
Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com Signed-off-by: Poonam Aggrwal Poonam.Aggrwal@freescale.com Signed-off-by: Dipen Dudhat Dipen.Dudhat@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
board/freescale/p1_p2_rdb/ddr.c | 15 +++++++++++---- board/freescale/p1_p2_rdb/tlb.c | 13 ++++--------- include/configs/P1_P2_RDB.h | 8 ++++---- 3 files changed, 19 insertions(+), 17 deletions(-)
applied to 85xx next
- k
participants (2)
-
Kumar Gala -
McClintock Matthew-B29882