[U-Boot] [PULL] u-boot-socfpga/master
Hi Tom,
SoCFPGA stuff for current release.
The following changes since commit 7f641d53bbb3a426a3bfb132d8346153e86a9d08:
Merge branch 'master' of git://git.denx.de/u-boot-ubi (2015-02-04 13:30:00 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-socfpga.git HEAD
for you to fetch changes up to 6da3e0c1758f7316025e342ef0801efba9bd7f23:
dt: socfpga: Import and enable Arria V DK DTS (2015-02-09 20:10:22 +0100)
---------------------------------------------------------------- Marek Vasut (10): arm: socfpga: Minor coding style fix arm: socfpga: Sync Cyclone V DK pinmux configuration arm: socfpga: Sync Cyclone V DK PLL configuration arm: socfpga: Add USB and UDC support for Cyclone V DK arm: socfpga: Drop cyclone5 suffix from board file name arm: socfpga: Zap checkboard() arm: socfpga: Zap board_early_init_f() arm: socfpga: Add Altera Arria V DK support dt: socfpga: Import and enable Cyclone V DK DTS dt: socfpga: Import and enable Arria V DK DTS
arch/arm/Kconfig | 5 + arch/arm/dts/Makefile | 5 +- arch/arm/dts/socfpga_arria5.dtsi | 34 +++++ arch/arm/dts/socfpga_arria5_socdk.dts | 74 +++++++++ arch/arm/dts/socfpga_cyclone5_socdk.dts | 79 ++++++++++ board/altera/socfpga/Kconfig | 16 ++ board/altera/socfpga/Makefile | 2 +- board/altera/socfpga/iocsr_config.c | 688 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/altera/socfpga/iocsr_config.h | 17 ++- board/altera/socfpga/pinmux_config.c | 403 +++++++++++++++++++++++++++++++++++++------------ board/altera/socfpga/pinmux_config.h | 14 +- board/altera/socfpga/pll_config.h | 34 ++--- board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} | 17 --- configs/socfpga_arria5_defconfig | 5 + configs/socfpga_cyclone5_defconfig | 2 + include/configs/socfpga_arria5.h | 107 +++++++++++++ include/configs/socfpga_common.h | 3 +- include/configs/socfpga_cyclone5.h | 9 ++ 18 files changed, 1365 insertions(+), 149 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria5.dtsi create mode 100644 arch/arm/dts/socfpga_arria5_socdk.dts create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk.dts rename board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} (86%) create mode 100644 configs/socfpga_arria5_defconfig create mode 100644 include/configs/socfpga_arria5.h
On Tue, Feb 17, 2015 at 09:11:01PM +0100, Marek Vasut wrote:
Hi Tom,
SoCFPGA stuff for current release.
The following changes since commit 7f641d53bbb3a426a3bfb132d8346153e86a9d08:
Merge branch 'master' of git://git.denx.de/u-boot-ubi (2015-02-04 13:30:00 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-socfpga.git HEAD
for you to fetch changes up to 6da3e0c1758f7316025e342ef0801efba9bd7f23:
dt: socfpga: Import and enable Arria V DK DTS (2015-02-09 20:10:22 +0100)
I see: $ ./tools/buildman/buildman -ve socfpga_arria5 boards.cfg is up to date. Nothing to do. Building current source for 1 boards (1 thread, 6 jobs per thread) arm: + socfpga_arria5 + priv->qspi_calibrated_cs = spi_chip_select(bus); + ^ +drivers/spi/cadence_qspi.c: At top level: +drivers/spi/cadence_qspi.c:320:21: error: variable 'cadence_spi_ops' has initializer but incomplete type + static const struct dm_spi_ops cadence_spi_ops = { + ^ +drivers/spi/cadence_qspi.c:321:2: error: unknown field 'xfer' specified in initializer + .xfer = cadence_spi_xfer, +drivers/spi/cadence_qspi.c:322:2: error: unknown field 'set_speed' specified in initializer + .set_speed = cadence_spi_set_speed, +drivers/spi/cadence_qspi.c:323:2: error: unknown field 'set_mode' specified in initializer + .set_mode = cadence_spi_set_mode, +make[2]: *** [drivers/spi/cadence_qspi.o] Error 1 +make[1]: *** [drivers/spi] Error 2 +make: *** [sub-make] Error 2 w+drivers/spi/cadence_qspi.c: In function 'spi_calibration': w+drivers/spi/cadence_qspi.c:115:2: warning: implicit declaration of function 'spi_chip_select' [-Wimplicit-function-declaration] w+drivers/spi/cadence_qspi.c:321:2: warning: excess elements in struct initializer [enabled by default] w+drivers/spi/cadence_qspi.c:321:2: warning: (near initialization for 'cadence_spi_ops') [enabled by default] w+drivers/spi/cadence_qspi.c:322:2: warning: excess elements in struct initializer [enabled by default] w+drivers/spi/cadence_qspi.c:322:2: warning: (near initialization for 'cadence_spi_ops') [enabled by default] w+drivers/spi/cadence_qspi.c:323:2: warning: excess elements in struct initializer [enabled by default] w+drivers/spi/cadence_qspi.c:323:2: warning: (near initialization for 'cadence_spi_ops') [enabled by default] 0 0 1 /1 socfpga_arria5 $
On Wednesday, February 18, 2015 at 04:04:07 AM, Tom Rini wrote:
On Tue, Feb 17, 2015 at 09:11:01PM +0100, Marek Vasut wrote:
Hi Tom,
SoCFPGA stuff for current release.
The following changes since commit 7f641d53bbb3a426a3bfb132d8346153e86a9d08: Merge branch 'master' of git://git.denx.de/u-boot-ubi (2015-02-04 13:30:00
-0500)
are available in the git repository at: git://git.denx.de/u-boot-socfpga.git HEAD
for you to fetch changes up to 6da3e0c1758f7316025e342ef0801efba9bd7f23: dt: socfpga: Import and enable Arria V DK DTS (2015-02-09 20:10:22 +0100)
I see: $ ./tools/buildman/buildman -ve socfpga_arria5 boards.cfg is up to date. Nothing to do. Building current source for 1 boards (1 thread, 6 jobs per thread) arm: + socfpga_arria5
- priv->qspi_calibrated_cs = spi_chip_select(bus);
- ^
+drivers/spi/cadence_qspi.c: At top level: +drivers/spi/cadence_qspi.c:320:21: error: variable 'cadence_spi_ops' has initializer but incomplete type + static const struct dm_spi_ops cadence_spi_ops = {
^+drivers/spi/cadence_qspi.c:321:2: error: unknown field 'xfer' specified in initializer + .xfer = cadence_spi_xfer, +drivers/spi/cadence_qspi.c:322:2: error: unknown field 'set_speed' specified in initializer + .set_speed = cadence_spi_set_speed, +drivers/spi/cadence_qspi.c:323:2: error: unknown field 'set_mode' specified in initializer + .set_mode = cadence_spi_set_mode, +make[2]: *** [drivers/spi/cadence_qspi.o] Error 1 +make[1]: *** [drivers/spi] Error 2 +make: *** [sub-make] Error 2 w+drivers/spi/cadence_qspi.c: In function 'spi_calibration': w+drivers/spi/cadence_qspi.c:115:2: warning: implicit declaration of function 'spi_chip_select' [-Wimplicit-function-declaration] w+drivers/spi/cadence_qspi.c:321:2: warning: excess elements in struct initializer [enabled by default] w+drivers/spi/cadence_qspi.c:321:2: warning: (near initialization for 'cadence_spi_ops') [enabled by default] w+drivers/spi/cadence_qspi.c:322:2: warning: excess elements in struct initializer [enabled by default] w+drivers/spi/cadence_qspi.c:322:2: warning: (near initialization for 'cadence_spi_ops') [enabled by default] w+drivers/spi/cadence_qspi.c:323:2: warning: excess elements in struct initializer [enabled by default] w+drivers/spi/cadence_qspi.c:323:2: warning: (near initialization for 'cadence_spi_ops') [enabled by default] 0 0 1 /1 socfpga_arria5 $
Damn. I'll send fixes for this.
Best regards, Marek Vasut
Fixed PR follows.
The following changes since commit 8176a874233eb5180701e2811b38c199369975b2:
Prepare v2015.04-rc3 (2015-03-03 18:08:39 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-socfpga.git HEAD
for you to fetch changes up to 053ae0a363276324aebbbdb1c2056a9380209f4b:
arm: socfpga: Enable DM and DM_SPI (2015-03-05 21:05:34 +0100)
---------------------------------------------------------------- Marek Vasut (11): arm: socfpga: Minor coding style fix arm: socfpga: Sync Cyclone V DK pinmux configuration arm: socfpga: Sync Cyclone V DK PLL configuration arm: socfpga: Add USB and UDC support for Cyclone V DK arm: socfpga: Drop cyclone5 suffix from board file name arm: socfpga: Zap checkboard() arm: socfpga: Zap board_early_init_f() arm: socfpga: Add Altera Arria V DK support dt: socfpga: Import and enable Cyclone V DK DTS dt: socfpga: Import and enable Arria V DK DTS arm: socfpga: Enable DM and DM_SPI
arch/arm/Kconfig | 5 + arch/arm/dts/Makefile | 5 +- arch/arm/dts/socfpga_arria5.dtsi | 34 +++++ arch/arm/dts/socfpga_arria5_socdk.dts | 74 +++++++++ arch/arm/dts/socfpga_cyclone5_socdk.dts | 79 ++++++++++ board/altera/socfpga/Kconfig | 16 ++ board/altera/socfpga/Makefile | 2 +- board/altera/socfpga/iocsr_config.c | 688 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/altera/socfpga/iocsr_config.h | 17 ++- board/altera/socfpga/pinmux_config.c | 403 +++++++++++++++++++++++++++++++++++++------------ board/altera/socfpga/pinmux_config.h | 14 +- board/altera/socfpga/pll_config.h | 34 ++--- board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} | 17 --- configs/socfpga_arria5_defconfig | 8 + configs/socfpga_cyclone5_defconfig | 5 + include/configs/socfpga_arria5.h | 107 +++++++++++++ include/configs/socfpga_common.h | 3 +- include/configs/socfpga_cyclone5.h | 9 ++ 18 files changed, 1371 insertions(+), 149 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria5.dtsi create mode 100644 arch/arm/dts/socfpga_arria5_socdk.dts create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk.dts rename board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} (86%) create mode 100644 configs/socfpga_arria5_defconfig create mode 100644 include/configs/socfpga_arria5.h
On Thu, Mar 05, 2015 at 09:06:59PM +0100, Marek Vasut wrote:
Fixed PR follows.
The following changes since commit 8176a874233eb5180701e2811b38c199369975b2:
Prepare v2015.04-rc3 (2015-03-03 18:08:39 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-socfpga.git HEAD
for you to fetch changes up to 053ae0a363276324aebbbdb1c2056a9380209f4b:
arm: socfpga: Enable DM and DM_SPI (2015-03-05 21:05:34 +0100)
Applied to u-boot/master, thanks!
participants (3)
-
Marek Vasut -
Tom Rini -
Tom Rini