[U-Boot] [PATCH] rockchip: add support for rk3288 miniarm board
Miniarm is a rockchip rk3288 based development board, which has lots of interface such as HDMI, USB, micro-SD card, Audio etc.
Signed-off-by: Ziyuan Xu xzy.xu@rock-chips.com ---
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3288-miniarm.dts | 61 +++ arch/arm/dts/rk3288-miniarm.dtsi | 533 +++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 10 + board/rockchip/miniarm_rk3288/Kconfig | 15 + board/rockchip/miniarm_rk3288/MAINTAINERS | 6 + board/rockchip/miniarm_rk3288/Makefile | 7 + board/rockchip/miniarm_rk3288/miniarm-rk3288.c | 15 + configs/miniarm-rk3288_defconfig | 65 +++ doc/README.rockchip | 3 +- include/configs/miniarm_rk3288.h | 26 ++ 11 files changed, 741 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3288-miniarm.dts create mode 100644 arch/arm/dts/rk3288-miniarm.dtsi create mode 100644 board/rockchip/miniarm_rk3288/Kconfig create mode 100644 board/rockchip/miniarm_rk3288/MAINTAINERS create mode 100644 board/rockchip/miniarm_rk3288/Makefile create mode 100644 board/rockchip/miniarm_rk3288/miniarm-rk3288.c create mode 100644 configs/miniarm-rk3288_defconfig create mode 100644 include/configs/miniarm_rk3288.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 639c06d..50ddb39 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-evb.dtb \ rk3288-fennec.dtb \ rk3288-popmetal.dtb \ + rk3288-miniarm.dtb \ rk3036-sdk.dtb \ rk3399-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ diff --git a/arch/arm/dts/rk3288-miniarm.dts b/arch/arm/dts/rk3288-miniarm.dts new file mode 100644 index 0000000..c741082 --- /dev/null +++ b/arch/arm/dts/rk3288-miniarm.dts @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +#include "rk3288-miniarm.dtsi" + +/ { + model = "Miniarm-RK3288"; + compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288"; + + chosen { + stdout-path = &uart2; + }; +}; + +&dmc { + rockchip,num-channels = <2>; + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + /* Add a dummy value to cause of-platdata think this is bytes */ + rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; + + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pwm1 { + status = "okay"; +}; + +&uart2 { + u-boot,dm-pre-reloc; + reg-shift = <2>; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio8 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-miniarm.dtsi b/arch/arm/dts/rk3288-miniarm.dtsi new file mode 100644 index 0000000..b889875 --- /dev/null +++ b/arch/arm/dts/rk3288-miniarm.dtsi @@ -0,0 +1,533 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "rk3288.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + button@0 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + pwr-led { + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + act-led { + gpios=<&gpio2 3 GPIO_ACTIVE_LOW>; + linux,default-trigger="mmc0"; + }; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* + * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from + * vcc_io directly. Those boards won't be able to power cycle SD cards + * but it shouldn't hurt to toggle this pin there anyway. + */ + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; /* wp not hooked up */ + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; + supports-sd; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc33_lan>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio4 7 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "ok"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_18>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vcc18_ldo1>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc18_ldo1: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_ldo1"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc33_mipi: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_mipi"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_codec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc33_sd: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc33_sd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc33_lan: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc33_lan"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + headset: nau8825@1a { + compatible = "nuvoton,nau8825"; + #sound-dai-cells = <0>; + reg = <0x1a>; + interrupt-parent = <&gpio6>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + nuvoton,jkdet-enable = <1>; + nuvoton,jkdet-pull-enable = <1>; + nuvoton,jkdet-pull-up = <0>; + nuvoton,jkdet-polarity = <1>; + nuvoton,vref-impedance = <2>; + nuvoton,micbias-voltage = <6>; + nuvoton,sar-threshold-num = <4>; + nuvoton,sar-threshold = <0xa 0x14 0x26 0x73>; + nuvoton,sar-hysteresis = <0>; + nuvoton,sar-voltage = <6>; + nuvoton,sar-compare-time = <0>; + nuvoton,sar-sampling-time = <0>; + nuvoton,short-key-debounce = <3>; + nuvoton,jack-insert-debounce = <7>; + nuvoton,jack-eject-debounce = <7>; + clock-names = "mclk"; + clocks = <&cru SCLK_I2S0_OUT>; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc18_ldo1>; + status ="okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status= "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + backlight { + bl_en: bl-en { + rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + eth_phy { + eth_phy_pwr: eth-phy-pwr { + rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on EVB board so bump up to 8ma. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pwr_3g: pwr-3g { + rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 8ec1920..aaa13b5 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -33,6 +33,14 @@ config TARGET_POPMETAL_RK3288 2GB DDR3. Expansion connectors provide access to I2C, SPI, UART, GPIOs and display interface.
+config TARGET_MINIARM_RK3288 + bool "miniarm-RK3288" + help + Miniarm is a RK3288-based development board with 2 USB ports, HDMI, + micro-SD card, audio, Gigabit Ethernet. It also includes on-board + 8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to + I2C, SPI, UART, GPIOs. + config TARGET_CHROMEBOOK_JERRY bool "Google/Rockchip Veyron-Jerry Chromebook" help @@ -76,4 +84,6 @@ source "board/rockchip/fennec_rk3288/Kconfig"
source "board/chipspark/popmetal_rk3288/Kconfig"
+source "board/rockchip/miniarm_rk3288/Kconfig" + endif diff --git a/board/rockchip/miniarm_rk3288/Kconfig b/board/rockchip/miniarm_rk3288/Kconfig new file mode 100644 index 0000000..529c09f --- /dev/null +++ b/board/rockchip/miniarm_rk3288/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MINIARM_RK3288 + +config SYS_BOARD + default "miniarm_rk3288" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "miniarm_rk3288" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/miniarm_rk3288/MAINTAINERS b/board/rockchip/miniarm_rk3288/MAINTAINERS new file mode 100644 index 0000000..7537b8f --- /dev/null +++ b/board/rockchip/miniarm_rk3288/MAINTAINERS @@ -0,0 +1,6 @@ +MINIARM-RK3288 +M: Lin Huang hl@rock-chips.com +S: Maintained +F: board/rockchip/miniarm_rk3288 +F: include/configs/miniarm_rk3288.h +F: configs/miniarm-rk3288_defconfig diff --git a/board/rockchip/miniarm_rk3288/Makefile b/board/rockchip/miniarm_rk3288/Makefile new file mode 100644 index 0000000..9419b91 --- /dev/null +++ b/board/rockchip/miniarm_rk3288/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += miniarm-rk3288.o diff --git a/board/rockchip/miniarm_rk3288/miniarm-rk3288.c b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c new file mode 100644 index 0000000..aad74ef --- /dev/null +++ b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +void board_boot_order(u32 *spl_boot_list) +{ + /* eMMC prior to sdcard */ + spl_boot_list[0] = BOOT_DEVICE_MMC2; + spl_boot_list[1] = BOOT_DEVICE_MMC1; +} diff --git a/configs/miniarm-rk3288_defconfig b/configs/miniarm-rk3288_defconfig new file mode 100644 index 0000000..33a4a56 --- /dev/null +++ b/configs/miniarm-rk3288_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3288=y +CONFIG_TARGET_MINIARM_RK3288=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3288-miniarm" +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_SYSRESET=y +CONFIG_DM_MMC=y +CONFIG_ROCKCHIP_DWMMC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_ROCKCHIP_RK3288_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK808=y +CONFIG_DM_REGULATOR=y +CONFIG_REGULATOR_RK808=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/doc/README.rockchip b/doc/README.rockchip index 1b3a602..b69a526 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -36,7 +36,7 @@ You will need: Building ========
-At present six RK3288 boards are supported: +At present seven RK3288 boards are supported:
- Firefly RK3288 - use firefly-rk3288 configuration - Radxa Rock 2 - use rock2 configuration @@ -44,6 +44,7 @@ At present six RK3288 boards are supported: - EVB RK3288 - use evb-rk3288 configuration - Fennec RK3288 - use fennec-rk3288 configuration - PopMetal RK3288 - use popmetal-rk3288 configuration + - Miniarm RK3288 - use miniarm-rk3288 configuration
Two RK3036 board are supported:
diff --git a/include/configs/miniarm_rk3288.h b/include/configs/miniarm_rk3288.h new file mode 100644 index 0000000..342557f --- /dev/null +++ b/include/configs/miniarm_rk3288.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include <configs/rk3288_common.h> + +#define CONFIG_SPL_MMC_SUPPORT + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +/* SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) + +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif
Hi Ziyuan,
On 27 July 2016 at 21:43, Ziyuan Xu xzy.xu@rock-chips.com wrote:
Miniarm is a rockchip rk3288 based development board, which has lots of interface such as HDMI, USB, micro-SD card, Audio etc.
Signed-off-by: Ziyuan Xu xzy.xu@rock-chips.com
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3288-miniarm.dts | 61 +++ arch/arm/dts/rk3288-miniarm.dtsi | 533 +++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 10 + board/rockchip/miniarm_rk3288/Kconfig | 15 + board/rockchip/miniarm_rk3288/MAINTAINERS | 6 + board/rockchip/miniarm_rk3288/Makefile | 7 + board/rockchip/miniarm_rk3288/miniarm-rk3288.c | 15 + configs/miniarm-rk3288_defconfig | 65 +++ doc/README.rockchip | 3 +- include/configs/miniarm_rk3288.h | 26 ++ 11 files changed, 741 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3288-miniarm.dts create mode 100644 arch/arm/dts/rk3288-miniarm.dtsi create mode 100644 board/rockchip/miniarm_rk3288/Kconfig create mode 100644 board/rockchip/miniarm_rk3288/MAINTAINERS create mode 100644 board/rockchip/miniarm_rk3288/Makefile create mode 100644 board/rockchip/miniarm_rk3288/miniarm-rk3288.c create mode 100644 configs/miniarm-rk3288_defconfig create mode 100644 include/configs/miniarm_rk3288.h
Acked-by: Simon Glass sjg@chromium.org
But please can you keep things in alpha order? See below.
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 639c06d..50ddb39 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-evb.dtb \ rk3288-fennec.dtb \ rk3288-popmetal.dtb \
rk3288-miniarm.dtb \
move up one line
rk3036-sdk.dtb \ rk3399-evb.dtbdtb-$(CONFIG_ARCH_MESON) += \ diff --git a/arch/arm/dts/rk3288-miniarm.dts b/arch/arm/dts/rk3288-miniarm.dts new file mode 100644 index 0000000..c741082 --- /dev/null +++ b/arch/arm/dts/rk3288-miniarm.dts @@ -0,0 +1,61 @@ +/*
- (C) Copyright 2016 Rockchip Electronics Co., Ltd
- SPDX-License-Identifier: GPL-2.0+ X11
- */
+/dts-v1/; +#include "rk3288-miniarm.dtsi"
+/ {
model = "Miniarm-RK3288";compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";chosen {stdout-path = &uart2;};+};
+&dmc {
rockchip,num-channels = <2>;rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x70x5 0xa 0x5 0x200 0x5 0x10 0x40 0x00x1 0x7 0x7 0x4 0xc 0x43 0x100 0x00x5 0x0>;rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c2000xa60 0x40 0x10 0x0>;/* Add a dummy value to cause of-platdata think this is bytes */rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;+};
+&pinctrl {
u-boot,dm-pre-reloc;+};
+&pwm1 {
status = "okay";+};
+&uart2 {
u-boot,dm-pre-reloc;reg-shift = <2>;+};
+&sdmmc {
u-boot,dm-pre-reloc;+};
+&emmc {
u-boot,dm-pre-reloc;+};
+&gpio3 {
u-boot,dm-pre-reloc;+};
+&gpio8 {
u-boot,dm-pre-reloc;+}; diff --git a/arch/arm/dts/rk3288-miniarm.dtsi b/arch/arm/dts/rk3288-miniarm.dtsi new file mode 100644 index 0000000..b889875 --- /dev/null +++ b/arch/arm/dts/rk3288-miniarm.dtsi @@ -0,0 +1,533 @@ +/*
- This file is dual-licensed: you can use it either under the terms
- of the GPL or the X11 license, at your option. Note that this dual
- licensing only applies to this file, and not this project as a
- whole.
- a) This file is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 2 of the
License, or (at your option) any later version.
This file is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
- Or, alternatively,
- b) Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without
restriction, including without limitation the rights to use,
copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following
conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.- */
+#include "rk3288.dtsi"
+/ {
memory {device_type = "memory";reg = <0x0 0x80000000>;};ext_gmac: external-gmac-clock {compatible = "fixed-clock";clock-frequency = <125000000>;clock-output-names = "ext_gmac";#clock-cells = <0>;};gpio-keys {compatible = "gpio-keys";#address-cells = <1>;#size-cells = <0>;autorepeat;pinctrl-names = "default";pinctrl-0 = <&pwrbtn>;button@0 {gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;label = "GPIO Key Power";linux,input-type = <1>;gpio-key,wakeup = <1>;debounce-interval = <100>;};};gpio-leds {compatible = "gpio-leds";pwr-led {gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;linux,default-trigger = "default-on";};act-led {gpios=<&gpio2 3 GPIO_ACTIVE_LOW>;linux,default-trigger="mmc0";};};vcc_sys: vsys-regulator {compatible = "regulator-fixed";regulator-name = "vcc_sys";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-always-on;regulator-boot-on;};/** NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from* vcc_io directly. Those boards won't be able to power cycle SD cards* but it shouldn't hurt to toggle this pin there anyway.*/vcc_sd: sdmmc-regulator {compatible = "regulator-fixed";gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;pinctrl-names = "default";pinctrl-0 = <&sdmmc_pwr>;regulator-name = "vcc_sd";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;startup-delay-us = <100000>;vin-supply = <&vcc_io>;};+};
+&cpu0 {
cpu0-supply = <&vdd_cpu>;+};
+&emmc {
broken-cd;bus-width = <8>;cap-mmc-highspeed;disable-wp;non-removable;num-slots = <1>;pinctrl-names = "default";pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;status = "okay";+};
+&sdmmc {
bus-width = <4>;cap-mmc-highspeed;cap-sd-highspeed;card-detect-delay = <200>;disable-wp; /* wp not hooked up */num-slots = <1>;pinctrl-names = "default";pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;status = "okay";supports-sd;vmmc-supply = <&vcc_sd>;vqmmc-supply = <&vccio_sd>;+};
+&gpu {
mali-supply = <&vdd_gpu>;status = "okay";+};
+&gmac {
phy-supply = <&vcc33_lan>;phy-mode = "rgmii";clock_in_out = "input";snps,reset-gpio = <&gpio4 7 0>;snps,reset-active-low;snps,reset-delays-us = <0 10000 1000000>;assigned-clocks = <&cru SCLK_MAC>;assigned-clock-parents = <&ext_gmac>;pinctrl-names = "default";pinctrl-0 = <&rgmii_pins>;tx_delay = <0x30>;rx_delay = <0x10>;status = "ok";+};
+&hdmi {
ddc-i2c-bus = <&i2c5>;status = "okay";+};
+&i2c0 {
status = "okay";clock-frequency = <400000>;rk808: pmic@1b {compatible = "rockchip,rk808";reg = <0x1b>;interrupt-parent = <&gpio0>;interrupts = <4 IRQ_TYPE_LEVEL_LOW>;pinctrl-names = "default";pinctrl-0 = <&pmic_int &global_pwroff>;rockchip,system-power-controller;wakeup-source;#clock-cells = <1>;clock-output-names = "xin32k", "rk808-clkout2";vcc1-supply = <&vcc_sys>;vcc2-supply = <&vcc_sys>;vcc3-supply = <&vcc_sys>;vcc4-supply = <&vcc_sys>;vcc6-supply = <&vcc_sys>;vcc7-supply = <&vcc_sys>;vcc8-supply = <&vcc_18>;vcc9-supply = <&vcc_io>;vcc10-supply = <&vcc_io>;vcc11-supply = <&vcc_sys>;vcc12-supply = <&vcc_io>;vddio-supply = <&vcc18_ldo1>;regulators {vdd_cpu: DCDC_REG1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <1350000>;regulator-name = "vdd_arm";regulator-state-mem {regulator-off-in-suspend;};};vdd_gpu: DCDC_REG2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <1250000>;regulator-name = "vdd_gpu";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1000000>;};};vcc_ddr: DCDC_REG3 {regulator-always-on;regulator-boot-on;regulator-name = "vcc_ddr";regulator-state-mem {regulator-on-in-suspend;};};vcc_io: DCDC_REG4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc_io";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vcc18_ldo1: LDO_REG1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc18_ldo1";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc33_mipi: LDO_REG2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc33_mipi";regulator-state-mem {regulator-off-in-suspend;};};vdd_10: LDO_REG3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1000000>;regulator-max-microvolt = <1000000>;regulator-name = "vdd_10";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1000000>;};};vcc18_codec: LDO_REG4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc18_codec";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vccio_sd: LDO_REG5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-name = "vccio_sd";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vdd10_lcd: LDO_REG6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1000000>;regulator-max-microvolt = <1000000>;regulator-name = "vdd10_lcd";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1000000>;};};vcc_18: LDO_REG7 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc_18";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc18_lcd: LDO_REG8 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc18_lcd";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc33_sd: SWITCH_REG1 {regulator-always-on;regulator-boot-on;regulator-name = "vcc33_sd";regulator-state-mem {regulator-on-in-suspend;};};vcc33_lan: SWITCH_REG2 {regulator-always-on;regulator-boot-on;regulator-name = "vcc33_lan";regulator-state-mem {regulator-on-in-suspend;};};};};+};
+&i2c2 {
status = "okay";headset: nau8825@1a {compatible = "nuvoton,nau8825";#sound-dai-cells = <0>;reg = <0x1a>;interrupt-parent = <&gpio6>;interrupts = <5 IRQ_TYPE_LEVEL_LOW>;nuvoton,jkdet-enable = <1>;nuvoton,jkdet-pull-enable = <1>;nuvoton,jkdet-pull-up = <0>;nuvoton,jkdet-polarity = <1>;nuvoton,vref-impedance = <2>;nuvoton,micbias-voltage = <6>;nuvoton,sar-threshold-num = <4>;nuvoton,sar-threshold = <0xa 0x14 0x26 0x73>;nuvoton,sar-hysteresis = <0>;nuvoton,sar-voltage = <6>;nuvoton,sar-compare-time = <0>;nuvoton,sar-sampling-time = <0>;nuvoton,short-key-debounce = <3>;nuvoton,jack-insert-debounce = <7>;nuvoton,jack-eject-debounce = <7>;clock-names = "mclk";clocks = <&cru SCLK_I2S0_OUT>;};+};
+&i2c5 {
status = "okay";+};
+&wdt {
status = "okay";+};
+&pwm0 {
status = "okay";+};
+&saradc {
vref-supply = <&vcc18_ldo1>;status ="okay";+};
+&uart0 {
status = "okay";+};
+&uart1 {
status = "okay";+};
+&uart2 {
status = "okay";+};
+&uart3 {
status = "okay";+};
+&uart4 {
status = "okay";+};
+&tsadc {
rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */status = "okay";+};
+&usbphy {
status = "okay";+};
+&usb_host0_ehci {
status = "okay";+};
+&usb_host1 {
status = "okay";+};
+&usb_otg {
status= "okay";+};
+&vopb {
status = "okay";+};
+&vopb_mmu {
status = "okay";+};
+&vopl {
status = "okay";+};
+&vopl_mmu {
status = "okay";+};
+&pinctrl {
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {drive-strength = <8>;};pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {bias-pull-up;drive-strength = <8>;};backlight {bl_en: bl-en {rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;};};buttons {pwrbtn: pwrbtn {rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;};};eth_phy {eth_phy_pwr: eth-phy-pwr {rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;};};pmic {pmic_int: pmic-int {rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;};};sdmmc {/** Default drive strength isn't enough to achieve even* high-speed mode on EVB board so bump up to 8ma.*/sdmmc_bus4: sdmmc-bus4 {rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,<6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,<6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,<6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;};sdmmc_clk: sdmmc-clk {rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;};sdmmc_cmd: sdmmc-cmd {rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;};sdmmc_pwr: sdmmc-pwr {rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;};};usb {host_vbus_drv: host-vbus-drv {rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;};pwr_3g: pwr-3g {rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;};};+}; diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 8ec1920..aaa13b5 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -33,6 +33,14 @@ config TARGET_POPMETAL_RK3288 2GB DDR3. Expansion connectors provide access to I2C, SPI, UART, GPIOs and display interface.
+config TARGET_MINIARM_RK3288
bool "miniarm-RK3288"helpMiniarm is a RK3288-based development board with 2 USB ports, HDMI,micro-SD card, audio, Gigabit Ethernet. It also includes on-board8GB eMMC and 2GB of SDRAM. Expansion connectors provide access toI2C, SPI, UART, GPIOs.config TARGET_CHROMEBOOK_JERRY bool "Google/Rockchip Veyron-Jerry Chromebook" help @@ -76,4 +84,6 @@ source "board/rockchip/fennec_rk3288/Kconfig"
source "board/chipspark/popmetal_rk3288/Kconfig"
+source "board/rockchip/miniarm_rk3288/Kconfig"
Move up to maintain alpha order
endif diff --git a/board/rockchip/miniarm_rk3288/Kconfig b/board/rockchip/miniarm_rk3288/Kconfig new file mode 100644 index 0000000..529c09f --- /dev/null +++ b/board/rockchip/miniarm_rk3288/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MINIARM_RK3288
+config SYS_BOARD
default "miniarm_rk3288"+config SYS_VENDOR
default "rockchip"+config SYS_CONFIG_NAME
default "miniarm_rk3288"+config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y+endif diff --git a/board/rockchip/miniarm_rk3288/MAINTAINERS b/board/rockchip/miniarm_rk3288/MAINTAINERS new file mode 100644 index 0000000..7537b8f --- /dev/null +++ b/board/rockchip/miniarm_rk3288/MAINTAINERS @@ -0,0 +1,6 @@ +MINIARM-RK3288 +M: Lin Huang hl@rock-chips.com +S: Maintained +F: board/rockchip/miniarm_rk3288 +F: include/configs/miniarm_rk3288.h +F: configs/miniarm-rk3288_defconfig diff --git a/board/rockchip/miniarm_rk3288/Makefile b/board/rockchip/miniarm_rk3288/Makefile new file mode 100644 index 0000000..9419b91 --- /dev/null +++ b/board/rockchip/miniarm_rk3288/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += miniarm-rk3288.o diff --git a/board/rockchip/miniarm_rk3288/miniarm-rk3288.c b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c new file mode 100644 index 0000000..aad74ef --- /dev/null +++ b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c @@ -0,0 +1,15 @@ +/*
- (C) Copyright 2016 Rockchip Electronics Co., Ltd
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <spl.h>
+void board_boot_order(u32 *spl_boot_list) +{
/* eMMC prior to sdcard */spl_boot_list[0] = BOOT_DEVICE_MMC2;spl_boot_list[1] = BOOT_DEVICE_MMC1;+} diff --git a/configs/miniarm-rk3288_defconfig b/configs/miniarm-rk3288_defconfig new file mode 100644 index 0000000..33a4a56 --- /dev/null +++ b/configs/miniarm-rk3288_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3288=y +CONFIG_TARGET_MINIARM_RK3288=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3288-miniarm" +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_SYSRESET=y +CONFIG_DM_MMC=y +CONFIG_ROCKCHIP_DWMMC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_ROCKCHIP_RK3288_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK808=y +CONFIG_DM_REGULATOR=y +CONFIG_REGULATOR_RK808=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/doc/README.rockchip b/doc/README.rockchip index 1b3a602..b69a526 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -36,7 +36,7 @@ You will need: Building ========
-At present six RK3288 boards are supported: +At present seven RK3288 boards are supported:
- Firefly RK3288 - use firefly-rk3288 configuration - Radxa Rock 2 - use rock2 configuration@@ -44,6 +44,7 @@ At present six RK3288 boards are supported: - EVB RK3288 - use evb-rk3288 configuration - Fennec RK3288 - use fennec-rk3288 configuration - PopMetal RK3288 - use popmetal-rk3288 configuration
- Miniarm RK3288 - use miniarm-rk3288 configuration
Can you sort all of these?
Two RK3036 board are supported:
diff --git a/include/configs/miniarm_rk3288.h b/include/configs/miniarm_rk3288.h new file mode 100644 index 0000000..342557f --- /dev/null +++ b/include/configs/miniarm_rk3288.h @@ -0,0 +1,26 @@ +/*
- (C) Copyright 2016 Rockchip Electronics Co., Ltd
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+#define ROCKCHIP_DEVICE_SETTINGS +#include <configs/rk3288_common.h>
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +/* SPL @ 32k for ~36k
- ENV @ 96k
- u-boot @ 128K
- */
+#define CONFIG_ENV_OFFSET (96 * 1024)
+#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10
+#endif
1.9.1
Regards, Simon
Hi Simon,
On 2016年08月01日 07:28, Simon Glass wrote:
Hi Ziyuan,
On 27 July 2016 at 21:43, Ziyuan Xu xzy.xu@rock-chips.com wrote:
Miniarm is a rockchip rk3288 based development board, which has lots of interface such as HDMI, USB, micro-SD card, Audio etc.
Signed-off-by: Ziyuan Xu xzy.xu@rock-chips.com
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3288-miniarm.dts | 61 +++ arch/arm/dts/rk3288-miniarm.dtsi | 533 +++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 10 + board/rockchip/miniarm_rk3288/Kconfig | 15 + board/rockchip/miniarm_rk3288/MAINTAINERS | 6 + board/rockchip/miniarm_rk3288/Makefile | 7 + board/rockchip/miniarm_rk3288/miniarm-rk3288.c | 15 + configs/miniarm-rk3288_defconfig | 65 +++ doc/README.rockchip | 3 +- include/configs/miniarm_rk3288.h | 26 ++ 11 files changed, 741 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3288-miniarm.dts create mode 100644 arch/arm/dts/rk3288-miniarm.dtsi create mode 100644 board/rockchip/miniarm_rk3288/Kconfig create mode 100644 board/rockchip/miniarm_rk3288/MAINTAINERS create mode 100644 board/rockchip/miniarm_rk3288/Makefile create mode 100644 board/rockchip/miniarm_rk3288/miniarm-rk3288.c create mode 100644 configs/miniarm-rk3288_defconfig create mode 100644 include/configs/miniarm_rk3288.h
Acked-by: Simon Glass sjg@chromium.org
But please can you keep things in alpha order? See below.
Okay, I will send v2 patch later, also keep your ASK tag.
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 639c06d..50ddb39 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-evb.dtb \ rk3288-fennec.dtb \ rk3288-popmetal.dtb \
rk3288-miniarm.dtb \move up one line
rk3036-sdk.dtb \ rk3399-evb.dtbdtb-$(CONFIG_ARCH_MESON) += \ diff --git a/arch/arm/dts/rk3288-miniarm.dts b/arch/arm/dts/rk3288-miniarm.dts new file mode 100644 index 0000000..c741082 --- /dev/null +++ b/arch/arm/dts/rk3288-miniarm.dts @@ -0,0 +1,61 @@ +/*
- (C) Copyright 2016 Rockchip Electronics Co., Ltd
- SPDX-License-Identifier: GPL-2.0+ X11
- */
+/dts-v1/; +#include "rk3288-miniarm.dtsi"
+/ {
model = "Miniarm-RK3288";compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";chosen {stdout-path = &uart2;};+};
+&dmc {
rockchip,num-channels = <2>;rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x70x5 0xa 0x5 0x200 0x5 0x10 0x40 0x00x1 0x7 0x7 0x4 0xc 0x43 0x100 0x00x5 0x0>;rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c2000xa60 0x40 0x10 0x0>;/* Add a dummy value to cause of-platdata think this is bytes */rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;+};
+&pinctrl {
u-boot,dm-pre-reloc;+};
+&pwm1 {
status = "okay";+};
+&uart2 {
u-boot,dm-pre-reloc;reg-shift = <2>;+};
+&sdmmc {
u-boot,dm-pre-reloc;+};
+&emmc {
u-boot,dm-pre-reloc;+};
+&gpio3 {
u-boot,dm-pre-reloc;+};
+&gpio8 {
u-boot,dm-pre-reloc;+}; diff --git a/arch/arm/dts/rk3288-miniarm.dtsi b/arch/arm/dts/rk3288-miniarm.dtsi new file mode 100644 index 0000000..b889875 --- /dev/null +++ b/arch/arm/dts/rk3288-miniarm.dtsi @@ -0,0 +1,533 @@ +/*
- This file is dual-licensed: you can use it either under the terms
- of the GPL or the X11 license, at your option. Note that this dual
- licensing only applies to this file, and not this project as a
- whole.
- a) This file is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 2 of the
License, or (at your option) any later version.
This file is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
- Or, alternatively,
- b) Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without
restriction, including without limitation the rights to use,
copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following
conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.- */
+#include "rk3288.dtsi"
+/ {
memory {device_type = "memory";reg = <0x0 0x80000000>;};ext_gmac: external-gmac-clock {compatible = "fixed-clock";clock-frequency = <125000000>;clock-output-names = "ext_gmac";#clock-cells = <0>;};gpio-keys {compatible = "gpio-keys";#address-cells = <1>;#size-cells = <0>;autorepeat;pinctrl-names = "default";pinctrl-0 = <&pwrbtn>;button@0 {gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;label = "GPIO Key Power";linux,input-type = <1>;gpio-key,wakeup = <1>;debounce-interval = <100>;};};gpio-leds {compatible = "gpio-leds";pwr-led {gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;linux,default-trigger = "default-on";};act-led {gpios=<&gpio2 3 GPIO_ACTIVE_LOW>;linux,default-trigger="mmc0";};};vcc_sys: vsys-regulator {compatible = "regulator-fixed";regulator-name = "vcc_sys";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-always-on;regulator-boot-on;};/** NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from* vcc_io directly. Those boards won't be able to power cycle SD cards* but it shouldn't hurt to toggle this pin there anyway.*/vcc_sd: sdmmc-regulator {compatible = "regulator-fixed";gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;pinctrl-names = "default";pinctrl-0 = <&sdmmc_pwr>;regulator-name = "vcc_sd";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;startup-delay-us = <100000>;vin-supply = <&vcc_io>;};+};
+&cpu0 {
cpu0-supply = <&vdd_cpu>;+};
+&emmc {
broken-cd;bus-width = <8>;cap-mmc-highspeed;disable-wp;non-removable;num-slots = <1>;pinctrl-names = "default";pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;status = "okay";+};
+&sdmmc {
bus-width = <4>;cap-mmc-highspeed;cap-sd-highspeed;card-detect-delay = <200>;disable-wp; /* wp not hooked up */num-slots = <1>;pinctrl-names = "default";pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;status = "okay";supports-sd;vmmc-supply = <&vcc_sd>;vqmmc-supply = <&vccio_sd>;+};
+&gpu {
mali-supply = <&vdd_gpu>;status = "okay";+};
+&gmac {
phy-supply = <&vcc33_lan>;phy-mode = "rgmii";clock_in_out = "input";snps,reset-gpio = <&gpio4 7 0>;snps,reset-active-low;snps,reset-delays-us = <0 10000 1000000>;assigned-clocks = <&cru SCLK_MAC>;assigned-clock-parents = <&ext_gmac>;pinctrl-names = "default";pinctrl-0 = <&rgmii_pins>;tx_delay = <0x30>;rx_delay = <0x10>;status = "ok";+};
+&hdmi {
ddc-i2c-bus = <&i2c5>;status = "okay";+};
+&i2c0 {
status = "okay";clock-frequency = <400000>;rk808: pmic@1b {compatible = "rockchip,rk808";reg = <0x1b>;interrupt-parent = <&gpio0>;interrupts = <4 IRQ_TYPE_LEVEL_LOW>;pinctrl-names = "default";pinctrl-0 = <&pmic_int &global_pwroff>;rockchip,system-power-controller;wakeup-source;#clock-cells = <1>;clock-output-names = "xin32k", "rk808-clkout2";vcc1-supply = <&vcc_sys>;vcc2-supply = <&vcc_sys>;vcc3-supply = <&vcc_sys>;vcc4-supply = <&vcc_sys>;vcc6-supply = <&vcc_sys>;vcc7-supply = <&vcc_sys>;vcc8-supply = <&vcc_18>;vcc9-supply = <&vcc_io>;vcc10-supply = <&vcc_io>;vcc11-supply = <&vcc_sys>;vcc12-supply = <&vcc_io>;vddio-supply = <&vcc18_ldo1>;regulators {vdd_cpu: DCDC_REG1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <1350000>;regulator-name = "vdd_arm";regulator-state-mem {regulator-off-in-suspend;};};vdd_gpu: DCDC_REG2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <1250000>;regulator-name = "vdd_gpu";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1000000>;};};vcc_ddr: DCDC_REG3 {regulator-always-on;regulator-boot-on;regulator-name = "vcc_ddr";regulator-state-mem {regulator-on-in-suspend;};};vcc_io: DCDC_REG4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc_io";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vcc18_ldo1: LDO_REG1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc18_ldo1";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc33_mipi: LDO_REG2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc33_mipi";regulator-state-mem {regulator-off-in-suspend;};};vdd_10: LDO_REG3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1000000>;regulator-max-microvolt = <1000000>;regulator-name = "vdd_10";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1000000>;};};vcc18_codec: LDO_REG4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc18_codec";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vccio_sd: LDO_REG5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-name = "vccio_sd";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vdd10_lcd: LDO_REG6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1000000>;regulator-max-microvolt = <1000000>;regulator-name = "vdd10_lcd";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1000000>;};};vcc_18: LDO_REG7 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc_18";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc18_lcd: LDO_REG8 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc18_lcd";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc33_sd: SWITCH_REG1 {regulator-always-on;regulator-boot-on;regulator-name = "vcc33_sd";regulator-state-mem {regulator-on-in-suspend;};};vcc33_lan: SWITCH_REG2 {regulator-always-on;regulator-boot-on;regulator-name = "vcc33_lan";regulator-state-mem {regulator-on-in-suspend;};};};};+};
+&i2c2 {
status = "okay";headset: nau8825@1a {compatible = "nuvoton,nau8825";#sound-dai-cells = <0>;reg = <0x1a>;interrupt-parent = <&gpio6>;interrupts = <5 IRQ_TYPE_LEVEL_LOW>;nuvoton,jkdet-enable = <1>;nuvoton,jkdet-pull-enable = <1>;nuvoton,jkdet-pull-up = <0>;nuvoton,jkdet-polarity = <1>;nuvoton,vref-impedance = <2>;nuvoton,micbias-voltage = <6>;nuvoton,sar-threshold-num = <4>;nuvoton,sar-threshold = <0xa 0x14 0x26 0x73>;nuvoton,sar-hysteresis = <0>;nuvoton,sar-voltage = <6>;nuvoton,sar-compare-time = <0>;nuvoton,sar-sampling-time = <0>;nuvoton,short-key-debounce = <3>;nuvoton,jack-insert-debounce = <7>;nuvoton,jack-eject-debounce = <7>;clock-names = "mclk";clocks = <&cru SCLK_I2S0_OUT>;};+};
+&i2c5 {
status = "okay";+};
+&wdt {
status = "okay";+};
+&pwm0 {
status = "okay";+};
+&saradc {
vref-supply = <&vcc18_ldo1>;status ="okay";+};
+&uart0 {
status = "okay";+};
+&uart1 {
status = "okay";+};
+&uart2 {
status = "okay";+};
+&uart3 {
status = "okay";+};
+&uart4 {
status = "okay";+};
+&tsadc {
rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */status = "okay";+};
+&usbphy {
status = "okay";+};
+&usb_host0_ehci {
status = "okay";+};
+&usb_host1 {
status = "okay";+};
+&usb_otg {
status= "okay";+};
+&vopb {
status = "okay";+};
+&vopb_mmu {
status = "okay";+};
+&vopl {
status = "okay";+};
+&vopl_mmu {
status = "okay";+};
+&pinctrl {
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {drive-strength = <8>;};pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {bias-pull-up;drive-strength = <8>;};backlight {bl_en: bl-en {rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;};};buttons {pwrbtn: pwrbtn {rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;};};eth_phy {eth_phy_pwr: eth-phy-pwr {rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;};};pmic {pmic_int: pmic-int {rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;};};sdmmc {/** Default drive strength isn't enough to achieve even* high-speed mode on EVB board so bump up to 8ma.*/sdmmc_bus4: sdmmc-bus4 {rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,<6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,<6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,<6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;};sdmmc_clk: sdmmc-clk {rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;};sdmmc_cmd: sdmmc-cmd {rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;};sdmmc_pwr: sdmmc-pwr {rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;};};usb {host_vbus_drv: host-vbus-drv {rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;};pwr_3g: pwr-3g {rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;};};+}; diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 8ec1920..aaa13b5 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -33,6 +33,14 @@ config TARGET_POPMETAL_RK3288 2GB DDR3. Expansion connectors provide access to I2C, SPI, UART, GPIOs and display interface.
+config TARGET_MINIARM_RK3288
bool "miniarm-RK3288"helpMiniarm is a RK3288-based development board with 2 USB ports, HDMI,micro-SD card, audio, Gigabit Ethernet. It also includes on-board8GB eMMC and 2GB of SDRAM. Expansion connectors provide access toI2C, SPI, UART, GPIOs.- config TARGET_CHROMEBOOK_JERRY bool "Google/Rockchip Veyron-Jerry Chromebook" help
@@ -76,4 +84,6 @@ source "board/rockchip/fennec_rk3288/Kconfig"
source "board/chipspark/popmetal_rk3288/Kconfig"
+source "board/rockchip/miniarm_rk3288/Kconfig"
Move up to maintain alpha order
- endif
diff --git a/board/rockchip/miniarm_rk3288/Kconfig b/board/rockchip/miniarm_rk3288/Kconfig new file mode 100644 index 0000000..529c09f --- /dev/null +++ b/board/rockchip/miniarm_rk3288/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MINIARM_RK3288
+config SYS_BOARD
default "miniarm_rk3288"+config SYS_VENDOR
default "rockchip"+config SYS_CONFIG_NAME
default "miniarm_rk3288"+config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y+endif diff --git a/board/rockchip/miniarm_rk3288/MAINTAINERS b/board/rockchip/miniarm_rk3288/MAINTAINERS new file mode 100644 index 0000000..7537b8f --- /dev/null +++ b/board/rockchip/miniarm_rk3288/MAINTAINERS @@ -0,0 +1,6 @@ +MINIARM-RK3288 +M: Lin Huang hl@rock-chips.com +S: Maintained +F: board/rockchip/miniarm_rk3288 +F: include/configs/miniarm_rk3288.h +F: configs/miniarm-rk3288_defconfig diff --git a/board/rockchip/miniarm_rk3288/Makefile b/board/rockchip/miniarm_rk3288/Makefile new file mode 100644 index 0000000..9419b91 --- /dev/null +++ b/board/rockchip/miniarm_rk3288/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += miniarm-rk3288.o diff --git a/board/rockchip/miniarm_rk3288/miniarm-rk3288.c b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c new file mode 100644 index 0000000..aad74ef --- /dev/null +++ b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c @@ -0,0 +1,15 @@ +/*
- (C) Copyright 2016 Rockchip Electronics Co., Ltd
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <spl.h>
+void board_boot_order(u32 *spl_boot_list) +{
/* eMMC prior to sdcard */spl_boot_list[0] = BOOT_DEVICE_MMC2;spl_boot_list[1] = BOOT_DEVICE_MMC1;+} diff --git a/configs/miniarm-rk3288_defconfig b/configs/miniarm-rk3288_defconfig new file mode 100644 index 0000000..33a4a56 --- /dev/null +++ b/configs/miniarm-rk3288_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3288=y +CONFIG_TARGET_MINIARM_RK3288=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3288-miniarm" +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_SYSRESET=y +CONFIG_DM_MMC=y +CONFIG_ROCKCHIP_DWMMC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_ROCKCHIP_RK3288_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK808=y +CONFIG_DM_REGULATOR=y +CONFIG_REGULATOR_RK808=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/doc/README.rockchip b/doc/README.rockchip index 1b3a602..b69a526 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -36,7 +36,7 @@ You will need: Building ========
-At present six RK3288 boards are supported: +At present seven RK3288 boards are supported:
- Firefly RK3288 - use firefly-rk3288 configuration - Radxa Rock 2 - use rock2 configuration@@ -44,6 +44,7 @@ At present six RK3288 boards are supported: - EVB RK3288 - use evb-rk3288 configuration - Fennec RK3288 - use fennec-rk3288 configuration - PopMetal RK3288 - use popmetal-rk3288 configuration
- Miniarm RK3288 - use miniarm-rk3288 configuration
Can you sort all of these?
Two RK3036 board are supported:
diff --git a/include/configs/miniarm_rk3288.h b/include/configs/miniarm_rk3288.h new file mode 100644 index 0000000..342557f --- /dev/null +++ b/include/configs/miniarm_rk3288.h @@ -0,0 +1,26 @@ +/*
- (C) Copyright 2016 Rockchip Electronics Co., Ltd
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+#define ROCKCHIP_DEVICE_SETTINGS +#include <configs/rk3288_common.h>
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +/* SPL @ 32k for ~36k
- ENV @ 96k
- u-boot @ 128K
- */
+#define CONFIG_ENV_OFFSET (96 * 1024)
+#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10
+#endif
1.9.1
Regards, Simon
participants (2)
-
Simon Glass -
Ziyuan Xu