[U-Boot] [PATCH v2 00/20] ARC: cache subsystem improvement/refactoring
This iv v2 version of "ARC: cache subsystem improvement/refactoring" patch series. You can find v1 patch series here: http://patchwork.ozlabs.org/cover/873039/
Eugeniy Paltsev (20): ARC: cache: move i$ entire operation to separate function ARC: cache: remove per-line I$ operations as unused ARC: cache: Add support of FLUSH_N_INV d$ operations ARC: introduce is_isa_X functions ARC: flush & invalidate D$ with a single command ARC: cache: move IOC initialization to separate function ARC: move BCR encodings to separate header file ARC: cache: allways check dcache status before entire/line operations ARC: cache: Use is_isa_arcv2() instead of CONFIG_ISA_ARCV2 ifdef ARC: cache: move slc status check into slc_entire_op and slc_rgn_op ARC: cache: get rid of [slc,pae,icache,dcache]_exists global variables ARC: move cache global variables to global data struct ARC: cache: move pae exists check into slc_upper_region_init ARC: move IOC enabling to compile time options ARC: cache: implement [i,d]cache_enabled as separate functions ARC: cache: fix SLC operations when SLC is bypassed for data ARC: implement function to sync and cleanup caches ARC: cache: add additional configuration checks ARC: cache: add missing cache cleanup before cache disable ARC: cache: refactor arc_ioc_setup function
arch/arc/Kconfig | 18 + arch/arc/include/asm/arc-bcr.h | 77 +++++ arch/arc/include/asm/arcregs.h | 11 + arch/arc/include/asm/cache.h | 7 + arch/arc/include/asm/global_data.h | 6 + arch/arc/lib/bootm.c | 4 +- arch/arc/lib/cache.c | 677 ++++++++++++++++++++++++------------- arch/arc/lib/init_helpers.c | 6 +- 8 files changed, 562 insertions(+), 244 deletions(-) create mode 100644 arch/arc/include/asm/arc-bcr.h
Move icache entire operation to separate function as we are planing to use it in another places (like sync_icache_dcache_all)
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/lib/cache.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 04f1d9d59b..26f0a1ff9b 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -315,20 +315,27 @@ void icache_disable(void) IC_CTRL_CACHE_DISABLE); }
-void invalidate_icache_all(void) +/* IC supports only invalidation */ +static inline void __ic_entire_invalidate(void) { + if (!icache_status()) + return; + /* Any write to IC_IVIC register triggers invalidation of entire I$ */ - if (icache_status()) { - write_aux_reg(ARC_AUX_IC_IVIC, 1); - /* - * As per ARC HS databook (see chapter 5.3.3.2) - * it is required to add 3 NOPs after each write to IC_IVIC. - */ - __builtin_arc_nop(); - __builtin_arc_nop(); - __builtin_arc_nop(); - read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ - } + write_aux_reg(ARC_AUX_IC_IVIC, 1); + /* + * As per ARC HS databook (see chapter 5.3.3.2) + * it is required to add 3 NOPs after each write to IC_IVIC. + */ + __builtin_arc_nop(); + __builtin_arc_nop(); + __builtin_arc_nop(); + read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ +} + +void invalidate_icache_all(void) +{ + __ic_entire_invalidate();
#ifdef CONFIG_ISA_ARCV2 if (slc_exists)
__cache_line_loop function was copied from linux kernel code where per line instruction cache operations are used. In uboot we use only entire instruction cache operations, so we can drop support of per line instruction cache operations from __cache_line_loop function as __cache_line_loop is never called with OP_INV_IC parameter.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/lib/cache.c | 30 +++++++----------------------- 1 file changed, 7 insertions(+), 23 deletions(-)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 26f0a1ff9b..2252542f16 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -23,7 +23,6 @@
#define OP_INV 0x1 #define OP_FLUSH 0x2 -#define OP_INV_IC 0x3
/* Bit val in SLC_CONTROL */ #define SLC_CTRL_DIS 0x001 @@ -373,30 +372,15 @@ void dcache_disable(void) }
#ifndef CONFIG_SYS_DCACHE_OFF -/* - * Common Helper for Line Operations on {I,D}-Cache - */ -static inline void __cache_line_loop(unsigned long paddr, unsigned long sz, - const int cacheop) +/* Common Helper for Line Operations on D-cache */ +static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, + const int cacheop) { unsigned int aux_cmd; -#if (CONFIG_ARC_MMU_VER == 3) - unsigned int aux_tag; -#endif int num_lines;
- if (cacheop == OP_INV_IC) { - aux_cmd = ARC_AUX_IC_IVIL; -#if (CONFIG_ARC_MMU_VER == 3) - aux_tag = ARC_AUX_IC_PTAG; -#endif - } else { - /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ - aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL; -#if (CONFIG_ARC_MMU_VER == 3) - aux_tag = ARC_AUX_DC_PTAG; -#endif - } + /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ + aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
sz += paddr & ~CACHE_LINE_MASK; paddr &= CACHE_LINE_MASK; @@ -405,7 +389,7 @@ static inline void __cache_line_loop(unsigned long paddr, unsigned long sz,
while (num_lines-- > 0) { #if (CONFIG_ARC_MMU_VER == 3) - write_aux_reg(aux_tag, paddr); + write_aux_reg(ARC_AUX_DC_PTAG, paddr); #endif write_aux_reg(aux_cmd, paddr); paddr += l1_line_sz; @@ -458,7 +442,7 @@ static inline void __dc_line_op(unsigned long paddr, unsigned long sz, { unsigned int ctrl_reg = __before_dc_op(cacheop);
- __cache_line_loop(paddr, sz, cacheop); + __dcache_line_loop(paddr, sz, cacheop); __after_dc_op(cacheop, ctrl_reg); } #else
As of today __dc_line_op and __dc_entire_op support only flush (OP_FLUSH) and invalidate (OP_INV) operations. Add support of flush and invalidate (OP_FLUSH_N_INV) operation which we planing to use in next patches.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/lib/cache.c | 42 +++++++++++++++++++----------------------- 1 file changed, 19 insertions(+), 23 deletions(-)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 2252542f16..83b77b9716 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -21,8 +21,9 @@ #define DC_CTRL_FLUSH_STATUS BIT(8) #define CACHE_VER_NUM_MASK 0xF
-#define OP_INV 0x1 -#define OP_FLUSH 0x2 +#define OP_INV BIT(0) +#define OP_FLUSH BIT(1) +#define OP_FLUSH_N_INV (OP_FLUSH | OP_INV)
/* Bit val in SLC_CONTROL */ #define SLC_CTRL_DIS 0x001 @@ -396,36 +397,32 @@ static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, } }
-static unsigned int __before_dc_op(const int op) +static void __before_dc_op(const int op) { - unsigned int reg; + unsigned int ctrl;
- if (op == OP_INV) { - /* - * IM is set by default and implies Flush-n-inv - * Clear it here for vanilla inv - */ - reg = read_aux_reg(ARC_AUX_DC_CTRL); - write_aux_reg(ARC_AUX_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH); - } + ctrl = read_aux_reg(ARC_AUX_DC_CTRL);
- return reg; + /* IM bit implies flush-n-inv, instead of vanilla inv */ + if (op == OP_INV) + ctrl &= ~DC_CTRL_INV_MODE_FLUSH; + else + ctrl |= DC_CTRL_INV_MODE_FLUSH; + + write_aux_reg(ARC_AUX_DC_CTRL, ctrl); }
-static void __after_dc_op(const int op, unsigned int reg) +static void __after_dc_op(const int op) { if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); - - /* Switch back to default Invalidate mode */ - if (op == OP_INV) - write_aux_reg(ARC_AUX_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH); }
static inline void __dc_entire_op(const int cacheop) { int aux; - unsigned int ctrl_reg = __before_dc_op(cacheop); + + __before_dc_op(cacheop);
if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ aux = ARC_AUX_DC_IVDC; @@ -434,16 +431,15 @@ static inline void __dc_entire_op(const int cacheop)
write_aux_reg(aux, 0x1);
- __after_dc_op(cacheop, ctrl_reg); + __after_dc_op(cacheop); }
static inline void __dc_line_op(unsigned long paddr, unsigned long sz, const int cacheop) { - unsigned int ctrl_reg = __before_dc_op(cacheop); - + __before_dc_op(cacheop); __dcache_line_loop(paddr, sz, cacheop); - __after_dc_op(cacheop, ctrl_reg); + __after_dc_op(cacheop); } #else #define __dc_entire_op(cacheop)
Introduce is_isa_arcv2 and is_isa_arcompact functions. As this functions only check configuration options and return compile-time constant they can be used instead of #ifdef's to to write clear code.
So we can write -------------->8--------------- if (is_isa_arcv2()) ioc_configure(); -------------->8--------------- instead of -------------->8--------------- ifdef CONFIG_ISA_ARCV2 ioc_configure(); endif -------------->8---------------
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/include/asm/arcregs.h | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 67f416305d..3a513149f5 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -8,6 +8,7 @@ #define _ASM_ARC_ARCREGS_H
#include <asm/cache.h> +#include <config.h>
/* * ARC architecture has additional address space - auxiliary registers. @@ -88,6 +89,16 @@
/* ARCNUM [15:8] - field to identify each core in a multi-core system */ #define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8) + +static const inline int is_isa_arcv2(void) +{ + return IS_ENABLED(CONFIG_ISA_ARCV2); +} + +static const inline int is_isa_arcompact(void) +{ + return IS_ENABLED(CONFIG_ISA_ARCOMPACT); +} #endif /* __ASSEMBLY__ */
#endif /* _ASM_ARC_ARCREGS_H */
We don't implement separate flush_dcache_all intentionally as entire data cache invalidation is dangerous operation even if we flush data cache right before invalidation.
There is the real example: We may hang in the next code if we store any context (like BLINK register) on stack in invalidate_dcache_all() function. BLINK register is the register where return address is automatically saved when we do function call with instructions like 'bl'.
void flush_dcache_all() { __dc_entire_op(OP_FLUSH); // Other code // }
void invalidate_dcache_all() { __dc_entire_op(OP_INV); // Other code // }
void foo(void) { flush_dcache_all(); invalidate_dcache_all(); }
Now let's see what really happens during that code execution:
foo() |->> call flush_dcache_all [return address is saved to BLINK register] [push BLINK] (save to stack) ![point 1] |->> call __dc_entire_op(OP_FLUSH) [return address is saved to BLINK register] [flush L1 D$] return [jump to BLINK] <<------ [other flush_dcache_all code] [pop BLINK] (get from stack) return [jump to BLINK] <<------ |->> call invalidate_dcache_all [return address is saved to BLINK register] [push BLINK] (save to stack) ![point 2] |->> call __dc_entire_op(OP_FLUSH) [return address is saved to BLINK register] [invalidate L1 D$] ![point 3] // Oops!!! // We lose return address from invalidate_dcache_all function: // we save it to stack and invalidate L1 D$ after that! return [jump to BLINK] <<------ [other invalidate_dcache_all code] [pop BLINK] (get from stack) // we don't have this data in L1 dcache as we invalidated it in [point 3] // so we get it from next memory level (for example DDR memory) // but in the memory we have value which we save in [point 1], which // is return address from flush_dcache_all function (instead of // address from current invalidate_dcache_all function which we // saved in [point 2] !) return [jump to BLINK] <<------ // As BLINK points to invalidate_dcache_all, we call it again and // loop forever.
Fortunately we may do flush and invalidation of D$ with a single one instruction which automatically mitigates a situation described above.
And because invalidate_dcache_all isn't used in common u-boot code we implement "flush and invalidate dcache all" instead.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/include/asm/cache.h | 1 + arch/arc/lib/cache.c | 89 +++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 85 insertions(+), 5 deletions(-)
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index d26d9fb18d..382c4126c3 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -30,6 +30,7 @@ #ifndef __ASSEMBLY__
void cache_init(void); +void flush_n_invalidate_dcache_all(void);
#endif /* __ASSEMBLY__ */
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 83b77b9716..42207b201c 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -12,6 +12,80 @@ #include <asm/arcregs.h> #include <asm/cache.h>
+/* + * [ NOTE 1 ]: + * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable + * operation may result in unexpected behavior and data loss even if we flush + * data cache right before invalidation. That may happens if we store any context + * on stack (like we store BLINK register on stack before function call). + * BLINK register is the register where return address is automatically saved + * when we do function call with instructions like 'bl'. + * + * There is the real example: + * We may hang in the next code as we store any BLINK register on stack in + * invalidate_dcache_all() function. + * + * void flush_dcache_all() { + * __dc_entire_op(OP_FLUSH); + * // Other code // + * } + * + * void invalidate_dcache_all() { + * __dc_entire_op(OP_INV); + * // Other code // + * } + * + * void foo(void) { + * flush_dcache_all(); + * invalidate_dcache_all(); + * } + * + * Now let's see what really happens during that code execution: + * + * foo() + * |->> call flush_dcache_all + * [return address is saved to BLINK register] + * [push BLINK] (save to stack) ![point 1] + * |->> call __dc_entire_op(OP_FLUSH) + * [return address is saved to BLINK register] + * [flush L1 D$] + * return [jump to BLINK] + * <<------ + * [other flush_dcache_all code] + * [pop BLINK] (get from stack) + * return [jump to BLINK] + * <<------ + * |->> call invalidate_dcache_all + * [return address is saved to BLINK register] + * [push BLINK] (save to stack) ![point 2] + * |->> call __dc_entire_op(OP_FLUSH) + * [return address is saved to BLINK register] + * [invalidate L1 D$] ![point 3] + * // Oops!!! + * // We lose return address from invalidate_dcache_all function: + * // we save it to stack and invalidate L1 D$ after that! + * return [jump to BLINK] + * <<------ + * [other invalidate_dcache_all code] + * [pop BLINK] (get from stack) + * // we don't have this data in L1 dcache as we invalidated it in [point 3] + * // so we get it from next memory level (for example DDR memory) + * // but in the memory we have value which we save in [point 1], which + * // is return address from flush_dcache_all function (instead of + * // address from current invalidate_dcache_all function which we + * // saved in [point 2] !) + * return [jump to BLINK] + * <<------ + * // As BLINK points to invalidate_dcache_all, we call it again and + * // loop forever. + * + * Fortunately we may fix that by using flush & invalidation of D$ with a single + * one instruction (instead of flush and invalidation instructions pair) and + * enabling force function inline with '__attribute__((always_inline))' gcc + * attribute to avoid any function call (and BLINK store) between cache flush + * and disable. + */ + /* Bit values in IC_CTRL */ #define IC_CTRL_CACHE_DISABLE BIT(0)
@@ -256,8 +330,7 @@ void cache_init(void) /* IOC Aperture size is equal to DDR size */ long ap_size = CONFIG_SYS_SDRAM_SIZE;
- flush_dcache_all(); - invalidate_dcache_all(); + flush_n_invalidate_dcache_all();
if (!is_power_of_2(ap_size) || ap_size < 4096) panic("IOC Aperture size must be power of 2 and bigger 4Kib"); @@ -483,13 +556,19 @@ void flush_cache(unsigned long start, unsigned long size) flush_dcache_range(start, start + size); }
-void invalidate_dcache_all(void) +/* + * As invalidate_dcache_all() is not used in generic U-Boot code and as we + * don't need it in arch/arc code alone (invalidate without flush) we implement + * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because + * it's much safer. See [ NOTE 1 ] for more details. + */ +void flush_n_invalidate_dcache_all(void) { - __dc_entire_op(OP_INV); + __dc_entire_op(OP_FLUSH_N_INV);
#ifdef CONFIG_ISA_ARCV2 if (slc_exists) - __slc_entire_op(OP_INV); + __slc_entire_op(OP_FLUSH_N_INV); #endif }
Move IOC initialization to separate function from cache_init function. This is the preparation for the next patch when we will switch to is_isa_arcv2() function using instead of "CONFIG_ISA_ARCV2" ifdef using.
Also it makes cache_init function clear.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/lib/cache.c | 56 ++++++++++++++++++++++++++++------------------------ 1 file changed, 30 insertions(+), 26 deletions(-)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 42207b201c..af07a11724 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -231,6 +231,34 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); } + +static void arc_ioc_setup(void) +{ + /* IOC Aperture start is equal to DDR start */ + unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; + /* IOC Aperture size is equal to DDR size */ + long ap_size = CONFIG_SYS_SDRAM_SIZE; + + flush_n_invalidate_dcache_all(); + + if (!is_power_of_2(ap_size) || ap_size < 4096) + panic("IOC Aperture size must be power of 2 and bigger 4Kib"); + + /* + * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, + * so setting 0x11 implies 512M, 0x12 implies 1G... + */ + write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, + order_base_2(ap_size / 1024) - 2); + + /* IOC Aperture start must be aligned to the size of the aperture */ + if (ap_base % ap_size != 0) + panic("IOC Aperture start must be aligned to the size of the aperture"); + + write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); + write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); + write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); +} #endif /* CONFIG_ISA_ARCV2 */
#ifdef CONFIG_ISA_ARCV2 @@ -324,32 +352,8 @@ void cache_init(void) #ifdef CONFIG_ISA_ARCV2 read_decode_cache_bcr_arcv2();
- if (ioc_exists) { - /* IOC Aperture start is equal to DDR start */ - unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; - /* IOC Aperture size is equal to DDR size */ - long ap_size = CONFIG_SYS_SDRAM_SIZE; - - flush_n_invalidate_dcache_all(); - - if (!is_power_of_2(ap_size) || ap_size < 4096) - panic("IOC Aperture size must be power of 2 and bigger 4Kib"); - - /* - * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, - * so setting 0x11 implies 512M, 0x12 implies 1G... - */ - write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, - order_base_2(ap_size / 1024) - 2); - - /* IOC Aperture start must be aligned to the size of the aperture */ - if (ap_base % ap_size != 0) - panic("IOC Aperture start must be aligned to the size of the aperture"); - - write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); - write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); - write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); - } + if (ioc_exists) + arc_ioc_setup();
read_decode_mmu_bcr();
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/include/asm/arc-bcr.h | 77 ++++++++++++++++++++++++++++++++++++++++++ arch/arc/lib/cache.c | 67 +++++------------------------------- 2 files changed, 85 insertions(+), 59 deletions(-) create mode 100644 arch/arc/include/asm/arc-bcr.h
diff --git a/arch/arc/include/asm/arc-bcr.h b/arch/arc/include/asm/arc-bcr.h new file mode 100644 index 0000000000..823906d946 --- /dev/null +++ b/arch/arc/include/asm/arc-bcr.h @@ -0,0 +1,77 @@ +/* + * ARC Build Configuration Registers, with encoded hardware config + * + * Copyright (C) 2018 Synopsys + * Author: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARC_BCR_H +#define __ARC_BCR_H +#ifndef __ASSEMBLY__ + +#include <config.h> + +union bcr_di_cache { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; +#else + unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; +#endif + } fields; + unsigned int word; +}; + +union bcr_slc_cfg { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:24, way:2, lsz:2, sz:4; +#else + unsigned int sz:4, lsz:2, way:2, pad:24; +#endif + } fields; + unsigned int word; +}; + +union bcr_generic { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:24, ver:8; +#else + unsigned int ver:8, pad:24; +#endif + } fields; + unsigned int word; +}; + +union bcr_clust_cfg { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8; +#else + unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7; +#endif + } fields; + unsigned int word; +}; + +union bcr_mmu_4 { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1, + n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3; +#else + /* DTLB ITLB JES JE JA */ + unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2, + pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8; +#endif + } fields; + unsigned int word; +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ARC_BCR_H */ diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index af07a11724..e6e439aab8 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -10,6 +10,7 @@ #include <linux/kernel.h> #include <linux/log2.h> #include <asm/arcregs.h> +#include <asm/arc-bcr.h> #include <asm/cache.h>
/* @@ -129,24 +130,11 @@ void read_decode_mmu_bcr(void) { /* TODO: should we compare mmu version from BCR and from CONFIG? */ #if (CONFIG_ARC_MMU_VER >= 4) - u32 tmp; + union bcr_mmu_4 mmu4;
- tmp = read_aux_reg(ARC_AUX_MMU_BCR); + mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR);
- struct bcr_mmu_4 { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1, - n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3; -#else - /* DTLB ITLB JES JE JA */ - unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2, - pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8; -#endif /* CONFIG_CPU_BIG_ENDIAN */ - } *mmu4; - - mmu4 = (struct bcr_mmu_4 *)&tmp; - - pae_exists = !!mmu4->pae; + pae_exists = !!mmu4.fields.pae; #endif /* (CONFIG_ARC_MMU_VER >= 4) */ }
@@ -264,27 +252,9 @@ static void arc_ioc_setup(void) #ifdef CONFIG_ISA_ARCV2 static void read_decode_cache_bcr_arcv2(void) { - union { - struct { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad:24, way:2, lsz:2, sz:4; -#else - unsigned int sz:4, lsz:2, way:2, pad:24; -#endif - } fields; - unsigned int word; - } slc_cfg; - - union { - struct { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad:24, ver:8; -#else - unsigned int ver:8, pad:24; -#endif - } fields; - unsigned int word; - } sbcr; + union bcr_slc_cfg slc_cfg; + union bcr_clust_cfg cbcr; + union bcr_generic sbcr;
sbcr.word = read_aux_reg(ARC_BCR_SLC); if (sbcr.fields.ver) { @@ -293,17 +263,6 @@ static void read_decode_cache_bcr_arcv2(void) slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; }
- union { - struct bcr_clust_cfg { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8; -#else - unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7; -#endif - } fields; - unsigned int word; - } cbcr; - cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); if (cbcr.fields.c && ioc_enable) ioc_exists = true; @@ -313,17 +272,7 @@ static void read_decode_cache_bcr_arcv2(void) void read_decode_cache_bcr(void) { int dc_line_sz = 0, ic_line_sz = 0; - - union { - struct { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; -#else - unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; -#endif - } fields; - unsigned int word; - } ibcr, dbcr; + union bcr_di_cache ibcr, dbcr;
ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); if (ibcr.fields.ver) {
As we are planning to get rid of dozens of ifdef's in cache.c we would better check dcache status before each entire/line operation then check CONFIG_SYS_DCACHE_OFF config option.
This makes the code clear. Another advantage is that the dcache entire/line functions remain functional even if we enable dcache in runtime.
As we need to check status before *each* function call and we dcache entire/line functions from different places we add this check directly into dcache entire/line functions instead of their callers to avoid code duplication.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/lib/cache.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index e6e439aab8..efba789062 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -398,7 +398,6 @@ void dcache_disable(void) DC_CTRL_CACHE_DISABLE); }
-#ifndef CONFIG_SYS_DCACHE_OFF /* Common Helper for Line Operations on D-cache */ static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, const int cacheop) @@ -448,6 +447,9 @@ static inline void __dc_entire_op(const int cacheop) { int aux;
+ if (!dcache_status()) + return; + __before_dc_op(cacheop);
if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ @@ -463,14 +465,13 @@ static inline void __dc_entire_op(const int cacheop) static inline void __dc_line_op(unsigned long paddr, unsigned long sz, const int cacheop) { + if (!dcache_status()) + return; + __before_dc_op(cacheop); __dcache_line_loop(paddr, sz, cacheop); __after_dc_op(cacheop); } -#else -#define __dc_entire_op(cacheop) -#define __dc_line_op(paddr, sz, cacheop) -#endif /* !CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_range(unsigned long start, unsigned long end) {
Use is_isa_arcv2() function where it is possible instead of CONFIG_ISA_ARCV2 define check to make code clear at the same time keeping pretty much the same functionality - code in branches under "if (is_isa_arcv2())" won't be compiled if CONFIG_ISA_ARCV2 is not defined, still need a couple of CONFIG_ISA_ARCV2 ifdefs to make compiler happy...
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/lib/cache.c | 59 ++++++++++++++++++++++++++-------------------------- 1 file changed, 29 insertions(+), 30 deletions(-)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index efba789062..354dbc600e 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -117,7 +117,6 @@ bool icache_exists __section(".data") = false;
#define CACHE_LINE_MASK (~(l1_line_sz - 1))
-#ifdef CONFIG_ISA_ARCV2 int slc_line_sz __section(".data"); bool slc_exists __section(".data") = false; bool ioc_exists __section(".data") = false; @@ -175,6 +174,8 @@ static void slc_upper_region_init(void)
static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) { +#ifdef CONFIG_ISA_ARCV2 + unsigned int ctrl; unsigned long end;
@@ -218,6 +219,8 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) read_aux_reg(ARC_AUX_SLC_CTRL);
while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); + +#endif /* CONFIG_ISA_ARCV2 */ }
static void arc_ioc_setup(void) @@ -247,11 +250,11 @@ static void arc_ioc_setup(void) write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); } -#endif /* CONFIG_ISA_ARCV2 */
-#ifdef CONFIG_ISA_ARCV2 static void read_decode_cache_bcr_arcv2(void) { +#ifdef CONFIG_ISA_ARCV2 + union bcr_slc_cfg slc_cfg; union bcr_clust_cfg cbcr; union bcr_generic sbcr; @@ -266,8 +269,9 @@ static void read_decode_cache_bcr_arcv2(void) cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); if (cbcr.fields.c && ioc_enable) ioc_exists = true; + +#endif /* CONFIG_ISA_ARCV2 */ } -#endif
void read_decode_cache_bcr(void) { @@ -298,10 +302,10 @@ void cache_init(void) { read_decode_cache_bcr();
-#ifdef CONFIG_ISA_ARCV2 - read_decode_cache_bcr_arcv2(); + if (is_isa_arcv2()) + read_decode_cache_bcr_arcv2();
- if (ioc_exists) + if (is_isa_arcv2() && ioc_exists) arc_ioc_setup();
read_decode_mmu_bcr(); @@ -311,9 +315,8 @@ void cache_init(void) * only if PAE exists in current HW. So we had to check pae_exist * before using them. */ - if (slc_exists && pae_exists) + if (is_isa_arcv2() && slc_exists && pae_exists) slc_upper_region_init(); -#endif /* CONFIG_ISA_ARCV2 */ }
int icache_status(void) @@ -363,10 +366,8 @@ void invalidate_icache_all(void) { __ic_entire_invalidate();
-#ifdef CONFIG_ISA_ARCV2 - if (slc_exists) + if (is_isa_arcv2() && slc_exists) __slc_entire_op(OP_INV); -#endif }
int dcache_status(void) @@ -478,15 +479,16 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) if (start >= end) return;
-#ifdef CONFIG_ISA_ARCV2 - if (!ioc_exists) -#endif + /* + * ARCv1 -> call __dc_line_op + * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op + * ARCv2 && IOC enabled -> nothing + */ + if (!is_isa_arcv2() || !ioc_exists) __dc_line_op(start, end - start, OP_INV);
-#ifdef CONFIG_ISA_ARCV2 - if (slc_exists && !ioc_exists) + if (is_isa_arcv2() && slc_exists && !ioc_exists) __slc_rgn_op(start, end - start, OP_INV); -#endif }
void flush_dcache_range(unsigned long start, unsigned long end) @@ -494,15 +496,16 @@ void flush_dcache_range(unsigned long start, unsigned long end) if (start >= end) return;
-#ifdef CONFIG_ISA_ARCV2 - if (!ioc_exists) -#endif + /* + * ARCv1 -> call __dc_line_op + * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op + * ARCv2 && IOC enabled -> nothing + */ + if (!is_isa_arcv2() || !ioc_exists) __dc_line_op(start, end - start, OP_FLUSH);
-#ifdef CONFIG_ISA_ARCV2 - if (slc_exists && !ioc_exists) + if (is_isa_arcv2() && slc_exists && !ioc_exists) __slc_rgn_op(start, end - start, OP_FLUSH); -#endif }
void flush_cache(unsigned long start, unsigned long size) @@ -520,18 +523,14 @@ void flush_n_invalidate_dcache_all(void) { __dc_entire_op(OP_FLUSH_N_INV);
-#ifdef CONFIG_ISA_ARCV2 - if (slc_exists) + if (is_isa_arcv2() && slc_exists) __slc_entire_op(OP_FLUSH_N_INV); -#endif }
void flush_dcache_all(void) { __dc_entire_op(OP_FLUSH);
-#ifdef CONFIG_ISA_ARCV2 - if (slc_exists) + if (is_isa_arcv2() && slc_exists) __slc_entire_op(OP_FLUSH); -#endif }
As of today we check slc status before each call of __slc_rgn_op or __slc_entire_op. So move status check into __slc_rgn_op and __slc_entire_op.
As we need to check status before *each* function call and we slc_entire_op and slc_rgn_op functions from different places we add this check directly into slc entire/line functions instead of their callers to avoid code duplication.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/lib/cache.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 354dbc600e..f147674ae8 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -141,6 +141,9 @@ static void __slc_entire_op(const int op) { unsigned int ctrl;
+ if (!slc_exists) + return; + ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
if (!(op & OP_FLUSH)) /* i.e. OP_INV */ @@ -179,6 +182,9 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) unsigned int ctrl; unsigned long end;
+ if (!slc_exists) + return; + /* * The Region Flush operation is specified by CTRL.RGN_OP[11..9] * - b'000 (default) is Flush, @@ -366,7 +372,7 @@ void invalidate_icache_all(void) { __ic_entire_invalidate();
- if (is_isa_arcv2() && slc_exists) + if (is_isa_arcv2()) __slc_entire_op(OP_INV); }
@@ -487,7 +493,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) if (!is_isa_arcv2() || !ioc_exists) __dc_line_op(start, end - start, OP_INV);
- if (is_isa_arcv2() && slc_exists && !ioc_exists) + if (is_isa_arcv2() && !ioc_exists) __slc_rgn_op(start, end - start, OP_INV); }
@@ -504,7 +510,7 @@ void flush_dcache_range(unsigned long start, unsigned long end) if (!is_isa_arcv2() || !ioc_exists) __dc_line_op(start, end - start, OP_FLUSH);
- if (is_isa_arcv2() && slc_exists && !ioc_exists) + if (is_isa_arcv2() && !ioc_exists) __slc_rgn_op(start, end - start, OP_FLUSH); }
@@ -523,7 +529,7 @@ void flush_n_invalidate_dcache_all(void) { __dc_entire_op(OP_FLUSH_N_INV);
- if (is_isa_arcv2() && slc_exists) + if (is_isa_arcv2()) __slc_entire_op(OP_FLUSH_N_INV); }
@@ -531,6 +537,6 @@ void flush_dcache_all(void) { __dc_entire_op(OP_FLUSH);
- if (is_isa_arcv2() && slc_exists) + if (is_isa_arcv2()) __slc_entire_op(OP_FLUSH); }
There is the problem with current implementation if we start u-boot from ROM, as we use cache global variables before ther initialization, so these variables are overwritten when we copy .data section from ROM.
So use icache_exists(), dcache_exists(), slc_exists(), pae_exists() functions which check BCRs every time instead of corresponding global variables.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/lib/cache.c | 67 +++++++++++++++++++++++++++++++++------------------- 1 file changed, 43 insertions(+), 24 deletions(-)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index f147674ae8..1b74f55ab7 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -94,7 +94,6 @@ #define DC_CTRL_CACHE_DISABLE BIT(0) #define DC_CTRL_INV_MODE_FLUSH BIT(6) #define DC_CTRL_FLUSH_STATUS BIT(8) -#define CACHE_VER_NUM_MASK 0xF
#define OP_INV BIT(0) #define OP_FLUSH BIT(1) @@ -112,20 +111,16 @@ * relocation but will be used after being zeroed. */ int l1_line_sz __section(".data"); -bool dcache_exists __section(".data") = false; -bool icache_exists __section(".data") = false;
#define CACHE_LINE_MASK (~(l1_line_sz - 1))
int slc_line_sz __section(".data"); -bool slc_exists __section(".data") = false; bool ioc_exists __section(".data") = false; -bool pae_exists __section(".data") = false;
/* To force enable IOC set ioc_enable to 'true' */ bool ioc_enable __section(".data") = false;
-void read_decode_mmu_bcr(void) +static inline bool pae_exists(void) { /* TODO: should we compare mmu version from BCR and from CONFIG? */ #if (CONFIG_ARC_MMU_VER >= 4) @@ -133,15 +128,46 @@ void read_decode_mmu_bcr(void)
mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR);
- pae_exists = !!mmu4.fields.pae; + if (mmu4.fields.pae) + return true; #endif /* (CONFIG_ARC_MMU_VER >= 4) */ + + return false; +} + +static inline bool icache_exists(void) +{ + union bcr_di_cache ibcr; + + ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); + return !!ibcr.fields.ver; +} + +static inline bool dcache_exists(void) +{ + union bcr_di_cache dbcr; + + dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); + return !!dbcr.fields.ver; +} + +static inline bool slc_exists(void) +{ + if (is_isa_arcv2()) { + union bcr_generic sbcr; + + sbcr.word = read_aux_reg(ARC_BCR_SLC); + return !!sbcr.fields.ver; + } + + return false; }
static void __slc_entire_op(const int op) { unsigned int ctrl;
- if (!slc_exists) + if (!slc_exists()) return;
ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); @@ -182,7 +208,7 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) unsigned int ctrl; unsigned long end;
- if (!slc_exists) + if (!slc_exists()) return;
/* @@ -263,12 +289,9 @@ static void read_decode_cache_bcr_arcv2(void)
union bcr_slc_cfg slc_cfg; union bcr_clust_cfg cbcr; - union bcr_generic sbcr;
- sbcr.word = read_aux_reg(ARC_BCR_SLC); - if (sbcr.fields.ver) { + if (slc_exists()) { slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); - slc_exists = true; slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; }
@@ -286,7 +309,6 @@ void read_decode_cache_bcr(void)
ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); if (ibcr.fields.ver) { - icache_exists = true; l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; if (!ic_line_sz) panic("Instruction exists but line length is 0\n"); @@ -294,7 +316,6 @@ void read_decode_cache_bcr(void)
dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); if (dbcr.fields.ver) { - dcache_exists = true; l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; if (!dc_line_sz) panic("Data cache exists but line length is 0\n"); @@ -314,20 +335,18 @@ void cache_init(void) if (is_isa_arcv2() && ioc_exists) arc_ioc_setup();
- read_decode_mmu_bcr(); - /* * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist * only if PAE exists in current HW. So we had to check pae_exist * before using them. */ - if (is_isa_arcv2() && slc_exists && pae_exists) + if (is_isa_arcv2() && slc_exists() && pae_exists()) slc_upper_region_init(); }
int icache_status(void) { - if (!icache_exists) + if (!icache_exists()) return 0;
if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) @@ -338,14 +357,14 @@ int icache_status(void)
void icache_enable(void) { - if (icache_exists) + if (icache_exists()) write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & ~IC_CTRL_CACHE_DISABLE); }
void icache_disable(void) { - if (icache_exists) + if (icache_exists()) write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | IC_CTRL_CACHE_DISABLE); } @@ -378,7 +397,7 @@ void invalidate_icache_all(void)
int dcache_status(void) { - if (!dcache_exists) + if (!dcache_exists()) return 0;
if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) @@ -389,7 +408,7 @@ int dcache_status(void)
void dcache_enable(void) { - if (!dcache_exists) + if (!dcache_exists()) return;
write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & @@ -398,7 +417,7 @@ void dcache_enable(void)
void dcache_disable(void) { - if (!dcache_exists) + if (!dcache_exists()) return;
write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
There is the problem with current implementation if we start u-boot from ROM, as we use global variables before ther initialization, so these variables are overwritten when we copy .data section from ROM.
So move these cache global variables into our arch "global data" structure so that we may really start from ROM.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/include/asm/global_data.h | 6 ++++++ arch/arc/lib/cache.c | 19 +++++++++---------- 2 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h index f0242f1ad6..43e1343095 100644 --- a/arch/arc/include/asm/global_data.h +++ b/arch/arc/include/asm/global_data.h @@ -7,9 +7,15 @@ #ifndef __ASM_ARC_GLOBAL_DATA_H #define __ASM_ARC_GLOBAL_DATA_H
+#include <config.h> + #ifndef __ASSEMBLY__ /* Architecture-specific global data */ struct arch_global_data { + int l1_line_sz; +#if defined(CONFIG_ISA_ARCV2) + int slc_line_sz; +#endif }; #endif /* __ASSEMBLY__ */
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 1b74f55ab7..b08c2111c8 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -87,6 +87,8 @@ * and disable. */
+DECLARE_GLOBAL_DATA_PTR; + /* Bit values in IC_CTRL */ #define IC_CTRL_CACHE_DISABLE BIT(0)
@@ -110,11 +112,8 @@ * But .bss section is not relocated and so it will be initilized before * relocation but will be used after being zeroed. */ -int l1_line_sz __section(".data"); - -#define CACHE_LINE_MASK (~(l1_line_sz - 1)) +#define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1))
-int slc_line_sz __section(".data"); bool ioc_exists __section(".data") = false;
/* To force enable IOC set ioc_enable to 'true' */ @@ -237,7 +236,7 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) * END needs to be setup before START (latter triggers the operation) * END can't be same as START, so add (l2_line_sz - 1) to sz */ - end = paddr + sz + slc_line_sz - 1; + end = paddr + sz + gd->arch.slc_line_sz - 1;
/* * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1) @@ -292,7 +291,7 @@ static void read_decode_cache_bcr_arcv2(void)
if (slc_exists()) { slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); - slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; + gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; }
cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); @@ -309,14 +308,14 @@ void read_decode_cache_bcr(void)
ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); if (ibcr.fields.ver) { - l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; + gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; if (!ic_line_sz) panic("Instruction exists but line length is 0\n"); }
dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); if (dbcr.fields.ver) { - l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; + gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; if (!dc_line_sz) panic("Data cache exists but line length is 0\n"); } @@ -437,14 +436,14 @@ static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, sz += paddr & ~CACHE_LINE_MASK; paddr &= CACHE_LINE_MASK;
- num_lines = DIV_ROUND_UP(sz, l1_line_sz); + num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz);
while (num_lines-- > 0) { #if (CONFIG_ARC_MMU_VER == 3) write_aux_reg(ARC_AUX_DC_PTAG, paddr); #endif write_aux_reg(aux_cmd, paddr); - paddr += l1_line_sz; + paddr += gd->arch.l1_line_sz; } }
Move pae exists check into slc_upper_region_init function itself instead of its caller as more appropriate place.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/lib/cache.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index b08c2111c8..031ebd7765 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -192,6 +192,14 @@ static void __slc_entire_op(const int op)
static void slc_upper_region_init(void) { + /* + * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist + * only if PAE exists in current HW. So we had to check pae_exist + * before using them. + */ + if (!pae_exists()) + return; + /* * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0 * as we don't use PAE40. @@ -334,12 +342,7 @@ void cache_init(void) if (is_isa_arcv2() && ioc_exists) arc_ioc_setup();
- /* - * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist - * only if PAE exists in current HW. So we had to check pae_exist - * before using them. - */ - if (is_isa_arcv2() && slc_exists() && pae_exists()) + if (is_isa_arcv2() && slc_exists()) slc_upper_region_init(); }
Use CONFIG_ARC_DBG_IOC_ENABLE Kconfig option instead of ioc_enable global variable.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/Kconfig | 18 ++++++++++++++++ arch/arc/include/asm/cache.h | 5 +++++ arch/arc/lib/cache.c | 49 ++++++++++++++++++++++++++------------------ 3 files changed, 52 insertions(+), 20 deletions(-)
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index e3f9db7b29..aee15d5353 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -116,6 +116,24 @@ config SYS_DCACHE_OFF bool "Do not use Data Cache" default n
+menuconfig ARC_DBG + bool "ARC debugging" + default n + +if ARC_DBG + +config ARC_DBG_IOC_ENABLE + bool "Enable IO coherency unit" + depends on CPU_ARCHS38 + default n + help + Enable IO coherency unit to debug problems with caches and + DMA peripherals. + NOTE: as of today linux will not work properly if this option + is enabled in u-boot! + +endif + choice prompt "Target select" default TARGET_AXS103 diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 382c4126c3..fe75409b5c 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -32,6 +32,11 @@ void cache_init(void); void flush_n_invalidate_dcache_all(void);
+static const inline int is_ioc_enabled(void) +{ + return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE); +} + #endif /* __ASSEMBLY__ */
#endif /* __ASM_ARC_CACHE_H */ diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 031ebd7765..ad14900135 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -107,18 +107,8 @@ DECLARE_GLOBAL_DATA_PTR; #define SLC_CTRL_BUSY 0x100 #define SLC_CTRL_RGN_OP_INV 0x200
-/* - * By default that variable will fall into .bss section. - * But .bss section is not relocated and so it will be initilized before - * relocation but will be used after being zeroed. - */ #define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1))
-bool ioc_exists __section(".data") = false; - -/* To force enable IOC set ioc_enable to 'true' */ -bool ioc_enable __section(".data") = false; - static inline bool pae_exists(void) { /* TODO: should we compare mmu version from BCR and from CONFIG? */ @@ -162,6 +152,30 @@ static inline bool slc_exists(void) return false; }
+static inline bool ioc_exists(void) +{ + if (is_isa_arcv2()) { + union bcr_clust_cfg cbcr; + + cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); + return cbcr.fields.c; + } + + return false; +} + +static inline bool ioc_enabled(void) +{ + /* + * We check only CONFIG option instead of IOC HW state check as IOC + * must be disabled by default. + */ + if (is_ioc_enabled()) + return ioc_exists(); + + return false; +} + static void __slc_entire_op(const int op) { unsigned int ctrl; @@ -295,17 +309,12 @@ static void read_decode_cache_bcr_arcv2(void) #ifdef CONFIG_ISA_ARCV2
union bcr_slc_cfg slc_cfg; - union bcr_clust_cfg cbcr;
if (slc_exists()) { slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; }
- cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); - if (cbcr.fields.c && ioc_enable) - ioc_exists = true; - #endif /* CONFIG_ISA_ARCV2 */ }
@@ -339,7 +348,7 @@ void cache_init(void) if (is_isa_arcv2()) read_decode_cache_bcr_arcv2();
- if (is_isa_arcv2() && ioc_exists) + if (is_isa_arcv2() && ioc_enabled()) arc_ioc_setup();
if (is_isa_arcv2() && slc_exists()) @@ -511,10 +520,10 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op * ARCv2 && IOC enabled -> nothing */ - if (!is_isa_arcv2() || !ioc_exists) + if (!is_isa_arcv2() || !ioc_enabled()) __dc_line_op(start, end - start, OP_INV);
- if (is_isa_arcv2() && !ioc_exists) + if (is_isa_arcv2() && !ioc_enabled()) __slc_rgn_op(start, end - start, OP_INV); }
@@ -528,10 +537,10 @@ void flush_dcache_range(unsigned long start, unsigned long end) * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op * ARCv2 && IOC enabled -> nothing */ - if (!is_isa_arcv2() || !ioc_exists) + if (!is_isa_arcv2() || !ioc_enabled()) __dc_line_op(start, end - start, OP_FLUSH);
- if (is_isa_arcv2() && !ioc_exists) + if (is_isa_arcv2() && !ioc_enabled()) __slc_rgn_op(start, end - start, OP_FLUSH); }
Implement icache_enabled and dcache_enabled as separate functions which can be used with inline attribute. This is preparation to make them always_inline.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/lib/cache.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index ad14900135..7052895bb7 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -132,6 +132,14 @@ static inline bool icache_exists(void) return !!ibcr.fields.ver; }
+static inline bool icache_enabled(void) +{ + if (!icache_exists()) + return false; + + return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE); +} + static inline bool dcache_exists(void) { union bcr_di_cache dbcr; @@ -140,6 +148,14 @@ static inline bool dcache_exists(void) return !!dbcr.fields.ver; }
+static inline bool dcache_enabled(void) +{ + if (!dcache_exists()) + return false; + + return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE); +} + static inline bool slc_exists(void) { if (is_isa_arcv2()) { @@ -357,13 +373,7 @@ void cache_init(void)
int icache_status(void) { - if (!icache_exists()) - return 0; - - if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) - return 0; - else - return 1; + return icache_enabled(); }
void icache_enable(void) @@ -383,7 +393,7 @@ void icache_disable(void) /* IC supports only invalidation */ static inline void __ic_entire_invalidate(void) { - if (!icache_status()) + if (!icache_enabled()) return;
/* Any write to IC_IVIC register triggers invalidation of entire I$ */ @@ -408,13 +418,7 @@ void invalidate_icache_all(void)
int dcache_status(void) { - if (!dcache_exists()) - return 0; - - if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) - return 0; - else - return 1; + return dcache_enabled(); }
void dcache_enable(void) @@ -484,7 +488,7 @@ static inline void __dc_entire_op(const int cacheop) { int aux;
- if (!dcache_status()) + if (!dcache_enabled()) return;
__before_dc_op(cacheop); @@ -502,7 +506,7 @@ static inline void __dc_entire_op(const int cacheop) static inline void __dc_line_op(unsigned long paddr, unsigned long sz, const int cacheop) { - if (!dcache_status()) + if (!dcache_enabled()) return;
__before_dc_op(cacheop);
If L1 data cache is disabled SL$ is bypassed for data and all load/store requests are sent directly to main memory.
If L1 instructiona cache is disabled SL$ is NOT bypassed for instructions and all instruction requests are fetched through SLC.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/lib/cache.c | 39 ++++++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 7052895bb7..a5aae3d232 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -168,6 +168,15 @@ static inline bool slc_exists(void) return false; }
+static inline bool slc_data_bypass(void) +{ + /* + * If L1 data cache is disabled SL$ is bypassed and all load/store + * requests are sent directly to main memory. + */ + return !dcache_enabled(); +} + static inline bool ioc_exists(void) { if (is_isa_arcv2()) { @@ -412,7 +421,13 @@ void invalidate_icache_all(void) { __ic_entire_invalidate();
- if (is_isa_arcv2()) + /* + * If SL$ is bypassed for data it is used only for instructions, + * so we need to invalidate it too. + * TODO: HS 3.0 supports SLC disable so we need to check slc + * enable/disable status here. + */ + if (is_isa_arcv2() && slc_data_bypass()) __slc_entire_op(OP_INV); }
@@ -520,14 +535,15 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) return;
/* - * ARCv1 -> call __dc_line_op - * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op - * ARCv2 && IOC enabled -> nothing + * ARCv1 -> call __dc_line_op + * ARCv2 && L1 D$ disabled -> nothing + * ARCv2 && L1 D$ enabled && IOC enabled -> nothing + * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op */ if (!is_isa_arcv2() || !ioc_enabled()) __dc_line_op(start, end - start, OP_INV);
- if (is_isa_arcv2() && !ioc_enabled()) + if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass()) __slc_rgn_op(start, end - start, OP_INV); }
@@ -537,14 +553,15 @@ void flush_dcache_range(unsigned long start, unsigned long end) return;
/* - * ARCv1 -> call __dc_line_op - * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op - * ARCv2 && IOC enabled -> nothing + * ARCv1 -> call __dc_line_op + * ARCv2 && L1 D$ disabled -> nothing + * ARCv2 && L1 D$ enabled && IOC enabled -> nothing + * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op */ if (!is_isa_arcv2() || !ioc_enabled()) __dc_line_op(start, end - start, OP_FLUSH);
- if (is_isa_arcv2() && !ioc_enabled()) + if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass()) __slc_rgn_op(start, end - start, OP_FLUSH); }
@@ -563,7 +580,7 @@ void flush_n_invalidate_dcache_all(void) { __dc_entire_op(OP_FLUSH_N_INV);
- if (is_isa_arcv2()) + if (is_isa_arcv2() && !slc_data_bypass()) __slc_entire_op(OP_FLUSH_N_INV); }
@@ -571,6 +588,6 @@ void flush_dcache_all(void) { __dc_entire_op(OP_FLUSH);
- if (is_isa_arcv2()) + if (is_isa_arcv2() && !slc_data_bypass()) __slc_entire_op(OP_FLUSH); }
Implement specialized function to clenup caches (and therefore sync I/D caches) which can be used for cleanup before linux launch or to sync caches during uboot relocation.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/include/asm/cache.h | 1 + arch/arc/lib/bootm.c | 4 ++-- arch/arc/lib/cache.c | 23 +++++++++++++++++++++++ arch/arc/lib/init_helpers.c | 6 +++--- 4 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index fe75409b5c..2269183615 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -31,6 +31,7 @@
void cache_init(void); void flush_n_invalidate_dcache_all(void); +void sync_n_cleanup_cache_all(void);
static const inline int is_ioc_enabled(void) { diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c index 9eef7070cf..c6800cb0ec 100644 --- a/arch/arc/lib/bootm.c +++ b/arch/arc/lib/bootm.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */
+#include <asm/cache.h> #include <common.h>
DECLARE_GLOBAL_DATA_PTR; @@ -45,8 +46,7 @@ int arch_fixup_fdt(void *blob) static int cleanup_before_linux(void) { disable_interrupts(); - flush_dcache_all(); - invalidate_icache_all(); + sync_n_cleanup_cache_all();
return 0; } diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index a5aae3d232..5d7583d868 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -591,3 +591,26 @@ void flush_dcache_all(void) if (is_isa_arcv2() && !slc_data_bypass()) __slc_entire_op(OP_FLUSH); } + +/* + * This is function to cleanup all caches (and therefore sync I/D caches) which + * can be used for cleanup before linux launch or to sync caches during + * relocation. + */ +void sync_n_cleanup_cache_all(void) +{ + __dc_entire_op(OP_FLUSH_N_INV); + + /* + * If SL$ is bypassed for data it is used only for instructions, + * and we shouldn't flush it. So invalidate it instead of flush_n_inv. + */ + if (is_isa_arcv2()) { + if (slc_data_bypass()) + __slc_entire_op(OP_INV); + else + __slc_entire_op(OP_FLUSH_N_INV); + } + + __ic_entire_invalidate(); +} diff --git a/arch/arc/lib/init_helpers.c b/arch/arc/lib/init_helpers.c index dbc8d68ffb..435fe96ef4 100644 --- a/arch/arc/lib/init_helpers.c +++ b/arch/arc/lib/init_helpers.c @@ -4,14 +4,14 @@ * SPDX-License-Identifier: GPL-2.0+ */
+#include <asm/cache.h> #include <common.h>
DECLARE_GLOBAL_DATA_PTR;
int init_cache_f_r(void) { -#ifndef CONFIG_SYS_DCACHE_OFF - flush_dcache_all(); -#endif + sync_n_cleanup_cache_all(); + return 0; }
Add additional cache configuration checks and note about supported configurations.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/lib/cache.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 5d7583d868..fd70ce8efe 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -85,6 +85,66 @@ * enabling force function inline with '__attribute__((always_inline))' gcc * attribute to avoid any function call (and BLINK store) between cache flush * and disable. + * + * + * [ NOTE 2 ]: + * As of today we only support the following cache configurations on ARC. + * Other configurations may exist in HW (for example, since version 3.0 HS + * supports SL$ (L2 system level cache) disable) but we don't support it in SW. + * Configuration 1: + * ______________________ + * | | + * | ARC CPU | + * |______________________| + * ___|___ ___|___ + * | | | | + * | L1 I$ | | L1 D$ | + * |_______| |_______| + * on/off on/off + * ___|______________|____ + * | | + * | main memory | + * |______________________| + * + * Configuration 2: + * ______________________ + * | | + * | ARC CPU | + * |______________________| + * ___|___ ___|___ + * | | | | + * | L1 I$ | | L1 D$ | + * |_______| |_______| + * on/off on/off + * ___|______________|____ + * | | + * | L2 (SL$) | + * |______________________| + * always must be on + * ___|______________|____ + * | | + * | main memory | + * |______________________| + * + * Configuration 3: + * ______________________ + * | | + * | ARC CPU | + * |______________________| + * ___|___ ___|___ + * | | | | + * | L1 I$ | | L1 D$ | + * |_______| |_______| + * on/off must be on + * ___|______________|____ _______ + * | | | | + * | L2 (SL$) |-----| IOC | + * |______________________| |_______| + * always must be on on/off + * ___|______________|____ + * | | + * | main memory | + * |______________________| */
DECLARE_GLOBAL_DATA_PTR; @@ -308,6 +368,14 @@ static void arc_ioc_setup(void) /* IOC Aperture size is equal to DDR size */ long ap_size = CONFIG_SYS_SDRAM_SIZE;
+ /* Unsupported configuration. See [ NOTE 2 ] for more details. */ + if (!slc_exists()) + panic("Try to enable IOC but SLC is not present"); + + /* Unsupported configuration. See [ NOTE 2 ] for more details. */ + if (!dcache_enabled()) + panic("Try to enable IOC but L1 D$ is disabled"); + flush_n_invalidate_dcache_all();
if (!is_power_of_2(ap_size) || ap_size < 4096) @@ -338,6 +406,13 @@ static void read_decode_cache_bcr_arcv2(void) if (slc_exists()) { slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; + + /* + * We don't support configuration where L1 I$ or L1 D$ is + * absent but SL$ exists. See [ NOTE 2 ] for more details. + */ + if (!icache_exists() || !dcache_exists()) + panic("Unsupported cache configuration: SLC exists but one of L1 caches is absent"); }
#endif /* CONFIG_ISA_ARCV2 */
Add missing cache cleanup before cache disable: * Flush and invalidate L1 D$ before disabling. Flush and invalidate SLC before L1 D$ disabling (as it will be bypassed for data) Otherwise we can lose some data when we disable L1 D$ if this data isn't flushed to next level cache. Or we can get wrong data if L1 D$ has some entries after enable which we modified when the L1 D$ was disabled. * Invalidate L1 I$ before disabling. Otherwise we can execute wrong instructions after L1 I$ enable if we modified any code when L1 I$ was disabled.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/lib/cache.c | 53 ++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 39 insertions(+), 14 deletions(-)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index fd70ce8efe..99776066d3 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -169,6 +169,16 @@ DECLARE_GLOBAL_DATA_PTR;
#define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1))
+/* + * We don't want to use '__always_inline' macro here as it can be redefined + * to simple 'inline' in some cases which breaks stuff. See [ NOTE 1 ] for more + * details about the reasons we need to use always_inline functions. + */ +#define inlined_cachefunc inline __attribute__((always_inline)) + +static inlined_cachefunc void __ic_entire_invalidate(void); +static inlined_cachefunc void __dc_entire_op(const int cacheop); + static inline bool pae_exists(void) { /* TODO: should we compare mmu version from BCR and from CONFIG? */ @@ -184,7 +194,7 @@ static inline bool pae_exists(void) return false; }
-static inline bool icache_exists(void) +static inlined_cachefunc bool icache_exists(void) { union bcr_di_cache ibcr;
@@ -192,7 +202,7 @@ static inline bool icache_exists(void) return !!ibcr.fields.ver; }
-static inline bool icache_enabled(void) +static inlined_cachefunc bool icache_enabled(void) { if (!icache_exists()) return false; @@ -200,7 +210,7 @@ static inline bool icache_enabled(void) return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE); }
-static inline bool dcache_exists(void) +static inlined_cachefunc bool dcache_exists(void) { union bcr_di_cache dbcr;
@@ -208,7 +218,7 @@ static inline bool dcache_exists(void) return !!dbcr.fields.ver; }
-static inline bool dcache_enabled(void) +static inlined_cachefunc bool dcache_enabled(void) { if (!dcache_exists()) return false; @@ -216,7 +226,7 @@ static inline bool dcache_enabled(void) return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE); }
-static inline bool slc_exists(void) +static inlined_cachefunc bool slc_exists(void) { if (is_isa_arcv2()) { union bcr_generic sbcr; @@ -228,7 +238,7 @@ static inline bool slc_exists(void) return false; }
-static inline bool slc_data_bypass(void) +static inlined_cachefunc bool slc_data_bypass(void) { /* * If L1 data cache is disabled SL$ is bypassed and all load/store @@ -261,7 +271,7 @@ static inline bool ioc_enabled(void) return false; }
-static void __slc_entire_op(const int op) +static inlined_cachefunc void __slc_entire_op(const int op) { unsigned int ctrl;
@@ -469,13 +479,17 @@ void icache_enable(void)
void icache_disable(void) { - if (icache_exists()) - write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | - IC_CTRL_CACHE_DISABLE); + if (!icache_exists()) + return; + + __ic_entire_invalidate(); + + write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | + IC_CTRL_CACHE_DISABLE); }
/* IC supports only invalidation */ -static inline void __ic_entire_invalidate(void) +static inlined_cachefunc void __ic_entire_invalidate(void) { if (!icache_enabled()) return; @@ -525,6 +539,17 @@ void dcache_disable(void) if (!dcache_exists()) return;
+ __dc_entire_op(OP_FLUSH_N_INV); + + /* + * As SLC will be bypassed for data after L1 D$ disable we need to + * flush it first before L1 D$ disable. Also we invalidate SLC to + * avoid any inconsistent data problems after enabling L1 D$ again with + * dcache_enable function. + */ + if (is_isa_arcv2()) + __slc_entire_op(OP_FLUSH_N_INV); + write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | DC_CTRL_CACHE_DISABLE); } @@ -553,7 +578,7 @@ static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, } }
-static void __before_dc_op(const int op) +static inlined_cachefunc void __before_dc_op(const int op) { unsigned int ctrl;
@@ -568,13 +593,13 @@ static void __before_dc_op(const int op) write_aux_reg(ARC_AUX_DC_CTRL, ctrl); }
-static void __after_dc_op(const int op) +static inlined_cachefunc void __after_dc_op(const int op) { if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); }
-static inline void __dc_entire_op(const int cacheop) +static inlined_cachefunc void __dc_entire_op(const int cacheop) { int aux;
Move all checks before cache flush and IOC setup.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- arch/arc/lib/cache.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 99776066d3..8203fae145 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -386,11 +386,15 @@ static void arc_ioc_setup(void) if (!dcache_enabled()) panic("Try to enable IOC but L1 D$ is disabled");
- flush_n_invalidate_dcache_all(); - if (!is_power_of_2(ap_size) || ap_size < 4096) panic("IOC Aperture size must be power of 2 and bigger 4Kib");
+ /* IOC Aperture start must be aligned to the size of the aperture */ + if (ap_base % ap_size != 0) + panic("IOC Aperture start must be aligned to the size of the aperture"); + + flush_n_invalidate_dcache_all(); + /* * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, * so setting 0x11 implies 512M, 0x12 implies 1G... @@ -398,10 +402,6 @@ static void arc_ioc_setup(void) write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, order_base_2(ap_size / 1024) - 2);
- /* IOC Aperture start must be aligned to the size of the aperture */ - if (ap_base % ap_size != 0) - panic("IOC Aperture start must be aligned to the size of the aperture"); - write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
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Eugeniy Paltsev