[U-Boot] Data cache on MPC8248 board
Hi all,
I have enabled cache on a MPC8248 board using Block Address Translation. RAM is cache enabled, everything else cache inhibited. Apparently cache is enabled fine, however system hangs using tftp command (in the middle of the transaction) or on external interrupt handling when I set up a timer from a standalone application. Please note that if I define DBAT0 cache inhibited, both tftp and the standalone program work fine.
Any help or advice is appreciated.
Find below the code I have used to replace dcache_enable in cpu/mpc8260/start.S, you will notice I am very novice with MPC assembler.
#define BL_16Mb 0x000000FC #define BL_32Mb 0x000001FC #define BL_64Mb 0x000003FC #define BL_128Mb 0x000007FC #define BL_256Mb 0x00001FFC #define Valid_Supervisor 0x00000002 #define Valid_User 0x00000001
#define Cache_Inhibited 0x00000020 #define Guarded 0x00000008
#define Read_Write 0x00000002
#define CTR 9 .globl dcache_enable dcache_enable: // Step 1: Disable_Cache addis r3, r0, 0 ori r3, r3, 0xC000 sync isync mfspr r11, HID0 isync andc r4, r11, r3 ori r12, r11, 0x0C00 sync isync mtspr HID0, r12 mtspr HID0, r4 isync // Step 2: Disable_Memory_Management sync li r12, 0x0030 mfmsr r11 andc r11, r11, r12 mtmsr r11 isync
// Step 3: Clear_Memory_Map lis r3, 0 lis r4, 0 mtspr IBAT0U, r3 mtspr IBAT0L, r4 isync mtspr DBAT0U, r3 mtspr DBAT0L, r4 isync mtspr IBAT1U, r3 mtspr IBAT1L, r4 isync mtspr DBAT1U, r3 mtspr DBAT1L, r4 isync mtspr IBAT2U, r3 mtspr IBAT2L, r4 isync mtspr DBAT2U, r3 mtspr DBAT2L, r4 isync mtspr IBAT3U, r3 mtspr IBAT3L, r4 isync mtspr DBAT3U, r3 mtspr DBAT3L, r4 isync
// Step 4: Set_Memory_Map lis r3, 0x0000 ori r3, r3, BL_128Mb + Valid_Supervisor + Valid_User lis r4, 0x0000 ori r4, r4, Read_Write mtspr IBAT0U, r3 mtspr IBAT0L, r4 isync
lis r3, 0x0000 ori r3, r3, BL_128Mb + Valid_Supervisor + Valid_User lis r4, 0x0000 ori r4, r4, Read_Write + Guarded mtspr DBAT0U, r3 mtspr DBAT0L, r4 isync
lis r3, 0x5000 ori r3, r3, BL_256Mb + Valid_Supervisor + Valid_User lis r4, 0x5000 ori r4, r4, Read_Write + Guarded + Cache_Inhibited mtspr DBAT1U, r3 mtspr DBAT1L, r4 isync
lis r3, 0xF000 ori r3, r3, BL_256Mb + Valid_Supervisor + Valid_User lis r4, 0xF000 ori r4, r4, Read_Write + Guarded + Cache_Inhibited mtspr DBAT2U, r3 mtspr DBAT3L, r4 isync
// Step 5: Enable_Memory_Management
li r11, 64 mtspr CTR, r11 isync tlbie 0x00 sync isync tlbie 0x01 sync isync tlbie 0x02 sync isync tlbie 0x03 sync isync tlbie 0x04 sync isync tlbie 0x05 sync isync tlbie 0x06 sync isync tlbie 0x07 sync isync tlbie 0x08 sync isync tlbie 0x09 sync isync tlbie 0x0A sync isync tlbie 0x0B sync isync tlbie 0x0C sync isync tlbie 0x0D sync isync tlbie 0x0E sync isync tlbie 0x0F sync isync tlbie 0x10 sync isync tlbie 0x11 sync isync tlbie 0x12 sync isync tlbie 0x13 sync isync tlbie 0x14 sync isync tlbie 0x15 sync isync tlbie 0x16 sync isync tlbie 0x17 sync isync tlbie 0x18 sync isync tlbie 0x19 sync isync tlbie 0x1A sync isync tlbie 0x1B sync isync tlbie 0x1C sync isync tlbie 0x1D sync isync tlbie 0x1E sync isync tlbie 0x1F sync mfmsr r11 ori r11, r11, 0x0030 mtmsr r11 isync // Step 6: Enable_Cache mfspr r11, HID0 ori r12, r11, 0xCC00 ori r11, r11, 0xC000 sync isync mtspr HID0, r12 mtspr HID0, r11 isync
blr
On Wed, Sep 10, 2008 at 10:51:50AM +0200, Rodrigo Vilar wrote:
I have enabled cache on a MPC8248 board using Block Address Translation. RAM is cache enabled, everything else cache inhibited. Apparently cache is enabled fine, however system hangs using tftp command (in the middle of the transaction) or on external interrupt handling when I set up a timer from a standalone application. Please note that if I define DBAT0 cache inhibited, both tftp and the standalone program work fine.
Do you have snooping enabled on all of the DMA devices you're using?
lis r3, 0xF000 ori r3, r3, BL_256Mb + Valid_Supervisor + Valid_User lis r4, 0xF000 ori r4, r4, Read_Write + Guarded + Cache_Inhibited mtspr DBAT2U, r3 mtspr DBAT3L, r4 isync
s/DBAT3L/DBAT2L/, presumably.
-Scott
Snooping is enabled on all the devices we handle. However it is not enabled on u-boot's serial console. We have managed to get dcache running making the following changes, I provide the answer should anyone be interested:
1) We have created a new function bat_enable, that defines the address translation for our board .globl bat_enable bat_enable: // Set_Memory_Map lis r3, 0x0000 ori r3, r3, BL_128Mb + Valid_Supervisor + Valid_User lis r4, 0x0000 ori r4, r4, Read_Write mtspr IBAT0U, r3 mtspr IBAT0L, r4 isync
lis r3, 0x0000 ori r3, r3, BL_128Kb + Valid_Supervisor + Valid_User lis r4, 0x0000 ori r4, r4, Read_Write + Guarded + Cache_Inhibited mtspr DBAT0U, r3 mtspr DBAT0L, r4 isync
lis r3, 0x0002 ori r3, r3, BL_128Mb + Valid_Supervisor + Valid_User lis r4, 0x0002 ori r4, r4, Read_Write + Guarded mtspr DBAT1U, r3 mtspr DBAT1L, r4 isync
lis r3, 0x5000 ori r3, r3, BL_256Mb + Valid_Supervisor + Valid_User lis r4, 0x5000 ori r4, r4, Read_Write + Guarded + Cache_Inhibited mtspr DBAT2U, r3 mtspr DBAT2L, r4 isync
lis r3, 0xF000 ori r3, r3, BL_256Mb + Valid_Supervisor + Valid_User lis r4, 0xF000 ori r4, r4, Read_Write + Guarded + Cache_Inhibited mtspr DBAT3U, r3 mtspr DBAT3L, r4 isync
li r3, 32 mtctr r3 li r3, 0 1: tlbie r3 addi r3, r3, 0x1000 bdnz 1b SYNC
/* Enable address translations */ mfmsr r3 ori r3, r3, 0x0030 mtmsr r3 isync
blr
2) We call this function in lib_ppc/board.c within function board_init_r before serial_initialise. Probably this is not the best location, any advice would be appreciated.
3) We had to modify include/ppc_asm.tmpl macro STD_EXCEPTION
rlwimi r20,r23,0,25,25; \ changed to rlwimi r20,r23,0,25,27; \
in order to keep the data translation bits in MSR after the interrupt. The instruction above is also used on CRITICAL_EXCEPTION, any advice on wether we should change it or not would also be appreciated.
4) We had to modify lib_ppc/interrupts.c function enable_interrupts adding asm("sync"); so as not to get "Bogus External Interrupt IRQ 0" after enabling data cache.
void enable_interrupts (void) { asm ("sync"); set_msr (get_msr () | MSR_EE); }
Thanks,
Rodrigo
2008/9/11 Scott Wood scottwood@freescale.com
On Wed, Sep 10, 2008 at 10:51:50AM +0200, Rodrigo Vilar wrote:
I have enabled cache on a MPC8248 board using Block Address Translation.
RAM
is cache enabled, everything else cache inhibited. Apparently cache is enabled fine, however system hangs using tftp command (in the middle of the transaction) or on external interrupt handling when
I
set up a timer from a standalone application. Please note that if I
define
DBAT0 cache inhibited, both tftp and the standalone program work fine.
Do you have snooping enabled on all of the DMA devices you're using?
lis r3, 0xF000 ori r3, r3, BL_256Mb + Valid_Supervisor + Valid_User lis r4, 0xF000 ori r4, r4, Read_Write + Guarded + Cache_Inhibited mtspr DBAT2U, r3 mtspr DBAT3L, r4 isync
s/DBAT3L/DBAT2L/, presumably.
-Scott
participants (2)
-
Rodrigo Vilar -
Scott Wood