[U-Boot-Users] [PATCH 1/2] Add support for mpc8313 based BUBBATWO
These patches add support for the mpc8313 based BUBBATWO board.
Signed-off-by: Tor Krill tor@excito.com --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + include/configs/BUBBATWO.h | 516 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 524 insertions(+), 0 deletions(-) create mode 100644 include/configs/BUBBATWO.h
diff --git a/MAINTAINERS b/MAINTAINERS index ac7572c..c188728 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -224,6 +224,10 @@ Sangmoon Kim dogoil@etinsys.com debris MPC8245 KVME080 MPC8245
+Tor Krill tor@excito.com + + BUBBATWO MPC8313 + Thomas Lange thomas@corelatus.se
GTH MPC860 diff --git a/MAKEALL b/MAKEALL index 0674069..da28c7a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -332,6 +332,7 @@ LIST_83xx=" \ MPC837XERDB \ sbc8349 \ TQM834x \ + BUBBATWO \ "
diff --git a/Makefile b/Makefile index 3401203..93f563f 100644 --- a/Makefile +++ b/Makefile @@ -1993,6 +1993,9 @@ MPC8313ERDB_66_config: unconfig fi ; @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
+BUBBATWO_config: unconfig + @$(MKCONFIG) BUBBATWO ppc mpc83xx bubbatwo excito + MPC8315ERDB_config: unconfig @$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
diff --git a/include/configs/BUBBATWO.h b/include/configs/BUBBATWO.h new file mode 100644 index 0000000..4e27c6f --- /dev/null +++ b/include/configs/BUBBATWO.h @@ -0,0 +1,516 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. + * Copyright (C) Excito Elektronik i Skåne, 2008. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * Excito Bubba|TWO board configuration file + * Based on the devikit config MPC8313ERDB.h + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 +#define CONFIG_MPC83XX 1 +#define CONFIG_MPC831X 1 +#define CONFIG_MPC8313 1 +#define CONFIG_EXCB2 1 + +#define CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI + +#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ + +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +#define CFG_IMMR 0xE0000000 + +#define CFG_MEMTEST_START 0x00001000 +#define CFG_MEMTEST_END 0x0fe00000 + +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE + +/* + * DDR configs for different memsizes. + * Memory size is read out from boardversion. + */ +#define CFG_DDR_CONFIG_256 ( CSCONFIG_EN \ + | CSCONFIG_BANK_BIT_3 | 0x00010000 /* TODO */ \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) + /* 0x80014102 */ +#define CFG_DDR_CONFIG_128 ( CSCONFIG_EN \ + | 0x00010000 /* TODO */ \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) + /* 0x80010102 */ + +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ + | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ + | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) + /* 0x00220802 */ +#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ + | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ + | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ + | (10 << TIMING_CFG1_REFREC_SHIFT ) \ + | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) + /* 0x3835a322 */ +#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ + | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ + | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ + | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ + | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) ) + /* 0x129048c6 */ /* P9-45,may need tuning */ +#define CFG_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \ + | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) + /* 0x05100500 */ +#if defined(CONFIG_DDR_2T_TIMING) +#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_2T_EN \ + | SDRAM_CFG_DBW_32 ) +#else +#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE ) + /* 0x43080000 */ +#endif +#define CFG_SDRAM_CFG2 0x00401000; +/* set burst length to 8 for 32-bit data path */ +#define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ + | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) + /* 0x44480632 */ +#define CFG_DDR_MODE_2 0x8000C000; + +#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /*0x02000000*/ +#define CFG_DDRCDR_VALUE ( DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR ) + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_LEGACY /* Use legacy mode not cfi-compliant */ +#define CFG_FLASH_LEGACY_512Kx16 /* Spansion 16bit 512KB on 16bit bus */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CFG_FLASH_SIZE 1 /* flash size in MB */ +#define CFG_FLASH_EMPTY_INFO /* display empty sectors */ +#undef CFG_FLASH_USE_BUFFER_WRITE /* Not supported by cfi legacy */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_9 \ + | OR_GPCM_EHTR \ + | OR_GPCM_EAD ) + /* 0xFF006FF7 TODO SLOW 16 MB flash size */ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 11 /* sectors per device */ + +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#endif + +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + */ +#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ +#define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ + | (0xFF << LBCR_BMT_SHIFT) \ + | 0xF ) /* 0x0004ff0f */ + +#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ + +/* local bus read write buffer mapping */ +#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ +#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ +#define CFG_LBLAWBAR3_PRELIM 0xFA000000 +#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* TSEC */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) +#define CONFIG_NET_MULTI +#define CFG_VSC8601_SKEWFIX + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MMIO_BASE 0x90000000 +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xE2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#define CONFIG_PCI_SKIP_HOST_BRIDGE + +/* + * TSEC configuration + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_GMII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 + +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0x01 +#define TSEC2_PHY_ADDR 0x00 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_ISL1208 +#define CFG_I2C_RTC_ADDR 0x6f + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#else + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PCI +#undef CONFIG_CMD_SCSI +#define CONFIG_CMD_CACHE + +#if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS +#endif + +#define CONFIG_CMDLINE_EDITING 1 + +/* For disk access */ +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_SATA_SIL3114 +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#define CONFIG_CMD_SATA +#define CFG_SATA_MAX_DEVICE 4 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x4000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +/* 66MHz IN, 133MHz CSB, 266 DDR, 333 CORE */ +/* 0x62050000 */ +#define CFG_HRCW_LOW (\ + 0x20000000 /* reserved, must be set */ |\ + HRCWL_DDRCM |\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_2_5X1) + +/* 0xa0606c00 */ +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) + +/* System IO Config */ +#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ +#define CFG_SICRL (SICRL_SPI_A | SICRL_SPI_B | SICRL_SPI_C | SICRL_SPI_D) /* SPI is IO */ + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) + +#define CFG_HID2 HID2_HBE + +/* DDR @ 0x00000000 */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10) +#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI2 not supported on 8313 */ +#define CFG_IBAT3L (0) +#define CFG_IBAT3U (0) +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CFG_IBAT6L (0xF0000000 | BATL_PP_10) +#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ETHADDR 00:22:02:00:95:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH0 +#define CONFIG_ETH1ADDR 00:22:02:00:95:02 + +#define CONFIG_IPADDR 192.168.0.49 +#define CONFIG_SERVERIP 192.168.0.200 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_NETMASK 255.0.0.0 +#define CONFIG_NETDEV eth1 + +#define CONFIG_HOSTNAME bubbatwo +#define CONFIG_ROOTPATH /nfs/root/path +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ +#define CONFIG_FDTFILE bubba.dtb + +#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ +#define CONFIG_BAUDRATE 115200 + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "ethprime=TSEC1\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "fdtaddr=400000\0" \ + "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ + "bootfile" MK_STR(CONFIG_BOOTFILE) "\0" \ + "console=ttyS0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "diskdev=/dev/sda1\0" \ + "bootdev=sata 0:2\0" \ + "linux=setenv bootargs root=$diskdev; "\ + "ext2load $bootdev 0x400000 /boot/$bootfile; " \ + "ext2load $bootdev 0x600000 /boot/$fdtfile; "\ + "bootm 0x400000 - 0x600000\0"\ + "bootcmd=run linux\0" + +#undef MK_STR +#undef XMK_STR + +#endif /* __CONFIG_H */
Signed-off-by: Tor Krill tor@excito.com --- board/excito/bubbatwo/Makefile | 50 +++++++++ board/excito/bubbatwo/bubba_commands.c | 93 +++++++++++++++++ board/excito/bubbatwo/bubbatwo.c | 175 ++++++++++++++++++++++++++++++++ board/excito/bubbatwo/bubbatwo.h | 30 ++++++ board/excito/bubbatwo/config.mk | 1 + board/excito/bubbatwo/sdram.c | 167 ++++++++++++++++++++++++++++++ 6 files changed, 516 insertions(+), 0 deletions(-) create mode 100644 board/excito/bubbatwo/Makefile create mode 100644 board/excito/bubbatwo/bubba_commands.c create mode 100644 board/excito/bubbatwo/bubbatwo.c create mode 100644 board/excito/bubbatwo/bubbatwo.h create mode 100644 board/excito/bubbatwo/config.mk create mode 100644 board/excito/bubbatwo/sdram.c
diff --git a/board/excito/bubbatwo/Makefile b/board/excito/bubbatwo/Makefile new file mode 100644 index 0000000..e379e0e --- /dev/null +++ b/board/excito/bubbatwo/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o sdram.o bubba_commands.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/excito/bubbatwo/bubba_commands.c b/board/excito/bubbatwo/bubba_commands.c new file mode 100644 index 0000000..7ac76e4 --- /dev/null +++ b/board/excito/bubbatwo/bubba_commands.c @@ -0,0 +1,93 @@ +/* + * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved. + * Author: Tor Krill tor@excito.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef BUBBA_COMMANDS_H +#define BUBBA_COMMANDS_H + +#include <common.h> +#include <config.h> +#include <command.h> + +#include <mpc83xx.h> + +#include "bubbatwo.h" + +/* Prototypes from sata_sil3114.c */ + +u8 sil3114_spin_up (int num); +u8 sil3114_spin_down (int num); + +static int pollbutton () +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + + return im->gpio[0].dat & BUTTON; +} + +int do_bubbacmd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int ret = 0, dev; + + switch (argc) { + case 0: + case 1: + case 2: + if (strncmp (argv[1], "button", 6) == 0) { + printf ("Button status: %d\n", pollbutton ()); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + break; + case 3: + if (strncmp (argv[1], "spindown", 8) == 0) { + dev = (int)simple_strtoul (argv[2], NULL, 10); + if (dev >= CFG_SATA_MAX_DEVICE) { + puts ("Unknown device\n"); + return 1; + } + ret = sil3114_spin_down (dev); + } else if (strncmp (argv[1], "spinup", 6) == 0) { + dev = (int)simple_strtoul (argv[2], NULL, 10); + if (dev >= CFG_SATA_MAX_DEVICE) { + puts ("Unknown device\n"); + return 1; + } + ret = sil3114_spin_up (dev); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + break; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + return ret; + +} + +U_BOOT_CMD (bubbacmd, 3, 1, do_bubbacmd, + "bubbacmd- Board specific commands for Bubba TWO\n", + "spindown [dev] - spin down disk dev\n" + "bubbacmd spinup [dev] - spin up disk dev\n" + "bubbacmd button - read button status\n"); +#endif diff --git a/board/excito/bubbatwo/bubbatwo.c b/board/excito/bubbatwo/bubbatwo.c new file mode 100644 index 0000000..5975822 --- /dev/null +++ b/board/excito/bubbatwo/bubbatwo.c @@ -0,0 +1,175 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 + * Copyright (C) Excito Elektronik i Skåne, 2008. + * + * Author: Scott Wood scottwood@freescale.com + * Modified for Bubba board: Tor Krill tor@excito.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif +#include <pci.h> +#include <mpc83xx.h> + +#include "bubbatwo.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + +#ifndef CFG_8313ERDB_BROKEN_PMC + if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) + gd->flags |= GD_FLG_SILENT; +#endif + + /* Setup iopins and check button */ + /* Disable open drain on pwr on */ + im->gpio[0].odr &= ~(1 << 0); + /* Set pwr on direction to output */ + im->gpio[0].dir |= (1 << 0); + /* Set HW-ID[0,1,2] and pwr btn to input */ + im->gpio[0].dir &= ~(HW_ID0 | HW_ID1 | HW_ID2 | BUTTON); + /* Set pwr on high */ + im->gpio[0].dat |= (1 << 0); + + /* Program PVM for LED */ + + /* Reset timer 1 and 2 */ + im->gtm[0].cfr1 = 0x00; + /* Enable timer 1, stopped and choose normal operation */ + im->gtm[0].cfr1 = 0x03; + + /* Timer prescaler set to 0x0f + * resulting in a prescale of 0x10 + */ + im->gtm[0].psr1 = 0x0f; + + /* Set prescale value and set restart + * when timer meets reference value + * Use internal system clock*/ + im->gtm[0].mdr1 |= 0x800a; + + /* Set reference value */ + im->gtm[0].rfr1 = 0x8000; + + /* Start timer1 */ + im->gtm[0].cfr1 = 0x01; + + return 0; +} + +int getboardversion (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + int rev = im->gpio[0].dat & (HW_ID0 | HW_ID1 | HW_ID2); + + rev = + ((rev & HW_ID0) >> 3) | ((rev & HW_ID1) >> 2) | ((rev & HW_ID2) << + 1); + + return rev; +} + +int checkboard (void) +{ + printf ("Board: Excito BUBBA|TWO (rev %d)\n", getboardversion ()); + return 0; +} + +static struct pci_region pci_regions[] = { + { + bus_start:CFG_PCI1_MEM_BASE, + phys_start:CFG_PCI1_MEM_PHYS, + size:CFG_PCI1_MEM_SIZE, + flags:PCI_REGION_MEM | PCI_REGION_PREFETCH}, + { + bus_start:CFG_PCI1_MMIO_BASE, + phys_start:CFG_PCI1_MMIO_PHYS, + size:CFG_PCI1_MMIO_SIZE, + flags:PCI_REGION_MEM}, + { + bus_start:CFG_PCI1_IO_BASE, + phys_start:CFG_PCI1_IO_PHYS, + size:CFG_PCI1_IO_SIZE, + flags:PCI_REGION_IO} +}; + +void pci_init_board (void) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; + int warmboot; + + /* Enable all 3 PCI_CLK_OUTPUTs. */ + clk->occr |= 0xe0000000; + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; +#ifndef CFG_8313ERDB_BROKEN_PMC + warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; +#endif + + mpc83xx_pci_init (1, reg, warmboot); +} + +#ifdef CONFIG_FLASH_CFI_LEGACY + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI Spansion S29AL004D flash, 16 bit flash / 16 bit bus. + */ +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; + } else { + return 0; + } +} + +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup (void *blob, bd_t * bd) +{ + ft_cpu_setup (blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup (blob, bd); +#endif +} +#endif diff --git a/board/excito/bubbatwo/bubbatwo.h b/board/excito/bubbatwo/bubbatwo.h new file mode 100644 index 0000000..972819d --- /dev/null +++ b/board/excito/bubbatwo/bubbatwo.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved. + * Author: Tor Krill tor@excito.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* GPIO definitions */ +#define HW_IDMASK 0x07 +#define HW_ID0 (1<<3) +#define HW_ID1 (1<<2) +#define HW_ID2 (1<<0) + +#define BUTTON (1<<1) + +int getboardversion(void); + diff --git a/board/excito/bubbatwo/config.mk b/board/excito/bubbatwo/config.mk new file mode 100644 index 0000000..f768264 --- /dev/null +++ b/board/excito/bubbatwo/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xFE000000 diff --git a/board/excito/bubbatwo/sdram.c b/board/excito/bubbatwo/sdram.c new file mode 100644 index 0000000..5169893 --- /dev/null +++ b/board/excito/bubbatwo/sdram.c @@ -0,0 +1,167 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 + * Copyright (C) Excito Elektronik i Skåne, 2008. + * + * Authors: Nick.Spence@freescale.com + * Wilson.Lo@freescale.com + * scottwood@freescale.com + * tor@excito.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc83xx.h> +#include <spd_sdram.h> + +#include <asm/bitops.h> +#include <asm/io.h> + +#include <asm/processor.h> + +#include "bubbatwo.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CFG_8313ERDB_BROKEN_PMC +static void resume_from_sleep (void) +{ + u32 magic = *(u32 *) 0; + + typedef void (*func_t) (void); + func_t resume = *(func_t *) 4; + + if (magic == 0xf5153ae5) + resume (); + + gd->flags &= ~GD_FLG_SILENT; + puts ("\nResume from sleep failed: bad magic word\n"); +} +#endif + +/* Lookup table for the different boardversions */ +static struct { + u32 memsize; + u32 config; +} meminfo[] = { + /* 0 - revA prototypes */ + { + memsize: 128, config:CFG_DDR_CONFIG_128}, + /* 1 - revB */ + { + memsize: 256, config:CFG_DDR_CONFIG_256}, + /* 2 - empty */ + { + memsize: 128, config:CFG_DDR_CONFIG_128}, + /* 3 - empty */ + { + memsize: 128, config:CFG_DDR_CONFIG_128}, + /* 4 - empty */ + { + memsize: 128, config:CFG_DDR_CONFIG_128}, + /* 5 - empty */ + { + memsize: 128, config:CFG_DDR_CONFIG_128}, + /* 6 - empty */ + { + memsize: 128, config:CFG_DDR_CONFIG_128}, + /* 7 - empty */ + { + memsize: 128, config:CFG_DDR_CONFIG_128} +}; + +/* Fixed sdram init -- doesn't use serial presence detect. + * + * This is useful for faster booting in configs where the RAM is unlikely + * to be changed, or for things like NAND booting where space is tight. + */ +static long fixed_sdram (void) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + int bver = getboardversion () & HW_IDMASK; + u32 msize = meminfo[bver].memsize * 1024 * 1024; + u32 msize_log2 = __ilog2 (msize); + + im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; + im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); + im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + + /* + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], + * or the DDR2 controller may fail to initialize correctly. + */ + udelay (50000); + + im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; + im->ddr.cs_config[0] = meminfo[bver].config; + + /* Currently we use only one CS, so disable the other bank. */ + im->ddr.cs_config[1] = 0; + + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + +#ifndef CFG_8313ERDB_BROKEN_PMC + if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) + im->ddr.sdram_cfg = CFG_SDRAM_CFG | SDRAM_CFG_BI; + else +#endif + im->ddr.sdram_cfg = CFG_SDRAM_CFG; + + im->ddr.sdram_cfg2 = CFG_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE_2; + + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + sync (); + + /* enable DDR controller */ + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + return msize; +} + +long int initdram (int board_type) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile lbus83xx_t *lbc = &im->lbus; + u32 msize; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + msize = fixed_sdram (); + + /* Local Bus setup lbcr and mrtpr */ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + sync (); + +#ifndef CFG_8313ERDB_BROKEN_PMC + if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) + resume_from_sleep (); +#endif + + /* return total bus SDRAM size(bytes) -- DDR */ + return msize; +}
On Mon, 2 Jun 2008 15:16:02 +0200 Tor Krill tor@excito.com wrote:
+U_BOOT_CMD (bubbacmd, 3, 1, do_bubbacmd,
"bubbacmd- Board specific commands for Bubba TWO\n","spindown [dev] - spin down disk dev\n""bubbacmd spinup [dev] - spin up disk dev\n""bubbacmd button - read button status\n");+#endif
I the spinup/spindown commands should be part of cmd_ide, no? Or rather, should they be eliminated in favour of "Das U-Boot way" of only powering up devices when accesses are requested? i.e, power up on a disk read command and power down after it's done?
btw, this also prevents me from applying this board support patch because of the sata_sil3114 driver dependency here.
+int getboardversion (void) +{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
- int rev = im->gpio[0].dat & (HW_ID0 | HW_ID1 | HW_ID2);
looks like the and op is unnecessary here..plus we're not doing volatile i/o accesses any more - use {in,out}_be32(), {set,clr}bits32() etc., this occurs many other places in this patch..
- rev =
((rev & HW_ID0) >> 3) | ((rev & HW_ID1) >> 2) | ((rev & HW_ID2) <<1);- return rev;
+}
return ((rev & HW_ID0) >> 3) | ((rev & HW_ID1) >> 2) | ((rev & HW_ID2) << 1);
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{
- if (banknum == 0) { /* non-CFI boot flash */
info->portwidth = FLASH_CFI_16BIT;info->chipwidth = FLASH_CFI_BY16;info->interface = FLASH_CFI_X16;return 1;- } else {
return 0;- }
else is superfluous
+/* Lookup table for the different boardversions */ +static struct {
- u32 memsize;
- u32 config;
+} meminfo[] = {
- /* 0 - revA prototypes */
- {
memsize: 128, config:CFG_DDR_CONFIG_128},- /* 1 - revB */
- {
memsize: 256, config:CFG_DDR_CONFIG_256},- /* 2 - empty */
- {
memsize: 128, config:CFG_DDR_CONFIG_128},- /* 3 - empty */
- {
memsize: 128, config:CFG_DDR_CONFIG_128},- /* 4 - empty */
- {
memsize: 128, config:CFG_DDR_CONFIG_128},- /* 5 - empty */
- {
memsize: 128, config:CFG_DDR_CONFIG_128},- /* 6 - empty */
- {
memsize: 128, config:CFG_DDR_CONFIG_128},- /* 7 - empty */
- {
memsize: 128, config:CFG_DDR_CONFIG_128}+};
would something like this be neater:
{ 128, CFG_DDR_CONFIG_128 }, /* 7 - empty */
?
Kim
Hi Tor,
These patches add support for the mpc8313 based BUBBATWO board.
Signed-off-by: Tor Krill tor@excito.com
MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + include/configs/BUBBATWO.h | 516 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 524 insertions(+), 0 deletions(-) create mode 100644 include/configs/BUBBATWO.h
diff --git a/MAINTAINERS b/MAINTAINERS index ac7572c..c188728 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -224,6 +224,10 @@ Sangmoon Kim dogoil@etinsys.com debris MPC8245 KVME080 MPC8245
+Tor Krill tor@excito.com
- BUBBATWO MPC8313
Thomas Lange thomas@corelatus.se
GTH MPC860 diff --git a/MAKEALL b/MAKEALL index 0674069..da28c7a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -332,6 +332,7 @@ LIST_83xx=" \ MPC837XERDB \ sbc8349 \ TQM834x \
- BUBBATWO \
"
Did you notice any unsorted list in MAKEALL? See?
diff --git a/Makefile b/Makefile index 3401203..93f563f 100644 --- a/Makefile +++ b/Makefile @@ -1993,6 +1993,9 @@ MPC8313ERDB_66_config: unconfig fi ; @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
+BUBBATWO_config: unconfig
- @$(MKCONFIG) BUBBATWO ppc mpc83xx bubbatwo excito
MPC8315ERDB_config: unconfig @$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
Although not every section is sorted, I'd vote also to use sorting here, simply to make such a large file more transparent.
diff --git a/include/configs/BUBBATWO.h b/include/configs/BUBBATWO.h new file mode 100644 index 0000000..4e27c6f --- /dev/null +++ b/include/configs/BUBBATWO.h @@ -0,0 +1,516 @@ +/*
- Copyright (C) Freescale Semiconductor, Inc. 2006.
- Copyright (C) Excito Elektronik i Skåne, 2008.
[...]
+#define CONFIG_ETHADDR 00:22:02:00:95:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH0 +#define CONFIG_ETH1ADDR 00:22:02:00:95:02
Having MAC-Addresses in U-Boot proper is considered to be a bug. See the long list of mails on this topic...
Cheers Detlev
participants (3)
-
Detlev Zundel -
Kim Phillips -
Tor Krill