[PATCH 1/6] arm: Remove flea3 board
This board has not been converted to CONFIG_DM by the deadline. Remove it.
Cc: Stefano Babic sbabic@denx.de Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/Kconfig | 6 - board/CarMediaLab/flea3/Kconfig | 15 -- board/CarMediaLab/flea3/MAINTAINERS | 6 - board/CarMediaLab/flea3/Makefile | 8 - board/CarMediaLab/flea3/flea3.c | 227 ------------------------ board/CarMediaLab/flea3/lowlevel_init.S | 24 --- configs/flea3_defconfig | 58 ------ drivers/serial/Kconfig | 3 +- include/configs/flea3.h | 155 ---------------- 9 files changed, 1 insertion(+), 501 deletions(-) delete mode 100644 board/CarMediaLab/flea3/Kconfig delete mode 100644 board/CarMediaLab/flea3/MAINTAINERS delete mode 100644 board/CarMediaLab/flea3/Makefile delete mode 100644 board/CarMediaLab/flea3/flea3.c delete mode 100644 board/CarMediaLab/flea3/lowlevel_init.S delete mode 100644 configs/flea3_defconfig delete mode 100644 include/configs/flea3.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 21f17c202f6c..909a308970b7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -568,11 +568,6 @@ config TARGET_STV0991 select SPI_FLASH imply CMD_DM
-config TARGET_FLEA3 - bool "Support flea3" - select CPU_ARM1136 - select GPIO_EXTRA_HEADER - config ARCH_BCM283X bool "Broadcom BCM283X family" select DM @@ -2107,7 +2102,6 @@ source "board/armltd/total_compute/Kconfig"
source "board/bosch/shc/Kconfig" source "board/bosch/guardian/Kconfig" -source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" source "board/Marvell/octeontx/Kconfig" source "board/Marvell/octeontx2/Kconfig" diff --git a/board/CarMediaLab/flea3/Kconfig b/board/CarMediaLab/flea3/Kconfig deleted file mode 100644 index 7113f2b51f6a..000000000000 --- a/board/CarMediaLab/flea3/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_FLEA3 - -config SYS_BOARD - default "flea3" - -config SYS_VENDOR - default "CarMediaLab" - -config SYS_SOC - default "mx35" - -config SYS_CONFIG_NAME - default "flea3" - -endif diff --git a/board/CarMediaLab/flea3/MAINTAINERS b/board/CarMediaLab/flea3/MAINTAINERS deleted file mode 100644 index c7b0df7bc429..000000000000 --- a/board/CarMediaLab/flea3/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -FLEA3 BOARD -M: Stefano Babic sbabic@denx.de -S: Maintained -F: board/CarMediaLab/flea3/ -F: include/configs/flea3.h -F: configs/flea3_defconfig diff --git a/board/CarMediaLab/flea3/Makefile b/board/CarMediaLab/flea3/Makefile deleted file mode 100644 index edaac8683b36..000000000000 --- a/board/CarMediaLab/flea3/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de -# -# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - -obj-y := flea3.o -obj-y += lowlevel_init.o diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c deleted file mode 100644 index ecd70ecbdc41..000000000000 --- a/board/CarMediaLab/flea3/flea3.c +++ /dev/null @@ -1,227 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011, Stefano Babic sbabic@denx.de - */ - -#include <common.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <env.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/iomux-mx35.h> -#include <i2c.h> -#include <linux/types.h> -#include <asm/gpio.h> -#include <asm/arch/sys_proto.h> -#include <netdev.h> -#include <fdt_support.h> -#include <mtd_node.h> -#include <jffs2/load_kernel.h> - -#ifndef CONFIG_BOARD_EARLY_INIT_F -#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" -#endif - -#define CCM_CCMR_CONFIG 0x003F4208 - -#define ESDCTL_DDR2_CONFIG 0x007FFC3F - -static inline void dram_wait(unsigned int count) -{ - volatile unsigned int wait = count; - - while (wait--) - ; -} - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - - return 0; -} - -static void board_setup_sdram(void) -{ - struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; - - /* Initialize with default values both CSD0/1 */ - writel(0x2000, &esdc->esdctl0); - writel(0x2000, &esdc->esdctl1); - - - mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG, - 13, 10, 2, 0x8080); -} - -static void setup_iomux_uart3(void) -{ - static const iomux_v3_cfg_t uart3_pads[] = { - MX35_PAD_RTS2__UART3_RXD_MUX, - MX35_PAD_CTS2__UART3_TXD_MUX, - }; - - imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); -} - -#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE) - -static void setup_iomux_i2c(void) -{ - static const iomux_v3_cfg_t i2c_pads[] = { - NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL), - - NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); -} - - -static void setup_iomux_spi(void) -{ - static const iomux_v3_cfg_t spi_pads[] = { - MX35_PAD_CSPI1_MOSI__CSPI1_MOSI, - MX35_PAD_CSPI1_MISO__CSPI1_MISO, - MX35_PAD_CSPI1_SS0__CSPI1_SS0, - MX35_PAD_CSPI1_SS1__CSPI1_SS1, - MX35_PAD_CSPI1_SCLK__CSPI1_SCLK, - }; - - imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); -} - -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* GPIO used to power off ethernet */ - MX35_PAD_STXFS4__GPIO2_31, - }; - - /* setup pins for FEC */ - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -int board_early_init_f(void) -{ - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - - /* setup GPIO3_1 to set HighVCore signal */ - imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1); - gpio_direction_output(65, 1); - - /* initialize PLL and clock configuration */ - writel(CCM_CCMR_CONFIG, &ccm->ccmr); - - writel(CCM_MPLL_532_HZ, &ccm->mpctl); - writel(CCM_PPLL_300_HZ, &ccm->ppctl); - - /* Set the core to run at 532 Mhz */ - writel(0x00001000, &ccm->pdr0); - - /* Set-up RAM */ - board_setup_sdram(); - - /* enable clocks */ - writel(readl(&ccm->cgr0) | - MXC_CCM_CGR0_EMI_MASK | - MXC_CCM_CGR0_EDIO_MASK | - MXC_CCM_CGR0_EPIT1_MASK, - &ccm->cgr0); - - writel(readl(&ccm->cgr1) | - MXC_CCM_CGR1_FEC_MASK | - MXC_CCM_CGR1_GPIO1_MASK | - MXC_CCM_CGR1_GPIO2_MASK | - MXC_CCM_CGR1_GPIO3_MASK | - MXC_CCM_CGR1_I2C1_MASK | - MXC_CCM_CGR1_I2C2_MASK | - MXC_CCM_CGR1_I2C3_MASK, - &ccm->cgr1); - - /* Set-up NAND */ - __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); - - /* Set pinmux for the required peripherals */ - setup_iomux_uart3(); - setup_iomux_i2c(); - setup_iomux_fec(); - setup_iomux_spi(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - /* Enable power for ethernet */ - gpio_direction_output(63, 0); - - udelay(2000); - - return 0; -} - -#ifdef CONFIG_REVISION_TAG -u32 get_board_rev(void) -{ - int rev = 0; - - return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; -} -#endif - -/* - * called prior to booting kernel or by 'fdt boardsetup' command - * - */ -int ft_board_setup(void *blob, struct bd_info *bd) -{ - static const struct node_info nodes[] = { - { "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */ - { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ - }; - - if (env_get("fdt_noauto")) { - puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); - return 0; - } - - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); - - return 0; -} diff --git a/board/CarMediaLab/flea3/lowlevel_init.S b/board/CarMediaLab/flea3/lowlevel_init.S deleted file mode 100644 index 8186b3922bad..000000000000 --- a/board/CarMediaLab/flea3/lowlevel_init.S +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011, Stefano Babic sbabic@denx.de - */ - -#include <config.h> -#include <asm/arch/lowlevel_macro.S> - -.globl lowlevel_init -lowlevel_init: - - core_init - - init_aips - - init_max - - init_m3if - - mov pc, lr diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig deleted file mode 100644 index 81e291a94160..000000000000 --- a/configs/flea3_defconfig +++ /dev/null @@ -1,58 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_TARGET_FLEA3=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_MALLOC_LEN=0x110000 -CONFIG_SYS_LOAD_ADDR=0x80800000 -CONFIG_FIT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="flea3 U-Boot > " -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xA0080000 -CONFIG_ENV_ADDR_REDUND=0xA0090000 -CONFIG_MXC_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_MXC=y -CONFIG_SYS_MXC_I2C3_SLAVE=0xfe -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ8XXX=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 36ee43210a9f..cbea165b9d54 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -645,8 +645,7 @@ config MCFUART
config MXC_UART bool "IMX serial port support" - depends on ARCH_MX25 || ARCH_MX31 || TARGET_FLEA3 \ - || MX5 || MX6 || MX7 || IMX8M + depends on ARCH_MX25 || ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M help If you have a machine based on a Motorola IMX CPU you can enable its onboard serial port by enabling this option. diff --git a/include/configs/flea3.h b/include/configs/flea3.h deleted file mode 100644 index 6c3b2c4bf554..000000000000 --- a/include/configs/flea3.h +++ /dev/null @@ -1,155 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011, Stefano Babic sbabic@denx.de - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de - * - * Configuration for the flea3 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - - /* High Level Configuration Options */ -#define CONFIG_MX35 - -/* Set TEXT at the beginning of the NOR flash */ - -/* This is required to setup the ESDC controller */ - -/* - * Hardware drivers - */ -#define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */ - -/* - * UART (console) - */ -#define CONFIG_MXC_UART_BASE UART3_BASE - -/* - * Command definition - */ - -#define CONFIG_NET_RETRY_COUNT 100 - -/* - * Ethernet on SOC (FEC) - */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1 - -#define CONFIG_ARP_TIMEOUT 200UL - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/* - * MTD Command for mtdparts - */ - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -/* Address and size of Redundant Environment Sector */ - -/* - * CFI FLASH driver setup - */ - -/* A non-standard buffered write algorithm */ - -/* - * NAND FLASH driver setup - */ -#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE - -/* - * Default environment and default scripts - * to update uboot and load kernel - */ - -#define CONFIG_HOSTNAME "flea3" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip_sta=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test -n ${ipdyn};then run addip_dyn;" \ - "else run addip_sta;fi\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc2,${baudrate}\0" \ - "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ - "loadaddr=80800000\0" \ - "kernel_addr_r=80800000\0" \ - "hostname=" CONFIG_HOSTNAME "\0" \ - "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ - "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ - "net_self=if run net_self_load;then " \ - "run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ - "else echo Images not loades;fi\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ - "update=protect off ${uboot_addr} +80000;" \ - "erase ${uboot_addr} +80000;" \ - "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ - "upd=if run load;then echo Updating u-boot;if run update;" \ - "then echo U-Boot updated;" \ - "else echo Error updating u-boot !;" \ - "echo Board without bootloader !!;" \ - "fi;" \ - "else echo U-Boot not downloaded..exiting;fi\0" \ - "bootcmd=run net_nfs\0" - -#endif /* __CONFIG_H */
This board has not been converted to CONFIG_DM by the deadline. Remove it.
Cc: Prafulla Wadaskar prafulla@marvell.com Cc: Stefan Roese sr@denx.de Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/Kconfig | 6 ---- board/Marvell/aspenite/Kconfig | 15 ---------- board/Marvell/aspenite/MAINTAINERS | 6 ---- board/Marvell/aspenite/Makefile | 8 ------ board/Marvell/aspenite/aspenite.c | 45 ------------------------------ configs/aspenite_defconfig | 19 ------------- drivers/mmc/mv_sdhci.c | 24 ---------------- include/configs/aspenite.h | 30 -------------------- 8 files changed, 153 deletions(-) delete mode 100644 board/Marvell/aspenite/Kconfig delete mode 100644 board/Marvell/aspenite/MAINTAINERS delete mode 100644 board/Marvell/aspenite/Makefile delete mode 100644 board/Marvell/aspenite/aspenite.c delete mode 100644 configs/aspenite_defconfig delete mode 100644 include/configs/aspenite.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 909a308970b7..9ef4f6519826 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -514,11 +514,6 @@ config ARCH_AT91 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB select SPL_SEPARATE_BSS if SPL
-config TARGET_ASPENITE - bool "Support aspenite" - select CPU_ARM926EJS - select GPIO_EXTRA_HEADER - config ARCH_DAVINCI bool "TI DaVinci" select CPU_ARM926EJS @@ -2102,7 +2097,6 @@ source "board/armltd/total_compute/Kconfig"
source "board/bosch/shc/Kconfig" source "board/bosch/guardian/Kconfig" -source "board/Marvell/aspenite/Kconfig" source "board/Marvell/octeontx/Kconfig" source "board/Marvell/octeontx2/Kconfig" source "board/armltd/vexpress64/Kconfig" diff --git a/board/Marvell/aspenite/Kconfig b/board/Marvell/aspenite/Kconfig deleted file mode 100644 index 4dd49c4452b9..000000000000 --- a/board/Marvell/aspenite/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_ASPENITE - -config SYS_BOARD - default "aspenite" - -config SYS_VENDOR - default "Marvell" - -config SYS_SOC - default "armada100" - -config SYS_CONFIG_NAME - default "aspenite" - -endif diff --git a/board/Marvell/aspenite/MAINTAINERS b/board/Marvell/aspenite/MAINTAINERS deleted file mode 100644 index a77d30eb78ce..000000000000 --- a/board/Marvell/aspenite/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ASPENITE BOARD -M: Prafulla Wadaskar prafulla@marvell.com -S: Maintained -F: board/Marvell/aspenite/ -F: include/configs/aspenite.h -F: configs/aspenite_defconfig diff --git a/board/Marvell/aspenite/Makefile b/board/Marvell/aspenite/Makefile deleted file mode 100644 index f67a978a12bc..000000000000 --- a/board/Marvell/aspenite/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2010 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com -# Contributor: Mahavir Jain mjain@marvell.com - -obj-y := aspenite.o diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c deleted file mode 100644 index 1f9389c0a7ab..000000000000 --- a/board/Marvell/aspenite/aspenite.c +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * Contributor: Mahavir Jain mjain@marvell.com - */ - -#include <common.h> -#include <init.h> -#include <mvmfp.h> -#include <asm/global_data.h> -#include <asm/mach-types.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mfp.h> -#include <asm/arch/armada100.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - u32 mfp_cfg[] = { - /* I2C */ - MFP105_CI2C_SDA, - MFP106_CI2C_SCL, - - /* Enable Console on UART1 */ - MFP107_UART1_RXD, - MFP108_UART1_TXD, - - MFP_EOC /*End of configureation*/ - }; - /* configure MFP's */ - mfp_config(mfp_cfg); - return 0; -} - -int board_init(void) -{ - /* arch number of Board */ - gd->bd->bi_arch_number = MACH_TYPE_ASPENITE; - /* adress of boot parameters */ - gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; - return 0; -} diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig deleted file mode 100644 index b85f7241b61d..000000000000 --- a/configs/aspenite_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_TARGET_ASPENITE=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x20000 -CONFIG_IDENT_STRING="\nMarvell-Aspenite DB" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -# CONFIG_NET is not set -# CONFIG_MMC is not set -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index 591137f50e39..336ebf141026 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -44,29 +44,6 @@ static void sdhci_mvebu_mbus_config(void __iomem *base)
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS static struct sdhci_ops mv_ops; - -#if defined(CONFIG_SHEEVA_88SV331xV5) -#define SD_CE_ATA_2 0xEA -#define MMC_CARD 0x1000 -#define MMC_WIDTH 0x0100 -static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) -{ - struct mmc *mmc = host->mmc; - u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2; - - if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) { - if (mmc->bus_width == 8) - writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata); - else - writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata); - } - - writeb(val, host->ioaddr + reg); -} - -#else -#define mv_sdhci_writeb NULL -#endif /* CONFIG_SHEEVA_88SV331xV5 */ #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) @@ -84,7 +61,6 @@ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) host->max_clk = max_clk; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS memset(&mv_ops, 0, sizeof(struct sdhci_ops)); - mv_ops.write_b = mv_sdhci_writeb; host->ops = &mv_ops; #endif
diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h deleted file mode 100644 index 4a25d5616531..000000000000 --- a/include/configs/aspenite.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * Contributor: Mahavir Jain mjain@marvell.com - */ - -#ifndef __CONFIG_ASPENITE_H -#define __CONFIG_ASPENITE_H - -/* - * High Level Configuration Options - */ -#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ -#define CONFIG_ARMADA100 1 /* SOC Family Name */ - -/* - * There is no internal RAM in ARMADA100, using DRAM - * TBD: dcache to be used for this - */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) - -#include "mv-common.h" - -/* - * Environment variables configurations - */ - -#endif /* __CONFIG_ASPENITE_H */
On 09.09.21 13:54, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline. Remove it.
Cc: Prafulla Wadaskar prafulla@marvell.com Cc: Stefan Roese sr@denx.de Signed-off-by: Tom Rini trini@konsulko.com
Acked-by: Stefan Roese sr@denx.de
Thanks, Stefan
arch/arm/Kconfig | 6 ---- board/Marvell/aspenite/Kconfig | 15 ---------- board/Marvell/aspenite/MAINTAINERS | 6 ---- board/Marvell/aspenite/Makefile | 8 ------ board/Marvell/aspenite/aspenite.c | 45 ------------------------------ configs/aspenite_defconfig | 19 ------------- drivers/mmc/mv_sdhci.c | 24 ---------------- include/configs/aspenite.h | 30 -------------------- 8 files changed, 153 deletions(-) delete mode 100644 board/Marvell/aspenite/Kconfig delete mode 100644 board/Marvell/aspenite/MAINTAINERS delete mode 100644 board/Marvell/aspenite/Makefile delete mode 100644 board/Marvell/aspenite/aspenite.c delete mode 100644 configs/aspenite_defconfig delete mode 100644 include/configs/aspenite.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 909a308970b7..9ef4f6519826 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -514,11 +514,6 @@ config ARCH_AT91 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB select SPL_SEPARATE_BSS if SPL
-config TARGET_ASPENITE
- bool "Support aspenite"
- select CPU_ARM926EJS
- select GPIO_EXTRA_HEADER
- config ARCH_DAVINCI bool "TI DaVinci" select CPU_ARM926EJS
@@ -2102,7 +2097,6 @@ source "board/armltd/total_compute/Kconfig"
source "board/bosch/shc/Kconfig" source "board/bosch/guardian/Kconfig" -source "board/Marvell/aspenite/Kconfig" source "board/Marvell/octeontx/Kconfig" source "board/Marvell/octeontx2/Kconfig" source "board/armltd/vexpress64/Kconfig" diff --git a/board/Marvell/aspenite/Kconfig b/board/Marvell/aspenite/Kconfig deleted file mode 100644 index 4dd49c4452b9..000000000000 --- a/board/Marvell/aspenite/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_ASPENITE
-config SYS_BOARD
- default "aspenite"
-config SYS_VENDOR
- default "Marvell"
-config SYS_SOC
- default "armada100"
-config SYS_CONFIG_NAME
- default "aspenite"
-endif diff --git a/board/Marvell/aspenite/MAINTAINERS b/board/Marvell/aspenite/MAINTAINERS deleted file mode 100644 index a77d30eb78ce..000000000000 --- a/board/Marvell/aspenite/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ASPENITE BOARD -M: Prafulla Wadaskar prafulla@marvell.com -S: Maintained -F: board/Marvell/aspenite/ -F: include/configs/aspenite.h -F: configs/aspenite_defconfig diff --git a/board/Marvell/aspenite/Makefile b/board/Marvell/aspenite/Makefile deleted file mode 100644 index f67a978a12bc..000000000000 --- a/board/Marvell/aspenite/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2010 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com -# Contributor: Mahavir Jain mjain@marvell.com
-obj-y := aspenite.o diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c deleted file mode 100644 index 1f9389c0a7ab..000000000000 --- a/board/Marvell/aspenite/aspenite.c +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- (C) Copyright 2010
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- Contributor: Mahavir Jain mjain@marvell.com
- */
-#include <common.h> -#include <init.h> -#include <mvmfp.h> -#include <asm/global_data.h> -#include <asm/mach-types.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mfp.h> -#include <asm/arch/armada100.h>
-DECLARE_GLOBAL_DATA_PTR;
-int board_early_init_f(void) -{
- u32 mfp_cfg[] = {
/* I2C */MFP105_CI2C_SDA,MFP106_CI2C_SCL,/* Enable Console on UART1 */MFP107_UART1_RXD,MFP108_UART1_TXD,MFP_EOC /*End of configureation*/- };
- /* configure MFP's */
- mfp_config(mfp_cfg);
- return 0;
-}
-int board_init(void) -{
- /* arch number of Board */
- gd->bd->bi_arch_number = MACH_TYPE_ASPENITE;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
- return 0;
-} diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig deleted file mode 100644 index b85f7241b61d..000000000000 --- a/configs/aspenite_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_TARGET_ASPENITE=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x20000 -CONFIG_IDENT_STRING="\nMarvell-Aspenite DB" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -# CONFIG_NET is not set -# CONFIG_MMC is not set -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index 591137f50e39..336ebf141026 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -44,29 +44,6 @@ static void sdhci_mvebu_mbus_config(void __iomem *base)
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS static struct sdhci_ops mv_ops;
-#if defined(CONFIG_SHEEVA_88SV331xV5) -#define SD_CE_ATA_2 0xEA -#define MMC_CARD 0x1000 -#define MMC_WIDTH 0x0100 -static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) -{
- struct mmc *mmc = host->mmc;
- u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2;
- if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
if (mmc->bus_width == 8)writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata);elsewritew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata);- }
- writeb(val, host->ioaddr + reg);
-}
-#else -#define mv_sdhci_writeb NULL -#endif /* CONFIG_SHEEVA_88SV331xV5 */ #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) @@ -84,7 +61,6 @@ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) host->max_clk = max_clk; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS memset(&mv_ops, 0, sizeof(struct sdhci_ops));
- mv_ops.write_b = mv_sdhci_writeb; host->ops = &mv_ops; #endif
diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h deleted file mode 100644 index 4a25d5616531..000000000000 --- a/include/configs/aspenite.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- (C) Copyright 2010
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- Contributor: Mahavir Jain mjain@marvell.com
- */
-#ifndef __CONFIG_ASPENITE_H -#define __CONFIG_ASPENITE_H
-/*
- High Level Configuration Options
- */
-#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ -#define CONFIG_ARMADA100 1 /* SOC Family Name */
-/*
- There is no internal RAM in ARMADA100, using DRAM
- TBD: dcache to be used for this
- */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
-#include "mv-common.h"
-/*
- Environment variables configurations
- */
-#endif /* __CONFIG_ASPENITE_H */
Viele Grüße, Stefan
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last ARCH_MX25 platform, remove those references as well.
Cc: Matthias Weisser weisserm@arcor.de Cc: Stefano Babic sbabic@denx.de Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/Kconfig | 9 - arch/arm/include/asm/arch-mx25/clock.h | 57 --- arch/arm/include/asm/arch-mx25/gpio.h | 13 - arch/arm/include/asm/arch-mx25/imx-regs.h | 504 ------------------ arch/arm/include/asm/arch-mx25/iomux-mx25.h | 537 -------------------- arch/arm/include/asm/arch-mx25/macro.h | 90 ---- arch/arm/mach-imx/mx2/Kconfig | 23 - board/syteco/zmx25/Kconfig | 15 - board/syteco/zmx25/MAINTAINERS | 6 - board/syteco/zmx25/Makefile | 7 - board/syteco/zmx25/lowlevel_init.S | 96 ---- board/syteco/zmx25/zmx25.c | 178 ------- configs/zmx25_defconfig | 38 -- drivers/serial/Kconfig | 2 +- drivers/w1/Kconfig | 2 +- drivers/watchdog/Kconfig | 2 +- include/configs/zmx25.h | 78 --- 17 files changed, 3 insertions(+), 1654 deletions(-) delete mode 100644 arch/arm/include/asm/arch-mx25/clock.h delete mode 100644 arch/arm/include/asm/arch-mx25/gpio.h delete mode 100644 arch/arm/include/asm/arch-mx25/imx-regs.h delete mode 100644 arch/arm/include/asm/arch-mx25/iomux-mx25.h delete mode 100644 arch/arm/include/asm/arch-mx25/macro.h delete mode 100644 arch/arm/mach-imx/mx2/Kconfig delete mode 100644 board/syteco/zmx25/Kconfig delete mode 100644 board/syteco/zmx25/MAINTAINERS delete mode 100644 board/syteco/zmx25/Makefile delete mode 100644 board/syteco/zmx25/lowlevel_init.S delete mode 100644 board/syteco/zmx25/zmx25.c delete mode 100644 configs/zmx25_defconfig delete mode 100644 include/configs/zmx25.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9ef4f6519826..70ab47cce056 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -812,13 +812,6 @@ config ARCH_MX23 select PL011_SERIAL select SUPPORT_SPL
-config ARCH_MX25 - bool "NXP MX25" - select CPU_ARM926EJS - select GPIO_EXTRA_HEADER - select MACH_IMX - imply MXC_GPIO - config ARCH_MX28 bool "NXP i.MX28 family" select CPU_ARM926EJS @@ -2015,8 +2008,6 @@ source "arch/arm/mach-octeontx2/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
-source "arch/arm/mach-imx/mx2/Kconfig" - source "arch/arm/mach-imx/mx3/Kconfig"
source "arch/arm/mach-imx/mx5/Kconfig" diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h deleted file mode 100644 index 3045b78d08f4..000000000000 --- a/arch/arm/include/asm/arch-mx25/clock.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * (c) 2009 Ilya Yanok, Emcraft Systems yanok@emcraft.com - * - * Modified for mx25 by John Rigby jrigby@gmail.com - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#ifdef CONFIG_MX25_HCLK_FREQ -#define MXC_HCLK CONFIG_MX25_HCLK_FREQ -#else -#define MXC_HCLK 24000000 -#endif - -#ifdef CONFIG_MX25_CLK32 -#define MXC_CLK32 CONFIG_MX25_CLK32 -#else -#define MXC_CLK32 32768 -#endif - -enum mxc_clock { - /* PER clocks (do not change order) */ - MXC_CSI_CLK, - MXC_EPIT_CLK, - MXC_ESAI_CLK, - MXC_ESDHC1_CLK, - MXC_ESDHC2_CLK, - MXC_GPT_CLK, - MXC_I2C_CLK, - MXC_LCDC_CLK, - MXC_NFC_CLK, - MXC_OWIRE_CLK, - MXC_PWM_CLK, - MXC_SIM1_CLK, - MXC_SIM2_CLK, - MXC_SSI1_CLK, - MXC_SSI2_CLK, - MXC_UART_CLK, - /* Other clocks */ - MXC_ARM_CLK, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_CSPI_CLK, - MXC_FEC_CLK, - MXC_CLK_NUM -}; - -int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq); -unsigned int mxc_get_clock(enum mxc_clock clk); - -#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK) -#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx25/gpio.h b/arch/arm/include/asm/arch-mx25/gpio.h deleted file mode 100644 index 1205695ce054..000000000000 --- a/arch/arm/include/asm/arch-mx25/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de - */ - - -#ifndef __ASM_ARCH_MX25_GPIO_H -#define __ASM_ARCH_MX25_GPIO_H - -#include <asm/mach-imx/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h deleted file mode 100644 index 57809697c1a8..000000000000 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ /dev/null @@ -1,504 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009, DENX Software Engineering - * Author: John Rigby <jcrigby@gmail.com - * - * Based on arch-mx31/imx-regs.h - * Copyright (C) 2009 Ilya Yanok, - * Emcraft Systems yanok@emcraft.com - * and arch-mx27/imx-regs.h - * Copyright (C) 2007 Pengutronix, - * Sascha Hauer s.hauer@pengutronix.de - * Copyright (C) 2009 Ilya Yanok, - * Emcraft Systems yanok@emcraft.com - */ - -#ifndef _IMX_REGS_H -#define _IMX_REGS_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* Clock Control Module (CCM) registers */ -struct ccm_regs { - u32 mpctl; /* Core PLL Control */ - u32 upctl; /* USB PLL Control */ - u32 cctl; /* Clock Control */ - u32 cgr0; /* Clock Gating Control 0 */ - u32 cgr1; /* Clock Gating Control 1 */ - u32 cgr2; /* Clock Gating Control 2 */ - u32 pcdr[4]; /* PER Clock Dividers */ - u32 rcsr; /* CCM Status */ - u32 crdr; /* CCM Reset and Debug */ - u32 dcvr0; /* DPTC Comparator Value 0 */ - u32 dcvr1; /* DPTC Comparator Value 1 */ - u32 dcvr2; /* DPTC Comparator Value 2 */ - u32 dcvr3; /* DPTC Comparator Value 3 */ - u32 ltr0; /* Load Tracking 0 */ - u32 ltr1; /* Load Tracking 1 */ - u32 ltr2; /* Load Tracking 2 */ - u32 ltr3; /* Load Tracking 3 */ - u32 ltbr0; /* Load Tracking Buffer 0 */ - u32 ltbr1; /* Load Tracking Buffer 1 */ - u32 pcmr0; /* Power Management Control 0 */ - u32 pcmr1; /* Power Management Control 1 */ - u32 pcmr2; /* Power Management Control 2 */ - u32 mcr; /* Miscellaneous Control */ - u32 lpimr0; /* Low Power Interrupt Mask 0 */ - u32 lpimr1; /* Low Power Interrupt Mask 1 */ -}; - -/* Enhanced SDRAM Controller (ESDRAMC) registers */ -struct esdramc_regs { - u32 ctl0; /* control 0 */ - u32 cfg0; /* configuration 0 */ - u32 ctl1; /* control 1 */ - u32 cfg1; /* configuration 1 */ - u32 misc; /* miscellaneous */ - u32 pad[3]; - u32 cdly1; /* Delay Line 1 configuration debug */ - u32 cdly2; /* delay line 2 configuration debug */ - u32 cdly3; /* delay line 3 configuration debug */ - u32 cdly4; /* delay line 4 configuration debug */ - u32 cdly5; /* delay line 5 configuration debug */ - u32 cdlyl; /* delay line cycle length debug */ -}; - -/* General Purpose Timer (GPT) registers */ -struct gpt_regs { - u32 ctrl; /* control */ - u32 pre; /* prescaler */ - u32 stat; /* status */ - u32 intr; /* interrupt */ - u32 cmp[3]; /* output compare 1-3 */ - u32 capt[2]; /* input capture 1-2 */ - u32 counter; /* counter */ -}; - -/* Watchdog Timer (WDOG) registers */ -struct wdog_regs { - u16 wcr; /* Control */ - u16 wsr; /* Service */ - u16 wrsr; /* Reset Status */ - u16 wicr; /* Interrupt Control */ - u16 wmcr; /* Misc Control */ -}; - -/* IIM control registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prg_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res1[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; - } bank[3]; -}; - -struct fuse_bank0_regs { - u32 fuse0_7[8]; - u32 uid[8]; - u32 fuse16_25[0xa]; - u32 mac_addr[6]; -}; - -struct fuse_bank1_regs { - u32 fuse0_21[0x16]; - u32 usr5; - u32 fuse23_29[7]; - u32 usr6[2]; -}; - -/* Multi-Layer AHB Crossbar Switch (MAX) registers */ -struct max_regs { - u32 mpr0; - u32 pad00[3]; - u32 sgpcr0; - u32 pad01[59]; - u32 mpr1; - u32 pad02[3]; - u32 sgpcr1; - u32 pad03[59]; - u32 mpr2; - u32 pad04[3]; - u32 sgpcr2; - u32 pad05[59]; - u32 mpr3; - u32 pad06[3]; - u32 sgpcr3; - u32 pad07[59]; - u32 mpr4; - u32 pad08[3]; - u32 sgpcr4; - u32 pad09[251]; - u32 mgpcr0; - u32 pad10[63]; - u32 mgpcr1; - u32 pad11[63]; - u32 mgpcr2; - u32 pad12[63]; - u32 mgpcr3; - u32 pad13[63]; - u32 mgpcr4; -}; - -/* AHB <-> IP-Bus Interface (AIPS) */ -struct aips_regs { - u32 mpr_0_7; - u32 mpr_8_15; -}; -/* LCD controller registers */ -struct lcdc_regs { - u32 lssar; /* Screen Start Address */ - u32 lsr; /* Size */ - u32 lvpwr; /* Virtual Page Width */ - u32 lcpr; /* Cursor Position */ - u32 lcwhb; /* Cursor Width Height and Blink */ - u32 lccmr; /* Color Cursor Mapping */ - u32 lpcr; /* Panel Configuration */ - u32 lhcr; /* Horizontal Configuration */ - u32 lvcr; /* Vertical Configuration */ - u32 lpor; /* Panning Offset */ - u32 lscr; /* Sharp Configuration */ - u32 lpccr; /* PWM Contrast Control */ - u32 ldcr; /* DMA Control */ - u32 lrmcr; /* Refresh Mode Control */ - u32 licr; /* Interrupt Configuration */ - u32 lier; /* Interrupt Enable */ - u32 lisr; /* Interrupt Status */ - u32 res0[3]; - u32 lgwsar; /* Graphic Window Start Address */ - u32 lgwsr; /* Graphic Window Size */ - u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */ - u32 lgwpor; /* Graphic Window Panning Offset */ - u32 lgwpr; /* Graphic Window Position */ - u32 lgwcr; /* Graphic Window Control */ - u32 lgwdcr; /* Graphic Window DMA Control */ - u32 res1[5]; - u32 lauscr; /* AUS Mode Control */ - u32 lausccr; /* AUS mode Cursor Control */ - u32 res2[31 + 64*7]; - u32 bglut; /* Background Lookup Table */ - u32 gwlut; /* Graphic Window Lookup Table */ -}; - -/* Wireless External Interface Module Registers */ -struct weim_regs { - u32 cscr0u; /* Chip Select 0 Upper Register */ - u32 cscr0l; /* Chip Select 0 Lower Register */ - u32 cscr0a; /* Chip Select 0 Addition Register */ - u32 pad0; - u32 cscr1u; /* Chip Select 1 Upper Register */ - u32 cscr1l; /* Chip Select 1 Lower Register */ - u32 cscr1a; /* Chip Select 1 Addition Register */ - u32 pad1; - u32 cscr2u; /* Chip Select 2 Upper Register */ - u32 cscr2l; /* Chip Select 2 Lower Register */ - u32 cscr2a; /* Chip Select 2 Addition Register */ - u32 pad2; - u32 cscr3u; /* Chip Select 3 Upper Register */ - u32 cscr3l; /* Chip Select 3 Lower Register */ - u32 cscr3a; /* Chip Select 3 Addition Register */ - u32 pad3; - u32 cscr4u; /* Chip Select 4 Upper Register */ - u32 cscr4l; /* Chip Select 4 Lower Register */ - u32 cscr4a; /* Chip Select 4 Addition Register */ - u32 pad4; - u32 cscr5u; /* Chip Select 5 Upper Register */ - u32 cscr5l; /* Chip Select 5 Lower Register */ - u32 cscr5a; /* Chip Select 5 Addition Register */ - u32 pad5; - u32 wcr; /* WEIM Configuration Register */ -}; - -/* Multi-Master Memory Interface */ -struct m3if_regs { - u32 ctl; /* Control Register */ - u32 wcfg0; /* Watermark Configuration Register 0 */ - u32 wcfg1; /* Watermark Configuration Register1 */ - u32 wcfg2; /* Watermark Configuration Register2 */ - u32 wcfg3; /* Watermark Configuration Register 3 */ - u32 wcfg4; /* Watermark Configuration Register 4 */ - u32 wcfg5; /* Watermark Configuration Register 5 */ - u32 wcfg6; /* Watermark Configuration Register 6 */ - u32 wcfg7; /* Watermark Configuration Register 7 */ - u32 wcsr; /* Watermark Control and Status Register */ - u32 scfg0; /* Snooping Configuration Register 0 */ - u32 scfg1; /* Snooping Configuration Register 1 */ - u32 scfg2; /* Snooping Configuration Register 2 */ - u32 ssr0; /* Snooping Status Register 0 */ - u32 ssr1; /* Snooping Status Register 1 */ - u32 res0; - u32 mlwe0; /* Master Lock WEIM CS0 Register */ - u32 mlwe1; /* Master Lock WEIM CS1 Register */ - u32 mlwe2; /* Master Lock WEIM CS2 Register */ - u32 mlwe3; /* Master Lock WEIM CS3 Register */ - u32 mlwe4; /* Master Lock WEIM CS4 Register */ - u32 mlwe5; /* Master Lock WEIM CS5 Register */ -}; - -/* Pulse width modulation */ -struct pwm_regs { - u32 cr; /* Control Register */ - u32 sr; /* Status Register */ - u32 ir; /* Interrupt Register */ - u32 sar; /* Sample Register */ - u32 pr; /* Period Register */ - u32 cnr; /* Counter Register */ -}; - -/* Enhanced Periodic Interrupt Timer */ -struct epit_regs { - u32 cr; /* Control register */ - u32 sr; /* Status register */ - u32 lr; /* Load register */ - u32 cmpr; /* Compare register */ - u32 cnr; /* Counter register */ -}; - -#endif - -#define ARCH_MXC - -/* AIPS 1 */ -#define IMX_AIPS1_BASE (0x43F00000) -#define IMX_MAX_BASE (0x43F04000) -#define IMX_CLKCTL_BASE (0x43F08000) -#define IMX_ETB_SLOT4_BASE (0x43F0C000) -#define IMX_ETB_SLOT5_BASE (0x43F10000) -#define IMX_ECT_CTIO_BASE (0x43F18000) -#define I2C1_BASE_ADDR (0x43F80000) -#define I2C3_BASE_ADDR (0x43F84000) -#define IMX_CAN1_BASE (0x43F88000) -#define IMX_CAN2_BASE (0x43F8C000) -#define UART1_BASE (0x43F90000) -#define UART2_BASE (0x43F94000) -#define I2C2_BASE_ADDR (0x43F98000) -#define IMX_OWIRE_BASE (0x43F9C000) -#define IMX_CSPI1_BASE (0x43FA4000) -#define IMX_KPP_BASE (0x43FA8000) -#define IMX_IOPADMUX_BASE (0x43FAC000) -#define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE -#define IMX_IOPADCTL_BASE (0x43FAC22C) -#define IMX_IOPADGRPCTL_BASE (0x43FAC418) -#define IMX_IOPADINPUTSEL_BASE (0x43FAC460) -#define IMX_AUDMUX_BASE (0x43FB0000) -#define IMX_ECT_IP1_BASE (0x43FB8000) -#define IMX_ECT_IP2_BASE (0x43FBC000) - -/* SPBA */ -#define IMX_SPBA_BASE (0x50000000) -#define IMX_CSPI3_BASE (0x50004000) -#define UART4_BASE (0x50008000) -#define UART3_BASE (0x5000C000) -#define IMX_CSPI2_BASE (0x50010000) -#define IMX_SSI2_BASE (0x50014000) -#define IMX_ESAI_BASE (0x50018000) -#define IMX_ATA_DMA_BASE (0x50020000) -#define IMX_SIM1_BASE (0x50024000) -#define IMX_SIM2_BASE (0x50028000) -#define UART5_BASE (0x5002C000) -#define IMX_TSC_BASE (0x50030000) -#define IMX_SSI1_BASE (0x50034000) -#define IMX_FEC_BASE (0x50038000) -#define IMX_SPBA_CTRL_BASE (0x5003C000) - -/* AIPS 2 */ -#define IMX_AIPS2_BASE (0x53F00000) -#define IMX_CCM_BASE (0x53F80000) -#define IMX_GPT4_BASE (0x53F84000) -#define IMX_GPT3_BASE (0x53F88000) -#define IMX_GPT2_BASE (0x53F8C000) -#define IMX_GPT1_BASE (0x53F90000) -#define IMX_EPIT1_BASE (0x53F94000) -#define IMX_EPIT2_BASE (0x53F98000) -#define IMX_GPIO4_BASE (0x53F9C000) -#define IMX_PWM2_BASE (0x53FA0000) -#define IMX_GPIO3_BASE (0x53FA4000) -#define IMX_PWM3_BASE (0x53FA8000) -#define IMX_SCC_BASE (0x53FAC000) -#define IMX_SCM_BASE (0x53FAE000) -#define IMX_SMN_BASE (0x53FAF000) -#define IMX_RNGD_BASE (0x53FB0000) -#define IMX_MMC_SDHC1_BASE (0x53FB4000) -#define IMX_MMC_SDHC2_BASE (0x53FB8000) -#define IMX_LCDC_BASE (0x53FBC000) -#define IMX_SLCDC_BASE (0x53FC0000) -#define IMX_PWM4_BASE (0x53FC8000) -#define IMX_GPIO1_BASE (0x53FCC000) -#define IMX_GPIO2_BASE (0x53FD0000) -#define IMX_SDMA_BASE (0x53FD4000) -#define IMX_WDT_BASE (0x53FDC000) -#define WDOG1_BASE_ADDR IMX_WDT_BASE -#define IMX_PWM1_BASE (0x53FE0000) -#define IMX_RTIC_BASE (0x53FEC000) -#define IMX_IIM_BASE (0x53FF0000) -#define IIM_BASE_ADDR IMX_IIM_BASE -#define IMX_USB_BASE (0x53FF4000) -/* - * This is in contradiction to the imx25 reference manual, which says that - * port 1's registers start at 0x53FF4200. The correct base address for - * port 1 is 0x53FF4400. The kernel uses 0x53FF4400 as well. - */ -#define IMX_USB_PORT_OFFSET 0x400 -#define IMX_CSI_BASE (0x53FF8000) -#define IMX_DRYICE_BASE (0x53FFC000) - -#define IMX_ARM926_ROMPATCH (0x60000000) -#define IMX_ARM926_ASIC (0x68000000) - -/* 128K Internal Static RAM */ -#define IMX_RAM_BASE (0x78000000) -#define IMX_RAM_SIZE (128 * 1024) - -/* SDRAM BANKS */ -#define IMX_SDRAM_BANK0_BASE (0x80000000) -#define IMX_SDRAM_BANK1_BASE (0x90000000) - -#define IMX_WEIM_CS0 (0xA0000000) -#define IMX_WEIM_CS1 (0xA8000000) -#define IMX_WEIM_CS2 (0xB0000000) -#define IMX_WEIM_CS3 (0xB2000000) -#define IMX_WEIM_CS4 (0xB4000000) -#define IMX_ESDRAMC_BASE (0xB8001000) -#define IMX_WEIM_CTRL_BASE (0xB8002000) -#define IMX_M3IF_CTRL_BASE (0xB8003000) -#define IMX_EMI_CTRL_BASE (0xB8004000) - -/* NAND Flash Controller */ -#define IMX_NFC_BASE (0xBB000000) -#define NFC_BASE_ADDR IMX_NFC_BASE - -/* CCM bitfields */ -#define CCM_PLL_MFI_SHIFT 10 -#define CCM_PLL_MFI_MASK 0xf -#define CCM_PLL_MFN_SHIFT 0 -#define CCM_PLL_MFN_MASK 0x3ff -#define CCM_PLL_MFD_SHIFT 16 -#define CCM_PLL_MFD_MASK 0x3ff -#define CCM_PLL_PD_SHIFT 26 -#define CCM_PLL_PD_MASK 0xf -#define CCM_CCTL_ARM_DIV_SHIFT 30 -#define CCM_CCTL_ARM_DIV_MASK 3 -#define CCM_CCTL_AHB_DIV_SHIFT 28 -#define CCM_CCTL_AHB_DIV_MASK 3 -#define CCM_CCTL_ARM_SRC (1 << 14) -#define CCM_CGR1_GPT1 (1 << 19) -#define CCM_PERCLK_REG(clk) (clk / 4) -#define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4)) -#define CCM_PERCLK_MASK 0x3f -#define CCM_RCSR_NF_16BIT_SEL (1 << 14) -#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) -#define CCM_CRDR_BT_UART_SRC_SHIFT 29 -#define CCM_CRDR_BT_UART_SRC_MASK 7 - -/* ESDRAM Controller register bitfields */ -#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) -#define ESDCTL_BL (1 << 7) -#define ESDCTL_FP (1 << 8) -#define ESDCTL_PWDT(x) (((x) & 3) << 10) -#define ESDCTL_SREFR(x) (((x) & 7) << 13) -#define ESDCTL_DSIZ_16_UPPER (0 << 16) -#define ESDCTL_DSIZ_16_LOWER (1 << 16) -#define ESDCTL_DSIZ_32 (2 << 16) -#define ESDCTL_COL8 (0 << 20) -#define ESDCTL_COL9 (1 << 20) -#define ESDCTL_COL10 (2 << 20) -#define ESDCTL_ROW11 (0 << 24) -#define ESDCTL_ROW12 (1 << 24) -#define ESDCTL_ROW13 (2 << 24) -#define ESDCTL_ROW14 (3 << 24) -#define ESDCTL_ROW15 (4 << 24) -#define ESDCTL_SP (1 << 27) -#define ESDCTL_SMODE_NORMAL (0 << 28) -#define ESDCTL_SMODE_PRECHARGE (1 << 28) -#define ESDCTL_SMODE_AUTO_REF (2 << 28) -#define ESDCTL_SMODE_LOAD_MODE (3 << 28) -#define ESDCTL_SMODE_MAN_REF (4 << 28) -#define ESDCTL_SDE (1 << 31) - -#define ESDCFG_TRC(x) (((x) & 0xf) << 0) -#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) -#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) -#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) -#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) -#define ESDCFG_TWR (1 << 15) -#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) -#define ESDCFG_TRP(x) (((x) & 0x3) << 18) -#define ESDCFG_TWTR (1 << 20) -#define ESDCFG_TXP(x) (((x) & 0x3) << 21) - -#define ESDMISC_RST (1 << 1) -#define ESDMISC_MDDREN (1 << 2) -#define ESDMISC_MDDR_DL_RST (1 << 3) -#define ESDMISC_MDDR_MDIS (1 << 4) -#define ESDMISC_LHD (1 << 5) -#define ESDMISC_MA10_SHARE (1 << 6) -#define ESDMISC_SDRAM_RDY (1 << 31) - -/* GPT bits */ -#define GPT_CTRL_SWR (1 << 15) /* Software reset */ -#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */ -#define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */ -#define GPT_CTRL_TEN 1 /* Timer enable */ - -/* WDOG enable */ -#define WCR_WDE 0x04 -#define WSR_UNLOCK1 0x5555 -#define WSR_UNLOCK2 0xAAAA - -/* MAX bits */ -#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0) - -/* M3IF bits */ -#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0) - -/* WEIM bits */ -/* 13 fields of the upper CS control register */ -#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ - cnc, wsc, ew, wws, edc) \ - ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \ - (psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \ - (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0) -/* 12 fields of the lower CS control register */ -#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \ - csa, ebc, dsz, csn, psr, cre, wrap, csen) \ - ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ - (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ - (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) -/* 14 fields of the additional CS control register */ -#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ - wwu, age, cnc2, fce) \ - ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ - (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ - (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ - (age) << 2 | (cnc2) << 1 | (fce) << 0) - -/* Names used in GPIO driver */ -#define GPIO1_BASE_ADDR IMX_GPIO1_BASE -#define GPIO2_BASE_ADDR IMX_GPIO2_BASE -#define GPIO3_BASE_ADDR IMX_GPIO3_BASE -#define GPIO4_BASE_ADDR IMX_GPIO4_BASE - -/* - * CSPI register definitions - */ -#define MXC_SPI_BASE_ADDRESSES \ - IMX_CSPI1_BASE, \ - IMX_CSPI2_BASE, \ - IMX_CSPI3_BASE - -#endif /* _IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx25/iomux-mx25.h b/arch/arm/include/asm/arch-mx25/iomux-mx25.h deleted file mode 100644 index 1ce7a8586f83..000000000000 --- a/arch/arm/include/asm/arch-mx25/iomux-mx25.h +++ /dev/null @@ -1,537 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 ADVANSEE - * Benoît Thébaudeau benoit.thebaudeau@advansee.com - * - * Based on mainline Linux i.MX iomux-mx25.h file: - * Copyright (C) 2009 by Lothar Wassmann LW@KARO-electronics.de - * - * Based on Linux arch/arm/mach-mx25/mx25_pins.h: - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h: - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH armlinux@phytec.de - */ - -#ifndef __IOMUX_MX25_H__ -#define __IOMUX_MX25_H__ - -#include <asm/mach-imx/iomux-v3.h> - -/* Pad control groupings */ -#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP -#define MX25_KPP_COL_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -/* - * The naming convention for the pad modes is MX25_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * See also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH PADCTRL */ -enum { - MX25_PAD_A10__A10 = IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A10__GPIO_4_0 = IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL), - - MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL), - MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL), - - MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL), - - MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL), - - MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL), - - MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL), - MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL), - MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS0__CS0 = IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS1__CS1 = IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS1__NF_CE3 = IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS1__GPIO_4_3 = IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__NF_CE1 = IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS5__NF_CE2 = IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL), - MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL), - MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL), - MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_BCLK__BCLK = IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_BCLK__GPIO_4_4 = IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL), - MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE), - MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D15__D15 = IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_D15__GPIO_4_5 = IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D14__D14 = IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D14__LD17 = IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_D14__GPIO_4_6 = IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D13__D13 = IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D13__LD18 = IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_D13__GPIO_4_7 = IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D12__D12 = IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D12__GPIO_4_8 = IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D11__D11 = IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D11__GPIO_4_9 = IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D10__D10 = IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D10__GPIO_4_10 = IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_D10__USBOTG_OC = IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP), - - MX25_PAD_D9__D9 = IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D9__GPIO_4_11 = IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_D9__USBH2_PWR = IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE), - - MX25_PAD_D8__D8 = IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D8__GPIO_4_12 = IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_D8__USBH2_OC = IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP), - - MX25_PAD_D7__D7 = IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D7__GPIO_4_13 = IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D6__D6 = IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D6__GPIO_4_14 = IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D5__D5 = IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D5__GPIO_4_15 = IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D4__D4 = IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D4__GPIO_4_16 = IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D3__D3 = IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D3__GPIO_4_17 = IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D2__D2 = IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D2__GPIO_4_18 = IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D1__D1 = IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D1__GPIO_4_19 = IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D0__D0 = IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D0__GPIO_4_20 = IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL), - MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL), - MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL), - - MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL), - - MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL), - - MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL), - - MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL), - - MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL), - MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL), - - MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP), - - MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL), - MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x07, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x07, 0x4b4, 1, NO_PAD_CTRL), - - MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL), - MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x07, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x07, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x01, 0x528, 1, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE), - MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN), - MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL), - MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL), - MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL), - MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL), - MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL), - - /* - * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD - * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM - * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon - * bug that configuring the SD1_CMD function doesn't enable the input path for - * this pin. - * This might have side effects for other hardware units that are connected to - * that pin and use the respective function as input. - */ - MX25_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL), - MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL), - MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL), - MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL), - MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL), - MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL), - MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL), - MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL), - MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL), - MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP), - MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL), - MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP), - MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_TDO__TDO = IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL), - - MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x06, 0, 0, PAD_CTL_PUS_22K_UP), - MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE), - - MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x06, 0x480, 1, PAD_CTL_PUS_22K_UP), - MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP), - - MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x06, 0, 0, PAD_CTL_PUS_22K_UP), - - MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x06, 0x484, 1, PAD_CTL_PUS_22K_UP), - - MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x01, 0x524, 2, NO_PAD_CTRL), - MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL), - - MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL), - - MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL), - MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_BOOT_MODE0__BOOT_MODE0 = IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_BOOT_MODE1__BOOT_MODE1 = IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_BOOT_MODE1__GPIO_4_31 = IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CTL_GRP_DVS_MISC = IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_FEC = IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_JTAG = IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_NFC = IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_CSI = IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_WEIM = IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_DDR = IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_CRM = IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_KPP = IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_SDHC1 = IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_LCD = IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_UART = IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_NFC = IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_CSI = IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_CSPI1 = IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DDRTYPE = IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_SDHC1 = IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_LCD = IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL), -}; - -#endif /* __IOMUX_MX25_H__ */ diff --git a/arch/arm/include/asm/arch-mx25/macro.h b/arch/arm/include/asm/arch-mx25/macro.h deleted file mode 100644 index 68bddf49526e..000000000000 --- a/arch/arm/include/asm/arch-mx25/macro.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Matthias Weisser weisserm@arcor.de - * - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby jrigby@gmail.com - * - * Common asm macros for imx25 - */ - -#ifndef __ASM_ARM_ARCH_MACRO_H__ -#define __ASM_ARM_ARCH_MACRO_H__ -#ifdef __ASSEMBLY__ - -#include <asm/arch/imx-regs.h> -#include <generated/asm-offsets.h> -#include <asm/macro.h> - -/* - * AIPS setup - Only setup MPROTx registers. - * The PACR default values are good. - * - * Default argument values: - * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to - * user-mode. - */ -.macro init_aips mpr=0x77777777 - ldr r0, =IMX_AIPS1_BASE - ldr r1, =\mpr - str r1, [r0, #AIPS_MPR_0_7] - str r1, [r0, #AIPS_MPR_8_15] - ldr r2, =IMX_AIPS2_BASE - str r1, [r2, #AIPS_MPR_0_7] - str r1, [r2, #AIPS_MPR_8_15] -.endm - -/* - * MAX (Multi-Layer AHB Crossbar Switch) setup - * - * Default argument values: - * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA - * - SGPCR: always park on last master - * - MGPCR: restore default values - */ -.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000 - ldr r0, =IMX_MAX_BASE - ldr r1, =\mpr - str r1, [r0, #MAX_MPR0] /* for S0 */ - str r1, [r0, #MAX_MPR1] /* for S1 */ - str r1, [r0, #MAX_MPR2] /* for S2 */ - str r1, [r0, #MAX_MPR3] /* for S3 */ - str r1, [r0, #MAX_MPR4] /* for S4 */ - ldr r1, =\sgpcr - str r1, [r0, #MAX_SGPCR0] /* for S0 */ - str r1, [r0, #MAX_SGPCR1] /* for S1 */ - str r1, [r0, #MAX_SGPCR2] /* for S2 */ - str r1, [r0, #MAX_SGPCR3] /* for S3 */ - str r1, [r0, #MAX_SGPCR4] /* for S4 */ - ldr r1, =\mgpcr - str r1, [r0, #MAX_MGPCR0] /* for M0 */ - str r1, [r0, #MAX_MGPCR1] /* for M1 */ - str r1, [r0, #MAX_MGPCR2] /* for M2 */ - str r1, [r0, #MAX_MGPCR3] /* for M3 */ - str r1, [r0, #MAX_MGPCR4] /* for M4 */ -.endm - -/* - * M3IF setup - * - * Default argument values: - * - CTL: - * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 - * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 - * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 - * MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 - * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000 - * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000 - * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 - * ------------ - * 0x00000001 - */ -.macro init_m3if ctl=0x00000001 - /* M3IF Control Register (M3IFCTL) */ - write32 IMX_M3IF_CTRL_BASE, \ctl -.endm - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARM_ARCH_MACRO_H__ */ diff --git a/arch/arm/mach-imx/mx2/Kconfig b/arch/arm/mach-imx/mx2/Kconfig deleted file mode 100644 index fad5dcc940aa..000000000000 --- a/arch/arm/mach-imx/mx2/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -if ARCH_MX25 - -config MX25 - bool - default y - select SYS_FSL_ERRATUM_ESDHC_A001 -choice - prompt "MX25 board select" - optional - -config TARGET_ZMX25 - bool "Support zmx25" - select BOARD_LATE_INIT - select CPU_ARM926EJS - -endchoice - -config SYS_SOC - default "mx25" - -source "board/syteco/zmx25/Kconfig" - -endif diff --git a/board/syteco/zmx25/Kconfig b/board/syteco/zmx25/Kconfig deleted file mode 100644 index 59a415d65fa9..000000000000 --- a/board/syteco/zmx25/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_ZMX25 - -config SYS_BOARD - default "zmx25" - -config SYS_VENDOR - default "syteco" - -config SYS_SOC - default "mx25" - -config SYS_CONFIG_NAME - default "zmx25" - -endif diff --git a/board/syteco/zmx25/MAINTAINERS b/board/syteco/zmx25/MAINTAINERS deleted file mode 100644 index 90f9fab7b84a..000000000000 --- a/board/syteco/zmx25/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ZMX25 BOARD -M: Matthias Weisser weisserm@arcor.de -S: Maintained -F: board/syteco/zmx25/ -F: include/configs/zmx25.h -F: configs/zmx25_defconfig diff --git a/board/syteco/zmx25/Makefile b/board/syteco/zmx25/Makefile deleted file mode 100644 index 49b3a8f18904..000000000000 --- a/board/syteco/zmx25/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (c) 2010 Graf-Syteco, Matthias Weisser -# weisserm@arcor.de - -obj-y += zmx25.o -obj-y += lowlevel_init.o diff --git a/board/syteco/zmx25/lowlevel_init.S b/board/syteco/zmx25/lowlevel_init.S deleted file mode 100644 index 7df93988412c..000000000000 --- a/board/syteco/zmx25/lowlevel_init.S +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Matthias Weisser weisserm@arcor.de - * - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby jrigby@gmail.com - * - * Based on U-Boot and RedBoot sources for several different i.mx - * platforms. - */ - -#include <asm/macro.h> -#include <asm/arch/macro.h> -#include <asm/arch/imx-regs.h> -#include <generated/asm-offsets.h> - -/* - * clocks - */ -.macro init_clocks - - /* disable clock output */ - write32 IMX_CCM_BASE + CCM_MCR, 0x00000000 - write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000 - - /* - * enable all implemented clocks in all three - * clock control registers - */ - write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff - write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff - write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff - - /* Devide NAND clock by 32 */ - write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F -.endm - -/* - * sdram controller init - */ -.macro init_lpddr - ldr r0, =IMX_ESDRAMC_BASE - ldr r2, =IMX_SDRAM_BANK0_BASE - - /* - * reset SDRAM controller - * then wait for initialization to complete - */ - ldr r1, =(1 << 1) | (1 << 2) - str r1, [r0, #ESDRAMC_ESDMISC] -1: ldr r3, [r0, #ESDRAMC_ESDMISC] - tst r3, #(1 << 31) - beq 1b - ldr r1, =(1 << 2) - str r1, [r0, #ESDRAMC_ESDMISC] - - ldr r1, =0x002a7420 - str r1, [r0, #ESDRAMC_ESDCFG0] - - /* control | precharge */ - ldr r1, =0x92216008 - str r1, [r0, #ESDRAMC_ESDCTL0] - /* dram command encoded in address */ - str r1, [r2, #0x400] - - /* auto refresh */ - ldr r1, =0xa2216008 - str r1, [r0, #ESDRAMC_ESDCTL0] - /* read dram twice to auto refresh */ - ldr r3, [r2] - ldr r3, [r2] - - /* control | load mode */ - ldr r1, =0xb2216008 - str r1, [r0, #ESDRAMC_ESDCTL0] - - /* mode register of lpddram */ - strb r1, [r2, #0x33] - - /* extended mode register of lpddrram */ - ldr r2, =0x81000000 - strb r1, [r2] - - /* control | normal */ - ldr r1, =0x82216008 - str r1, [r0, #ESDRAMC_ESDCTL0] -.endm - -.globl lowlevel_init -lowlevel_init: - init_aips - init_max - init_clocks - init_lpddr - mov pc, lr diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c deleted file mode 100644 index 2d4c5cce8920..000000000000 --- a/board/syteco/zmx25/zmx25.c +++ /dev/null @@ -1,178 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (c) 2011 Graf-Syteco, Matthias Weisser - * weisserm@arcor.de - * - * Based on tx25.c: - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby jrigby@gmail.com - * - * Based on imx27lite.c: - * Copyright (C) 2008,2009 Eric Jarrige jorasse@users.sourceforge.net - * Copyright (C) 2009 Ilya Yanok yanok@emcraft.com - * And: - * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat - */ -#include <common.h> -#include <cpu_func.h> -#include <env.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx25.h> -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init() -{ - static const iomux_v3_cfg_t sdhc1_pads[] = { - NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL), - }; - - static const iomux_v3_cfg_t dig_out_pads[] = { - MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */ - MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */ - NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */ - NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */ - }; - - static const iomux_v3_cfg_t led_pads[] = { - MX25_PAD_CSI_D9__GPIO_4_21, - MX25_PAD_CSI_D4__GPIO_1_29, - }; - - static const iomux_v3_cfg_t can_pads[] = { - NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL), - }; - - static const iomux_v3_cfg_t i2c3_pads[] = { - MX25_PAD_CSPI1_SS1__I2C3_DAT, - MX25_PAD_GPIO_E__I2C3_CLK, - }; - - icache_enable(); - - /* Setup of core voltage selection pin to run at 1.4V */ - imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */ - gpio_direction_output(IMX_GPIO_NR(3, 15), 1); - - /* Setup of SD card pins*/ - imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); - - /* Setup of digital output for USB power and OC */ - imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */ - gpio_direction_output(IMX_GPIO_NR(1, 28), 1); - - imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */ - gpio_direction_input(IMX_GPIO_NR(1, 18)); - - /* Setup of digital output control pins */ - imx_iomux_v3_setup_multiple_pads(dig_out_pads, - ARRAY_SIZE(dig_out_pads)); - - /* Switch both output drivers off */ - gpio_direction_output(IMX_GPIO_NR(1, 7), 0); - gpio_direction_output(IMX_GPIO_NR(1, 6), 0); - - /* Setup of key input pin */ - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0)); - gpio_direction_input(IMX_GPIO_NR(2, 29)); - - /* Setup of status LED outputs */ - imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads)); - - /* Switch both LEDs off */ - gpio_direction_output(IMX_GPIO_NR(4, 21), 0); - gpio_direction_output(IMX_GPIO_NR(1, 29), 0); - - /* Setup of CAN1 and CAN2 signals */ - imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads)); - - /* Setup of I2C3 signals */ - imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads)); - - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int board_late_init(void) -{ - const char *e; - -#ifdef CONFIG_FEC_MXC -/* - * FIXME: need to revisit this - * The original code enabled PUE and 100-k pull-down without PKE, so the right - * value here is likely: - * 0 for no pull - * or: - * PAD_CTL_PUS_100K_DOWN for 100-k pull-down - */ -#define FEC_OUT_PAD_CTRL 0 - - static const iomux_v3_cfg_t fec_pads[] = { - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX25_PAD_FEC_RX_DV__FEC_RX_DV, - MX25_PAD_FEC_RDATA0__FEC_RDATA0, - NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL), - MX25_PAD_FEC_MDIO__FEC_MDIO, - MX25_PAD_FEC_RDATA1__FEC_RDATA1, - NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL), - - MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */ - MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */ - }; - - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); - - /* assert PHY reset (low) */ - gpio_direction_output(IMX_GPIO_NR(3, 16), 0); - - udelay(5000); - - /* deassert PHY reset */ - gpio_set_value(IMX_GPIO_NR(3, 16), 1); - - udelay(5000); -#endif - - e = env_get("gs_base_board"); - if (e != NULL) { - if (strcmp(e, "G283") == 0) { - int key = gpio_get_value(IMX_GPIO_NR(2, 29)); - - if (key) { - /* Switch on both LEDs to inidcate boot mode */ - gpio_set_value(IMX_GPIO_NR(1, 29), 0); - gpio_set_value(IMX_GPIO_NR(4, 21), 0); - - env_set("preboot", "run gs_slow_boot"); - } else - env_set("preboot", "run gs_fast_boot"); - } - } - - return 0; -} - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, - PHYS_SDRAM_SIZE); - return 0; -} diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig deleted file mode 100644 index df6d93473359..000000000000 --- a/configs/zmx25_defconfig +++ /dev/null @@ -1,38 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX25=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_TARGET_ZMX25=y -CONFIG_IMX_CONFIG="" -CONFIG_SYS_MALLOC_LEN=0x3f8000 -CONFIG_SYS_LOAD_ADDR=0x80000000 -CONFIG_BOOTDELAY=5 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="boot in %d s\n" -CONFIG_AUTOBOOT_DELAY_STR="delaygs" -CONFIG_AUTOBOOT_STOP_STR="stopgs" -CONFIG_USE_PREBOOT=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="zmx25> " -CONFIG_CMD_IMLS=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xA0040000 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_LZO=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index cbea165b9d54..3bb5b02eabb3 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -645,7 +645,7 @@ config MCFUART
config MXC_UART bool "IMX serial port support" - depends on ARCH_MX25 || ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M + depends on ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M help If you have a machine based on a Motorola IMX CPU you can enable its onboard serial port by enabling this option. diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig index a2c51083b156..0ffc1b6444b6 100644 --- a/drivers/w1/Kconfig +++ b/drivers/w1/Kconfig @@ -20,7 +20,7 @@ config W1_GPIO
config W1_MXC bool "Enable 1-wire controller on i.MX processors" - depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5 + depends on ARCH_MX31 || ARCH_MX5 help Support the one wire controller found in some members of the NXP i.MX SoC family. diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 6fbb5c1b6d51..eaa6f16f5c98 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -24,7 +24,7 @@ config WATCHDOG_AUTOSTART
config WATCHDOG_TIMEOUT_MSECS int "Watchdog timeout in msec" - default 128000 if ARCH_MX25 || ARCH_MX31 || ARCH_MX5 || ARCH_MX6 + default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6 default 128000 if ARCH_MX7 || ARCH_VF610 default 30000 if ARCH_SOCFPGA default 60000 diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h deleted file mode 100644 index 46596e921a0c..000000000000 --- a/include/configs/zmx25.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (c) 2011 Graf-Syteco, Matthias Weisser - * weisserm@arcor.de - * - * Configuation settings for the zmx25 board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - -#define CONFIG_SYS_TIMER_RATE 32768 -#define CONFIG_SYS_TIMER_COUNTER \ - (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) - -/* - * Environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "gs_fast_boot=setenv bootdelay 5\0" \ - "gs_slow_boot=setenv bootdelay 10\0" \ - "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \ - "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \ - "bootm 0x81000000; bootelf 0x81000000\0" - -/* - * Hardware drivers - */ - -/* - * Serial - */ -#define CONFIG_MXC_UART_BASE UART2_BASE - -/* - * Ethernet - */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x00 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_MXC -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL -#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN) -#define CONFIG_EHCI_IS_TDI -#endif /* CONFIG_CMD_USB */ - -/* SDRAM */ -#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */ -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */ - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE 0xA0000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -/* - * CFI FLASH driver setup - */ - -#endif /* __CONFIG_H */
On Thu, Sep 09, 2021 at 07:54:50AM -0400, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last ARCH_MX25 platform, remove those references as well.
Cc: Matthias Weisser weisserm@arcor.de Cc: Stefano Babic sbabic@denx.de Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/next, thanks!
This board has not been converted to CONFIG_DM by the deadline. Remove it.
Cc: Marek Vasut marex@denx.de Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-imx/mxs/Kconfig | 4 - board/ppcag/bg0900/Kconfig | 15 ---- board/ppcag/bg0900/MAINTAINERS | 6 -- board/ppcag/bg0900/Makefile | 10 --- board/ppcag/bg0900/bg0900.c | 89 ------------------- board/ppcag/bg0900/spl_boot.c | 152 --------------------------------- configs/bg0900_defconfig | 43 ---------- include/configs/bg0900.h | 39 --------- 8 files changed, 358 deletions(-) delete mode 100644 board/ppcag/bg0900/Kconfig delete mode 100644 board/ppcag/bg0900/MAINTAINERS delete mode 100644 board/ppcag/bg0900/Makefile delete mode 100644 board/ppcag/bg0900/bg0900.c delete mode 100644 board/ppcag/bg0900/spl_boot.c delete mode 100644 configs/bg0900_defconfig delete mode 100644 include/configs/bg0900.h
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index 9f48ffda414a..b2026a3758a5 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -39,9 +39,6 @@ choice prompt "MX28 board select" optional
-config TARGET_BG0900 - bool "Support bg0900" - config TARGET_MX28EVK bool "Support mx28evk" select BOARD_EARLY_INIT_F @@ -56,6 +53,5 @@ config SYS_SOC
source "board/freescale/mx28evk/Kconfig" source "board/liebherr/xea/Kconfig" -source "board/ppcag/bg0900/Kconfig"
endif diff --git a/board/ppcag/bg0900/Kconfig b/board/ppcag/bg0900/Kconfig deleted file mode 100644 index d7f2368a230d..000000000000 --- a/board/ppcag/bg0900/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_BG0900 - -config SYS_BOARD - default "bg0900" - -config SYS_VENDOR - default "ppcag" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "bg0900" - -endif diff --git a/board/ppcag/bg0900/MAINTAINERS b/board/ppcag/bg0900/MAINTAINERS deleted file mode 100644 index 853c0d59c8d1..000000000000 --- a/board/ppcag/bg0900/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BG0900 BOARD -M: Marek Vasut marex@denx.de -S: Maintained -F: board/ppcag/bg0900/ -F: include/configs/bg0900.h -F: configs/bg0900_defconfig diff --git a/board/ppcag/bg0900/Makefile b/board/ppcag/bg0900/Makefile deleted file mode 100644 index 540bd9dc12f7..000000000000 --- a/board/ppcag/bg0900/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := bg0900.o -else -obj-y := spl_boot.o -endif diff --git a/board/ppcag/bg0900/bg0900.c b/board/ppcag/bg0900/bg0900.c deleted file mode 100644 index 578f5c73b6cb..000000000000 --- a/board/ppcag/bg0900/bg0900.c +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * PPC-AG BG0900 board - * - * Copyright (C) 2013 Marek Vasut marex@denx.de - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <linux/delay.h> -#include <linux/mii.h> -#include <miiphy.h> -#include <netdev.h> -#include <errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - /* IO1 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK1, 480000); - - /* SSP2 clock at 160MHz */ - mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(struct bd_info *bis) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - struct eth_device *dev; - int ret; - - ret = cpu_eth_init(bis); - - /* BG0900 uses ENET_CLK PAD to drive FEC clock */ - writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, - &clkctrl_regs->hw_clkctrl_enet); - - /* Reset FEC PHYs */ - gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); - udelay(200); - gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); - - ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); - if (ret) { - puts("FEC MXS: Unable to init FEC0\n"); - return ret; - } - - dev = eth_get_dev_by_name("FEC0"); - if (!dev) { - puts("FEC MXS: Unable to get FEC0 device entry\n"); - return -EINVAL; - } - - return ret; -} - -#endif diff --git a/board/ppcag/bg0900/spl_boot.c b/board/ppcag/bg0900/spl_boot.c deleted file mode 100644 index b46bc8939a38..000000000000 --- a/board/ppcag/bg0900/spl_boot.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * PPC-AG BG0900 Boot setup - * - * Copyright (C) 2013 Marek Vasut marex@denx.de - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) - -const iomux_cfg_t iomux_setup[] = { - /* DUART */ - MX28_PAD_PWM0__DUART_RX, - MX28_PAD_PWM1__DUART_TX, - - /* GPMI NAND */ - MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDN__GPMI_RDN | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), - MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, - - /* FEC0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, - - /* FEC0 Reset */ - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - - /* EMI */ - MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, - MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, - - MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - - /* SPI2 (for SPI flash) */ - MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_SS0__SSP2_D3 | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), -}; - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - /* - * DDR Controller Registers - * Manufacturer: Winbond - * Device Part Number: W972GG6JB-25I - * Clock Freq.: 200MHz - * Density: 2Gb - * Chip Selects: 1 - * Number of Banks: 8 - * Row address: 14 - * Column address: 10 - */ - - dram_vals[0x74 / 4] = 0x0102010A; - dram_vals[0x98 / 4] = 0x04005003; - dram_vals[0x9c / 4] = 0x090000c8; - - dram_vals[0xa8 / 4] = 0x0036b009; - dram_vals[0xac / 4] = 0x03270612; - - dram_vals[0xb0 / 4] = 0x02020202; - dram_vals[0xb4 / 4] = 0x00c80029; - - dram_vals[0xc0 / 4] = 0x00011900; - - dram_vals[0x12c / 4] = 0x07400300; - dram_vals[0x130 / 4] = 0x07400300; - dram_vals[0x2c4 / 4] = 0x02030303; -} - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig deleted file mode 100644 index a3282eba41a8..000000000000 --- a/configs/bg0900_defconfig +++ /dev/null @@ -1,43 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_IMX_CONFIG="" -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_BG0900=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_SYS_LOAD_ADDR=0x42000000 -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyAMA0,115200" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h deleted file mode 100644 index d9599b859112..000000000000 --- a/include/configs/bg0900.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Marek Vasut marex@denx.de - */ -#ifndef __CONFIGS_BG0900_H__ -#define __CONFIGS_BG0900_H__ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#endif - -/* Boot Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTCOMMAND "bootm" - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_spi_firmware_filename=u-boot.sb\0" \ - "update_spi_firmware_maxsz=0x80000\0" \ - "update_spi_firmware=" /* Update the SPI flash firmware */ \ - "if sf probe 2:0 ; then " \ - "if tftp ${update_spi_firmware_filename} ; then " \ - "sf erase 0x0 +${filesize} ; " \ - "sf write ${loadaddr} 0x0 ${filesize} ; " \ - "fi ; " \ - "fi\0" - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_BG0900_H__ */
On Thu, Sep 09, 2021 at 07:54:51AM -0400, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline. Remove it.
Cc: Marek Vasut marex@denx.de Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/next, thanks!
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last orion5x platform, remove that support as well.
Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Stefan Roese sr@denx.de Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/Kconfig | 7 - arch/arm/Makefile | 1 - arch/arm/include/asm/arch-orion5x/spl.h | 9 - arch/arm/mach-orion5x/Kconfig | 18 -- arch/arm/mach-orion5x/Makefile | 26 -- arch/arm/mach-orion5x/cpu.c | 298 ------------------ arch/arm/mach-orion5x/dram.c | 58 ---- arch/arm/mach-orion5x/include/mach/cpu.h | 242 -------------- .../arm/mach-orion5x/include/mach/mv88f5182.h | 23 -- arch/arm/mach-orion5x/include/mach/orion5x.h | 66 ---- arch/arm/mach-orion5x/lowlevel_init.S | 286 ----------------- arch/arm/mach-orion5x/timer.c | 174 ---------- arch/arm/mach-orion5x/u-boot-spl.lds | 60 ---- board/LaCie/edminiv2/Kconfig | 12 - board/LaCie/edminiv2/MAINTAINERS | 6 - board/LaCie/edminiv2/Makefile | 10 - board/LaCie/edminiv2/edminiv2.c | 57 ---- configs/edminiv2_defconfig | 47 --- drivers/i2c/mvtwsi.c | 4 +- drivers/net/Kconfig | 2 +- drivers/net/mvgbe.c | 2 - drivers/usb/host/Kconfig | 2 +- drivers/usb/host/ehci-marvell.c | 2 - env/flash.c | 3 +- include/configs/edminiv2.h | 169 ---------- 25 files changed, 4 insertions(+), 1580 deletions(-) delete mode 100644 arch/arm/include/asm/arch-orion5x/spl.h delete mode 100644 arch/arm/mach-orion5x/Kconfig delete mode 100644 arch/arm/mach-orion5x/Makefile delete mode 100644 arch/arm/mach-orion5x/cpu.c delete mode 100644 arch/arm/mach-orion5x/dram.c delete mode 100644 arch/arm/mach-orion5x/include/mach/cpu.h delete mode 100644 arch/arm/mach-orion5x/include/mach/mv88f5182.h delete mode 100644 arch/arm/mach-orion5x/include/mach/orion5x.h delete mode 100644 arch/arm/mach-orion5x/lowlevel_init.S delete mode 100644 arch/arm/mach-orion5x/timer.c delete mode 100644 arch/arm/mach-orion5x/u-boot-spl.lds delete mode 100644 board/LaCie/edminiv2/Kconfig delete mode 100644 board/LaCie/edminiv2/MAINTAINERS delete mode 100644 board/LaCie/edminiv2/Makefile delete mode 100644 board/LaCie/edminiv2/edminiv2.c delete mode 100644 configs/edminiv2_defconfig delete mode 100644 include/configs/edminiv2.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 70ab47cce056..c98b2fe54216 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -545,11 +545,6 @@ config ARCH_MVEBU select SPI imply CMD_DM
-config ARCH_ORION5X - bool "Marvell Orion" - select CPU_ARM926EJS - select GPIO_EXTRA_HEADER - config TARGET_STV0991 bool "Support stv0991" select CPU_V7A @@ -2032,8 +2027,6 @@ source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
-source "arch/arm/mach-orion5x/Kconfig" - source "arch/arm/mach-owl/Kconfig"
source "arch/arm/mach-rmobile/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c68e598a675b..eb7802b59099 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -68,7 +68,6 @@ machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MVEBU) += mvebu machine-$(CONFIG_ARCH_NEXELL) += nexell machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 -machine-$(CONFIG_ARCH_ORION5X) += orion5x machine-$(CONFIG_ARCH_OWL) += owl machine-$(CONFIG_ARCH_RMOBILE) += rmobile machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip diff --git a/arch/arm/include/asm/arch-orion5x/spl.h b/arch/arm/include/asm/arch-orion5x/spl.h deleted file mode 100644 index dc0a9b9099cb..000000000000 --- a/arch/arm/include/asm/arch-orion5x/spl.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 Albert ARIBAUD albert.u.boot@aribaud.net - */ - -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NOR 1 diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig deleted file mode 100644 index 5baa6fb935ae..000000000000 --- a/arch/arm/mach-orion5x/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if ARCH_ORION5X - -choice - prompt "Marvell Orion board select" - optional - -config TARGET_EDMINIV2 - bool "LaCie Ethernet Disk mini V2" - select SUPPORT_SPL - -endchoice - -config SYS_SOC - default "orion5x" - -source "board/LaCie/edminiv2/Kconfig" - -endif diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile deleted file mode 100644 index a8b87f6d7103..000000000000 --- a/arch/arm/mach-orion5x/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net -# -# Based on original Kirkwood support which is -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com - -obj-y = cpu.o -obj-y += dram.o -obj-y += timer.o - -ifndef CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT -obj-y += lowlevel_init.o -endif - -# some files can only build in ARM or THUMB2, not THUMB1 - -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD -ifndef CONFIG_HAS_THUMB2 - -CFLAGS_cpu.o := -marm - -endif -endif diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c deleted file mode 100644 index ffae9a01e37c..000000000000 --- a/arch/arm/mach-orion5x/cpu.c +++ /dev/null @@ -1,298 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net - * - * Based on original Kirkwood support which is - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <net.h> -#include <netdev.h> -#include <asm/cache.h> -#include <asm/io.h> -#include <u-boot/md5.h> -#include <asm/arch/cpu.h> - -#define BUFLEN 16 - -void reset_cpu(void) -{ - struct orion5x_cpu_registers *cpureg = - (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE; - - writel(readl(&cpureg->rstoutn_mask) | (1 << 2), - &cpureg->rstoutn_mask); - writel(readl(&cpureg->sys_soft_rst) | 1, - &cpureg->sys_soft_rst); - while (1) - ; -} - -/* - * Compute Window Size field value from size expressed in bytes - * Used with the Base register to set the address window size and location. - * Must be programmed from LSB to MSB as sequence of ones followed by - * sequence of zeros. The number of ones specifies the size of the window in - * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB). - * NOTES: - * 1) A sizeval equal to 0x0 specifies 4 GiB. - * 2) A return value of 0x0 specifies 64 KiB. - */ -unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) -{ - /* - * Calculate the number of 64 KiB blocks needed minus one (rounding up). - * For sizeval > 0 this is equivalent to: - * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1 - */ - sizeval = (sizeval - 1) >> 16; - - /* - * Propagate 'one' bits to the right by 'oring' them. - * We need only treat bits 15-0. - */ - sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */ - sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */ - sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */ - sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/ - - return sizeval; -} - -/* - * orion5x_config_adr_windows - Configure address Windows - * - * There are 8 address windows supported by Orion5x Soc to addess different - * devices. Each window can be configured for size, BAR and remap addr - * Below configuration is standard for most of the cases - * - * If remap function not used, remap_lo must be set as base - * - * NOTES: - * - * 1) in order to avoid windows with inconsistent control and base values - * (which could prevent access to BOOTCS and hence execution from FLASH) - * always disable window before writing the base value then reenable it - * by writing the control value. - * - * 2) in order to avoid losing access to BOOTCS when disabling window 7, - * first configure window 6 for BOOTCS, then configure window 7 for BOOTCS, - * then configure windows 6 for its own target. - * - * Reference Documentation: - * Mbus-L to Mbus Bridge Registers Configuration. - * (Sec 25.1 and 25.3 of Datasheet) - */ -int orion5x_config_adr_windows(void) -{ - struct orion5x_win_registers *winregs = - (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE; - -/* Disable window 0, configure it for its intended target, enable it. */ - writel(0, &winregs[0].ctrl); - writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base); - writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo); - writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi); - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM, - ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM, - ORION5X_WIN_ENABLE), &winregs[0].ctrl); -/* Disable window 1, configure it for its intended target, enable it. */ - writel(0, &winregs[1].ctrl); - writel(ORION5X_ADR_PCIE_IO, &winregs[1].base); - writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo); - writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi); - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO, - ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO, - ORION5X_WIN_ENABLE), &winregs[1].ctrl); -/* Disable window 2, configure it for its intended target, enable it. */ - writel(0, &winregs[2].ctrl); - writel(ORION5X_ADR_PCI_MEM, &winregs[2].base); - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM, - ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM, - ORION5X_WIN_ENABLE), &winregs[2].ctrl); -/* Disable window 3, configure it for its intended target, enable it. */ - writel(0, &winregs[3].ctrl); - writel(ORION5X_ADR_PCI_IO, &winregs[3].base); - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO, - ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO, - ORION5X_WIN_ENABLE), &winregs[3].ctrl); -/* Disable window 4, configure it for its intended target, enable it. */ - writel(0, &winregs[4].ctrl); - writel(ORION5X_ADR_DEV_CS0, &winregs[4].base); - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0, - ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0, - ORION5X_WIN_ENABLE), &winregs[4].ctrl); -/* Disable window 5, configure it for its intended target, enable it. */ - writel(0, &winregs[5].ctrl); - writel(ORION5X_ADR_DEV_CS1, &winregs[5].base); - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1, - ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1, - ORION5X_WIN_ENABLE), &winregs[5].ctrl); -/* Disable window 6, configure it for FLASH, enable it. */ - writel(0, &winregs[6].ctrl); - writel(ORION5X_ADR_BOOTROM, &winregs[6].base); - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM, - ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM, - ORION5X_WIN_ENABLE), &winregs[6].ctrl); -/* Disable window 7, configure it for FLASH, enable it. */ - writel(0, &winregs[7].ctrl); - writel(ORION5X_ADR_BOOTROM, &winregs[7].base); - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM, - ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM, - ORION5X_WIN_ENABLE), &winregs[7].ctrl); -/* Disable window 6, configure it for its intended target, enable it. */ - writel(0, &winregs[6].ctrl); - writel(ORION5X_ADR_DEV_CS2, &winregs[6].base); - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2, - ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2, - ORION5X_WIN_ENABLE), &winregs[6].ctrl); - - return 0; -} - -/* - * Orion5x identification is done through PCIE space. - */ - -u32 orion5x_device_id(void) -{ - return readl(PCIE_DEV_ID_OFF) >> 16; -} - -u32 orion5x_device_rev(void) -{ - return readl(PCIE_DEV_REV_OFF) & 0xff; -} - -#if defined(CONFIG_DISPLAY_CPUINFO) - -/* Display device and revision IDs. - * This function must cover all known device/revision - * combinations, not only the one for which u-boot is - * compiled; this way, one can identify actual HW in - * case of a mismatch. - */ -int print_cpuinfo(void) -{ - char dev_str[7]; /* room enough for 0x0000 plus null byte */ - char rev_str[5]; /* room enough for 0x00 plus null byte */ - char *dev_name = NULL; - char *rev_name = NULL; - - u32 dev = orion5x_device_id(); - u32 rev = orion5x_device_rev(); - - if (dev == MV88F5181_DEV_ID) { - dev_name = "MV88F5181"; - if (rev == MV88F5181_REV_B1) - rev_name = "B1"; - else if (rev == MV88F5181L_REV_A1) { - dev_name = "MV88F5181L"; - rev_name = "A1"; - } else if (rev == MV88F5181L_REV_A0) { - dev_name = "MV88F5181L"; - rev_name = "A0"; - } - } else if (dev == MV88F5182_DEV_ID) { - dev_name = "MV88F5182"; - if (rev == MV88F5182_REV_A2) - rev_name = "A2"; - } else if (dev == MV88F5281_DEV_ID) { - dev_name = "MV88F5281"; - if (rev == MV88F5281_REV_D2) - rev_name = "D2"; - else if (rev == MV88F5281_REV_D1) - rev_name = "D1"; - else if (rev == MV88F5281_REV_D0) - rev_name = "D0"; - } else if (dev == MV88F6183_DEV_ID) { - dev_name = "MV88F6183"; - if (rev == MV88F6183_REV_B0) - rev_name = "B0"; - } - if (dev_name == NULL) { - sprintf(dev_str, "0x%04x", dev); - dev_name = dev_str; - } - if (rev_name == NULL) { - sprintf(rev_str, "0x%02x", rev); - rev_name = rev_str; - } - - printf("SoC: Orion5x %s-%s\n", dev_name, rev_name); - - return 0; -} -#endif /* CONFIG_DISPLAY_CPUINFO */ - -#ifdef CONFIG_ARCH_CPU_INIT -int arch_cpu_init(void) -{ - /* Enable and invalidate L2 cache in write through mode */ - invalidate_l2_cache(); - -#ifdef CONFIG_SPL_BUILD - orion5x_config_adr_windows(); -#endif - - return 0; -} -#endif /* CONFIG_ARCH_CPU_INIT */ - -/* - * SOC specific misc init - */ -#if defined(CONFIG_ARCH_MISC_INIT) -int arch_misc_init(void) -{ - u32 temp; - - /*CPU streaming & write allocate */ - temp = readfr_extra_feature_reg(); - temp &= ~(1 << 28); /* disable wr alloc */ - writefr_extra_feature_reg(temp); - - temp = readfr_extra_feature_reg(); - temp &= ~(1 << 29); /* streaming disabled */ - writefr_extra_feature_reg(temp); - - /* L2Cache settings */ - temp = readfr_extra_feature_reg(); - /* Disable L2C pre fetch - Set bit 24 */ - temp |= (1 << 24); - /* enable L2C - Set bit 22 */ - temp |= (1 << 22); - writefr_extra_feature_reg(temp); - - icache_enable(); - /* Change reset vector to address 0x0 */ - temp = get_cr(); - set_cr(temp & ~CR_V); - - /* Set CPIOs and MPPs - values provided by board - include file */ - writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00); - writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04); - writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50); - writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00); - writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04); - writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c); - - /* initialize timer */ - timer_init_r(); - return 0; -} -#endif /* CONFIG_ARCH_MISC_INIT */ - -#ifdef CONFIG_MVGBE -int cpu_eth_init(struct bd_info *bis) -{ - mvgbe_initialize(bis); - return 0; -} -#endif diff --git a/arch/arm/mach-orion5x/dram.c b/arch/arm/mach-orion5x/dram.c deleted file mode 100644 index c9a3750e48de..000000000000 --- a/arch/arm/mach-orion5x/dram.c +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net - * - * Based on original Kirkwood support which is - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#include <common.h> -#include <config.h> -#include <init.h> -#include <asm/arch/cpu.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * orion5x_sdram_bar - reads SDRAM Base Address Register - */ -u32 orion5x_sdram_bar(enum memory_bank bank) -{ - struct orion5x_ddr_addr_decode_registers *winregs = - (struct orion5x_ddr_addr_decode_registers *) - ORION5X_DRAM_BASE; - - u32 result = 0; - u32 enable = 0x01 & winregs[bank].size; - - if ((!enable) || (bank > BANK3)) - return 0; - - result = winregs[bank].base; - return result; -} -int dram_init (void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size( - (long *) orion5x_sdram_bar(0), - CONFIG_MAX_RAM_BANK_SIZE); - return 0; -} - -int dram_init_banksize(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = orion5x_sdram_bar(i); - gd->bd->bi_dram[i].size = get_ram_size( - (long *) (gd->bd->bi_dram[i].start), - CONFIG_MAX_RAM_BANK_SIZE); - } - - return 0; -} diff --git a/arch/arm/mach-orion5x/include/mach/cpu.h b/arch/arm/mach-orion5x/include/mach/cpu.h deleted file mode 100644 index c3ff89669e45..000000000000 --- a/arch/arm/mach-orion5x/include/mach/cpu.h +++ /dev/null @@ -1,242 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net - * - * Based on original Kirorion5x_ood support which is - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#ifndef _ORION5X_CPU_H -#define _ORION5X_CPU_H - -#include <asm/system.h> - -#ifndef __ASSEMBLY__ - -#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ - | (attr << 8) | (orion5x_winctrl_calcsize(size) << 16)) - -#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \ - ((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c) - -enum memory_bank { - BANK0, - BANK1, - BANK2, - BANK3 -}; - -enum orion5x_cpu_winen { - ORION5X_WIN_DISABLE, - ORION5X_WIN_ENABLE -}; - -enum orion5x_cpu_target { - ORION5X_TARGET_DRAM = 0, - ORION5X_TARGET_DEVICE = 1, - ORION5X_TARGET_PCI = 3, - ORION5X_TARGET_PCIE = 4, - ORION5X_TARGET_SASRAM = 9 -}; - -enum orion5x_cpu_attrib { - ORION5X_ATTR_DRAM_CS0 = 0x0e, - ORION5X_ATTR_DRAM_CS1 = 0x0d, - ORION5X_ATTR_DRAM_CS2 = 0x0b, - ORION5X_ATTR_DRAM_CS3 = 0x07, - ORION5X_ATTR_PCI_MEM = 0x59, - ORION5X_ATTR_PCI_IO = 0x51, - ORION5X_ATTR_PCIE_MEM = 0x59, - ORION5X_ATTR_PCIE_IO = 0x51, - ORION5X_ATTR_SASRAM = 0x00, - ORION5X_ATTR_DEV_CS0 = 0x1e, - ORION5X_ATTR_DEV_CS1 = 0x1d, - ORION5X_ATTR_DEV_CS2 = 0x1b, - ORION5X_ATTR_BOOTROM = 0x0f -}; - -/* - * Device Address MAP BAR values - * - * All addresses and sizes not defined by board code - * will be given default values here. - */ - -#if !defined (ORION5X_ADR_PCIE_MEM) -#define ORION5X_ADR_PCIE_MEM 0x90000000 -#endif - -#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO) -#define ORION5X_ADR_PCIE_MEM_REMAP_LO 0x90000000 -#endif - -#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI) -#define ORION5X_ADR_PCIE_MEM_REMAP_HI 0 -#endif - -#if !defined (ORION5X_SZ_PCIE_MEM) -#define ORION5X_SZ_PCIE_MEM (128*1024*1024) -#endif - -#if !defined (ORION5X_ADR_PCIE_IO) -#define ORION5X_ADR_PCIE_IO 0xf0000000 -#endif - -#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO) -#define ORION5X_ADR_PCIE_IO_REMAP_LO 0xf0000000 -#endif - -#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI) -#define ORION5X_ADR_PCIE_IO_REMAP_HI 0 -#endif - -#if !defined (ORION5X_SZ_PCIE_IO) -#define ORION5X_SZ_PCIE_IO (64*1024) -#endif - -#if !defined (ORION5X_ADR_PCI_MEM) -#define ORION5X_ADR_PCI_MEM 0x98000000 -#endif - -#if !defined (ORION5X_SZ_PCI_MEM) -#define ORION5X_SZ_PCI_MEM (128*1024*1024) -#endif - -#if !defined (ORION5X_ADR_PCI_IO) -#define ORION5X_ADR_PCI_IO 0xf0100000 -#endif - -#if !defined (ORION5X_SZ_PCI_IO) -#define ORION5X_SZ_PCI_IO (64*1024) -#endif - -#if !defined (ORION5X_ADR_DEV_CS0) -#define ORION5X_ADR_DEV_CS0 0xfa000000 -#endif - -#if !defined (ORION5X_SZ_DEV_CS0) -#define ORION5X_SZ_DEV_CS0 (2*1024*1024) -#endif - -#if !defined (ORION5X_ADR_DEV_CS1) -#define ORION5X_ADR_DEV_CS1 0xf8000000 -#endif - -#if !defined (ORION5X_SZ_DEV_CS1) -#define ORION5X_SZ_DEV_CS1 (32*1024*1024) -#endif - -#if !defined (ORION5X_ADR_DEV_CS2) -#define ORION5X_ADR_DEV_CS2 0xfa800000 -#endif - -#if !defined (ORION5X_SZ_DEV_CS2) -#define ORION5X_SZ_DEV_CS2 (1*1024*1024) -#endif - -#if !defined (ORION5X_ADR_BOOTROM) -#define ORION5X_ADR_BOOTROM 0xFFF80000 -#endif - -#if !defined (ORION5X_SZ_BOOTROM) -#define ORION5X_SZ_BOOTROM (512*1024) -#endif - -/* - * PCIE registers are used for SoC device ID and revision - */ -#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000) -#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008) - -/* - * The following definitions are intended for identifying - * the real device and revision on which u-boot is running - * even if it was compiled only for a specific one. Thus, - * these constants must not be considered chip-specific. - */ - -/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ -#define MV88F5181_DEV_ID 0x5181 -#define MV88F5181_REV_B1 3 -#define MV88F5181L_REV_A0 8 -#define MV88F5181L_REV_A1 9 -/* Orion-NAS (88F5182) */ -#define MV88F5182_DEV_ID 0x5182 -#define MV88F5182_REV_A2 2 -/* Orion-2 (88F5281) */ -#define MV88F5281_DEV_ID 0x5281 -#define MV88F5281_REV_D0 4 -#define MV88F5281_REV_D1 5 -#define MV88F5281_REV_D2 6 -/* Orion-1-90 (88F6183) */ -#define MV88F6183_DEV_ID 0x6183 -#define MV88F6183_REV_B0 3 - -/* - * read feroceon core extra feature register - * using co-proc instruction - */ -static inline unsigned int readfr_extra_feature_reg(void) -{ - unsigned int val; - asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r" - (val) : : "cc"); - return val; -} - -/* - * write feroceon core extra feature register - * using co-proc instruction - */ -static inline void writefr_extra_feature_reg(unsigned int val) -{ - asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r" - (val) : "cc"); - isb(); -} - -/* - * AHB to Mbus Bridge Registers - * Source: 88F5182 User Manual, Appendix A, section A.4 - * Note: only windows 0 and 1 have remap capability. - */ -struct orion5x_win_registers { - u32 ctrl; - u32 base; - u32 remap_lo; - u32 remap_hi; -}; - -/* - * CPU control and status Registers - * Source: 88F5182 User Manual, Appendix A, section A.4 - */ -struct orion5x_cpu_registers { - u32 config; /*0x20100 */ - u32 ctrl_stat; /*0x20104 */ - u32 rstoutn_mask; /* 0x20108 */ - u32 sys_soft_rst; /* 0x2010C */ - u32 ahb_mbus_cause_irq; /* 0x20110 */ - u32 ahb_mbus_mask_irq; /* 0x20114 */ -}; - -/* - * DDR SDRAM Controller Address Decode Registers - * Source: 88F5182 User Manual, Appendix A, section A.5.1 - */ -struct orion5x_ddr_addr_decode_registers { - u32 base; - u32 size; -}; - -/* - * functions - */ -u32 orion5x_device_id(void); -u32 orion5x_device_rev(void); -unsigned int orion5x_winctrl_calcsize(unsigned int sizeval); -void timer_init_r(void); -#endif /* __ASSEMBLY__ */ -#endif /* _ORION5X_CPU_H */ diff --git a/arch/arm/mach-orion5x/include/mach/mv88f5182.h b/arch/arm/mach-orion5x/include/mach/mv88f5182.h deleted file mode 100644 index 0e9fe0dc51af..000000000000 --- a/arch/arm/mach-orion5x/include/mach/mv88f5182.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net - * - * Based on original Kirkwood 88F6182 support which is - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * - * Header file for Feroceon CPU core 88F5182 SOC. - */ - -#ifndef _CONFIG_88F5182_H -#define _CONFIG_88F5182_H - -/* SOC specific definitions */ -#define F88F5182_REGS_PHYS_BASE 0xf1000000 -#define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE - -/* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ - -#endif /* _CONFIG_88F5182_H */ diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h deleted file mode 100644 index 4b1b0b0f3716..000000000000 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net - * - * Based on original Kirkwood support which is - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - * - * Header file for Marvell's Orion SoC with Feroceon CPU core. - */ - -#ifndef _ASM_ARCH_ORION5X_H -#define _ASM_ARCH_ORION5X_H - -#if defined(CONFIG_FEROCEON) - -/* SOC specific definations */ -#define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x) - -/* Documented registers */ -#define ORION5X_DRAM_BASE (ORION5X_REGISTER(0x01500)) -#define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000)) -#define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000)) -#define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100)) -#define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000)) -#define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100)) -#define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000)) -#define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100)) -#define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300)) -#define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000)) -#define ORION5X_REG_PCIE_BASE (ORION5X_REGISTER(0x40000)) -#define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000)) -#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000)) -#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000)) -#define ORION5X_SATA_BASE (ORION5X_REGISTER(0x80000)) -#define ORION5X_SATA_PORT0_OFFSET 0x2000 -#define ORION5X_SATA_PORT1_OFFSET 0x4000 - -/* Orion5x GbE controller has a single port */ -#define MAX_MVGBE_DEVS 1 -#define MVGBE0_BASE ORION5X_EGIGA_BASE - -/* Orion5x USB Host controller is port 1 */ -#define MVUSB0_BASE ORION5X_USB20_HOST_PORT_BASE -#define MVUSB0_CPU_ATTR_DRAM_CS0 ORION5X_ATTR_DRAM_CS0 -#define MVUSB0_CPU_ATTR_DRAM_CS1 ORION5X_ATTR_DRAM_CS1 -#define MVUSB0_CPU_ATTR_DRAM_CS2 ORION5X_ATTR_DRAM_CS2 -#define MVUSB0_CPU_ATTR_DRAM_CS3 ORION5X_ATTR_DRAM_CS3 - -/* Kirkwood CPU memory windows */ -#define MVCPU_WIN_CTRL_DATA ORION5X_CPU_WIN_CTRL_DATA -#define MVCPU_WIN_ENABLE ORION5X_WIN_ENABLE -#define MVCPU_WIN_DISABLE ORION5X_WIN_DISABLE - -#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024) - -/* include here SoC variants. 5181, 5281, 6183 should go here when - adding support for them, and this comment should then be updated. */ -#if defined(CONFIG_88F5182) -#include <asm/arch/mv88f5182.h> -#else -#error "SOC Name not defined" -#endif -#endif /* CONFIG_FEROCEON */ -#endif /* _ASM_ARCH_ORION5X_H */ diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S deleted file mode 100644 index aa3fcf7c3010..000000000000 --- a/arch/arm/mach-orion5x/lowlevel_init.S +++ /dev/null @@ -1,286 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#include <config.h> -#include "asm/arch/orion5x.h" - -/* - * Configuration values for SDRAM access setup - */ - -#define SDRAM_CONFIG 0x3148400 -#define SDRAM_MODE 0x62 -#define SDRAM_CONTROL 0x4041000 -#define SDRAM_TIME_CTRL_LOW 0x11602220 -#define SDRAM_TIME_CTRL_HI 0x40c -#define SDRAM_OPEN_PAGE_EN 0x0 -/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */ -#define SDRAM_BANK0_SIZE 0x3ff0001 -#define SDRAM_ADDR_CTRL 0x10 - -#define SDRAM_OP_NOP 0x05 -#define SDRAM_OP_SETMODE 0x03 - -#define SDRAM_PAD_CTRL_WR_EN 0x80000000 -#define SDRAM_PAD_CTRL_TUNE_EN 0x00010000 -#define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f -#define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0 - -/* - * For Guideline MEM-3 - Drive Strength value - */ - -#define DDR1_PAD_STRENGTH_DEFAULT 0x00001000 -#define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000 - -/* - * For Guideline MEM-4 - DQS Reference Delay Tuning - */ - -#define MSAR_ARMDDRCLCK_MASK 0x000000f0 -#define MSAR_ARMDDRCLCK_H_MASK 0x00000100 - -#define MSAR_ARMDDRCLCK_333_167 0x00000000 -#define MSAR_ARMDDRCLCK_500_167 0x00000030 -#define MSAR_ARMDDRCLCK_667_167 0x00000060 -#define MSAR_ARMDDRCLCK_400_200_1 0x000001E0 -#define MSAR_ARMDDRCLCK_400_200 0x00000010 -#define MSAR_ARMDDRCLCK_600_200 0x00000050 -#define MSAR_ARMDDRCLCK_800_200 0x00000070 - -#define FTDLL_DDR1_166MHZ 0x0047F001 - -#define FTDLL_DDR1_200MHZ 0x0044D001 - -/* - * Low-level init happens right after start.S has switched to SVC32, - * flushed and disabled caches and disabled MMU. We're still running - * from the boot chip select, so the first thing SPL should do is to - * set up the RAM to copy U-Boot into. - */ - -.globl lowlevel_init - -lowlevel_init: - -#ifdef CONFIG_SPL_BUILD - - /* Use 'r2 as the base for internal register accesses */ - ldr r2, =ORION5X_REGS_PHY_BASE - - /* move internal registers from the default 0xD0000000 - * to their intended location, defined by SoC */ - ldr r3, =0xD0000000 - add r3, r3, #0x20000 - str r2, [r3, #0x80] - - /* Use R3 as the base for DRAM registers */ - add r3, r2, #0x01000 - - /*DDR SDRAM Initialization Control */ - ldr r0, =0x00000001 - str r0, [r3, #0x480] - - /* Use R3 as the base for PCI registers */ - add r3, r2, #0x31000 - - /* Disable arbiter */ - ldr r0, =0x00000030 - str r0, [r3, #0xd00] - - /* Use R3 as the base for DRAM registers */ - add r3, r2, #0x01000 - - /* set all dram windows to 0 */ - mov r0, #0 - str r0, [r3, #0x504] - str r0, [r3, #0x50C] - str r0, [r3, #0x514] - str r0, [r3, #0x51C] - - /* 1) Configure SDRAM */ - ldr r0, =SDRAM_CONFIG - str r0, [r3, #0x400] - - /* 2) Set SDRAM Control reg */ - ldr r0, =SDRAM_CONTROL - str r0, [r3, #0x404] - - /* 3) Write SDRAM address control register */ - ldr r0, =SDRAM_ADDR_CTRL - str r0, [r3, #0x410] - - /* 4) Write SDRAM bank 0 size register */ - ldr r0, =SDRAM_BANK0_SIZE - str r0, [r3, #0x504] - /* keep other banks disabled */ - - /* 5) Write SDRAM open pages control register */ - ldr r0, =SDRAM_OPEN_PAGE_EN - str r0, [r3, #0x414] - - /* 6) Write SDRAM timing Low register */ - ldr r0, =SDRAM_TIME_CTRL_LOW - str r0, [r3, #0x408] - - /* 7) Write SDRAM timing High register */ - ldr r0, =SDRAM_TIME_CTRL_HI - str r0, [r3, #0x40C] - - /* 8) Write SDRAM mode register */ - /* The CPU must not attempt to change the SDRAM Mode register setting */ - /* prior to DRAM controller completion of the DRAM initialization */ - /* sequence. To guarantee this restriction, it is recommended that */ - /* the CPU sets the SDRAM Operation register to NOP command, performs */ - /* read polling until the register is back in Normal operation value, */ - /* and then sets SDRAM Mode register to its new value. */ - - /* 8.1 write 'nop' to SDRAM operation */ - ldr r0, =SDRAM_OP_NOP - str r0, [r3, #0x418] - - /* 8.2 poll SDRAM operation until back in 'normal' mode. */ -1: - ldr r0, [r3, #0x418] - cmp r0, #0 - bne 1b - - /* 8.3 Now its safe to write new value to SDRAM Mode register */ - ldr r0, =SDRAM_MODE - str r0, [r3, #0x41C] - - /* 8.4 Set new mode */ - ldr r0, =SDRAM_OP_SETMODE - str r0, [r3, #0x418] - - /* 8.5 poll SDRAM operation until back in 'normal' mode. */ -2: - ldr r0, [r3, #0x418] - cmp r0, #0 - bne 2b - - /* DDR SDRAM Address/Control Pads Calibration */ - ldr r0, [r3, #0x4C0] - - /* Set Bit [31] to make the register writable */ - orr r0, r0, #SDRAM_PAD_CTRL_WR_EN - str r0, [r3, #0x4C0] - - bic r0, r0, #SDRAM_PAD_CTRL_WR_EN - bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN - bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK - bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK - - /* Get the final N locked value of driving strength [22:17] */ - mov r1, r0 - mov r1, r1, LSL #9 - mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */ - orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */ - - /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ - orr r0, r0, r1 - str r0, [r3, #0x4C0] - - /* DDR SDRAM Data Pads Calibration */ - ldr r0, [r3, #0x4C4] - - /* Set Bit [31] to make the register writable */ - orr r0, r0, #SDRAM_PAD_CTRL_WR_EN - str r0, [r3, #0x4C4] - - bic r0, r0, #SDRAM_PAD_CTRL_WR_EN - bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN - bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK - bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK - - /* Get the final N locked value of driving strength [22:17] */ - mov r1, r0 - mov r1, r1, LSL #9 - mov r1, r1, LSR #26 - orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */ - - /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ - orr r0, r0, r1 - - str r0, [r3, #0x4C4] - - /* Implement Guideline (GL# MEM-3) Drive Strength Value */ - /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ - - ldr r1, =DDR1_PAD_STRENGTH_DEFAULT - - /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */ - ldr r0, [r3, #0x4C0] - orr r0, r0, #SDRAM_PAD_CTRL_WR_EN - str r0, [r3, #0x4C0] - - /* Correct strength and disable writes again */ - bic r0, r0, #SDRAM_PAD_CTRL_WR_EN - bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK - orr r0, r0, r1 - str r0, [r3, #0x4C0] - - /* Enable writes to DDR SDRAM Data Pads Calibration register */ - ldr r0, [r3, #0x4C4] - orr r0, r0, #SDRAM_PAD_CTRL_WR_EN - str r0, [r3, #0x4C4] - - /* Correct strength and disable writes again */ - bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK - bic r0, r0, #SDRAM_PAD_CTRL_WR_EN - orr r0, r0, r1 - str r0, [r3, #0x4C4] - - /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ - /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ - - /* Get the "sample on reset" register for the DDR frequancy */ - ldr r3, =0x10000 - ldr r0, [r3, #0x010] - ldr r1, =MSAR_ARMDDRCLCK_MASK - and r1, r0, r1 - - ldr r0, =FTDLL_DDR1_166MHZ - cmp r1, #MSAR_ARMDDRCLCK_333_167 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_500_167 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_667_167 - beq 3f - - ldr r0, =FTDLL_DDR1_200MHZ - cmp r1, #MSAR_ARMDDRCLCK_400_200_1 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_400_200 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_600_200 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_800_200 - beq 3f - - ldr r0, =0 - -3: - /* Use R3 as the base for DRAM registers */ - add r3, r2, #0x01000 - - ldr r2, [r3, #0x484] - orr r2, r2, r0 - str r2, [r3, #0x484] - - /* enable for 2 GB DDR; detection should find out real amount */ - sub r0, r0, r0 - str r0, [r3, #0x500] - ldr r0, =0x7fff0001 - str r0, [r3, #0x504] - -#endif /* CONFIG_SPL_BUILD */ - - /* Return to U-Boot via saved link register */ - mov pc, lr diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c deleted file mode 100644 index 0adf3dcc6483..000000000000 --- a/arch/arm/mach-orion5x/timer.c +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net - * - * Based on original Kirkwood support which is - * Copyright (C) Marvell International Ltd. and its affiliates - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#include <common.h> -#include <init.h> -#include <time.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <linux/delay.h> - -#define UBOOT_CNTR 0 /* counter to use for uboot timer */ - -/* Timer reload and current value registers */ -struct orion5x_tmr_val { - u32 reload; /* Timer reload reg */ - u32 val; /* Timer value reg */ -}; - -/* Timer registers */ -struct orion5x_tmr_registers { - u32 ctrl; /* Timer control reg */ - u32 pad[3]; - struct orion5x_tmr_val tmr[2]; - u32 wdt_reload; - u32 wdt_val; -}; - -struct orion5x_tmr_registers *orion5x_tmr_regs = - (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE; - -/* - * ARM Timers Registers Map - */ -#define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl) -#define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload) -#define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val) - -/* - * ARM Timers Control Register - * CPU_TIMERS_CTRL_REG (CTCR) - */ -#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) -#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) -#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) - -#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) -#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) - -/* - * ARM Timer\Watchdog Reload Register - * CNTMR_RELOAD_REG (TRR) - */ -#define TRG_ARM_TIMER_REL_OFFS 0 -#define TRG_ARM_TIMER_REL_MASK 0xffffffff - -/* - * ARM Timer\Watchdog Register - * CNTMR_VAL_REG (TVRG) - */ -#define TVR_ARM_TIMER_OFFS 0 -#define TVR_ARM_TIMER_MASK 0xffffffff -#define TVR_ARM_TIMER_MAX 0xffffffff -#define TIMER_LOAD_VAL 0xffffffff - -static inline ulong read_timer(void) -{ - return readl(CNTMR_VAL_REG(UBOOT_CNTR)) - / (CONFIG_SYS_TCLK / 1000); -} - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc - -static ulong get_timer_masked(void) -{ - ulong now = read_timer(); - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + - (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; - } - lastdec = now; - - return timestamp; -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -static inline ulong uboot_cntr_val(void) -{ - return readl(CNTMR_VAL_REG(UBOOT_CNTR)); -} - -void __udelay(unsigned long usec) -{ - uint current; - ulong delayticks; - - current = uboot_cntr_val(); - delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); - - if (current < delayticks) { - delayticks -= current; - while (uboot_cntr_val() < current) - ; - while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val()) - ; - } else { - while (uboot_cntr_val() > (current - delayticks)) - ; - } -} - -/* - * init the counter - */ -int timer_init(void) -{ - unsigned int cntmrctrl; - - /* load value into timer */ - writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); - writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); - - /* enable timer in auto reload mode */ - cntmrctrl = readl(CNTMR_CTRL_REG); - cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); - cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); - writel(cntmrctrl, CNTMR_CTRL_REG); - return 0; -} - -void timer_init_r(void) -{ - /* init the timestamp and lastdec value */ - lastdec = read_timer(); - timestamp = 0; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return (ulong)CONFIG_SYS_HZ; -} diff --git a/arch/arm/mach-orion5x/u-boot-spl.lds b/arch/arm/mach-orion5x/u-boot-spl.lds deleted file mode 100644 index a537fe02954b..000000000000 --- a/arch/arm/mach-orion5x/u-boot-spl.lds +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 Albert ARIBAUD albert.u.boot@aribaud.net - * - * Based on: - * - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie tangliang@allwinnertech.com - * - * Based on omap-common/u-boot-spl.lds: - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, garyj@denx.de - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V aneesh@ti.com - */ -MEMORY { .nor : ORIGIN = IMAGE_TEXT_BASE,\ - LENGTH = IMAGE_MAX_SIZE } -MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ - LENGTH = CONFIG_SPL_BSS_MAX_SIZE } - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - .text : - { - __start = .; - *(.vectors) - CPUDIR/start.o (.text) - *(.text*) - } > .nor - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.nor - - . = ALIGN(4); - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } > .nor - - . = ALIGN(4); - __image_copy_end = .; - _end = .; - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } > .bss -} diff --git a/board/LaCie/edminiv2/Kconfig b/board/LaCie/edminiv2/Kconfig deleted file mode 100644 index ac3fe3fbcb3e..000000000000 --- a/board/LaCie/edminiv2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_EDMINIV2 - -config SYS_BOARD - default "edminiv2" - -config SYS_VENDOR - default "LaCie" - -config SYS_CONFIG_NAME - default "edminiv2" - -endif diff --git a/board/LaCie/edminiv2/MAINTAINERS b/board/LaCie/edminiv2/MAINTAINERS deleted file mode 100644 index e0591f4b80e1..000000000000 --- a/board/LaCie/edminiv2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -EDMINIV2 BOARD -M: Albert ARIBAUD albert.u.boot@aribaud.net -S: Maintained -F: board/LaCie/edminiv2/ -F: include/configs/edminiv2.h -F: configs/edminiv2_defconfig diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile deleted file mode 100644 index 5252c2b0e60e..000000000000 --- a/board/LaCie/edminiv2/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net -# -# Based on original Kirkwood support which is -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com - -obj-y := edminiv2.o ../common/common.o diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c deleted file mode 100644 index 9c066a283c99..000000000000 --- a/board/LaCie/edminiv2/edminiv2.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#include <common.h> -#include <miiphy.h> -#include <net.h> -#include <asm/arch/orion5x.h> -#include <asm/global_data.h> -#include "../common/common.h" -#include <spl.h> -#include <ns16550.h> -#include <asm/mach-types.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* arch number of board */ - gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2; - - /* boot parameter start at 256th byte of RAM base */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; - - return 0; -} - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) -{ - mv_phy_88e1116_init("egiga0", 8); -} -#endif /* CONFIG_RESET_PHY_R */ - -/* - * SPL serial setup and NOR boot device selection - */ - -#ifdef CONFIG_SPL_BUILD - -void spl_board_init(void) -{ - preloader_console_init(); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_NOR; -} - -#endif /* CONFIG_SPL_BUILD */ diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig deleted file mode 100644 index e74f4dbed95c..000000000000 --- a/configs/edminiv2_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_ORION5X=y -CONFIG_SPL_LDSCRIPT="arch/arm/mach-orion5x/u-boot-spl.lds" -CONFIG_SYS_TEXT_BASE=0x00800000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x2000 -CONFIG_SYS_MALLOC_LEN=0x40000 -CONFIG_SPL_TEXT_BASE=0xffff0000 -CONFIG_TARGET_EDMINIV2=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_IDENT_STRING=" EDMiniV2" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="EDMiniV2> " -CONFIG_CMD_IMLS=y -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_EXT2=y -CONFIG_ISO_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xFFF84000 -CONFIG_NETCONSOLE=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index d33e2c7c9d83..7c89fc719592 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -28,9 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; */
#if !CONFIG_IS_ENABLED(DM_I2C) -#if defined(CONFIG_ARCH_ORION5X) -#include <asm/arch/orion5x.h> -#elif (defined(CONFIG_ARCH_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) +#if (defined(CONFIG_ARCH_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) #include <asm/arch/soc.h> #elif defined(CONFIG_ARCH_SUNXI) #include <asm/arch/i2c.h> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 8b1add19e8f1..9461e2e191e9 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -415,7 +415,7 @@ config KSZ9477
config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" - depends on ARCH_KIRKWOOD || ARCH_ORION5X + depends on ARCH_KIRKWOOD select PHYLIB if DM_ETH help This driver supports the network interface units in the diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index ce5b8eed64b4..b9b036fd133a 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -29,8 +29,6 @@
#if defined(CONFIG_ARCH_KIRKWOOD) #include <asm/arch/soc.h> -#elif defined(CONFIG_ARCH_ORION5X) -#include <asm/arch/orion5x.h> #endif
#include "mvgbe.h" diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 8957bb56a6be..a1882a17f857 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -138,7 +138,7 @@ config USB_EHCI_ATMEL
config USB_EHCI_MARVELL bool "Support for Marvell on-chip EHCI USB controller" - depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X + depends on ARCH_MVEBU || ARCH_KIRKWOOD default y ---help--- Enables support for the on-chip EHCI controller on MVEBU SoCs. diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 5420bb9772b5..412abdabd6eb 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -18,8 +18,6 @@
#if defined(CONFIG_ARCH_KIRKWOOD) #include <asm/arch/soc.h> -#elif defined(CONFIG_ARCH_ORION5X) -#include <asm/arch/orion5x.h> #endif
DECLARE_GLOBAL_DATA_PTR; diff --git a/env/flash.c b/env/flash.c index ebee9069e4e3..2f9c5de65fdd 100644 --- a/env/flash.c +++ b/env/flash.c @@ -34,8 +34,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* TODO(sjg@chromium.org): Figure out all these special cases */ #if (!defined(CONFIG_MICROBLAZE) && !defined(CONFIG_ARCH_ZYNQ) && \ - !defined(CONFIG_TARGET_MCCMON6) && !defined(CONFIG_TARGET_X600) && \ - !defined(CONFIG_TARGET_EDMINIV2)) || \ + !defined(CONFIG_TARGET_MCCMON6) && !defined(CONFIG_TARGET_X600)) || \ !defined(CONFIG_SPL_BUILD) #define LOADENV #endif diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h deleted file mode 100644 index fbe468010bfc..000000000000 --- a/include/configs/edminiv2.h +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net - * - * Based on original Kirkwood support which is - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#ifndef _CONFIG_EDMINIV2_H -#define _CONFIG_EDMINIV2_H - -/* - * SPL - */ - -#define CONFIG_SPL_MAX_SIZE 0x0000fff0 -#define CONFIG_SPL_STACK 0x00020000 -#define CONFIG_SPL_BSS_START_ADDR 0x00020000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff -#define CONFIG_SYS_SPL_MALLOC_START 0x00040000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff -#define CONFIG_SYS_UBOOT_BASE 0xfff90000 -#define CONFIG_SYS_UBOOT_START 0x00800000 - -/* - * High Level Configuration Options (easy to change) - */ - -#define CONFIG_FEROCEON 1 /* CPU Core subversion */ -#define CONFIG_88F5182 1 /* SOC Name */ - -#include <asm/arch/orion5x.h> -/* - * CLKs configurations - */ - -/* - * Board-specific values for Orion5x MPP low level init: - * - MPPs 12 to 15 are SATA LEDs (mode 5) - * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for - * MPP16 to MPP19, mode 0 for others - */ - -#define ORION5X_MPP0_7 0x00000003 -#define ORION5X_MPP8_15 0x55550000 -#define ORION5X_MPP16_23 0x00005555 - -/* - * Board-specific values for Orion5x GPIO low level init: - * - GPIO3 is input (RTC interrupt) - * - GPIO16 is Power LED control (0 = on, 1 = off) - * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) - * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) - * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) - * - GPIO22 is SATA disk power status () - * - GPIO23 is supply status for SATA disk () - * - GPIO24 is supply control for board (write 1 to power off) - * Last GPIO is 25, further bits are supposed to be 0. - * Enable mask has ones for INPUT, 0 for OUTPUT. - * Default is LED ON, board ON :) - */ - -#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca -#define ORION5X_GPIO_OUT_VALUE 0x00000000 -#define ORION5X_GPIO_IN_POLARITY 0x000000d0 - -/* - * NS16550 Configuration - */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } - -/* - * FLASH configuration - */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BASE 0xfff80000 - -/* auto boot */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ - -/* - * Network - */ - -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ -#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ -#define CONFIG_PHY_BASE_ADR 0x8 -#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ -#endif - -/* - * IDE - */ -#ifdef CONFIG_IDE -#define __io -/* Needs byte-swapping for ATA data register */ -#define CONFIG_IDE_SWAP_IO -/* Data, registers and alternate blocks are at the same offset */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) -#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) -#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) -/* Each 8-bit ATA register is aligned to a 4-bytes address */ -#define CONFIG_SYS_ATA_STRIDE 4 -/* Controller supports 48-bits LBA addressing */ -#define CONFIG_LBA48 -/* A single bus, a single device */ -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 -/* ATA registers base is at SATA controller base */ -#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE -/* ATA bus 0 is orion5x port 1 on ED Mini V2 */ -#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET -/* end of IDE defines */ -#endif /* CMD_IDE */ - -/* - * Common USB/EHCI configuration - */ -#ifdef CONFIG_CMD_USB -#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE -#endif /* CONFIG_CMD_USB */ - -/* - * I2C related stuff - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE -#endif - -/* - * Environment variables configurations - */ - -/* - * Other required minimal configurations - */ - -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 - -/* Enable command line editing */ - -/* provide extensive help */ - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* _CONFIG_EDMINIV2_H */
On 09.09.21 13:54, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last orion5x platform, remove that support as well.
Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Stefan Roese sr@denx.de Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/Kconfig | 7 - arch/arm/Makefile | 1 - arch/arm/include/asm/arch-orion5x/spl.h | 9 - arch/arm/mach-orion5x/Kconfig | 18 -- arch/arm/mach-orion5x/Makefile | 26 -- arch/arm/mach-orion5x/cpu.c | 298 ------------------ arch/arm/mach-orion5x/dram.c | 58 ---- arch/arm/mach-orion5x/include/mach/cpu.h | 242 -------------- .../arm/mach-orion5x/include/mach/mv88f5182.h | 23 -- arch/arm/mach-orion5x/include/mach/orion5x.h | 66 ---- arch/arm/mach-orion5x/lowlevel_init.S | 286 ----------------- arch/arm/mach-orion5x/timer.c | 174 ---------- arch/arm/mach-orion5x/u-boot-spl.lds | 60 ----
If nobody steps up to start / continue maintaining orion5, then:
Acked-by: Stefan Roese sr@denx.de
Thanks, Stefan
board/LaCie/edminiv2/Kconfig | 12 - board/LaCie/edminiv2/MAINTAINERS | 6 - board/LaCie/edminiv2/Makefile | 10 - board/LaCie/edminiv2/edminiv2.c | 57 ---- configs/edminiv2_defconfig | 47 --- drivers/i2c/mvtwsi.c | 4 +- drivers/net/Kconfig | 2 +- drivers/net/mvgbe.c | 2 - drivers/usb/host/Kconfig | 2 +- drivers/usb/host/ehci-marvell.c | 2 - env/flash.c | 3 +- include/configs/edminiv2.h | 169 ---------- 25 files changed, 4 insertions(+), 1580 deletions(-) delete mode 100644 arch/arm/include/asm/arch-orion5x/spl.h delete mode 100644 arch/arm/mach-orion5x/Kconfig delete mode 100644 arch/arm/mach-orion5x/Makefile delete mode 100644 arch/arm/mach-orion5x/cpu.c delete mode 100644 arch/arm/mach-orion5x/dram.c delete mode 100644 arch/arm/mach-orion5x/include/mach/cpu.h delete mode 100644 arch/arm/mach-orion5x/include/mach/mv88f5182.h delete mode 100644 arch/arm/mach-orion5x/include/mach/orion5x.h delete mode 100644 arch/arm/mach-orion5x/lowlevel_init.S delete mode 100644 arch/arm/mach-orion5x/timer.c delete mode 100644 arch/arm/mach-orion5x/u-boot-spl.lds delete mode 100644 board/LaCie/edminiv2/Kconfig delete mode 100644 board/LaCie/edminiv2/MAINTAINERS delete mode 100644 board/LaCie/edminiv2/Makefile delete mode 100644 board/LaCie/edminiv2/edminiv2.c delete mode 100644 configs/edminiv2_defconfig delete mode 100644 include/configs/edminiv2.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 70ab47cce056..c98b2fe54216 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -545,11 +545,6 @@ config ARCH_MVEBU select SPI imply CMD_DM
-config ARCH_ORION5X
- bool "Marvell Orion"
- select CPU_ARM926EJS
- select GPIO_EXTRA_HEADER
- config TARGET_STV0991 bool "Support stv0991" select CPU_V7A
@@ -2032,8 +2027,6 @@ source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
-source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/mach-owl/Kconfig"
source "arch/arm/mach-rmobile/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c68e598a675b..eb7802b59099 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -68,7 +68,6 @@ machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MVEBU) += mvebu machine-$(CONFIG_ARCH_NEXELL) += nexell machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 -machine-$(CONFIG_ARCH_ORION5X) += orion5x machine-$(CONFIG_ARCH_OWL) += owl machine-$(CONFIG_ARCH_RMOBILE) += rmobile machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip diff --git a/arch/arm/include/asm/arch-orion5x/spl.h b/arch/arm/include/asm/arch-orion5x/spl.h deleted file mode 100644 index dc0a9b9099cb..000000000000 --- a/arch/arm/include/asm/arch-orion5x/spl.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- (C) Copyright 2014 Albert ARIBAUD albert.u.boot@aribaud.net
- */
-#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_
-#define BOOT_DEVICE_NOR 1 diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig deleted file mode 100644 index 5baa6fb935ae..000000000000 --- a/arch/arm/mach-orion5x/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if ARCH_ORION5X
-choice
- prompt "Marvell Orion board select"
- optional
-config TARGET_EDMINIV2
- bool "LaCie Ethernet Disk mini V2"
- select SUPPORT_SPL
-endchoice
-config SYS_SOC
- default "orion5x"
-source "board/LaCie/edminiv2/Kconfig"
-endif diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile deleted file mode 100644 index a8b87f6d7103..000000000000 --- a/arch/arm/mach-orion5x/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net -# -# Based on original Kirkwood support which is -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com
-obj-y = cpu.o -obj-y += dram.o -obj-y += timer.o
-ifndef CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT -obj-y += lowlevel_init.o -endif
-# some files can only build in ARM or THUMB2, not THUMB1
-ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD -ifndef CONFIG_HAS_THUMB2
-CFLAGS_cpu.o := -marm
-endif -endif diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c deleted file mode 100644 index ffae9a01e37c..000000000000 --- a/arch/arm/mach-orion5x/cpu.c +++ /dev/null @@ -1,298 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net
- Based on original Kirkwood support which is
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- */
-#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <net.h> -#include <netdev.h> -#include <asm/cache.h> -#include <asm/io.h> -#include <u-boot/md5.h> -#include <asm/arch/cpu.h>
-#define BUFLEN 16
-void reset_cpu(void) -{
- struct orion5x_cpu_registers *cpureg =
(struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;- writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
&cpureg->rstoutn_mask);- writel(readl(&cpureg->sys_soft_rst) | 1,
&cpureg->sys_soft_rst);- while (1)
;-}
-/*
- Compute Window Size field value from size expressed in bytes
- Used with the Base register to set the address window size and location.
- Must be programmed from LSB to MSB as sequence of ones followed by
- sequence of zeros. The number of ones specifies the size of the window in
- 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
- NOTES:
- A sizeval equal to 0x0 specifies 4 GiB.
- A return value of 0x0 specifies 64 KiB.
- */
-unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) -{
- /*
* Calculate the number of 64 KiB blocks needed minus one (rounding up).* For sizeval > 0 this is equivalent to:* sizeval = (u32) ceil((double) sizeval / 65536.0) - 1*/- sizeval = (sizeval - 1) >> 16;
- /*
* Propagate 'one' bits to the right by 'oring' them.* We need only treat bits 15-0.*/- sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */
- sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */
- sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */
- sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/
- return sizeval;
-}
-/*
- orion5x_config_adr_windows - Configure address Windows
- There are 8 address windows supported by Orion5x Soc to addess different
- devices. Each window can be configured for size, BAR and remap addr
- Below configuration is standard for most of the cases
- If remap function not used, remap_lo must be set as base
- NOTES:
- in order to avoid windows with inconsistent control and base values
- (which could prevent access to BOOTCS and hence execution from FLASH)
- always disable window before writing the base value then reenable it
- by writing the control value.
- in order to avoid losing access to BOOTCS when disabling window 7,
- first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
- then configure windows 6 for its own target.
- Reference Documentation:
- Mbus-L to Mbus Bridge Registers Configuration.
- (Sec 25.1 and 25.3 of Datasheet)
- */
-int orion5x_config_adr_windows(void) -{
- struct orion5x_win_registers *winregs =
(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;-/* Disable window 0, configure it for its intended target, enable it. */
- writel(0, &winregs[0].ctrl);
- writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
- writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
- writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,ORION5X_WIN_ENABLE), &winregs[0].ctrl);-/* Disable window 1, configure it for its intended target, enable it. */
- writel(0, &winregs[1].ctrl);
- writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
- writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
- writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,ORION5X_WIN_ENABLE), &winregs[1].ctrl);-/* Disable window 2, configure it for its intended target, enable it. */
- writel(0, &winregs[2].ctrl);
- writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,ORION5X_WIN_ENABLE), &winregs[2].ctrl);-/* Disable window 3, configure it for its intended target, enable it. */
- writel(0, &winregs[3].ctrl);
- writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,ORION5X_WIN_ENABLE), &winregs[3].ctrl);-/* Disable window 4, configure it for its intended target, enable it. */
- writel(0, &winregs[4].ctrl);
- writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,ORION5X_WIN_ENABLE), &winregs[4].ctrl);-/* Disable window 5, configure it for its intended target, enable it. */
- writel(0, &winregs[5].ctrl);
- writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,ORION5X_WIN_ENABLE), &winregs[5].ctrl);-/* Disable window 6, configure it for FLASH, enable it. */
- writel(0, &winregs[6].ctrl);
- writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,ORION5X_WIN_ENABLE), &winregs[6].ctrl);-/* Disable window 7, configure it for FLASH, enable it. */
- writel(0, &winregs[7].ctrl);
- writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,ORION5X_WIN_ENABLE), &winregs[7].ctrl);-/* Disable window 6, configure it for its intended target, enable it. */
- writel(0, &winregs[6].ctrl);
- writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,ORION5X_WIN_ENABLE), &winregs[6].ctrl);- return 0;
-}
-/*
- Orion5x identification is done through PCIE space.
- */
-u32 orion5x_device_id(void) -{
- return readl(PCIE_DEV_ID_OFF) >> 16;
-}
-u32 orion5x_device_rev(void) -{
- return readl(PCIE_DEV_REV_OFF) & 0xff;
-}
-#if defined(CONFIG_DISPLAY_CPUINFO)
-/* Display device and revision IDs.
- This function must cover all known device/revision
- combinations, not only the one for which u-boot is
- compiled; this way, one can identify actual HW in
- case of a mismatch.
- */
-int print_cpuinfo(void) -{
- char dev_str[7]; /* room enough for 0x0000 plus null byte */
- char rev_str[5]; /* room enough for 0x00 plus null byte */
- char *dev_name = NULL;
- char *rev_name = NULL;
- u32 dev = orion5x_device_id();
- u32 rev = orion5x_device_rev();
- if (dev == MV88F5181_DEV_ID) {
dev_name = "MV88F5181";if (rev == MV88F5181_REV_B1)rev_name = "B1";else if (rev == MV88F5181L_REV_A1) {dev_name = "MV88F5181L";rev_name = "A1";} else if (rev == MV88F5181L_REV_A0) {dev_name = "MV88F5181L";rev_name = "A0";}- } else if (dev == MV88F5182_DEV_ID) {
dev_name = "MV88F5182";if (rev == MV88F5182_REV_A2)rev_name = "A2";- } else if (dev == MV88F5281_DEV_ID) {
dev_name = "MV88F5281";if (rev == MV88F5281_REV_D2)rev_name = "D2";else if (rev == MV88F5281_REV_D1)rev_name = "D1";else if (rev == MV88F5281_REV_D0)rev_name = "D0";- } else if (dev == MV88F6183_DEV_ID) {
dev_name = "MV88F6183";if (rev == MV88F6183_REV_B0)rev_name = "B0";- }
- if (dev_name == NULL) {
sprintf(dev_str, "0x%04x", dev);dev_name = dev_str;- }
- if (rev_name == NULL) {
sprintf(rev_str, "0x%02x", rev);rev_name = rev_str;- }
- printf("SoC: Orion5x %s-%s\n", dev_name, rev_name);
- return 0;
-} -#endif /* CONFIG_DISPLAY_CPUINFO */
-#ifdef CONFIG_ARCH_CPU_INIT -int arch_cpu_init(void) -{
- /* Enable and invalidate L2 cache in write through mode */
- invalidate_l2_cache();
-#ifdef CONFIG_SPL_BUILD
- orion5x_config_adr_windows();
-#endif
- return 0;
-} -#endif /* CONFIG_ARCH_CPU_INIT */
-/*
- SOC specific misc init
- */
-#if defined(CONFIG_ARCH_MISC_INIT) -int arch_misc_init(void) -{
- u32 temp;
- /*CPU streaming & write allocate */
- temp = readfr_extra_feature_reg();
- temp &= ~(1 << 28); /* disable wr alloc */
- writefr_extra_feature_reg(temp);
- temp = readfr_extra_feature_reg();
- temp &= ~(1 << 29); /* streaming disabled */
- writefr_extra_feature_reg(temp);
- /* L2Cache settings */
- temp = readfr_extra_feature_reg();
- /* Disable L2C pre fetch - Set bit 24 */
- temp |= (1 << 24);
- /* enable L2C - Set bit 22 */
- temp |= (1 << 22);
- writefr_extra_feature_reg(temp);
- icache_enable();
- /* Change reset vector to address 0x0 */
- temp = get_cr();
- set_cr(temp & ~CR_V);
- /* Set CPIOs and MPPs - values provided by board
include file */- writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
- writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
- writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
- writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
- writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
- writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);
- /* initialize timer */
- timer_init_r();
- return 0;
-} -#endif /* CONFIG_ARCH_MISC_INIT */
-#ifdef CONFIG_MVGBE -int cpu_eth_init(struct bd_info *bis) -{
- mvgbe_initialize(bis);
- return 0;
-} -#endif diff --git a/arch/arm/mach-orion5x/dram.c b/arch/arm/mach-orion5x/dram.c deleted file mode 100644 index c9a3750e48de..000000000000 --- a/arch/arm/mach-orion5x/dram.c +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net
- Based on original Kirkwood support which is
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- */
-#include <common.h> -#include <config.h> -#include <init.h> -#include <asm/arch/cpu.h> -#include <asm/global_data.h>
-DECLARE_GLOBAL_DATA_PTR;
-/*
- orion5x_sdram_bar - reads SDRAM Base Address Register
- */
-u32 orion5x_sdram_bar(enum memory_bank bank) -{
- struct orion5x_ddr_addr_decode_registers *winregs =
(struct orion5x_ddr_addr_decode_registers *)ORION5X_DRAM_BASE;- u32 result = 0;
- u32 enable = 0x01 & winregs[bank].size;
- if ((!enable) || (bank > BANK3))
return 0;- result = winregs[bank].base;
- return result;
-} -int dram_init (void) -{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size(
(long *) orion5x_sdram_bar(0),CONFIG_MAX_RAM_BANK_SIZE);- return 0;
-}
-int dram_init_banksize(void) -{
- int i;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);gd->bd->bi_dram[i].size = get_ram_size((long *) (gd->bd->bi_dram[i].start),CONFIG_MAX_RAM_BANK_SIZE);- }
- return 0;
-} diff --git a/arch/arm/mach-orion5x/include/mach/cpu.h b/arch/arm/mach-orion5x/include/mach/cpu.h deleted file mode 100644 index c3ff89669e45..000000000000 --- a/arch/arm/mach-orion5x/include/mach/cpu.h +++ /dev/null @@ -1,242 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net
- Based on original Kirorion5x_ood support which is
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- */
-#ifndef _ORION5X_CPU_H -#define _ORION5X_CPU_H
-#include <asm/system.h>
-#ifndef __ASSEMBLY__
-#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
| (attr << 8) | (orion5x_winctrl_calcsize(size) << 16))-#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \
((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)-enum memory_bank {
- BANK0,
- BANK1,
- BANK2,
- BANK3
-};
-enum orion5x_cpu_winen {
- ORION5X_WIN_DISABLE,
- ORION5X_WIN_ENABLE
-};
-enum orion5x_cpu_target {
- ORION5X_TARGET_DRAM = 0,
- ORION5X_TARGET_DEVICE = 1,
- ORION5X_TARGET_PCI = 3,
- ORION5X_TARGET_PCIE = 4,
- ORION5X_TARGET_SASRAM = 9
-};
-enum orion5x_cpu_attrib {
- ORION5X_ATTR_DRAM_CS0 = 0x0e,
- ORION5X_ATTR_DRAM_CS1 = 0x0d,
- ORION5X_ATTR_DRAM_CS2 = 0x0b,
- ORION5X_ATTR_DRAM_CS3 = 0x07,
- ORION5X_ATTR_PCI_MEM = 0x59,
- ORION5X_ATTR_PCI_IO = 0x51,
- ORION5X_ATTR_PCIE_MEM = 0x59,
- ORION5X_ATTR_PCIE_IO = 0x51,
- ORION5X_ATTR_SASRAM = 0x00,
- ORION5X_ATTR_DEV_CS0 = 0x1e,
- ORION5X_ATTR_DEV_CS1 = 0x1d,
- ORION5X_ATTR_DEV_CS2 = 0x1b,
- ORION5X_ATTR_BOOTROM = 0x0f
-};
-/*
- Device Address MAP BAR values
- All addresses and sizes not defined by board code
- will be given default values here.
- */
-#if !defined (ORION5X_ADR_PCIE_MEM) -#define ORION5X_ADR_PCIE_MEM 0x90000000 -#endif
-#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO) -#define ORION5X_ADR_PCIE_MEM_REMAP_LO 0x90000000 -#endif
-#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI) -#define ORION5X_ADR_PCIE_MEM_REMAP_HI 0 -#endif
-#if !defined (ORION5X_SZ_PCIE_MEM) -#define ORION5X_SZ_PCIE_MEM (128*1024*1024) -#endif
-#if !defined (ORION5X_ADR_PCIE_IO) -#define ORION5X_ADR_PCIE_IO 0xf0000000 -#endif
-#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO) -#define ORION5X_ADR_PCIE_IO_REMAP_LO 0xf0000000 -#endif
-#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI) -#define ORION5X_ADR_PCIE_IO_REMAP_HI 0 -#endif
-#if !defined (ORION5X_SZ_PCIE_IO) -#define ORION5X_SZ_PCIE_IO (64*1024) -#endif
-#if !defined (ORION5X_ADR_PCI_MEM) -#define ORION5X_ADR_PCI_MEM 0x98000000 -#endif
-#if !defined (ORION5X_SZ_PCI_MEM) -#define ORION5X_SZ_PCI_MEM (128*1024*1024) -#endif
-#if !defined (ORION5X_ADR_PCI_IO) -#define ORION5X_ADR_PCI_IO 0xf0100000 -#endif
-#if !defined (ORION5X_SZ_PCI_IO) -#define ORION5X_SZ_PCI_IO (64*1024) -#endif
-#if !defined (ORION5X_ADR_DEV_CS0) -#define ORION5X_ADR_DEV_CS0 0xfa000000 -#endif
-#if !defined (ORION5X_SZ_DEV_CS0) -#define ORION5X_SZ_DEV_CS0 (2*1024*1024) -#endif
-#if !defined (ORION5X_ADR_DEV_CS1) -#define ORION5X_ADR_DEV_CS1 0xf8000000 -#endif
-#if !defined (ORION5X_SZ_DEV_CS1) -#define ORION5X_SZ_DEV_CS1 (32*1024*1024) -#endif
-#if !defined (ORION5X_ADR_DEV_CS2) -#define ORION5X_ADR_DEV_CS2 0xfa800000 -#endif
-#if !defined (ORION5X_SZ_DEV_CS2) -#define ORION5X_SZ_DEV_CS2 (1*1024*1024) -#endif
-#if !defined (ORION5X_ADR_BOOTROM) -#define ORION5X_ADR_BOOTROM 0xFFF80000 -#endif
-#if !defined (ORION5X_SZ_BOOTROM) -#define ORION5X_SZ_BOOTROM (512*1024) -#endif
-/*
- PCIE registers are used for SoC device ID and revision
- */
-#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000) -#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
-/*
- The following definitions are intended for identifying
- the real device and revision on which u-boot is running
- even if it was compiled only for a specific one. Thus,
- these constants must not be considered chip-specific.
- */
-/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ -#define MV88F5181_DEV_ID 0x5181 -#define MV88F5181_REV_B1 3 -#define MV88F5181L_REV_A0 8 -#define MV88F5181L_REV_A1 9 -/* Orion-NAS (88F5182) */ -#define MV88F5182_DEV_ID 0x5182 -#define MV88F5182_REV_A2 2 -/* Orion-2 (88F5281) */ -#define MV88F5281_DEV_ID 0x5281 -#define MV88F5281_REV_D0 4 -#define MV88F5281_REV_D1 5 -#define MV88F5281_REV_D2 6 -/* Orion-1-90 (88F6183) */ -#define MV88F6183_DEV_ID 0x6183 -#define MV88F6183_REV_B0 3
-/*
- read feroceon core extra feature register
- using co-proc instruction
- */
-static inline unsigned int readfr_extra_feature_reg(void) -{
- unsigned int val;
- asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
(val) : : "cc");- return val;
-}
-/*
- write feroceon core extra feature register
- using co-proc instruction
- */
-static inline void writefr_extra_feature_reg(unsigned int val) -{
- asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
(val) : "cc");- isb();
-}
-/*
- AHB to Mbus Bridge Registers
- Source: 88F5182 User Manual, Appendix A, section A.4
- Note: only windows 0 and 1 have remap capability.
- */
-struct orion5x_win_registers {
- u32 ctrl;
- u32 base;
- u32 remap_lo;
- u32 remap_hi;
-};
-/*
- CPU control and status Registers
- Source: 88F5182 User Manual, Appendix A, section A.4
- */
-struct orion5x_cpu_registers {
- u32 config; /*0x20100 */
- u32 ctrl_stat; /*0x20104 */
- u32 rstoutn_mask; /* 0x20108 */
- u32 sys_soft_rst; /* 0x2010C */
- u32 ahb_mbus_cause_irq; /* 0x20110 */
- u32 ahb_mbus_mask_irq; /* 0x20114 */
-};
-/*
- DDR SDRAM Controller Address Decode Registers
- Source: 88F5182 User Manual, Appendix A, section A.5.1
- */
-struct orion5x_ddr_addr_decode_registers {
- u32 base;
- u32 size;
-};
-/*
- functions
- */
-u32 orion5x_device_id(void); -u32 orion5x_device_rev(void); -unsigned int orion5x_winctrl_calcsize(unsigned int sizeval); -void timer_init_r(void); -#endif /* __ASSEMBLY__ */ -#endif /* _ORION5X_CPU_H */ diff --git a/arch/arm/mach-orion5x/include/mach/mv88f5182.h b/arch/arm/mach-orion5x/include/mach/mv88f5182.h deleted file mode 100644 index 0e9fe0dc51af..000000000000 --- a/arch/arm/mach-orion5x/include/mach/mv88f5182.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net
- Based on original Kirkwood 88F6182 support which is
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- Header file for Feroceon CPU core 88F5182 SOC.
- */
-#ifndef _CONFIG_88F5182_H -#define _CONFIG_88F5182_H
-/* SOC specific definitions */ -#define F88F5182_REGS_PHYS_BASE 0xf1000000 -#define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE
-/* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
-#endif /* _CONFIG_88F5182_H */ diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h deleted file mode 100644 index 4b1b0b0f3716..000000000000 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net
- Based on original Kirkwood support which is
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- Header file for Marvell's Orion SoC with Feroceon CPU core.
- */
-#ifndef _ASM_ARCH_ORION5X_H -#define _ASM_ARCH_ORION5X_H
-#if defined(CONFIG_FEROCEON)
-/* SOC specific definations */ -#define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x)
-/* Documented registers */ -#define ORION5X_DRAM_BASE (ORION5X_REGISTER(0x01500)) -#define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000)) -#define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000)) -#define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100)) -#define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000)) -#define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100)) -#define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000)) -#define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100)) -#define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300)) -#define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000)) -#define ORION5X_REG_PCIE_BASE (ORION5X_REGISTER(0x40000)) -#define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000)) -#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000)) -#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000)) -#define ORION5X_SATA_BASE (ORION5X_REGISTER(0x80000)) -#define ORION5X_SATA_PORT0_OFFSET 0x2000 -#define ORION5X_SATA_PORT1_OFFSET 0x4000
-/* Orion5x GbE controller has a single port */ -#define MAX_MVGBE_DEVS 1 -#define MVGBE0_BASE ORION5X_EGIGA_BASE
-/* Orion5x USB Host controller is port 1 */ -#define MVUSB0_BASE ORION5X_USB20_HOST_PORT_BASE -#define MVUSB0_CPU_ATTR_DRAM_CS0 ORION5X_ATTR_DRAM_CS0 -#define MVUSB0_CPU_ATTR_DRAM_CS1 ORION5X_ATTR_DRAM_CS1 -#define MVUSB0_CPU_ATTR_DRAM_CS2 ORION5X_ATTR_DRAM_CS2 -#define MVUSB0_CPU_ATTR_DRAM_CS3 ORION5X_ATTR_DRAM_CS3
-/* Kirkwood CPU memory windows */ -#define MVCPU_WIN_CTRL_DATA ORION5X_CPU_WIN_CTRL_DATA -#define MVCPU_WIN_ENABLE ORION5X_WIN_ENABLE -#define MVCPU_WIN_DISABLE ORION5X_WIN_DISABLE
-#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024)
-/* include here SoC variants. 5181, 5281, 6183 should go here when
- adding support for them, and this comment should then be updated. */
-#if defined(CONFIG_88F5182) -#include <asm/arch/mv88f5182.h> -#else -#error "SOC Name not defined" -#endif -#endif /* CONFIG_FEROCEON */ -#endif /* _ASM_ARCH_ORION5X_H */ diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S deleted file mode 100644 index aa3fcf7c3010..000000000000 --- a/arch/arm/mach-orion5x/lowlevel_init.S +++ /dev/null @@ -1,286 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- */
-#include <config.h> -#include "asm/arch/orion5x.h"
-/*
- Configuration values for SDRAM access setup
- */
-#define SDRAM_CONFIG 0x3148400 -#define SDRAM_MODE 0x62 -#define SDRAM_CONTROL 0x4041000 -#define SDRAM_TIME_CTRL_LOW 0x11602220 -#define SDRAM_TIME_CTRL_HI 0x40c -#define SDRAM_OPEN_PAGE_EN 0x0 -/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */ -#define SDRAM_BANK0_SIZE 0x3ff0001 -#define SDRAM_ADDR_CTRL 0x10
-#define SDRAM_OP_NOP 0x05 -#define SDRAM_OP_SETMODE 0x03
-#define SDRAM_PAD_CTRL_WR_EN 0x80000000 -#define SDRAM_PAD_CTRL_TUNE_EN 0x00010000 -#define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f -#define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0
-/*
- For Guideline MEM-3 - Drive Strength value
- */
-#define DDR1_PAD_STRENGTH_DEFAULT 0x00001000 -#define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000
-/*
- For Guideline MEM-4 - DQS Reference Delay Tuning
- */
-#define MSAR_ARMDDRCLCK_MASK 0x000000f0 -#define MSAR_ARMDDRCLCK_H_MASK 0x00000100
-#define MSAR_ARMDDRCLCK_333_167 0x00000000 -#define MSAR_ARMDDRCLCK_500_167 0x00000030 -#define MSAR_ARMDDRCLCK_667_167 0x00000060 -#define MSAR_ARMDDRCLCK_400_200_1 0x000001E0 -#define MSAR_ARMDDRCLCK_400_200 0x00000010 -#define MSAR_ARMDDRCLCK_600_200 0x00000050 -#define MSAR_ARMDDRCLCK_800_200 0x00000070
-#define FTDLL_DDR1_166MHZ 0x0047F001
-#define FTDLL_DDR1_200MHZ 0x0044D001
-/*
- Low-level init happens right after start.S has switched to SVC32,
- flushed and disabled caches and disabled MMU. We're still running
- from the boot chip select, so the first thing SPL should do is to
- set up the RAM to copy U-Boot into.
- */
-.globl lowlevel_init
-lowlevel_init:
-#ifdef CONFIG_SPL_BUILD
- /* Use 'r2 as the base for internal register accesses */
- ldr r2, =ORION5X_REGS_PHY_BASE
- /* move internal registers from the default 0xD0000000
* to their intended location, defined by SoC */- ldr r3, =0xD0000000
- add r3, r3, #0x20000
- str r2, [r3, #0x80]
- /* Use R3 as the base for DRAM registers */
- add r3, r2, #0x01000
- /*DDR SDRAM Initialization Control */
- ldr r0, =0x00000001
- str r0, [r3, #0x480]
- /* Use R3 as the base for PCI registers */
- add r3, r2, #0x31000
- /* Disable arbiter */
- ldr r0, =0x00000030
- str r0, [r3, #0xd00]
- /* Use R3 as the base for DRAM registers */
- add r3, r2, #0x01000
- /* set all dram windows to 0 */
- mov r0, #0
- str r0, [r3, #0x504]
- str r0, [r3, #0x50C]
- str r0, [r3, #0x514]
- str r0, [r3, #0x51C]
- /* 1) Configure SDRAM */
- ldr r0, =SDRAM_CONFIG
- str r0, [r3, #0x400]
- /* 2) Set SDRAM Control reg */
- ldr r0, =SDRAM_CONTROL
- str r0, [r3, #0x404]
- /* 3) Write SDRAM address control register */
- ldr r0, =SDRAM_ADDR_CTRL
- str r0, [r3, #0x410]
- /* 4) Write SDRAM bank 0 size register */
- ldr r0, =SDRAM_BANK0_SIZE
- str r0, [r3, #0x504]
- /* keep other banks disabled */
- /* 5) Write SDRAM open pages control register */
- ldr r0, =SDRAM_OPEN_PAGE_EN
- str r0, [r3, #0x414]
- /* 6) Write SDRAM timing Low register */
- ldr r0, =SDRAM_TIME_CTRL_LOW
- str r0, [r3, #0x408]
- /* 7) Write SDRAM timing High register */
- ldr r0, =SDRAM_TIME_CTRL_HI
- str r0, [r3, #0x40C]
- /* 8) Write SDRAM mode register */
- /* The CPU must not attempt to change the SDRAM Mode register setting */
- /* prior to DRAM controller completion of the DRAM initialization */
- /* sequence. To guarantee this restriction, it is recommended that */
- /* the CPU sets the SDRAM Operation register to NOP command, performs */
- /* read polling until the register is back in Normal operation value, */
- /* and then sets SDRAM Mode register to its new value. */
- /* 8.1 write 'nop' to SDRAM operation */
- ldr r0, =SDRAM_OP_NOP
- str r0, [r3, #0x418]
- /* 8.2 poll SDRAM operation until back in 'normal' mode. */
-1:
- ldr r0, [r3, #0x418]
- cmp r0, #0
- bne 1b
- /* 8.3 Now its safe to write new value to SDRAM Mode register */
- ldr r0, =SDRAM_MODE
- str r0, [r3, #0x41C]
- /* 8.4 Set new mode */
- ldr r0, =SDRAM_OP_SETMODE
- str r0, [r3, #0x418]
- /* 8.5 poll SDRAM operation until back in 'normal' mode. */
-2:
- ldr r0, [r3, #0x418]
- cmp r0, #0
- bne 2b
- /* DDR SDRAM Address/Control Pads Calibration */
- ldr r0, [r3, #0x4C0]
- /* Set Bit [31] to make the register writable */
- orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
- str r0, [r3, #0x4C0]
- bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
- bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN
- bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK
- bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK
- /* Get the final N locked value of driving strength [22:17] */
- mov r1, r0
- mov r1, r1, LSL #9
- mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
- orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
- /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
- orr r0, r0, r1
- str r0, [r3, #0x4C0]
- /* DDR SDRAM Data Pads Calibration */
- ldr r0, [r3, #0x4C4]
- /* Set Bit [31] to make the register writable */
- orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
- str r0, [r3, #0x4C4]
- bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
- bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN
- bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK
- bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK
- /* Get the final N locked value of driving strength [22:17] */
- mov r1, r0
- mov r1, r1, LSL #9
- mov r1, r1, LSR #26
- orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
- /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
- orr r0, r0, r1
- str r0, [r3, #0x4C4]
- /* Implement Guideline (GL# MEM-3) Drive Strength Value */
- /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
- ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
- /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
- ldr r0, [r3, #0x4C0]
- orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
- str r0, [r3, #0x4C0]
- /* Correct strength and disable writes again */
- bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
- bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK
- orr r0, r0, r1
- str r0, [r3, #0x4C0]
- /* Enable writes to DDR SDRAM Data Pads Calibration register */
- ldr r0, [r3, #0x4C4]
- orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
- str r0, [r3, #0x4C4]
- /* Correct strength and disable writes again */
- bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK
- bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
- orr r0, r0, r1
- str r0, [r3, #0x4C4]
- /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
- /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
- /* Get the "sample on reset" register for the DDR frequancy */
- ldr r3, =0x10000
- ldr r0, [r3, #0x010]
- ldr r1, =MSAR_ARMDDRCLCK_MASK
- and r1, r0, r1
- ldr r0, =FTDLL_DDR1_166MHZ
- cmp r1, #MSAR_ARMDDRCLCK_333_167
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_500_167
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_667_167
- beq 3f
- ldr r0, =FTDLL_DDR1_200MHZ
- cmp r1, #MSAR_ARMDDRCLCK_400_200_1
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_400_200
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_600_200
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_800_200
- beq 3f
- ldr r0, =0
-3:
- /* Use R3 as the base for DRAM registers */
- add r3, r2, #0x01000
- ldr r2, [r3, #0x484]
- orr r2, r2, r0
- str r2, [r3, #0x484]
- /* enable for 2 GB DDR; detection should find out real amount */
- sub r0, r0, r0
- str r0, [r3, #0x500]
- ldr r0, =0x7fff0001
- str r0, [r3, #0x504]
-#endif /* CONFIG_SPL_BUILD */
- /* Return to U-Boot via saved link register */
- mov pc, lr
diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c deleted file mode 100644 index 0adf3dcc6483..000000000000 --- a/arch/arm/mach-orion5x/timer.c +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net
- Based on original Kirkwood support which is
- Copyright (C) Marvell International Ltd. and its affiliates
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- */
-#include <common.h> -#include <init.h> -#include <time.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <linux/delay.h>
-#define UBOOT_CNTR 0 /* counter to use for uboot timer */
-/* Timer reload and current value registers */ -struct orion5x_tmr_val {
- u32 reload; /* Timer reload reg */
- u32 val; /* Timer value reg */
-};
-/* Timer registers */ -struct orion5x_tmr_registers {
- u32 ctrl; /* Timer control reg */
- u32 pad[3];
- struct orion5x_tmr_val tmr[2];
- u32 wdt_reload;
- u32 wdt_val;
-};
-struct orion5x_tmr_registers *orion5x_tmr_regs =
- (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
-/*
- ARM Timers Registers Map
- */
-#define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl) -#define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload) -#define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
-/*
- ARM Timers Control Register
- CPU_TIMERS_CTRL_REG (CTCR)
- */
-#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) -#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) -#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) -#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-/*
- ARM Timer\Watchdog Reload Register
- CNTMR_RELOAD_REG (TRR)
- */
-#define TRG_ARM_TIMER_REL_OFFS 0 -#define TRG_ARM_TIMER_REL_MASK 0xffffffff
-/*
- ARM Timer\Watchdog Register
- CNTMR_VAL_REG (TVRG)
- */
-#define TVR_ARM_TIMER_OFFS 0 -#define TVR_ARM_TIMER_MASK 0xffffffff -#define TVR_ARM_TIMER_MAX 0xffffffff -#define TIMER_LOAD_VAL 0xffffffff
-static inline ulong read_timer(void) -{
- return readl(CNTMR_VAL_REG(UBOOT_CNTR))
/ (CONFIG_SYS_TCLK / 1000);-}
-DECLARE_GLOBAL_DATA_PTR;
-#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc
-static ulong get_timer_masked(void) -{
- ulong now = read_timer();
- if (lastdec >= now) {
/* normal mode */timestamp += lastdec - now;- } else {
/* we have an overflow ... */timestamp += lastdec +(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;- }
- lastdec = now;
- return timestamp;
-}
-ulong get_timer(ulong base) -{
- return get_timer_masked() - base;
-}
-static inline ulong uboot_cntr_val(void) -{
- return readl(CNTMR_VAL_REG(UBOOT_CNTR));
-}
-void __udelay(unsigned long usec) -{
- uint current;
- ulong delayticks;
- current = uboot_cntr_val();
- delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
- if (current < delayticks) {
delayticks -= current;while (uboot_cntr_val() < current);while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val());- } else {
while (uboot_cntr_val() > (current - delayticks));- }
-}
-/*
- init the counter
- */
-int timer_init(void) -{
- unsigned int cntmrctrl;
- /* load value into timer */
- writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
- writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
- /* enable timer in auto reload mode */
- cntmrctrl = readl(CNTMR_CTRL_REG);
- cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
- cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
- writel(cntmrctrl, CNTMR_CTRL_REG);
- return 0;
-}
-void timer_init_r(void) -{
- /* init the timestamp and lastdec value */
- lastdec = read_timer();
- timestamp = 0;
-}
-/*
- This function is derived from PowerPC code (read timebase as long long).
- On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void) -{
- return get_timer(0);
-}
-/*
- This function is derived from PowerPC code (timebase clock frequency).
- On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void) -{
- return (ulong)CONFIG_SYS_HZ;
-} diff --git a/arch/arm/mach-orion5x/u-boot-spl.lds b/arch/arm/mach-orion5x/u-boot-spl.lds deleted file mode 100644 index a537fe02954b..000000000000 --- a/arch/arm/mach-orion5x/u-boot-spl.lds +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- (C) Copyright 2014 Albert ARIBAUD albert.u.boot@aribaud.net
- Based on:
- Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- Tom Cubie tangliang@allwinnertech.com
- Based on omap-common/u-boot-spl.lds:
- (C) Copyright 2002
- Gary Jennejohn, DENX Software Engineering, garyj@denx.de
- (C) Copyright 2010
- Texas Instruments, <www.ti.com>
- Aneesh V aneesh@ti.com
- */
-MEMORY { .nor : ORIGIN = IMAGE_TEXT_BASE,\
LENGTH = IMAGE_MAX_SIZE }-MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{
- .text :
- {
__start = .;*(.vectors)CPUDIR/start.o (.text)*(.text*)- } > .nor
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.nor
- . = ALIGN(4);
- .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor
- . = ALIGN(4);
- .u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));- } > .nor
- . = ALIGN(4);
- __image_copy_end = .;
- _end = .;
- .bss :
- {
. = ALIGN(4);__bss_start = .;*(.bss*). = ALIGN(4);__bss_end = .;- } > .bss
-} diff --git a/board/LaCie/edminiv2/Kconfig b/board/LaCie/edminiv2/Kconfig deleted file mode 100644 index ac3fe3fbcb3e..000000000000 --- a/board/LaCie/edminiv2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_EDMINIV2
-config SYS_BOARD
- default "edminiv2"
-config SYS_VENDOR
- default "LaCie"
-config SYS_CONFIG_NAME
- default "edminiv2"
-endif diff --git a/board/LaCie/edminiv2/MAINTAINERS b/board/LaCie/edminiv2/MAINTAINERS deleted file mode 100644 index e0591f4b80e1..000000000000 --- a/board/LaCie/edminiv2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -EDMINIV2 BOARD -M: Albert ARIBAUD albert.u.boot@aribaud.net -S: Maintained -F: board/LaCie/edminiv2/ -F: include/configs/edminiv2.h -F: configs/edminiv2_defconfig diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile deleted file mode 100644 index 5252c2b0e60e..000000000000 --- a/board/LaCie/edminiv2/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net -# -# Based on original Kirkwood support which is -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com
-obj-y := edminiv2.o ../common/common.o diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c deleted file mode 100644 index 9c066a283c99..000000000000 --- a/board/LaCie/edminiv2/edminiv2.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- */
-#include <common.h> -#include <miiphy.h> -#include <net.h> -#include <asm/arch/orion5x.h> -#include <asm/global_data.h> -#include "../common/common.h" -#include <spl.h> -#include <ns16550.h> -#include <asm/mach-types.h>
-DECLARE_GLOBAL_DATA_PTR;
-int board_init(void) -{
- /* arch number of board */
- gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
- /* boot parameter start at 256th byte of RAM base */
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
- return 0;
-}
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) -{
- mv_phy_88e1116_init("egiga0", 8);
-} -#endif /* CONFIG_RESET_PHY_R */
-/*
- SPL serial setup and NOR boot device selection
- */
-#ifdef CONFIG_SPL_BUILD
-void spl_board_init(void) -{
- preloader_console_init();
-}
-u32 spl_boot_device(void) -{
- return BOOT_DEVICE_NOR;
-}
-#endif /* CONFIG_SPL_BUILD */ diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig deleted file mode 100644 index e74f4dbed95c..000000000000 --- a/configs/edminiv2_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_ORION5X=y -CONFIG_SPL_LDSCRIPT="arch/arm/mach-orion5x/u-boot-spl.lds" -CONFIG_SYS_TEXT_BASE=0x00800000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x2000 -CONFIG_SYS_MALLOC_LEN=0x40000 -CONFIG_SPL_TEXT_BASE=0xffff0000 -CONFIG_TARGET_EDMINIV2=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_IDENT_STRING=" EDMiniV2" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="EDMiniV2> " -CONFIG_CMD_IMLS=y -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_EXT2=y -CONFIG_ISO_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xFFF84000 -CONFIG_NETCONSOLE=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index d33e2c7c9d83..7c89fc719592 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -28,9 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; */
#if !CONFIG_IS_ENABLED(DM_I2C) -#if defined(CONFIG_ARCH_ORION5X) -#include <asm/arch/orion5x.h> -#elif (defined(CONFIG_ARCH_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) +#if (defined(CONFIG_ARCH_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) #include <asm/arch/soc.h> #elif defined(CONFIG_ARCH_SUNXI) #include <asm/arch/i2c.h> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 8b1add19e8f1..9461e2e191e9 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -415,7 +415,7 @@ config KSZ9477
config MVGBE bool "Marvell Orion5x/Kirkwood network interface support"
- depends on ARCH_KIRKWOOD || ARCH_ORION5X
- depends on ARCH_KIRKWOOD select PHYLIB if DM_ETH help This driver supports the network interface units in the
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index ce5b8eed64b4..b9b036fd133a 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -29,8 +29,6 @@
#if defined(CONFIG_ARCH_KIRKWOOD) #include <asm/arch/soc.h> -#elif defined(CONFIG_ARCH_ORION5X) -#include <asm/arch/orion5x.h> #endif
#include "mvgbe.h" diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 8957bb56a6be..a1882a17f857 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -138,7 +138,7 @@ config USB_EHCI_ATMEL
config USB_EHCI_MARVELL bool "Support for Marvell on-chip EHCI USB controller"
- depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X
- depends on ARCH_MVEBU || ARCH_KIRKWOOD default y ---help--- Enables support for the on-chip EHCI controller on MVEBU SoCs.
diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 5420bb9772b5..412abdabd6eb 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -18,8 +18,6 @@
#if defined(CONFIG_ARCH_KIRKWOOD) #include <asm/arch/soc.h> -#elif defined(CONFIG_ARCH_ORION5X) -#include <asm/arch/orion5x.h> #endif
DECLARE_GLOBAL_DATA_PTR; diff --git a/env/flash.c b/env/flash.c index ebee9069e4e3..2f9c5de65fdd 100644 --- a/env/flash.c +++ b/env/flash.c @@ -34,8 +34,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* TODO(sjg@chromium.org): Figure out all these special cases */ #if (!defined(CONFIG_MICROBLAZE) && !defined(CONFIG_ARCH_ZYNQ) && \
- !defined(CONFIG_TARGET_MCCMON6) && !defined(CONFIG_TARGET_X600) && \
- !defined(CONFIG_TARGET_EDMINIV2)) || \
- !defined(CONFIG_TARGET_MCCMON6) && !defined(CONFIG_TARGET_X600)) || \ !defined(CONFIG_SPL_BUILD) #define LOADENV #endif
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h deleted file mode 100644 index fbe468010bfc..000000000000 --- a/include/configs/edminiv2.h +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net
- Based on original Kirkwood support which is
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- */
-#ifndef _CONFIG_EDMINIV2_H -#define _CONFIG_EDMINIV2_H
-/*
- SPL
- */
-#define CONFIG_SPL_MAX_SIZE 0x0000fff0 -#define CONFIG_SPL_STACK 0x00020000 -#define CONFIG_SPL_BSS_START_ADDR 0x00020000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff -#define CONFIG_SYS_SPL_MALLOC_START 0x00040000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff -#define CONFIG_SYS_UBOOT_BASE 0xfff90000 -#define CONFIG_SYS_UBOOT_START 0x00800000
-/*
- High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON 1 /* CPU Core subversion */ -#define CONFIG_88F5182 1 /* SOC Name */
-#include <asm/arch/orion5x.h> -/*
- CLKs configurations
- */
-/*
- Board-specific values for Orion5x MPP low level init:
- MPPs 12 to 15 are SATA LEDs (mode 5)
- Others are GPIO/unused (mode 3 for MPP0, mode 5 for
- MPP16 to MPP19, mode 0 for others
- */
-#define ORION5X_MPP0_7 0x00000003 -#define ORION5X_MPP8_15 0x55550000 -#define ORION5X_MPP16_23 0x00005555
-/*
- Board-specific values for Orion5x GPIO low level init:
- GPIO3 is input (RTC interrupt)
- GPIO16 is Power LED control (0 = on, 1 = off)
- GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
- GPIO18 is Power Button status (0 = Released, 1 = Pressed)
- GPIO19 is SATA disk power toggle (toggles on 0-to-1)
- GPIO22 is SATA disk power status ()
- GPIO23 is supply status for SATA disk ()
- GPIO24 is supply control for board (write 1 to power off)
- Last GPIO is 25, further bits are supposed to be 0.
- Enable mask has ones for INPUT, 0 for OUTPUT.
- Default is LED ON, board ON :)
- */
-#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca -#define ORION5X_GPIO_OUT_VALUE 0x00000000 -#define ORION5X_GPIO_IN_POLARITY 0x000000d0
-/*
- NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
-/*
- Serial Port configuration
- The following definitions let you select what serial you want to use
- for your console driver.
- */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
-/*
- FLASH configuration
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BASE 0xfff80000
-/* auto boot */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
-/*
- Network
- */
-#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ -#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ -#define CONFIG_PHY_BASE_ADR 0x8 -#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ -#endif
-/*
- IDE
- */
-#ifdef CONFIG_IDE -#define __io -/* Needs byte-swapping for ATA data register */ -#define CONFIG_IDE_SWAP_IO -/* Data, registers and alternate blocks are at the same offset */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) -#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) -#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) -/* Each 8-bit ATA register is aligned to a 4-bytes address */ -#define CONFIG_SYS_ATA_STRIDE 4 -/* Controller supports 48-bits LBA addressing */ -#define CONFIG_LBA48 -/* A single bus, a single device */ -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 -/* ATA registers base is at SATA controller base */ -#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE -/* ATA bus 0 is orion5x port 1 on ED Mini V2 */ -#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET -/* end of IDE defines */ -#endif /* CMD_IDE */
-/*
- Common USB/EHCI configuration
- */
-#ifdef CONFIG_CMD_USB -#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE -#endif /* CONFIG_CMD_USB */
-/*
- I2C related stuff
- */
-#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE -#endif
-/*
- Environment variables configurations
- */
-/*
- Other required minimal configurations
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
-/* Enable command line editing */
-/* provide extensive help */
-/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-#endif /* _CONFIG_EDMINIV2_H */
Viele Grüße, Stefan
On Thu, Sep 09, 2021 at 02:05:29PM +0200, Stefan Roese wrote:
On 09.09.21 13:54, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last orion5x platform, remove that support as well.
Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Stefan Roese sr@denx.de Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/Kconfig | 7 - arch/arm/Makefile | 1 - arch/arm/include/asm/arch-orion5x/spl.h | 9 - arch/arm/mach-orion5x/Kconfig | 18 -- arch/arm/mach-orion5x/Makefile | 26 -- arch/arm/mach-orion5x/cpu.c | 298 ------------------ arch/arm/mach-orion5x/dram.c | 58 ---- arch/arm/mach-orion5x/include/mach/cpu.h | 242 -------------- .../arm/mach-orion5x/include/mach/mv88f5182.h | 23 -- arch/arm/mach-orion5x/include/mach/orion5x.h | 66 ---- arch/arm/mach-orion5x/lowlevel_init.S | 286 ----------------- arch/arm/mach-orion5x/timer.c | 174 ---------- arch/arm/mach-orion5x/u-boot-spl.lds | 60 ----
If nobody steps up to start / continue maintaining orion5, then:
Hi,
It would be a shame to remove the whole Orion support.
If you can wait until this week-end, I'll look into my boxes if I can find an Ethernet Disk mini v2.
If it is the case, I'll do the CONFIG_DM conversion.
Thanks in advance.
Simon
On Fri, Sep 10, 2021 at 12:54:10AM +0200, Simon Guinot wrote:
On Thu, Sep 09, 2021 at 02:05:29PM +0200, Stefan Roese wrote:
On 09.09.21 13:54, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last orion5x platform, remove that support as well.
Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Stefan Roese sr@denx.de Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/Kconfig | 7 - arch/arm/Makefile | 1 - arch/arm/include/asm/arch-orion5x/spl.h | 9 - arch/arm/mach-orion5x/Kconfig | 18 -- arch/arm/mach-orion5x/Makefile | 26 -- arch/arm/mach-orion5x/cpu.c | 298 ------------------ arch/arm/mach-orion5x/dram.c | 58 ---- arch/arm/mach-orion5x/include/mach/cpu.h | 242 -------------- .../arm/mach-orion5x/include/mach/mv88f5182.h | 23 -- arch/arm/mach-orion5x/include/mach/orion5x.h | 66 ---- arch/arm/mach-orion5x/lowlevel_init.S | 286 ----------------- arch/arm/mach-orion5x/timer.c | 174 ---------- arch/arm/mach-orion5x/u-boot-spl.lds | 60 ----
If nobody steps up to start / continue maintaining orion5, then:
Hi,
It would be a shame to remove the whole Orion support.
If you can wait until this week-end, I'll look into my boxes if I can find an Ethernet Disk mini v2.
If it is the case, I'll do the CONFIG_DM conversion.
OK, I can wait a bit more for an answer here as my plan would be to take this series in to -next. Thanks!
Hi Simon,
On 10.09.21 00:54, Simon Guinot wrote:
On Thu, Sep 09, 2021 at 02:05:29PM +0200, Stefan Roese wrote:
On 09.09.21 13:54, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last orion5x platform, remove that support as well.
Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Stefan Roese sr@denx.de Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/Kconfig | 7 - arch/arm/Makefile | 1 - arch/arm/include/asm/arch-orion5x/spl.h | 9 - arch/arm/mach-orion5x/Kconfig | 18 -- arch/arm/mach-orion5x/Makefile | 26 -- arch/arm/mach-orion5x/cpu.c | 298 ------------------ arch/arm/mach-orion5x/dram.c | 58 ---- arch/arm/mach-orion5x/include/mach/cpu.h | 242 -------------- .../arm/mach-orion5x/include/mach/mv88f5182.h | 23 -- arch/arm/mach-orion5x/include/mach/orion5x.h | 66 ---- arch/arm/mach-orion5x/lowlevel_init.S | 286 ----------------- arch/arm/mach-orion5x/timer.c | 174 ---------- arch/arm/mach-orion5x/u-boot-spl.lds | 60 ----
If nobody steps up to start / continue maintaining orion5, then:
Hi,
It would be a shame to remove the whole Orion support.
If you can wait until this week-end, I'll look into my boxes if I can find an Ethernet Disk mini v2.
If it is the case, I'll do the CONFIG_DM conversion.
Thanks Simon, that would be great.
Thanks, Stefan
Hi Stefan and Tom,
I finally managed to find a Disk Mini v2 Ethernet card and I will be working on the DM conversion as soon as possible.
Please, let me know what is my deadline to complete this job ?
Simon
On Fri, Sep 10, 2021 at 06:41:14AM +0200, Stefan Roese wrote:
Hi Simon,
On 10.09.21 00:54, Simon Guinot wrote:
On Thu, Sep 09, 2021 at 02:05:29PM +0200, Stefan Roese wrote:
On 09.09.21 13:54, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last orion5x platform, remove that support as well.
Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Stefan Roese sr@denx.de Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/Kconfig | 7 - arch/arm/Makefile | 1 - arch/arm/include/asm/arch-orion5x/spl.h | 9 - arch/arm/mach-orion5x/Kconfig | 18 -- arch/arm/mach-orion5x/Makefile | 26 -- arch/arm/mach-orion5x/cpu.c | 298 ------------------ arch/arm/mach-orion5x/dram.c | 58 ---- arch/arm/mach-orion5x/include/mach/cpu.h | 242 -------------- .../arm/mach-orion5x/include/mach/mv88f5182.h | 23 -- arch/arm/mach-orion5x/include/mach/orion5x.h | 66 ---- arch/arm/mach-orion5x/lowlevel_init.S | 286 ----------------- arch/arm/mach-orion5x/timer.c | 174 ---------- arch/arm/mach-orion5x/u-boot-spl.lds | 60 ----
If nobody steps up to start / continue maintaining orion5, then:
Hi,
It would be a shame to remove the whole Orion support.
If you can wait until this week-end, I'll look into my boxes if I can find an Ethernet Disk mini v2.
If it is the case, I'll do the CONFIG_DM conversion.
Thanks Simon, that would be great.
Thanks, Stefan
On Tue, Sep 14, 2021 at 10:37:43AM +0200, Simon Guinot wrote:
Hi Stefan and Tom,
I finally managed to find a Disk Mini v2 Ethernet card and I will be working on the DM conversion as soon as possible.
Please, let me know what is my deadline to complete this job ?
Great. So, the deadline for DM conversion was v2020.01, which means I was going to remove it for the v2022.01 release. That's pretty far away. But there's also only a handful of non-converted platforms, so I was going to instead try and drop everything for v2021.01. Do you think you can have this converted by some time in October? End of October would be OK. If you need more time than that, let me know.
But please update the MAINTAINERS file now :)
On Tue, Sep 14, 2021 at 07:43:10AM -0400, Tom Rini wrote:
On Tue, Sep 14, 2021 at 10:37:43AM +0200, Simon Guinot wrote:
Hi Stefan and Tom,
I finally managed to find a Disk Mini v2 Ethernet card and I will be working on the DM conversion as soon as possible.
Please, let me know what is my deadline to complete this job ?
Great. So, the deadline for DM conversion was v2020.01, which means I was going to remove it for the v2022.01 release. That's pretty far away. But there's also only a handful of non-converted platforms, so I was going to instead try and drop everything for v2021.01. Do you think you can have this converted by some time in October? End of October would be OK. If you need more time than that, let me know.
Yes I think it should be good by the end of october. And if for some reason I am unable to meet the deadline, then I'll let you know soon enough. So you would still have the option of dropping the board.
But please update the MAINTAINERS file now :)
I just sent a patch.
Simon
This board has not been converted to CONFIG_DM by the deadline. Remove it.
Cc: Priyanka Jain priyanka.jain@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/powerpc/cpu/mpc83xx/Kconfig | 52 --- arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 | 6 +- arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 | 6 +- arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 | 6 +- arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 | 6 +- arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 | 6 +- arch/powerpc/cpu/mpc83xx/hid/Kconfig | 4 +- arch/powerpc/cpu/mpc83xx/hrcw/Kconfig | 117 ++---- arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h | 12 +- arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr | 44 -- board/freescale/mpc8349emds/Kconfig | 25 -- board/freescale/mpc8349emds/MAINTAINERS | 9 - board/freescale/mpc8349emds/Makefile | 8 - board/freescale/mpc8349emds/ddr.c | 100 ----- board/freescale/mpc8349emds/mpc8349emds.c | 277 ------------- board/freescale/mpc8349emds/pci.c | 118 ------ configs/MPC8349EMDS_PCI64_defconfig | 127 ------ configs/MPC8349EMDS_SDRAM_defconfig | 138 ------- configs/MPC8349EMDS_SLAVE_defconfig | 127 ------ configs/MPC8349EMDS_defconfig | 130 ------ include/configs/MPC8349EMDS.h | 319 --------------- include/configs/MPC8349EMDS_SDRAM.h | 376 ------------------ 22 files changed, 45 insertions(+), 1968 deletions(-) delete mode 100644 board/freescale/mpc8349emds/Kconfig delete mode 100644 board/freescale/mpc8349emds/MAINTAINERS delete mode 100644 board/freescale/mpc8349emds/Makefile delete mode 100644 board/freescale/mpc8349emds/ddr.c delete mode 100644 board/freescale/mpc8349emds/mpc8349emds.c delete mode 100644 board/freescale/mpc8349emds/pci.c delete mode 100644 configs/MPC8349EMDS_PCI64_defconfig delete mode 100644 configs/MPC8349EMDS_SDRAM_defconfig delete mode 100644 configs/MPC8349EMDS_SLAVE_defconfig delete mode 100644 configs/MPC8349EMDS_defconfig delete mode 100644 include/configs/MPC8349EMDS.h delete mode 100644 include/configs/MPC8349EMDS_SDRAM.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index fcf4ef2b3600..cff98f7599fa 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -8,22 +8,6 @@ choice prompt "Target select" optional
-config TARGET_MPC8349EMDS - bool "Support MPC8349EMDS" - select ARCH_MPC8349 - select BOARD_EARLY_INIT_F - select SYS_FSL_DDR - select SYS_FSL_DDR_BE - select SYS_FSL_HAS_DDR2 - -config TARGET_MPC8349EMDS_SDRAM - bool "Support MPC8349EMDS_SDRAM" - select ARCH_MPC8349 - select BOARD_EARLY_INIT_F - select SYS_FSL_DDR - select SYS_FSL_DDR_BE - select SYS_FSL_HAS_DDR2 - config TARGET_MPC837XERDB bool "Support MPC837XERDB" select ARCH_MPC837X @@ -173,15 +157,6 @@ config ARCH_MPC834X bool select SYS_CACHE_SHIFT_5
-config ARCH_MPC8349 - bool - select ARCH_MPC834X - select MPC83XX_PCI_SUPPORT - select MPC83XX_TSEC1_SUPPORT - select MPC83XX_TSEC2_SUPPORT - select MPC83XX_LDP_PIN - select MPC83XX_SECOND_I2C - config ARCH_MPC8360 bool select MPC83XX_QUICC_ENGINE @@ -220,36 +195,9 @@ source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig" source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig" source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
-menu "Legacy options" - -if ARCH_MPC8349 - -#TODO(mario.six@gdsys.cc): Remove when mpc83xx PCI has been converted to DM/DT -choice - prompt "PMC slot configuration" - -config PCI_ALL_PCI1 - bool "All PMC slots on PCI1" - -config PCI_ONE_PCI1 - bool "First PMC1 on PCI1" - -config PCI_TWO_PCI1 - bool "First two PMC1 on PCI1" - -endchoice - -config PCI_64BIT - bool "PMC2 is 64bit" - -endif - -endmenu - config FSL_ELBC bool
-source "board/freescale/mpc8349emds/Kconfig" source "board/freescale/mpc837xerdb/Kconfig" source "board/ids/ids8313/Kconfig" source "board/keymile/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 index 23e81ab0bf91..208eed0495ae 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 @@ -22,7 +22,7 @@ config BR0_PORTSIZE_16BIT
config BR0_PORTSIZE_32BIT depends on !BR0_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit"
endchoice @@ -58,11 +58,11 @@ config BR0_MACHINE_GPCM bool "GPCM"
config BR0_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM"
config BR0_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM"
config BR0_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 index 08dcc7dd2ba3..1dc3e75076cb 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 @@ -22,7 +22,7 @@ config BR1_PORTSIZE_16BIT
config BR1_PORTSIZE_32BIT depends on !BR1_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit"
endchoice @@ -58,11 +58,11 @@ config BR1_MACHINE_GPCM bool "GPCM"
config BR1_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM"
config BR1_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM"
config BR1_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 index 298d87f5e0f4..a9b2546cd88e 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 @@ -22,7 +22,7 @@ config BR2_PORTSIZE_16BIT
config BR2_PORTSIZE_32BIT depends on !BR2_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit"
endchoice @@ -58,11 +58,11 @@ config BR2_MACHINE_GPCM bool "GPCM"
config BR2_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM"
config BR2_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM"
config BR2_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 index 963831bfcbd1..94442cdc9778 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 @@ -22,7 +22,7 @@ config BR3_PORTSIZE_16BIT
config BR3_PORTSIZE_32BIT depends on !BR3_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit"
endchoice @@ -58,11 +58,11 @@ config BR3_MACHINE_GPCM bool "GPCM"
config BR3_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM"
config BR3_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM"
config BR3_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 index 0063dab96223..5d69385a23da 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 @@ -22,7 +22,7 @@ config BR4_PORTSIZE_16BIT
config BR4_PORTSIZE_32BIT depends on !BR4_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit"
endchoice @@ -58,11 +58,11 @@ config BR4_MACHINE_GPCM bool "GPCM"
config BR4_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM"
config BR4_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM"
config BR4_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/hid/Kconfig b/arch/powerpc/cpu/mpc83xx/hid/Kconfig index c367ad2ce157..1f61108ceee6 100644 --- a/arch/powerpc/cpu/mpc83xx/hid/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/hid/Kconfig @@ -434,7 +434,7 @@ config HID2_IWLCK_1 config HID2_IWLCK_2 bool "Way 0 through 2 locked"
-if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 +if ARCH_MPC8360 || ARCH_MPC8379
config HID2_IWLCK_3 bool "Way 0 through 3 locked" @@ -470,7 +470,7 @@ config HID2_DWLCK_1 config HID2_DWLCK_2 bool "Way 0 through 2 locked"
-if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 +if ARCH_MPC8360 || ARCH_MPC8379
config HID2_DWLCK_3 bool "Way 0 through 3 locked" diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig index 75ec9c9a3464..71fa73801ae1 100644 --- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig @@ -7,7 +7,7 @@ config LBMC_CLOCK_MODE_1_1 bool "1 : 1"
config LBMC_CLOCK_MODE_1_2 - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + depends on ARCH_MPC8360 || ARCH_MPC837X bool "1 : 2"
endchoice @@ -19,12 +19,12 @@ config DDR_MC_CLOCK_MODE_1_2 bool "1 : 2"
config DDR_MC_CLOCK_MODE_1_1 - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + depends on ARCH_MPC8360 || ARCH_MPC837X bool "1 : 1"
endchoice
-if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349 +if !ARCH_MPC8313 && !ARCH_MPC832X
choice prompt "System PLL VCO division" @@ -67,43 +67,43 @@ config SYSTEM_PLL_FACTOR_6_1 bool "6 : 1"
config SYSTEM_PLL_FACTOR_7_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "7 : 1"
config SYSTEM_PLL_FACTOR_8_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "8 : 1"
config SYSTEM_PLL_FACTOR_9_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "9 : 1"
config SYSTEM_PLL_FACTOR_10_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "10 : 1"
config SYSTEM_PLL_FACTOR_11_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "11 : 1"
config SYSTEM_PLL_FACTOR_12_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "12 : 1"
config SYSTEM_PLL_FACTOR_13_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "13 : 1"
config SYSTEM_PLL_FACTOR_14_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "14 : 1"
config SYSTEM_PLL_FACTOR_15_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "15 : 1"
config SYSTEM_PLL_FACTOR_16_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 + depends on ARCH_MPV8360 bool "16 : 1"
endchoice @@ -310,21 +310,6 @@ config PCI_HOST_MODE_ENABLE
endchoice
-if ARCH_MPC8349 - -choice - prompt "PCI 64-bit mode" - -config PCI_64BIT_MODE_DISABLE - bool "Disabled" - -config PCI_64BIT_MODE_ENABLE - bool "Enabled" - -endchoice - -endif - choice prompt "PCI internal arbiter 1 mode"
@@ -336,21 +321,6 @@ config PCI_INT_ARBITER1_ENABLE
endchoice
-if ARCH_MPC8349 - -choice - prompt "PCI internal arbiter 2 mode" - -config PCI_INT_ARBITER2_DISABLE - bool "Disabled" - -config PCI_INT_ARBITER2_ENABLE - bool "Enabled" - -endchoice - -endif - if ARCH_MPC8360
choice @@ -425,10 +395,6 @@ config BOOT_ROM_INTERFACE_PCI1 depends on MPC83XX_PCI_SUPPORT bool "PCI1"
-config BOOT_ROM_INTERFACE_PCI2 - depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349 - bool "PCI2" - config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM depends on ARCH_MPC837X bool "PCI2" @@ -448,15 +414,15 @@ config BOOT_ROM_INTERFACE_GPCM_16BIT bool "Local bus GPCM - 16-bit ROM"
config BOOT_ROM_INTERFACE_GPCM_32BIT - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + depends on ARCH_MPC8360 || ARCH_MPC837X bool "Local bus GPCM - 32-bit ROM"
config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "Local bus NAND Flash- 8-bit small page ROM"
config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "Local bus NAND Flash- 8-bit large page ROM"
endchoice @@ -467,11 +433,10 @@ choice prompt "TSEC1 mode"
config TSEC1_MODE_MII - depends on !ARCH_MPC8349 bool "MII"
config TSEC1_MODE_RMII - depends on ARCH_MPC831X && !ARCH_MPC8349 + depends on ARCH_MPC831X bool "RMII"
config TSEC1_MODE_RGMII @@ -481,14 +446,6 @@ config TSEC1_MODE_RTBI depends on ARCH_MPC831X || ARCH_MPC837X bool "RTBI"
-config TSEC1_MODE_GMII - depends on ARCH_MPC8349 - bool "GMII" - -config TSEC1_MODE_TBI - depends on ARCH_MPC8349 - bool "TBI" - config TSEC1_MODE_SGMII depends on ARCH_MPC831X || ARCH_MPC837X bool "SGMII" @@ -503,11 +460,10 @@ choice prompt "TSEC2 mode"
config TSEC2_MODE_MII - depends on !ARCH_MPC8349 bool "MII"
config TSEC2_MODE_RMII - depends on ARCH_MPC831X && !ARCH_MPC8349 + depends on ARCH_MPC831X bool "RMII"
config TSEC2_MODE_RGMII @@ -517,14 +473,6 @@ config TSEC2_MODE_RTBI depends on ARCH_MPC831X || ARCH_MPC837X bool "RTBI"
-config TSEC2_MODE_GMII - depends on ARCH_MPC8349 - bool "GMII" - -config TSEC2_MODE_TBI - depends on ARCH_MPC8349 - bool "TBI" - config TSEC2_MODE_SGMII depends on ARCH_MPC831X || ARCH_MPC837X bool "SGMII" @@ -559,7 +507,7 @@ endchoice
endif
-if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360 +if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8360
choice prompt "LALE timing" @@ -603,7 +551,7 @@ config DDR_MC_CLOCK_MODE
config SYSTEM_PLL_VCO_DIV int - default 0 if ARCH_MPC8349 || ARCH_MPC832X + default 0 if ARCH_MPC832X default 2 if ARCH_MPC8313 default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X @@ -675,7 +623,6 @@ config BOOT_ROM_INTERFACE hex default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM default 0x4 if BOOT_ROM_INTERFACE_PCI1 - default 0x8 if BOOT_ROM_INTERFACE_PCI2 default 0x8 if BOOT_ROM_INTERFACE_ESDHC default 0xc if BOOT_ROM_INTERFACE_SPI default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM @@ -690,26 +637,18 @@ config TSEC1_MODE default 0x0 if !MPC83XX_TSEC1_SUPPORT default 0x0 if TSEC1_MODE_MII default 0x1 if TSEC1_MODE_RMII - default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349 - default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349 + default 0x3 if TSEC1_MODE_RGMII + default 0x5 if TSEC1_MODE_RTBI default 0x6 if TSEC1_MODE_SGMII - default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349 - default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349 - default 0x2 if TSEC1_MODE_GMII - default 0x3 if TSEC1_MODE_TBI
config TSEC2_MODE hex default 0x0 if !MPC83XX_TSEC2_SUPPORT default 0x0 if TSEC2_MODE_MII default 0x1 if TSEC2_MODE_RMII - default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349 - default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349 + default 0x3 if TSEC2_MODE_RGMII + default 0x5 if TSEC2_MODE_RTBI default 0x6 if TSEC2_MODE_SGMII - default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349 - default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349 - default 0x2 if TSEC2_MODE_GMII - default 0x3 if TSEC2_MODE_TBI
config SECONDARY_DDR_IO int @@ -792,9 +731,7 @@ config PCI_HOST_MODE
config PCI_64BIT_MODE int - default 0 if !ARCH_MPC8349 - default 0 if PCI_64BIT_MODE_DISABLE - default 1 if PCI_64BIT_MODE_ENABLE + default 0
config PCI_INT_ARBITER1 int @@ -804,9 +741,7 @@ config PCI_INT_ARBITER1
config PCI_INT_ARBITER2 int - default 0 if !ARCH_MPC8349 - default 0 if PCI_INT_ARBITER2_DISABLE - default 1 if PCI_INT_ARBITER2_ENABLE + default 0
config PCI_CLOCK_OUTPUT_DRIVE int diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h index 7d66ba726b91..0f3426789181 100644 --- a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h +++ b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h @@ -1,11 +1,3 @@ -#ifdef CONFIG_ARCH_MPC8349 -#define TSEC1_MODE_SHIFT 17 -#define TSEC2_MODE_SHIFT 19 -#else -#define TSEC1_MODE_SHIFT 18 -#define TSEC2_MODE_SHIFT 21 -#endif - #define CONFIG_SYS_HRCW_LOW (\ (CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\ (CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\ @@ -28,8 +20,8 @@ (CONFIG_BOOT_SEQUENCER << (31 - 7)) |\ (CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\ (CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\ - (CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\ - (CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\ + (CONFIG_TSEC1_MODE << (31 - 18)) |\ + (CONFIG_TSEC2_MODE << (31 - 21)) |\ (CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\ (CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\ (CONFIG_LALE_TIMING << (31 - 29)) |\ diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr index f32309e6c0f0..33e1295df149 100644 --- a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr +++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr @@ -38,50 +38,6 @@ endchoice
endif
-if ARCH_MPC8349 - -choice - prompt "TSEC1 emergency priority" - -config SPCR_TSEC1EP_UNSET - bool "Don't set value" - -config SPCR_TSEC1EP_0 - bool "Level 0 (lowest priority)" - -config SPCR_TSEC1EP_1 - bool "Level 1" - -config SPCR_TSEC1EP_2 - bool "Level 2" - -config SPCR_TSEC1EP_3 - bool "Level 3 (highest priority)" - -endchoice - -choice - prompt "TSEC2 emergency priority" - -config SPCR_TSEC2EP_UNSET - bool "Don't set value" - -config SPCR_TSEC2EP_0 - bool "Level 0 (lowest priority)" - -config SPCR_TSEC2EP_1 - bool "Level 1" - -config SPCR_TSEC2EP_2 - bool "Level 2" - -config SPCR_TSEC2EP_3 - bool "Level 3 (highest priority)" - -endchoice - -endif - config SPCR_OPT hex default 0x0 if SPCR_OPT_UNSET diff --git a/board/freescale/mpc8349emds/Kconfig b/board/freescale/mpc8349emds/Kconfig deleted file mode 100644 index d1541180799e..000000000000 --- a/board/freescale/mpc8349emds/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -if TARGET_MPC8349EMDS - -config SYS_BOARD - default "mpc8349emds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8349EMDS" - -endif - -if TARGET_MPC8349EMDS_SDRAM - -config SYS_BOARD - default "mpc8349emds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8349EMDS_SDRAM" - -endif diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS deleted file mode 100644 index a8f26a9a3169..000000000000 --- a/board/freescale/mpc8349emds/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -MPC8349EMDS BOARD -#M: Kim Phillips kim.phillips@freescale.com -S: Orphan (since 2018-05) -F: board/freescale/mpc8349emds/ -F: include/configs/MPC8349EMDS.h -F: configs/MPC8349EMDS_defconfig -F: configs/MPC8349EMDS_SDRAM_defconfig -F: configs/MPC8349EMDS_PCI64_defconfig -F: configs/MPC8349EMDS_SLAVE_defconfig diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile deleted file mode 100644 index af02f65cb004..000000000000 --- a/board/freescale/mpc8349emds/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8349emds.o -obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c deleted file mode 100644 index ac5ddc6d94b8..000000000000 --- a/board/freescale/mpc8349emds/ddr.c +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 cpo; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - {2, 300, 4, 4, 2, 0}, - {2, 365, 4, 6, 2, 0}, - {2, 450, 4, 7, 2, 0}, - {2, 850, 4, 31, 2, 0}, - {1, 300, 4, 4, 2, 0}, - {1, 365, 4, 6, 2, 0}, - {1, 450, 4, 7, 2, 0}, - {1, 850, 4, 31, 2, 0}, - {} -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - unsigned int i; - ulong ddr_freq; - - if (ctrl_num != 0) /* we have only one controller */ - return; - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (pdimm[i].n_ranks) - break; - } - if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */ - return; - - pbsp = udimm0; - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm[i].n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->twot_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - popts->twot_en = pbsp_highest->force_2t; - } else { - panic("DIMM is not supported by this board"); - } - -found: - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - popts->dqs_config = 0; /* only true DQS signal is used on board */ -} diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c deleted file mode 100644 index eff248104dc0..000000000000 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ /dev/null @@ -1,277 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <fdt_support.h> -#include <init.h> -#include <ioports.h> -#include <mpc83xx.h> -#include <asm/bitops.h> -#include <asm/global_data.h> -#include <asm/mpc8349_pci.h> -#include <i2c.h> -#include <spi.h> -#include <miiphy.h> -#ifdef CONFIG_SYS_FSL_DDR2 -#include <fsl_ddr_sdram.h> -#else -#include <spd_sdram.h> -#endif -#include <linux/delay.h> - -#if defined(CONFIG_OF_LIBFDT) -#include <linux/libfdt.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int fixed_sdram(void); -void sdram_init(void); - -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx) -void ddr_enable_ecc(unsigned int dram_size); -#endif - -int board_early_init_f (void) -{ - volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR; - - /* Enable flash write */ - bcsr[1] &= ~0x01; - -#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY - /* Use USB PHY on SYS board */ - bcsr[5] |= 0x02; -#endif - - return 0; -} - -int dram_init(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - phys_size_t msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -ENXIO; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; -#if defined(CONFIG_SPD_EEPROM) -#ifndef CONFIG_SYS_FSL_DDR2 - msize = spd_sdram() * 1024 * 1024; -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - ddr_enable_ecc(msize); -#endif -#else - msize = fsl_ddr_sdram(); -#endif -#else - msize = fixed_sdram() * 1024 * 1024; -#endif - /* - * Initialize SDRAM if it is on local bus. - */ - sdram_init(); - - /* set total bus SDRAM size(bytes) -- DDR */ - gd->ram_size = msize; - - return 0; -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_DDR_SIZE; - u32 ddr_size = msize << 20; /* DDR size in bytes */ - u32 ddr_size_log2 = __ilog2(ddr_size); - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - -#if (CONFIG_SYS_DDR_SIZE != 256) -#warning Currenly any ddr size other than 256 is not supported -#endif -#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) -#warning Chip select bounds is only configurable in 16MB increments -#endif - im->ddr.csbnds[2].csbnds = - ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> - CSBNDS_EA_SHIFT) & CSBNDS_EA); - im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; - - /* currently we use only one CS, so disable the other banks */ - im->ddr.cs_config[0] = 0; - im->ddr.cs_config[1] = 0; - im->ddr.cs_config[3] = 0; - - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - - im->ddr.sdram_cfg = - SDRAM_CFG_SREN - | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - udelay(200); - - /* enable DDR controller */ - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - return msize; -} -#endif/*!CONFIG_SYS_SPD_EEPROM*/ - - -int checkboard (void) -{ - /* - * Warning: do not read the BCSR registers here - * - * There is a timing bug in the 8349E and 8349EA BCSR code - * version 1.2 (read from BCSR 11) that will cause the CFI - * flash initialization code to overwrite BCSR 0, disabling - * the serial ports and gigabit ethernet - */ - - puts("Board: Freescale MPC8349EMDS\n"); - return 0; -} - -/* - * if MPC8349EMDS is soldered with SDRAM - */ -#if defined(CONFIG_SYS_BR2_PRELIM) \ - && defined(CONFIG_SYS_OR2_PRELIM) \ - && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ - && defined(CONFIG_SYS_LBLAWAR2_PRELIM) -/* - * Initialize SDRAM memory on the Local Bus. - */ - -void sdram_init(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbc_t *lbc = &immap->im_lbc; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 | - LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 | - LSDMR_WRC3 | LSDMR_CL3; - /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c - */ - - /* setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = 0x00000000; - /* LB refresh timer prescal, 266MHz/32 */ - lbc->mrtpr = 0x20000000; - /* LB sdram refresh timer, about 6us */ - lbc->lsrt = 0x32000000; - asm("sync"); - - /* - * Configure the SDRAM controller Machine Mode Register. - */ - - /* 0x40636733; normal operation */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - - /* 0x68636733; precharge all the banks */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - /* 0x48636733; auto refresh */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; - asm("sync"); - /*1 times*/ - *sdram_addr = 0xff; - udelay(100); - /*2 times*/ - *sdram_addr = 0xff; - udelay(100); - /*3 times*/ - *sdram_addr = 0xff; - udelay(100); - /*4 times*/ - *sdram_addr = 0xff; - udelay(100); - /*5 times*/ - *sdram_addr = 0xff; - udelay(100); - /*6 times*/ - *sdram_addr = 0xff; - udelay(100); - /*7 times*/ - *sdram_addr = 0xff; - udelay(100); - /*8 times*/ - *sdram_addr = 0xff; - udelay(100); - - /* 0x58636733; mode register write operation */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - /* 0x40636733; normal operation */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); -} -#else -void sdram_init(void) -{ -} -#endif - -/* - * The following are used to control the SPI chip selects for the SPI command. - */ -#ifdef CONFIG_MPC8XXX_SPI - -#define SPI_CS_MASK 0x80000000 - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat &= ~SPI_CS_MASK; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat |= SPI_CS_MASK; -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} -#endif diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c deleted file mode 100644 index 8c76c46d4200..000000000000 --- a/board/freescale/mpc8349emds/pci.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - */ - -#include <init.h> -#include <asm/mmu.h> -#include <asm/io.h> -#include <common.h> -#include <mpc83xx.h> -#include <pci.h> -#include <i2c.h> -#include <asm/fsl_i2c.h> -#include <linux/delay.h> - -static struct pci_region pci1_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; - -#ifdef CONFIG_MPC83XX_PCI2 -static struct pci_region pci2_regions[] = { - { - bus_start: CONFIG_SYS_PCI2_MEM_BASE, - phys_start: CONFIG_SYS_PCI2_MEM_PHYS, - size: CONFIG_SYS_PCI2_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI2_IO_BASE, - phys_start: CONFIG_SYS_PCI2_IO_PHYS, - size: CONFIG_SYS_PCI2_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI2_MMIO_BASE, - phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, - size: CONFIG_SYS_PCI2_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; -#endif - -#ifndef CONFIG_PCISLAVE -void pib_init(void) -{ - u8 val8, orig_i2c_bus; - /* - * Assign PIB PMC slot to desired PCI bus - */ - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); -#if defined(CONFIG_PCI_64BIT) - val8 = 0xf4; /* PMC2:PCI1/64-bit */ -#elif defined(CONFIG_PCI_ALL_PCI1) - val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ -#elif defined(CONFIG_PCI_ONE_PCI1) - val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ -#else - val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ -#endif - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - asm("eieio"); - -#if defined(CONFIG_PCI_64BIT) - printf("PCI1: 64-bit on PMC2\n"); -#elif defined(CONFIG_PCI_ALL_PCI1) - printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); -#elif defined(CONFIG_PCI_ONE_PCI1) - printf("PCI1: 32-bit on PMC1\n"); - printf("PCI2: 32-bit on PMC2, PMC3\n"); -#else - printf("PCI1: 32-bit on PMC1, PMC2\n"); - printf("PCI2: 32-bit on PMC3\n"); -#endif - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); -} - -#endif /* CONFIG_PCISLAVE */ diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig deleted file mode 100644 index 457a1eef031a..000000000000 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ /dev/null @@ -1,127 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_MALLOC_LEN=0x40000 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC8349EMDS=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_64BIT_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_GMII=y -CONFIG_TSEC2_MODE_GMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="IMMR" -CONFIG_BAT5_BASE=0xE0000000 -CONFIG_BAT5_LENGTH_256_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="STACK_IN_DCACHE" -CONFIG_BAT6_BASE=0xF0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE2400000 -CONFIG_LBLAW1_NAME="BCSR" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="BCSR" -CONFIG_BR1_OR1_BASE=0xE2400000 -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSEC1EP_3=y -CONFIG_SPCR_TSEC2EP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_4=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="echo;echo Type "run flash_nfs" to mount root filesystem over NFS;echo" -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_ENV_ADDR_REDUND=0xFE0A0000 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=400000 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig deleted file mode 100644 index 5f568977cb28..000000000000 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ /dev/null @@ -1,138 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_MALLOC_LEN=0x40000 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC8349EMDS_SDRAM=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_PCI_INT_ARBITER2_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_GMII=y -CONFIG_TSEC2_MODE_GMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="IMMR" -CONFIG_BAT5_BASE=0xE0000000 -CONFIG_BAT5_LENGTH_256_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="STACK_IN_DCACHE" -CONFIG_BAT6_BASE=0xF0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE2400000 -CONFIG_LBLAW1_NAME="BCSR" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_LBLAW2=y -CONFIG_LBLAW2_BASE=0xF0000000 -CONFIG_LBLAW2_NAME="SDRAM" -CONFIG_LBLAW2_LENGTH_64_MBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="BCSR" -CONFIG_BR1_OR1_BASE=0xE2400000 -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_ELBC_BR2_OR2=y -CONFIG_BR2_OR2_NAME="SDRAM" -CONFIG_BR2_OR2_BASE=0xF0000000 -CONFIG_BR2_PORTSIZE_32BIT=y -CONFIG_BR2_MACHINE_SDRAM=y -CONFIG_OR2_COLS_9=y -CONFIG_OR2_ROWS_13=y -CONFIG_OR2_EAD_EXTRA=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_4=y -CONFIG_PCI_ONE_PCI1=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_ENV_ADDR_REDUND=0xFE0A0000 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=400000 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig deleted file mode 100644 index 763d6fa398c2..000000000000 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ /dev/null @@ -1,127 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_MALLOC_LEN=0x40000 -CONFIG_SYS_CLK_FREQ=66666666 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC8349EMDS=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_PCI_64BIT_MODE_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_GMII=y -CONFIG_TSEC2_MODE_GMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="IMMR" -CONFIG_BAT5_BASE=0xE0000000 -CONFIG_BAT5_LENGTH_256_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="STACK_IN_DCACHE" -CONFIG_BAT6_BASE=0xF0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE2400000 -CONFIG_LBLAW1_NAME="BCSR" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="BCSR" -CONFIG_BR1_OR1_BASE=0xE2400000 -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSEC1EP_3=y -CONFIG_SPCR_TSEC2EP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_4=y -CONFIG_PCI_ONE_PCI1=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" -CONFIG_BOOTDELAY=6 -CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="echo;echo Type "run flash_nfs" to mount root filesystem over NFS;echo" -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_ENV_ADDR_REDUND=0xFE0A0000 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=400000 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig deleted file mode 100644 index df9c9d3a4010..000000000000 --- a/configs/MPC8349EMDS_defconfig +++ /dev/null @@ -1,130 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_MALLOC_LEN=0x40000 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC8349EMDS=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_4_1=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_PCI_INT_ARBITER2_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_GMII=y -CONFIG_TSEC2_MODE_GMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="IMMR" -CONFIG_BAT5_BASE=0xE0000000 -CONFIG_BAT5_LENGTH_256_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="STACK_IN_DCACHE" -CONFIG_BAT6_BASE=0xF0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE2400000 -CONFIG_LBLAW1_NAME="BCSR" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="BCSR" -CONFIG_BR1_OR1_BASE=0xE2400000 -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSEC1EP_3=y -CONFIG_SPCR_TSEC2EP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_4=y -CONFIG_PCI_ONE_PCI1=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="echo;echo Type "run flash_nfs" to mount root filesystem over NFS;echo" -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_ENV_ADDR_REDUND=0xFE0A0000 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=400000 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h deleted file mode 100644 index 2f1fc6a6a2b9..000000000000 --- a/include/configs/MPC8349EMDS.h +++ /dev/null @@ -1,319 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * mpc8349emds board configuration file - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ - -/* - * DDR Setup - */ -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ - -/* - * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver - * unselect it to use old spd_sdram.c - */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x52 -#define SPD_EEPROM_ADDRESS2 0x51 -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -/* - * DDRCDR - DDR Control Driver Register - */ -#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 - -#if defined(CONFIG_SPD_EEPROM) -/* - * Determine DDR configuration from I2C interface. - */ -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ -#else -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_TIMING_1 0x36332321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ - -/* the default burst length is 4 - for 64-bit data path */ - /* DLL,normal,seq,4/2.5, 4 burst len */ -#define CONFIG_SYS_DDR_MODE 0x00000022 -#endif - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* - * BCSR register on local bus 32KB, 8-bit wide for MDS config reg - */ -#define CONFIG_SYS_BCSR 0xE2400000 - /* Access window base at BCSR base */ - - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* SPI */ -#undef CONFIG_SOFT_SPI /* SPI bit-banged */ - -/* GPIOs. Used as SPI chip selects */ -#define CONFIG_SYS_GPIO1_PRELIM -#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ -#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ - -/* TSEC */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* USB */ -#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xFIXME - #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif /* CONFIG_PCI */ - -/* - * TSEC configuration - */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Configure on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT -/* Address and size of Redundant Environment Sector */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -/* - * System performance - */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ - -/* System IO Config */ -#define CONFIG_SYS_SICRH 0 -#define CONFIG_SYS_SICRL SICRL_LDP_A - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_HOSTNAME "mpc8349emds" -#define CONFIG_ROOTPATH "/nfsroot/rootfs" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=mpc8349emds\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ - "update=protect off fe000000 fe03ffff; " \ - "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ - "upd=run load update\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc834x_mds.dtb\0" \ - "" - -#define NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h deleted file mode 100644 index d6a151d20ce6..000000000000 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ /dev/null @@ -1,376 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * mpc8349emds board configuration file - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ - -/* - * DDR Setup - */ -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ - -/* - * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver - * unselect it to use old spd_sdram.c - */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x52 -#define SPD_EEPROM_ADDRESS2 0x51 -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -/* - * DDRCDR - DDR Control Driver Register - */ -#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 - -#if defined(CONFIG_SPD_EEPROM) -/* - * Determine DDR configuration from I2C interface. - */ -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ -#else -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_TIMING_1 0x36332321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ - -/* the default burst length is 4 - for 64-bit data path */ - /* DLL,normal,seq,4/2.5, 4 burst len */ -#define CONFIG_SYS_DDR_MODE 0x00000022 -#endif - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* - * BCSR register on local bus 32KB, 8-bit wide for MDS config reg - */ -#define CONFIG_SYS_BCSR 0xE2400000 - /* Access window base at BCSR base */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ - -/* - * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. - */ - -/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - */ - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 - */ - - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ - | LSDMR_BSMA1516 \ - | LSDMR_RFCR8 \ - | LSDMR_PRETOACT6 \ - | LSDMR_ACTTORW3 \ - | LSDMR_BL8 \ - | LSDMR_WRC3 \ - | LSDMR_CL3) - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* SPI */ -#undef CONFIG_SOFT_SPI /* SPI bit-banged */ - -/* GPIOs. Used as SPI chip selects */ -#define CONFIG_SYS_GPIO1_PRELIM -#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ -#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ - -/* TSEC */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* USB */ -#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xFIXME - #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif /* CONFIG_PCI */ - -/* - * TSEC configuration - */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Configure on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT -/* Address and size of Redundant Environment Sector */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -/* - * System performance - */ -#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ -#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ - -/* System IO Config */ -#define CONFIG_SYS_SICRH 0 -#define CONFIG_SYS_SICRL SICRL_LDP_A - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_HOSTNAME "mpc8349emds" -#define CONFIG_ROOTPATH "/nfsroot/rootfs" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=mpc8349emds\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ - "update=protect off fe000000 fe03ffff; " \ - "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ - "upd=run load update\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc834x_mds.dtb\0" \ - "" - -#define NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* __CONFIG_H */
On Thu, Sep 09, 2021 at 07:54:53AM -0400, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline. Remove it.
Cc: Priyanka Jain priyanka.jain@nxp.com Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/next, thanks!
On 09.09.21 13:54, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline. Remove it.
Cc: Stefano Babic sbabic@denx.de Signed-off-by: Tom Rini trini@konsulko.com
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
arch/arm/Kconfig | 6 - board/CarMediaLab/flea3/Kconfig | 15 -- board/CarMediaLab/flea3/MAINTAINERS | 6 - board/CarMediaLab/flea3/Makefile | 8 - board/CarMediaLab/flea3/flea3.c | 227 ------------------------ board/CarMediaLab/flea3/lowlevel_init.S | 24 --- configs/flea3_defconfig | 58 ------ drivers/serial/Kconfig | 3 +- include/configs/flea3.h | 155 ---------------- 9 files changed, 1 insertion(+), 501 deletions(-) delete mode 100644 board/CarMediaLab/flea3/Kconfig delete mode 100644 board/CarMediaLab/flea3/MAINTAINERS delete mode 100644 board/CarMediaLab/flea3/Makefile delete mode 100644 board/CarMediaLab/flea3/flea3.c delete mode 100644 board/CarMediaLab/flea3/lowlevel_init.S delete mode 100644 configs/flea3_defconfig delete mode 100644 include/configs/flea3.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 21f17c202f6c..909a308970b7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -568,11 +568,6 @@ config TARGET_STV0991 select SPI_FLASH imply CMD_DM
-config TARGET_FLEA3
- bool "Support flea3"
- select CPU_ARM1136
- select GPIO_EXTRA_HEADER
- config ARCH_BCM283X bool "Broadcom BCM283X family" select DM
@@ -2107,7 +2102,6 @@ source "board/armltd/total_compute/Kconfig"
source "board/bosch/shc/Kconfig" source "board/bosch/guardian/Kconfig" -source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" source "board/Marvell/octeontx/Kconfig" source "board/Marvell/octeontx2/Kconfig" diff --git a/board/CarMediaLab/flea3/Kconfig b/board/CarMediaLab/flea3/Kconfig deleted file mode 100644 index 7113f2b51f6a..000000000000 --- a/board/CarMediaLab/flea3/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_FLEA3
-config SYS_BOARD
- default "flea3"
-config SYS_VENDOR
- default "CarMediaLab"
-config SYS_SOC
- default "mx35"
-config SYS_CONFIG_NAME
- default "flea3"
-endif diff --git a/board/CarMediaLab/flea3/MAINTAINERS b/board/CarMediaLab/flea3/MAINTAINERS deleted file mode 100644 index c7b0df7bc429..000000000000 --- a/board/CarMediaLab/flea3/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -FLEA3 BOARD -M: Stefano Babic sbabic@denx.de -S: Maintained -F: board/CarMediaLab/flea3/ -F: include/configs/flea3.h -F: configs/flea3_defconfig diff --git a/board/CarMediaLab/flea3/Makefile b/board/CarMediaLab/flea3/Makefile deleted file mode 100644 index edaac8683b36..000000000000 --- a/board/CarMediaLab/flea3/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de -# -# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-obj-y := flea3.o -obj-y += lowlevel_init.o diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c deleted file mode 100644 index ecd70ecbdc41..000000000000 --- a/board/CarMediaLab/flea3/flea3.c +++ /dev/null @@ -1,227 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de
- (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- Copyright (C) 2011, Stefano Babic sbabic@denx.de
- */
-#include <common.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <env.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/iomux-mx35.h> -#include <i2c.h> -#include <linux/types.h> -#include <asm/gpio.h> -#include <asm/arch/sys_proto.h> -#include <netdev.h> -#include <fdt_support.h> -#include <mtd_node.h> -#include <jffs2/load_kernel.h>
-#ifndef CONFIG_BOARD_EARLY_INIT_F -#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" -#endif
-#define CCM_CCMR_CONFIG 0x003F4208
-#define ESDCTL_DDR2_CONFIG 0x007FFC3F
-static inline void dram_wait(unsigned int count) -{
- volatile unsigned int wait = count;
- while (wait--)
;-}
-DECLARE_GLOBAL_DATA_PTR;
-int dram_init(void) -{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);- return 0;
-}
-static void board_setup_sdram(void) -{
- struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
- /* Initialize with default values both CSD0/1 */
- writel(0x2000, &esdc->esdctl0);
- writel(0x2000, &esdc->esdctl1);
- mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
13, 10, 2, 0x8080);-}
-static void setup_iomux_uart3(void) -{
- static const iomux_v3_cfg_t uart3_pads[] = {
MX35_PAD_RTS2__UART3_RXD_MUX,MX35_PAD_CTS2__UART3_TXD_MUX,- };
- imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
-}
-#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
-static void setup_iomux_i2c(void) -{
- static const iomux_v3_cfg_t i2c_pads[] = {
NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),- };
- imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
-}
-static void setup_iomux_spi(void) -{
- static const iomux_v3_cfg_t spi_pads[] = {
MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,MX35_PAD_CSPI1_MISO__CSPI1_MISO,MX35_PAD_CSPI1_SS0__CSPI1_SS0,MX35_PAD_CSPI1_SS1__CSPI1_SS1,MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,- };
- imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
-}
-static void setup_iomux_fec(void) -{
- static const iomux_v3_cfg_t fec_pads[] = {
MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,MX35_PAD_FEC_RX_DV__FEC_RX_DV,MX35_PAD_FEC_COL__FEC_COL,MX35_PAD_FEC_RDATA0__FEC_RDATA_0,MX35_PAD_FEC_TDATA0__FEC_TDATA_0,MX35_PAD_FEC_TX_EN__FEC_TX_EN,MX35_PAD_FEC_MDC__FEC_MDC,MX35_PAD_FEC_MDIO__FEC_MDIO,MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,MX35_PAD_FEC_CRS__FEC_CRS,MX35_PAD_FEC_RDATA1__FEC_RDATA_1,MX35_PAD_FEC_TDATA1__FEC_TDATA_1,MX35_PAD_FEC_RDATA2__FEC_RDATA_2,MX35_PAD_FEC_TDATA2__FEC_TDATA_2,MX35_PAD_FEC_RDATA3__FEC_RDATA_3,MX35_PAD_FEC_TDATA3__FEC_TDATA_3,/* GPIO used to power off ethernet */MX35_PAD_STXFS4__GPIO2_31,- };
- /* setup pins for FEC */
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-int board_early_init_f(void) -{
- struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;- /* setup GPIO3_1 to set HighVCore signal */
- imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
- gpio_direction_output(65, 1);
- /* initialize PLL and clock configuration */
- writel(CCM_CCMR_CONFIG, &ccm->ccmr);
- writel(CCM_MPLL_532_HZ, &ccm->mpctl);
- writel(CCM_PPLL_300_HZ, &ccm->ppctl);
- /* Set the core to run at 532 Mhz */
- writel(0x00001000, &ccm->pdr0);
- /* Set-up RAM */
- board_setup_sdram();
- /* enable clocks */
- writel(readl(&ccm->cgr0) |
MXC_CCM_CGR0_EMI_MASK |MXC_CCM_CGR0_EDIO_MASK |MXC_CCM_CGR0_EPIT1_MASK,&ccm->cgr0);- writel(readl(&ccm->cgr1) |
MXC_CCM_CGR1_FEC_MASK |MXC_CCM_CGR1_GPIO1_MASK |MXC_CCM_CGR1_GPIO2_MASK |MXC_CCM_CGR1_GPIO3_MASK |MXC_CCM_CGR1_I2C1_MASK |MXC_CCM_CGR1_I2C2_MASK |MXC_CCM_CGR1_I2C3_MASK,&ccm->cgr1);- /* Set-up NAND */
- __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
- /* Set pinmux for the required peripherals */
- setup_iomux_uart3();
- setup_iomux_i2c();
- setup_iomux_fec();
- setup_iomux_spi();
- return 0;
-}
-int board_init(void) -{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- /* Enable power for ethernet */
- gpio_direction_output(63, 0);
- udelay(2000);
- return 0;
-}
-#ifdef CONFIG_REVISION_TAG -u32 get_board_rev(void) -{
- int rev = 0;
- return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
-} -#endif
-/*
- called prior to booting kernel or by 'fdt boardsetup' command
- */
-int ft_board_setup(void *blob, struct bd_info *bd) -{
- static const struct node_info nodes[] = {
{ "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */{ "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */- };
- if (env_get("fdt_noauto")) {
puts(" Skiping ft_board_setup (fdt_noauto defined)\n");return 0;- }
- fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
- return 0;
-} diff --git a/board/CarMediaLab/flea3/lowlevel_init.S b/board/CarMediaLab/flea3/lowlevel_init.S deleted file mode 100644 index 8186b3922bad..000000000000 --- a/board/CarMediaLab/flea3/lowlevel_init.S +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de
- (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- Copyright (C) 2011, Stefano Babic sbabic@denx.de
- */
-#include <config.h> -#include <asm/arch/lowlevel_macro.S>
-.globl lowlevel_init -lowlevel_init:
- core_init
- init_aips
- init_max
- init_m3if
- mov pc, lr
diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig deleted file mode 100644 index 81e291a94160..000000000000 --- a/configs/flea3_defconfig +++ /dev/null @@ -1,58 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_TARGET_FLEA3=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_MALLOC_LEN=0x110000 -CONFIG_SYS_LOAD_ADDR=0x80800000 -CONFIG_FIT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="flea3 U-Boot > " -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xA0080000 -CONFIG_ENV_ADDR_REDUND=0xA0090000 -CONFIG_MXC_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_MXC=y -CONFIG_SYS_MXC_I2C3_SLAVE=0xfe -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ8XXX=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 36ee43210a9f..cbea165b9d54 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -645,8 +645,7 @@ config MCFUART
config MXC_UART bool "IMX serial port support"
- depends on ARCH_MX25 || ARCH_MX31 || TARGET_FLEA3 \
|| MX5 || MX6 || MX7 || IMX8M
- depends on ARCH_MX25 || ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M help If you have a machine based on a Motorola IMX CPU you can enable its onboard serial port by enabling this option.
diff --git a/include/configs/flea3.h b/include/configs/flea3.h deleted file mode 100644 index 6c3b2c4bf554..000000000000 --- a/include/configs/flea3.h +++ /dev/null @@ -1,155 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- (C) Copyright 2011, Stefano Babic sbabic@denx.de
- (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de
- Configuration for the flea3 board.
- */
-#ifndef __CONFIG_H -#define __CONFIG_H
-#include <asm/arch/imx-regs.h>
- /* High Level Configuration Options */
-#define CONFIG_MX35
-/* Set TEXT at the beginning of the NOR flash */
-/* This is required to setup the ESDC controller */
-/*
- Hardware drivers
- */
-#define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */
-/*
- UART (console)
- */
-#define CONFIG_MXC_UART_BASE UART3_BASE
-/*
- Command definition
- */
-#define CONFIG_NET_RETRY_COUNT 100
-/*
- Ethernet on SOC (FEC)
- */
-#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1
-#define CONFIG_ARP_TIMEOUT 200UL
-/*
- Miscellaneous configurable options
- */
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-/*
- Physical Memory Map
- */
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_GBL_DATA_OFFSET)-/*
- MTD Command for mtdparts
- */
-/*
- FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-/* Address and size of Redundant Environment Sector */
-/*
- CFI FLASH driver setup
- */
-/* A non-standard buffered write algorithm */
-/*
- NAND FLASH driver setup
- */
-#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE
-/*
- Default environment and default scripts
- to update uboot and load kernel
- */
-#define CONFIG_HOSTNAME "flea3" -#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip_sta=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \":${hostname}:${netdev}:off panic=1\0" \- "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
- "addip=if test -n ${ipdyn};then run addip_dyn;" \
"else run addip_sta;fi\0" \- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addtty=setenv bootargs ${bootargs}" \
" console=ttymxc2,${baudrate}\0" \- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
- "loadaddr=80800000\0" \
- "kernel_addr_r=80800000\0" \
- "hostname=" CONFIG_HOSTNAME "\0" \
- "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
- "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr}\0" \- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
"run nfsargs addip addtty addmtd addmisc;" \"bootm ${kernel_addr_r}\0" \- "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \- "net_self=if run net_self_load;then " \
"run ramargs addip addtty addmtd addmisc;" \"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \"else echo Images not loades;fi\0" \- "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
- "update=protect off ${uboot_addr} +80000;" \
"erase ${uboot_addr} +80000;" \"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \- "upd=if run load;then echo Updating u-boot;if run update;" \
"then echo U-Boot updated;" \"else echo Error updating u-boot !;" \"echo Board without bootloader !!;" \"fi;" \"else echo U-Boot not downloaded..exiting;fi\0" \- "bootcmd=run net_nfs\0"
-#endif /* __CONFIG_H */
participants (4)
-
Simon Guinot -
Stefan Roese -
Stefano Babic -
Tom Rini