[U-Boot] [PATCH v4 0/7] iMX6 SabreSD SPL Support
This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board.
After applying the following patches, it will produces SPL and u-boot.img binary images. You should run the two commands below to store it in your SD or eMMC.
sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69
Changes (v2): Merged the SPL support into the main board file Remove the compilation warmings
Changes (v3): Removed sp and gd Use imx_ddr_size to set the ram_size
Changes (v4): Add a separate board configuration file to enable SPL (mx6sabresd_spl_defconfig).
Mapped DCD data to mx6_mmdc_calibration, mx6dq_iomux_grp_regs, mx6dq_iomux_ddr_regs and mx6_ddr3_cfg data structures.
Read 11 and 12 bits of BOOT_CFG register to actually determine the active mmc port.
John Tobias (7): imx6: add spl config for mx6sabresd kconfig: imx6: add SUPPORT_SPL mmc: imx6: call spl_board_mmc_init imx6: add spl in the header file imx6: add some flexibility for defining macros imx6: SPL support for iMX6 SabreSD imx6: add data configuration file for SPL
arch/arm/Kconfig | 1 + board/freescale/mx6sabresd/mx6sabresd.c | 187 +++++++++++++++++++++++++- board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 58 ++++++++ configs/mx6sabresd_spl_defconfig | 5 + drivers/mmc/mmc.c | 9 +- include/configs/imx6_spl.h | 4 + include/configs/mx6sabresd.h | 7 + include/mmc.h | 3 + 8 files changed, 269 insertions(+), 5 deletions(-) create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg create mode 100644 configs/mx6sabresd_spl_defconfig
add a build configuration file for mx6sabresd with spl support
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- configs/mx6sabresd_spl_defconfig | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 configs/mx6sabresd_spl_defconfig
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig new file mode 100644 index 0000000..b7b26df --- /dev/null +++ b/configs/mx6sabresd_spl_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6sabresd_spl.cfg,SPL,MX6Q" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_MX6SABRESD=y +
add SUPPORT_SPL feature for iMX6 SabreSD. It need to use mx6sabresd_spl_defconfig to compile it.
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 22eb2d5..ab0d284 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -609,6 +609,7 @@ config TARGET_MX6QSABREAUTO config TARGET_MX6SABRESD bool "Support mx6sabresd" select CPU_V7 + select SUPPORT_SPL
config TARGET_MX6SLEVK bool "Support mx6slevk"
When the spl_mmc_load_image function being called, it will call mmc_initialize function. By default, it will call board_mmc_init.
The main purpose of board_mmc_init (in practice) is to initialize all the mmc ports defined by CONFIG_SYS_FSL_USDHC_NUM.
While, in spl_board_mmc_init, it read the bootstrap to see which mmc port is active and configure it.
Then, it pass the configuration to fsl_esdhc_initialize for initialization. Finally, the spl_mmc_load_image could load and run the u-boot.img
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- drivers/mmc/mmc.c | 9 ++++++--- include/mmc.h | 3 +++ 2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 44a4feb..88c1b03 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1441,11 +1441,14 @@ int mmc_initialize(bd_t *bis) INIT_LIST_HEAD (&mmc_devices); cur_dev_num = 0;
- if (board_mmc_init(bis) < 0) +#ifdef CONFIG_SPL_BUILD + if (spl_board_mmc_init(bis) < 0) cpu_mmc_init(bis); +#else + if (board_mmc_init(bis) < 0) + cpu_mmc_init(bis);
-#ifndef CONFIG_SPL_BUILD - print_mmc_devices(','); + print_mmc_devices(','); #endif
do_preinit(); diff --git a/include/mmc.h b/include/mmc.h index d74a190..37119b8 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -388,6 +388,9 @@ int mmc_legacy_init(int verbose); int board_mmc_init(bd_t *bis); int cpu_mmc_init(bd_t *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); +#ifdef CONFIG_SPL +int spl_board_mmc_init(bd_t *bis); +#endif
/* Set block count limit because of 16 bit register limit on some hardware*/ #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
add the spl info in the header file. It includes the stack address of iMX6Q which is 0x0093FFB8
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- include/configs/mx6sabresd.h | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 938030d..4d2e54a 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -12,6 +12,13 @@ #include <asm/arch/imx-regs.h> #include <asm/imx-common/gpio.h>
+#ifdef CONFIG_SPL +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_STACK 0x0093FFB8 +#include "imx6_spl.h" +#endif + #define CONFIG_MACH_TYPE 3980 #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONSOLE_DEV "ttymxc0"
iMX6 SabreSD has a different stack address (0x0093FFB8) compare to the default stack address defined in the file.
The CONFIG_SYS_TEXT_BASE is defined in mx6sabre_common.h. It is better to add the #ifndef to avoid compilation warnings.
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- include/configs/imx6_spl.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 5a5f940..4ff37b3 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -29,7 +29,9 @@ #define CONFIG_SPL_TEXT_BASE 0x00908000 #define CONFIG_SPL_MAX_SIZE 0x10000 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7" +#ifndef CONFIG_SPL_STACK #define CONFIG_SPL_STACK 0x0091FFB8 +#endif #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT @@ -66,7 +68,9 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ #define CONFIG_SYS_SPL_MALLOC_START 0x18300000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3200000 /* 50 MB */ +#ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x17800000 #endif +#endif
#endif
On Tue, Nov 11, 2014 at 8:50 PM, John Tobias john.tobias.ph@gmail.com wrote:
iMX6 SabreSD has a different stack address (0x0093FFB8) compare to the default stack address defined in the file.
Why you are using a different stack?
Hi Otavio,
In iMX6DQ data sheet the stack address is 0x0093FFB8 (page 383). While, in iMX6SDL datasheet (page 393) is 0x0091FFB8.
Regards,
john
On Tue, Nov 11, 2014 at 3:58 PM, Otavio Salvador otavio@ossystems.com.br wrote:
On Tue, Nov 11, 2014 at 8:50 PM, John Tobias john.tobias.ph@gmail.com wrote:
iMX6 SabreSD has a different stack address (0x0093FFB8) compare to the default stack address defined in the file.
Why you are using a different stack?
-- Otavio Salvador O.S. Systems http://www.ossystems.com.br http://code.ossystems.com.br Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750
On Tue, Nov 11, 2014 at 10:15 PM, John Tobias john.tobias.ph@gmail.com wrote:
In iMX6DQ data sheet the stack address is 0x0093FFB8 (page 383). While, in iMX6SDL datasheet (page 393) is 0x0091FFB8.
I am worrying how Compulab and Gateworks are using SPL if it is wrong.
I think Gateworks is based on iMX6SDL.
On Tue, Nov 11, 2014 at 4:52 PM, Otavio Salvador otavio@ossystems.com.br wrote:
On Tue, Nov 11, 2014 at 10:15 PM, John Tobias john.tobias.ph@gmail.com wrote:
In iMX6DQ data sheet the stack address is 0x0093FFB8 (page 383). While, in iMX6SDL datasheet (page 393) is 0x0091FFB8.
I am worrying how Compulab and Gateworks are using SPL if it is wrong.
-- Otavio Salvador O.S. Systems http://www.ossystems.com.br http://code.ossystems.com.br Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750
On 11/11/2014 5:52 PM, Otavio Salvador wrote:
On Tue, Nov 11, 2014 at 10:15 PM, John Tobias john.tobias.ph@gmail.com wrote:
In iMX6DQ data sheet the stack address is 0x0093FFB8 (page 383). While, in iMX6SDL datasheet (page 393) is 0x0091FFB8.
I am worrying how Compulab and Gateworks are using SPL if it is wrong.
iMX6SDL has 128KB OCRAM, 0x00900000 - 0x0091ffff iMX6DQ has 256KB OCRAM, 0x00900000 - 0x0093ffff
So, if we want 1 image to support both, we should choose 0x0091FFB8.
I don't know whether that is a goal here.
On Tue, Nov 11, 2014 at 10:59 PM, Troy Kisky troy.kisky@boundarydevices.com wrote:
iMX6SDL has 128KB OCRAM, 0x00900000 - 0x0091ffff iMX6DQ has 256KB OCRAM, 0x00900000 - 0x0093ffff
So, if we want 1 image to support both, we should choose 0x0091FFB8.
Agreed.
John,
Can't you just use the default 0x0091FFB8 value? Doesn't it work for you?
Regards,
Fabio Estevam
I'll go ahead and use the same address.
Regards,
john
On Tue, Nov 11, 2014 at 5:02 PM, Fabio Estevam festevam@gmail.com wrote:
On Tue, Nov 11, 2014 at 10:59 PM, Troy Kisky troy.kisky@boundarydevices.com wrote:
iMX6SDL has 128KB OCRAM, 0x00900000 - 0x0091ffff iMX6DQ has 256KB OCRAM, 0x00900000 - 0x0093ffff
So, if we want 1 image to support both, we should choose 0x0091FFB8.
Agreed.
John,
Can't you just use the default 0x0091FFB8 value? Doesn't it work for you?
Regards,
Fabio Estevam
Hi John,
On 12/11/2014 01:15, John Tobias wrote:
Hi Otavio,
In iMX6DQ data sheet the stack address is 0x0093FFB8 (page 383). While, in iMX6SDL datasheet (page 393) is 0x0091FFB8.
????
I admit that I should take a coffe, and after that maybe I can realize what you are saying. Anyway, it is normal for processors to set the stack pointer. If at a certain point the stack pointer is automatically set, well, this is another case. The internal ROM will set the stack pointer to a well defined address when it starts, but it does not mean that is fixed for other part of code. The problem arises if from our code (SPL) we call functions inside the ROM, and of course this can have conflicts if they share the same address range. This is also not your case - if that happens, two separate stack area must be taken.
What you are referring is the stack pointer of the ROM. Well, the processors have different ROMs (only Freescale knows the differences) and of course they can use differently the IRAM. But when the ROM gives the control to the loaded image (SPL), this can use the whole IRAM (with the use case exception I mentioned before).
That is the reason because ventana and Compulab have no problems at all.
IMHO what you are saying is not correct. Maybe I see things different after a cup of coffee :-D.
Best regards, Stefano Babic
On 12/11/2014 01:15, John Tobias wrote:
In iMX6DQ data sheet the stack address is 0x0093FFB8 (page 383). While, in iMX6SDL datasheet (page 393) is 0x0091FFB8.
On 12 Nov 2014, sbabic@denx.de wrote:
I admit that I should take a coffe, and after that maybe I can realize what you are saying. Anyway, it is normal for processors to set the stack pointer. If at a certain point the stack pointer is automatically set, well, this is another case. The internal ROM will set the stack pointer to a well defined address when it starts, but it does not mean that is fixed for other part of code. The problem arises if from our code (SPL) we call functions inside the ROM, and of course this can have conflicts if they share the same address range. This is also not your case - if that happens, two separate stack area must be taken.
What you are referring is the stack pointer of the ROM. Well, the processors have different ROMs (only Freescale knows the differences) and of course they can use differently the IRAM. But when the ROM gives the control to the loaded image (SPL), this can use the whole IRAM (with the use case exception I mentioned before).
That is the reason because ventana and Compulab have no problems at all.
Yes; this is my understanding as well. I think there is some HABv4 document which says what IRAM offsets are used and should be reserved fro all CPUs. For the iMx25 at least, it seems you may set the stack address to whatever you like when calling the ROM code. It is the HAB data that must not be touched.
So even if calls are made to the ROM code, I think you are free to set the stack address to whatever you want.
On Tue, Nov 11, 2014 at 5:02 PM, Fabio Estevam festevam@gmail.com wrote:
iMX6SDL has 128KB OCRAM, 0x00900000 - 0x0091ffff iMX6DQ has 256KB OCRAM, 0x00900000 - 0x0093ffff
So, if we want 1 image to support both, we should choose 0x0091FFB8.
This is true. However, you will limit the size on the iMX6DQ platform. Maybe that is fine for an SPL. I think you can also use address aliasing. Does the iMX6SDL fully decode? It maybe that 0x0093ffff on the iMX6SDL will go to the 0x0091ffff address. Did we try 0x0093FFB8 on the iMX6SDL and it doesn't work?
I have used the aliasing to setup cache/non-cache ranges to the IRAM. This is nice if you have L1 (primary 1M/4M MMU section entries) and need to have non-cached entries for DMA (ethernet, usb, etc). But that is probably not relevant for the SPL?
Fwiw, Bill Pringlemeir.
This patch will enable the support for SPL on iMX6 SabreSD. It tested on SD2 and SD3 mmc port.
It uses mx6dq_dram_iocfg and mx6_dram_cfg for ddr configuration.
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- board/freescale/mx6sabresd/mx6sabresd.c | 187 +++++++++++++++++++++++++++++++- 1 file changed, 185 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 3d81fff..16cfb44 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -27,6 +27,8 @@ #include <i2c.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> +#include <asm/arch/mx6-ddr.h> + DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ @@ -55,8 +57,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - + gd->ram_size = imx_ddr_size(); return 0; }
@@ -607,3 +608,185 @@ int checkboard(void) puts("Board: MX6-SabreSD\n"); return 0; } + +#ifdef CONFIG_SPL_BUILD +#include <spl.h> +#include <libfdt.h> + +#define BOOT_CFG 0x020D8004 +struct fsl_esdhc_cfg spl_usdhc_cfg; + +const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = 0x000C0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x001F001F, + .p0_mpwldectrl1 = 0x001F001F, + .p1_mpwldectrl0 = 0x00440044, + .p1_mpwldectrl1 = 0x00440044, + .p0_mpdgctrl0 = 0x434B0350, + .p0_mpdgctrl1 = 0x034C0359, + .p1_mpdgctrl0 = 0x434B0350, + .p1_mpdgctrl1 = 0x03650348, + .p0_mprddlctl = 0x4436383B, + .p1_mprddlctl = 0x39393341, + .p0_mpwrdlctl = 0x35373933, + .p1_mpwrdlctl = 0x48254A36, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 64, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* + * This section require the differentiation + * between iMX6 Sabre Families. + * But for now, it will configure only for + * SabreSD. + */ +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = mem_ddr.width/32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 2, + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +int spl_board_mmc_init(bd_t *bis) +{ + unsigned reg = readl(BOOT_CFG) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x2 SD2 + * 0x3 SD4 + */ + switch (reg & 0x3) { + case 0x1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + spl_usdhc_cfg.esdhc_base = USDHC2_BASE_ADDR; + spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = spl_usdhc_cfg.sdhc_clk; + break; + case 0x2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + spl_usdhc_cfg.esdhc_base = USDHC3_BASE_ADDR; + spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gd->arch.sdhc_clk = spl_usdhc_cfg.sdhc_clk; + break; + case 0x3: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + spl_usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR; + spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + gd->arch.sdhc_clk = spl_usdhc_cfg.sdhc_clk; + break; + } + + return fsl_esdhc_initialize(bis, &spl_usdhc_cfg); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} +#endif
It's a trim version of mx6q_4x_mt41j128.cfg. It just removed the related settings for DDR
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg
diff --git a/board/freescale/mx6sabresd/mx6sabresd_spl.cfg b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg new file mode 100644 index 0000000..2bf4817 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu r64343@freescale.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb
participants (6)
-
Bill Pringlemeir -
Fabio Estevam -
John Tobias -
Otavio Salvador -
Stefano Babic -
Troy Kisky