[U-Boot] [PATCH 1/3] fsl-ddr: Fix the turnaround timing for TIMING_CFG_4
From: Dave Liu daveliu@freescale.com
Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and OTF case, BL/2 cycles is enough for fixed BL8. Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 will improve the memory performance.
Signed-off-by: Dave Liu daveliu@freescale.com --- cpu/mpc8xxx/ddr/ctrl_regs.c | 19 +++++++++++++------ 1 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index adc4f6e..caac943 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -934,7 +934,8 @@ static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) }
/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */ -static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr) +static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) { unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ @@ -943,9 +944,15 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr) unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
#if defined(CONFIG_FSL_DDR3) - /* We need set BL/2 + 4 for BC4 or OTF */ - rrt = 4; /* BL/2 + 4 clocks */ - wwt = 4; /* BL/2 + 4 clocks */ + if (popts->burst_length == DDR_BL8) { + /* We set BL/2 for fixed BL8 */ + rrt = 0; /* BL/2 clocks */ + wwt = 0; /* BL/2 clocks */ + } else { + /* We need to set BL/2 + 2 to BC4 and OTF */ + rrt = 2; /* BL/2 + 2 clocks */ + wwt = 2; /* BL/2 + 2 clocks */ + } dll_lock = 1; /* tDLLK = 512 clocks from spec */ #endif ddr->timing_cfg_4 = (0 @@ -1343,7 +1350,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_sdram_clk_cntl(ddr, popts); set_ddr_init_addr(ddr); set_ddr_init_ext_addr(ddr); - set_timing_cfg_4(ddr); + set_timing_cfg_4(ddr, popts); set_timing_cfg_5(ddr);
set_ddr_zq_cntl(ddr, zq_en);
From: Dave Liu daveliu@freescale.com
For 64B cacheline SoC, set the fixed 8-beat burst len, for 32B cacheline SoC, set the On-The-Fly as default.
Signed-off-by: Dave Liu daveliu@freescale.com --- cpu/mpc8xxx/ddr/options.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c index 3dcd33d..8e62279 100644 --- a/cpu/mpc8xxx/ddr/options.c +++ b/cpu/mpc8xxx/ddr/options.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008, 2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -109,8 +109,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
/* Choose burst length. */ #if defined(CONFIG_FSL_DDR3) +#if defined(CONFIG_E500MC) + popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */ + popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ +#else popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ +#endif #else popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ #endif
From: Dave Liu daveliu@freescale.com
add the macro definition for Rtt_Nom termination value for DDR3
Signed-off-by: Dave Liu daveliu@freescale.com --- include/asm-ppc/fsl_ddr_sdram.h | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 3216a50..02920db 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -24,6 +24,12 @@ #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ #define DDR_BL8 8 /* burst length 8 */
+#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ +#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ +#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ +#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ +#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ + #if defined(CONFIG_FSL_DDR1) #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
Dear Kumar Gala,
In message 1269194951-17996-1-git-send-email-galak@kernel.crashing.org you wrote:
From: Dave Liu daveliu@freescale.com
Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and OTF case, BL/2 cycles is enough for fixed BL8. Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 will improve the memory performance.
Signed-off-by: Dave Liu daveliu@freescale.com
cpu/mpc8xxx/ddr/ctrl_regs.c | 19 +++++++++++++------ 1 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index adc4f6e..caac943 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1,5 +1,5 @@ /*
- Copyright 2008-2009 Freescale Semiconductor, Inc.
- Copyright 2008-2010 Freescale Semiconductor, Inc.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
... * Version 2 as published by the Free Software Foundation.
As it turns out, basicly all FSL DDR code (and lots more of the FSL code) are GPL v2 only:
board/freescale/mpc8323erdb/mpc8323erdb.c board/freescale/mpc8536ds/ddr.c board/freescale/mpc8540ads/ddr.c board/freescale/mpc8541cds/ddr.c board/freescale/mpc8544ds/ddr.c board/freescale/mpc8548cds/ddr.c board/freescale/mpc8555cds/ddr.c board/freescale/mpc8560ads/ddr.c board/freescale/mpc8568mds/ddr.c board/freescale/mpc8572ds/ddr.c board/freescale/mpc8610hpcd/ddr.c board/freescale/mpc8641hpcn/ddr.c board/freescale/mpc8569mds/ddr.c board/freescale/p2020ds/ddr.c board/mpc8540eval/ddr.c cpu/mpc85xx/ddr-gen2.c cpu/mpc85xx/ddr-gen1.c cpu/mpc85xx/ddr-gen3.c cpu/mpc86xx/ddr-8641.c cpu/mpc86xx/fdt.c cpu/mpc8xxx/ddr/common_timing_params.h cpu/mpc8xxx/ddr/Makefile cpu/mpc8xxx/ddr/lc_common_dimm_params.c cpu/mpc8xxx/ddr/ddr.h cpu/mpc8xxx/ddr/ddr1_dimm_params.c cpu/mpc8xxx/ddr/ddr2_dimm_params.c cpu/mpc8xxx/ddr/main.c cpu/mpc8xxx/ddr/ddr3_dimm_params.c cpu/mpc8xxx/ddr/util.c cpu/mpc8xxx/ddr/ctrl_regs.c cpu/mpc8xxx/ddr/options.c cpu/mpc8xxx/Makefile drivers/i2c/fsl_i2c.c drivers/pci/fsl_pci_init.c include/asm-m68k/fsl_i2c.h include/asm-ppc/fsl_i2c.h include/asm-ppc/fsl_ddr_dimm_params.h include/asm-ppc/fsl_law.h include/asm-ppc/mpc8xxx_spi.h include/asm-ppc/fsl_dma.h include/asm-ppc/fsl_ddr_sdram.h include/configs/MPC8323ERDB.h include/configs/MPC8610HPCD.h etc. etc.
Can we please fix this?
Best regards,
Wolfgang Denk
On Mar 22, 2010, at 5:51 PM, Wolfgang Denk wrote:
Dear Kumar Gala,
In message 1269194951-17996-1-git-send-email-galak@kernel.crashing.org you wrote:
From: Dave Liu daveliu@freescale.com
Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and OTF case, BL/2 cycles is enough for fixed BL8. Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 will improve the memory performance.
Signed-off-by: Dave Liu daveliu@freescale.com
cpu/mpc8xxx/ddr/ctrl_regs.c | 19 +++++++++++++------ 1 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index adc4f6e..caac943 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1,5 +1,5 @@ /*
- Copyright 2008-2009 Freescale Semiconductor, Inc.
- Copyright 2008-2010 Freescale Semiconductor, Inc.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
...
- Version 2 as published by the Free Software Foundation.
As it turns out, basicly all FSL DDR code (and lots more of the FSL code) are GPL v2 only:
board/freescale/mpc8323erdb/mpc8323erdb.c board/freescale/mpc8536ds/ddr.c board/freescale/mpc8540ads/ddr.c board/freescale/mpc8541cds/ddr.c board/freescale/mpc8544ds/ddr.c board/freescale/mpc8548cds/ddr.c board/freescale/mpc8555cds/ddr.c board/freescale/mpc8560ads/ddr.c board/freescale/mpc8568mds/ddr.c board/freescale/mpc8572ds/ddr.c board/freescale/mpc8610hpcd/ddr.c board/freescale/mpc8641hpcn/ddr.c board/freescale/mpc8569mds/ddr.c board/freescale/p2020ds/ddr.c board/mpc8540eval/ddr.c cpu/mpc85xx/ddr-gen2.c cpu/mpc85xx/ddr-gen1.c cpu/mpc85xx/ddr-gen3.c cpu/mpc86xx/ddr-8641.c cpu/mpc86xx/fdt.c cpu/mpc8xxx/ddr/common_timing_params.h cpu/mpc8xxx/ddr/Makefile cpu/mpc8xxx/ddr/lc_common_dimm_params.c cpu/mpc8xxx/ddr/ddr.h cpu/mpc8xxx/ddr/ddr1_dimm_params.c cpu/mpc8xxx/ddr/ddr2_dimm_params.c cpu/mpc8xxx/ddr/main.c cpu/mpc8xxx/ddr/ddr3_dimm_params.c cpu/mpc8xxx/ddr/util.c cpu/mpc8xxx/ddr/ctrl_regs.c cpu/mpc8xxx/ddr/options.c cpu/mpc8xxx/Makefile drivers/i2c/fsl_i2c.c drivers/pci/fsl_pci_init.c include/asm-m68k/fsl_i2c.h include/asm-ppc/fsl_i2c.h include/asm-ppc/fsl_ddr_dimm_params.h include/asm-ppc/fsl_law.h include/asm-ppc/mpc8xxx_spi.h include/asm-ppc/fsl_dma.h include/asm-ppc/fsl_ddr_sdram.h include/configs/MPC8323ERDB.h include/configs/MPC8610HPCD.h etc. etc.
Can we please fix this?
I'm looking into it, but am not holding up these patches on it. Ok?
- k
participants (2)
-
Kumar Gala -
Wolfgang Denk