[U-Boot] [PATCH v5 0/18] tegra: Add fdt definitions and USB driver
This series brings in the Linux kernel fdt file and provides a working USB driver for Tegra2 Seaboard.
(I have done this in one series since otherwise most of the fdt additions will just look like dead code.)
The driver requires CONFIG_OF_CONTROL and a device tree to operate.
Some enhancements to fdtdec are required to make this easier, and these are included in the series also. I have had to bring in basic GPIO support due to the request to put the USB VBUS into the fdt.
Since the kernel recently got a very minimal USB binding, I have started with that and extended it where appropriate.
Tegra likes to have cache-aligned buffers. I have dropped the patch which implements this since we will solve this problem by making callers align their buffers (as we did with MMC).
Changes in v2: - Add setting of pinmux for USB VBUS GPIO - Decode USB VBUS GPIO from the fdt - Decode phy type differently (to match new kernel fdt) - Improve debug() printouts in case of failure to init USB - Remove 0x from fdt aliases - Remove non-fdt operation of USB, since it is not needed - Remove unneeded CONFIG_TEGRA_USBx defines - Rename params to timing - Rename tegra20-usb to tegra20-ehcui (to match new kernel fdt) - Store entire fdt config in port list, not just register pointer - Use "okay" instead of "ok" for fdt node status
Changes in v3: - Disable USB2 which is not used on Seaboard - Drop Tegra USB alignment patch as we will deal with this another way - Fix device tree indenting with tabs instead of spaces - Remove "okay" from nodes since this is the default anyway - Remove usbparams properties from fdt and moved them to C code
Changes in v4: - Add clock bindings for Tegra2x - Add fdtdec function to return peripheral ID - Add staging area for device tree bindings used in U-Boot - Use peripheral clock node to obtain peripheral ID - Use updated fdtdec alias functiona to get USB aliases
Changes in v5: - Add CONFIG_EHCI_DCACHE which is needed for dcache operation - Add additional debugging to report active USB ports - Add dr_mode property to control host/device/otg mode - Add nvidia,has-legacy-mode property per review comments - Allow any port to operate in otg mode - Change device tree comment style from // to /* */ - Correct PTS_MASK value to be unsigned - Drop unused CONFIG_USB_EHCI_DATA_ALIGN option - Fixed endian bug in fdtdec_decode_gpios() - Implement new device tree properties - Make sure GPIO name is NULL if incorrectly decoded - Put pinmux setting into a board-specific function - Remove checking of peripheral ID and try to use only device tree - Remove support-host-mode property - Report error if phy clock does not start up - Update README to indicate that we will commit fdt documentation to U-Boot
Simon Glass (18): fdt: Add basic support for decoding GPIO definitions arm: fdt: Ensure that an embedded fdt is word-aligned arm: fdt: Add skeleton device tree file from kernel tegra: fdt: Add Tegra2x device tree file from kernel tegra: fdt: Add device tree file for Tegra2 Seaboard from kernel fdt: Add staging area for device tree binding documentation fdt: Add tegra-usb bindings file from linux tegra: fdt: Add additional USB binding tegra: fdt: Add clock bindings tegra: usb: fdt: Add additional device tree definitions for USB ports tegra: usb: fdt: Add USB definitions for Tegra2 Seaboard usb: Add support for txfifo threshold fdt: Add function to return peripheral/clock ID tegra: usb: Add support for Tegra USB peripheral tegra: usb: Add USB support to nvidia boards tegra: usb: Add common USB defines for tegra2 boards tegra: usb: Enable USB on Seaboard tegra: fdt: Enable FDT support for Seaboard
README | 3 + arch/arm/cpu/armv7/tegra2/Makefile | 4 +- arch/arm/cpu/armv7/tegra2/config.mk | 2 + arch/arm/cpu/armv7/tegra2/usb.c | 460 ++++++++++++++++++++++++ arch/arm/cpu/armv7/u-boot.lds | 5 + arch/arm/dts/skeleton.dtsi | 13 + arch/arm/dts/tegra20.dtsi | 202 +++++++++++ arch/arm/include/asm/arch-tegra2/tegra2.h | 2 + arch/arm/include/asm/arch-tegra2/usb.h | 252 +++++++++++++ board/nvidia/common/board.c | 12 + board/nvidia/common/board.h | 6 + board/nvidia/dts/tegra2-seaboard.dts | 46 +++ board/nvidia/seaboard/seaboard.c | 6 + doc/device-tree-bindings/README | 17 + doc/device-tree-bindings/clock/tegra-periphclk | 51 +++ doc/device-tree-bindings/usb/tegra-usb.txt | 25 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-hcd.c | 7 + drivers/usb/host/ehci-tegra.c | 62 ++++ drivers/usb/host/ehci.h | 6 +- dts/Makefile | 2 +- include/configs/seaboard.h | 12 + include/configs/tegra2-common.h | 10 + include/fdtdec.h | 59 +++ lib/fdtdec.c | 93 +++++ 25 files changed, 1355 insertions(+), 3 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/usb.c create mode 100644 arch/arm/dts/skeleton.dtsi create mode 100644 arch/arm/dts/tegra20.dtsi create mode 100644 arch/arm/include/asm/arch-tegra2/usb.h create mode 100644 board/nvidia/dts/tegra2-seaboard.dts create mode 100644 doc/device-tree-bindings/README create mode 100644 doc/device-tree-bindings/clock/tegra-periphclk create mode 100644 doc/device-tree-bindings/usb/tegra-usb.txt create mode 100644 drivers/usb/host/ehci-tegra.c
This adds some support into fdtdec for reading GPIO definitions from the fdt. We permit up to FDT_GPIO_MAX GPIOs in the system. Each GPIO is of the form:
gpio-function-name = <phandle gpio_num flags>;
where:
phandle is a pointer to the GPIO node gpio_num is the number of the GPIO (0 to 223) flags is a flag, as follows:
bit meaning 0 0=polarity normal, 1=active low (inverted)
An example is:
enable-propounder-gpios = <&gpio 43 0>;
which means that GPIO 43 is used to enable the propounder (setting the GPIO high), or that you can detect that the propounder is enabled by checking if the GPIO is high (the fdt does not indicate input/output).
Two main functions are provided:
fdtdec_decode_gpio() reads a GPIO property from an fdt node and decodes it into a structure.
fdtdec_setup_gpio() sets up the GPIO by calling gpio_request for you.
Both functions can cope with the property being missing, which is taken to mean that that GPIO function is not available or is not needed.
[For reference, from Stephen Warren swarren@nvidia.com. It may be that we add this extra complexity later if needed:
The correct way to parse such a GPIO property in general is:
* Read the first cell. * Find the node referenced by the phandle (the controller). * Ensure property gpio-controller is present in the controller node. * Read property #gpio-cells from the controller node. * Extract #gpio-cells from the original property. * Keep processing more cells from the original property; there may be multiple GPIOs listed.
According to the binding documentation in the Linux kernel, Samsung Exynos4 doesn't use this format, and while all other chips do have a flags cell, about 50% of the controllers indicate the cell is unused. ]
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v5: - Fixed endian bug in fdtdec_decode_gpios() - Make sure GPIO name is NULL if incorrectly decoded
include/fdtdec.h | 45 ++++++++++++++++++++++++++++++ lib/fdtdec.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+), 0 deletions(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h index 047f603..6c0a2d1 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -61,6 +61,23 @@ enum fdt_compat_id { COMPAT_COUNT, };
+/* GPIOs are numbered from 0 */ +enum { + FDT_GPIO_NONE = -1U, /* an invalid GPIO used to end our list */ + + FDT_GPIO_ACTIVE_LOW = 1 << 0, /* input is active low (else high) */ +}; + +/* This is the state of a GPIO pin as defined by the fdt */ +struct fdt_gpio_state { + const char *name; /* name of the fdt property defining this */ + uint gpio; /* GPIO number, or FDT_GPIO_NONE if none */ + u8 flags; /* FDT_GPIO_... flags */ +}; + +/* This tells us whether a fdt_gpio_state record is valid or not */ +#define fdt_gpio_isvalid(x) ((x)->gpio != FDT_GPIO_NONE) + /** * Find the next numbered alias for a peripheral. This is used to enumerate * all the peripherals of a certain type. @@ -227,3 +244,31 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, * @return 1 if the properly is present; 0 if it isn't present */ int fdtdec_get_bool(const void *blob, int node, const char *prop_name); + +/** + * Decode a single GPIOs from an FDT. + * + * If the property is not found, then the GPIO structure will still be + * initialised, with gpio set to FDT_GPIO_NONE. This makes it easy to + * provide optional GPIOs. + * + * @param blob FDT blob to use + * @param node Node to look at + * @param prop_name Node property name + * @param gpio gpio elements to fill from FDT + * @return 0 if ok, -FDT_ERR_NOTFOUND if the property is missing. + */ +int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name, + struct fdt_gpio_state *gpio); + +/** + * Set up a GPIO pin according to the provided gpio information. At present this + * just requests the GPIO. + * + * If the gpio is FDT_GPIO_NONE, no action is taken. This makes it easy to + * deal with optional GPIOs. + * + * @param gpio GPIO info to use for set up + * @return 0 if all ok or gpio was FDT_GPIO_NONE; -1 on error + */ +int fdtdec_setup_gpio(struct fdt_gpio_state *gpio); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 977528b..c748cac 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -24,6 +24,9 @@ #include <libfdt.h> #include <fdtdec.h>
+/* we need the generic GPIO interface here */ +#include <asm-generic/gpio.h> + DECLARE_GLOBAL_DATA_PTR;
/* @@ -336,3 +339,79 @@ int fdtdec_get_bool(const void *blob, int node, const char *prop_name) cell = fdt_getprop(blob, node, prop_name, &len); return cell != NULL; } + +/** + * Decode a list of GPIOs from an FDT. This creates a list of GPIOs with no + * terminating item. + * + * @param blob FDT blob to use + * @param node Node to look at + * @param prop_name Node property name + * @param gpio Array of gpio elements to fill from FDT. This will be + * untouched if either 0 or an error is returned + * @param max_count Maximum number of elements allowed + * @return number of GPIOs read if ok, -FDT_ERR_BADLAYOUT if max_count would + * be exceeded, or -FDT_ERR_NOTFOUND if the property is missing. + */ +static int fdtdec_decode_gpios(const void *blob, int node, + const char *prop_name, struct fdt_gpio_state *gpio, + int max_count) +{ + const struct fdt_property *prop; + const u32 *cell; + const char *name; + int len, i; + + debug("%s: %s\n", __func__, prop_name); + assert(max_count > 0); + prop = fdt_get_property(blob, node, prop_name, &len); + if (!prop) { + debug("FDT: %s: property '%s' missing\n", __func__, prop_name); + return -FDT_ERR_NOTFOUND; + } + + /* We will use the name to tag the GPIO */ + name = fdt_string(blob, fdt32_to_cpu(prop->nameoff)); + cell = (u32 *)prop->data; + len /= sizeof(u32) * 3; /* 3 cells per GPIO record */ + if (len > max_count) { + debug("FDT: %s: too many GPIOs / cells for " + "property '%s'\n", __func__, prop_name); + return -FDT_ERR_BADLAYOUT; + } + + /* Read out the GPIO data from the cells */ + for (i = 0; i < len; i++, cell += 3) { + gpio[i].gpio = fdt32_to_cpu(cell[1]); + gpio[i].flags = fdt32_to_cpu(cell[2]); + gpio[i].name = name; + } + + return len; +} + +int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name, + struct fdt_gpio_state *gpio) +{ + int err; + + debug("%s: %s\n", __func__, prop_name); + gpio->gpio = FDT_GPIO_NONE; + gpio->name = NULL; + err = fdtdec_decode_gpios(blob, node, prop_name, gpio, 1); + return err == 1 ? 0 : err; +} + +int fdtdec_setup_gpio(struct fdt_gpio_state *gpio) +{ + /* + * Return success if there is no GPIO defined. This is used for + * optional GPIOs) + */ + if (!fdt_gpio_isvalid(gpio)) + return 0; + + if (gpio_request(gpio->gpio, gpio->name)) + return -1; + return 0; +}
By putting the fdt blob into a distinctive area we can ensure that it appears at the start of the data section and is word-aligned.
Note: It does not seem to be possible to get objcopy to honour its --section-alignment flag, which would otherwise provide an easier fix for this problem.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/cpu/armv7/u-boot.lds | 5 +++++ dts/Makefile | 2 +- 2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds index 40ecf78..793e51b 100644 --- a/arch/arm/cpu/armv7/u-boot.lds +++ b/arch/arm/cpu/armv7/u-boot.lds @@ -43,6 +43,11 @@ SECTIONS
. = ALIGN(4); .data : { + /* + * Sadly objcopy seems to ignore --section-alignment. + * Put any embedded device tree first so it is aligned. + */ + *(.dts.data) *(.data) }
diff --git a/dts/Makefile b/dts/Makefile index 5792afd..83547d4 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -79,7 +79,7 @@ $(obj)dt.o: $(DT_BIN) \ cd $(dir ${DT_BIN}) && \ $(OBJCOPY) -I binary -O $${oformat} -B $${oarch} \ - $(notdir ${DT_BIN}) $@ + --prefix-sections=.dts $(notdir ${DT_BIN}) $@ rm $(DT_BIN)
OBJS-$(CONFIG_OF_EMBED) := dt.o
This was taken from commit b48c54e2 at: git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/dts/skeleton.dtsi | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) create mode 100644 arch/arm/dts/skeleton.dtsi
diff --git a/arch/arm/dts/skeleton.dtsi b/arch/arm/dts/skeleton.dtsi new file mode 100644 index 0000000..b41d241 --- /dev/null +++ b/arch/arm/dts/skeleton.dtsi @@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0>; }; +};
This was taken from commit b48c54e2 at: git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
config.mk is updated to provide this file to boards through the built-in mechanism:
/include/ ARCH_CPU_DTS
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/cpu/armv7/tegra2/config.mk | 2 + arch/arm/dts/tegra20.dtsi | 168 +++++++++++++++++++++++++++++++++++ 2 files changed, 170 insertions(+), 0 deletions(-) create mode 100644 arch/arm/dts/tegra20.dtsi
diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk index 2303dba..fe9ef5b 100644 --- a/arch/arm/cpu/armv7/tegra2/config.mk +++ b/arch/arm/cpu/armv7/tegra2/config.mk @@ -31,3 +31,5 @@ CFLAGS_arch/arm/lib/board.o += -march=armv4t endif
USE_PRIVATE_LIBGCC = yes + +CONFIG_ARCH_DEVICE_TREE := tegra20 diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi new file mode 100644 index 0000000..a9a98ea --- /dev/null +++ b/arch/arm/dts/tegra20.dtsi @@ -0,0 +1,168 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra20"; + interrupt-parent = <&intc>; + + intc: interrupt-controller@50041000 { + compatible = "nvidia,tegra20-gic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = < 0x50041000 0x1000 >, + < 0x50040100 0x0100 >; + }; + + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C000 0x100>; + interrupts = < 70 >; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 116 >; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C500 0x100>; + interrupts = < 124 >; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000D000 0x200>; + interrupts = < 85 >; + }; + + i2s@70002800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002800 0x200>; + interrupts = < 45 >; + dma-channel = < 2 >; + }; + + i2s@70002a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002a00 0x200>; + interrupts = < 35 >; + dma-channel = < 1 >; + }; + + das@70000c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-das"; + reg = <0x70000c00 0x80>; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra20-gpio"; + reg = < 0x6000d000 0x1000 >; + interrupts = < 64 65 66 67 87 119 121 >; + #gpio-cells = <2>; + gpio-controller; + }; + + pinmux: pinmux@70000000 { + compatible = "nvidia,tegra20-pinmux"; + reg = < 0x70000014 0x10 /* Tri-state registers */ + 0x70000080 0x20 /* Mux registers */ + 0x700000a0 0x14 /* Pull-up/down registers */ + 0x70000868 0xa8 >; /* Pad control registers */ + }; + + serial@70006000 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = < 68 >; + }; + + serial@70006040 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = < 69 >; + }; + + serial@70006200 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = < 78 >; + }; + + serial@70006300 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = < 122 >; + }; + + serial@70006400 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = < 123 >; + }; + + sdhci@c8000000 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000000 0x200>; + interrupts = < 46 >; + }; + + sdhci@c8000200 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000200 0x200>; + interrupts = < 47 >; + }; + + sdhci@c8000400 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000400 0x200>; + interrupts = < 51 >; + }; + + sdhci@c8000600 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000600 0x200>; + interrupts = < 63 >; + }; + + usb@c5000000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5000000 0x4000>; + interrupts = < 52 >; + phy_type = "utmi"; + }; + + usb@c5004000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5004000 0x4000>; + interrupts = < 53 >; + phy_type = "ulpi"; + }; + + usb@c5008000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5008000 0x4000>; + interrupts = < 129 >; + phy_type = "utmi"; + }; + +};
This was taken from commit b48c54e2 at: git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
Signed-off-by: Simon Glass sjg@chromium.org ---
board/nvidia/dts/tegra2-seaboard.dts | 36 ++++++++++++++++++++++++++++++++++ 1 files changed, 36 insertions(+), 0 deletions(-) create mode 100644 board/nvidia/dts/tegra2-seaboard.dts
diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts new file mode 100644 index 0000000..dde5d03 --- /dev/null +++ b/board/nvidia/dts/tegra2-seaboard.dts @@ -0,0 +1,36 @@ +/dts-v1/; + +/memreserve/ 0x1c000000 0x04000000; +/include/ ARCH_CPU_DTS + +/ { + model = "NVIDIA Seaboard"; + compatible = "nvidia,seaboard", "nvidia,tegra20"; + + chosen { + bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; + }; + + memory { + device_type = "memory"; + reg = < 0x00000000 0x40000000 >; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + sdhci@c8000400 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + }; + + sdhci@c8000600 { + support-8bit; + }; + + usb@c5000000 { + nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ + }; +};
Add a directory to hold device tree binding files, to permit easy review of this material in U-Boot patches.
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v4: - Add staging area for device tree bindings used in U-Boot
Changes in v5: - Update README to indicate that we will commit fdt documentation to U-Boot
doc/device-tree-bindings/README | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-) create mode 100644 doc/device-tree-bindings/README
diff --git a/doc/device-tree-bindings/README b/doc/device-tree-bindings/README new file mode 100644 index 0000000..2ea3439 --- /dev/null +++ b/doc/device-tree-bindings/README @@ -0,0 +1,17 @@ +Device Tree Bindings Staging Area +================================= + +This directory contains device tree bindings for U-Boot. + +These follow along with Linux kernel bindings, with a few additions. By +adding the files here, U-Boot patches can clearly show thees additions. +This makes it easier for device tree people to review these additions in +patches sent to the U-Boot mailing list. + +The intent IS to commit these files to U-Boot. Hopefully at some point +the files will be stored in another repo (shared with Linux) which is +brought in as needed. Changes here are intended to mirror changes in the +Linux Documentation/devicetree/bindings/ directory. + +sjg@chromium.org +17-Jan-12
This file is taken from the Linux mailing list.
Signed-off-by: Simon Glass sjg@chromium.org ---
doc/device-tree-bindings/usb/tegra-usb.txt | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) create mode 100644 doc/device-tree-bindings/usb/tegra-usb.txt
diff --git a/doc/device-tree-bindings/usb/tegra-usb.txt b/doc/device-tree-bindings/usb/tegra-usb.txt new file mode 100644 index 0000000..035d63d --- /dev/null +++ b/doc/device-tree-bindings/usb/tegra-usb.txt @@ -0,0 +1,13 @@ +Tegra SOC USB controllers + +The device node for a USB controller that is part of a Tegra +SOC is as described in the document "Open Firmware Recommended +Practice : Universal Serial Bus" with the following modifications +and additions : + +Required properties : + - compatible : Should be "nvidia,tegra20-ehci" for USB controllers + used in host mode. + - phy_type : Should be one of "ulpi" or "utmi". + - nvidia,vbus-gpio : If present, specifies a gpio that needs to be + activated for the bus to be powered.
This adds a property to indicate a port which can switch between host and device mode.
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v5: - Add dr_mode property to control host/device/otg mode - Add nvidia,has-legacy-mode property per review comments
doc/device-tree-bindings/usb/tegra-usb.txt | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/doc/device-tree-bindings/usb/tegra-usb.txt b/doc/device-tree-bindings/usb/tegra-usb.txt index 035d63d..b7174a3 100644 --- a/doc/device-tree-bindings/usb/tegra-usb.txt +++ b/doc/device-tree-bindings/usb/tegra-usb.txt @@ -11,3 +11,15 @@ Required properties : - phy_type : Should be one of "ulpi" or "utmi". - nvidia,vbus-gpio : If present, specifies a gpio that needs to be activated for the bus to be powered. + +Optional properties: + - dr_mode : dual role mode. Indicates the working mode for + nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral", + or "otg". Default to "host" if not defined for backward compatibility. + host means this is a host controller + peripheral means it is device controller + otg means it can operate as either ("on the go") + - nvidia,has-legacy-mode : boolean indicates whether this controller can + operate in legacy mode (as APX 2500 / 2600). In legacy mode some + registers are accessed through the APB_MISC base address instead of + the USB controller.
On 01/24/2012 04:21 PM, Simon Glass wrote:
This adds a property to indicate a port which can switch between host and device mode.
...
diff --git a/doc/device-tree-bindings/usb/tegra-usb.txt b/doc/device-tree-bindings/usb/tegra-usb.txt
...
+Optional properties:
...
- nvidia,has-legacy-mode : boolean indicates whether this controller can
- operate in legacy mode (as APX 2500 / 2600). In legacy mode some
- registers are accessed through the APB_MISC base address instead of
- the USB controller.
I was hoping to represent this as a different compatible value, in the same way as one of Tegra's I2C controllers is, eg. nvidia,tegra20-ehci and nvidia,tegra20-ehci-legacy.
However, I suppose representing this using a property is OK too.
Either way, can you please also push this patch to the Linux kernel (and the associated changes to tegra*.dtsi) in order to run it past the other Tegra maintainers before committing to it within U-Boot.
Thanks.
Hi Stephen,
On Thu, Feb 2, 2012 at 1:55 PM, Stephen Warren swarren@nvidia.com wrote:
On 01/24/2012 04:21 PM, Simon Glass wrote:
This adds a property to indicate a port which can switch between host and device mode.
...
diff --git a/doc/device-tree-bindings/usb/tegra-usb.txt b/doc/device-tree-bindings/usb/tegra-usb.txt
...
+Optional properties:
...
- - nvidia,has-legacy-mode : boolean indicates whether this controller can
- operate in legacy mode (as APX 2500 / 2600). In legacy mode some
- registers are accessed through the APB_MISC base address instead of
- the USB controller.
I was hoping to represent this as a different compatible value, in the same way as one of Tegra's I2C controllers is, eg. nvidia,tegra20-ehci and nvidia,tegra20-ehci-legacy.
However, I suppose representing this using a property is OK too.
I prefer this because this is a legacy issue, and I feel that creating a different compatible node when no one actually uses legacy mode is an unnecessary complexity.
Either way, can you please also push this patch to the Linux kernel (and the associated changes to tegra*.dtsi) in order to run it past the other Tegra maintainers before committing to it within U-Boot.
OK I have done this.
Thanks.
-- nvpublic
Regards, Simon
This adds a basic binding for the oscillator and peripheral clocks. The second cell is the clock number, defined as the bit number within the clock enable register if the peripheral clock.
This uses the RFC clock bindings from Grant Likely so may change later:
https://lkml.org/lkml/2011/12/12/498
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v4: - Add clock bindings for Tegra2x
arch/arm/dts/tegra20.dtsi | 27 ++++++++++++ doc/device-tree-bindings/clock/tegra-periphclk | 51 ++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 0 deletions(-) create mode 100644 doc/device-tree-bindings/clock/tegra-periphclk
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index a9a98ea..ec75747 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -4,6 +4,33 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&intc>;
+ clocks = <&osc_clk>; + clock-names = "osc_clk"; + clock-ranges; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + + /* The frequency of this clock is board-specific */ + osc_clk: oscclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + /* + * This node provides clocks to all peripherals. We don't + * enumerate the clock names for now since there are no + * users of this information. + */ + periph_clk: periphclk { + compatible = "tegra,periphclk"; + #clock-cells = <1>; + clocks = <&osc_clk>; + reg = <0x60006000 400>; + }; + }; + intc: interrupt-controller@50041000 { compatible = "nvidia,tegra20-gic"; interrupt-controller; diff --git a/doc/device-tree-bindings/clock/tegra-periphclk b/doc/device-tree-bindings/clock/tegra-periphclk new file mode 100644 index 0000000..8d21e4d --- /dev/null +++ b/doc/device-tree-bindings/clock/tegra-periphclk @@ -0,0 +1,51 @@ +Clock controllers + +(there isn't yet a binding in Linux, so this describes what is in U-Boot) + +The device node for a clock controller is as described in the document +"Open Firmware Recommended Practice : Universal Serial Bus" with the +following modifications and additions : + +This is based on Grant Likely's proposed patch for clock bindings. + +Required properties : + - compatible : Should be "tegra,periphclk" for peripheral clock controller + - clocks : Should contain a single phandle pointing to the oscillator clock + +Peripherals which refer to a clock should have a property called "clocks" with +two cells: phandle of the peripheral clock and the clock ID number (which +is the bit number in the peripheral clock controller enable register numbered +from 0). + +Example: + +clocks { + #address-cells = <1>; + #size-cells = <1>; + + /* The frequency of this clock is board-specific */ + osc_clk: oscclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + /* + * This node provides clocks to all peripherals. We don't + * enumerate the clock names for now since there are no + * users of this information. + */ + periph_clk: periphclk { + compatible = "tegra,periphclk"; + #clock-cells = <1>; + clocks = <&osc_clk>; + reg = <0x60006000 400>; + }; +}; + +usb@c5004000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5004000 0x4000>; + interrupts = < 53 >; + phy_type = "ulpi"; + clocks = <&periph_clk 58>; // PERIPH_ID_USB2 +};
This adds clock references to the USB part of the device tree for U-Boot.
The USB timing information may vary between boards sometimes, but for now we hard-code it in C. This is because all current T2x boards use the same values, we will deal with T3x later and we first need to agree on the format for this timing information in the fdt and may in fact decide that it has no place there.
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v5: - Add dr_mode property to control host/device/otg mode - Add nvidia,has-legacy-mode property per review comments - Change device tree comment style from // to /* */
arch/arm/dts/tegra20.dtsi | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index ec75747..b2e3a40 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -176,6 +176,9 @@ reg = <0xc5000000 0x4000>; interrupts = < 52 >; phy_type = "utmi"; + clocks = <&periph_clk 22>; /* PERIPH_ID_USBD */ + dr_mode = "otg"; + nvidia,has-legacy-mode; };
usb@c5004000 { @@ -183,6 +186,8 @@ reg = <0xc5004000 0x4000>; interrupts = < 53 >; phy_type = "ulpi"; + clocks = <&periph_clk 58>; /* PERIPH_ID_USB2 */ + dr_mode = "host"; };
usb@c5008000 { @@ -190,6 +195,8 @@ reg = <0xc5008000 0x4000>; interrupts = < 129 >; phy_type = "utmi"; + clocks = <&periph_clk 59>; /* PERIPH_ID_USB3 */ + dr_mode = "otg"; };
};
On 01/24/2012 04:21 PM, Simon Glass wrote:
This adds clock references to the USB part of the device tree for U-Boot.
The USB timing information may vary between boards sometimes, but for now we hard-code it in C. This is because all current T2x boards use the same values, we will deal with T3x later and we first need to agree on the format for this timing information in the fdt and may in fact decide that it has no place there.
The patch below does more than what's covered by this description...
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v5:
- Add dr_mode property to control host/device/otg mode
- Add nvidia,has-legacy-mode property per review comments
- Change device tree comment style from // to /* */
arch/arm/dts/tegra20.dtsi | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index ec75747..b2e3a40 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -176,6 +176,9 @@ reg = <0xc5000000 0x4000>; interrupts = < 52 >; phy_type = "utmi";
clocks = <&periph_clk 22>; /* PERIPH_ID_USBD */dr_mode = "otg";
The dr_mode value is board-specific, so should be in tegra-seaboard.dts not tegra20.dtsi.
For example, on true Seaboard, perhaps USB3 could operate in "otg" mode since it's an external port, whereas on Springbank, USB3 is hard-wired to a keyboard controller, so should be marked "host" mode only.
Related, I assume that any port marked as "otg" needs to have a VBUS GPIO defined so that it can be turned off in device mode, or is VBUS controlled by some other mechanism in some cases? Given that, I /think/ you can't actually mark USB3 as "otg" or "device" on Seaboard since there's no VBUS GPIO.
Hi Stephen,
On Thu, Feb 2, 2012 at 2:07 PM, Stephen Warren swarren@nvidia.com wrote:
On 01/24/2012 04:21 PM, Simon Glass wrote:
This adds clock references to the USB part of the device tree for U-Boot.
The USB timing information may vary between boards sometimes, but for now we hard-code it in C. This is because all current T2x boards use the same values, we will deal with T3x later and we first need to agree on the format for this timing information in the fdt and may in fact decide that it has no place there.
The patch below does more than what's covered by this description...
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v5:
- Add dr_mode property to control host/device/otg mode
- Add nvidia,has-legacy-mode property per review comments
- Change device tree comment style from // to /* */
arch/arm/dts/tegra20.dtsi | Â Â 7 +++++++ Â 1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index ec75747..b2e3a40 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -176,6 +176,9 @@ Â Â Â Â Â Â Â reg = <0xc5000000 0x4000>; Â Â Â Â Â Â Â interrupts = < 52 >; Â Â Â Â Â Â Â phy_type = "utmi";
- clocks = <&periph_clk 22>; Â Â Â /* PERIPH_ID_USBD */
- dr_mode = "otg";
The dr_mode value is board-specific, so should be in tegra-seaboard.dts not tegra20.dtsi.
Done
For example, on true Seaboard, perhaps USB3 could operate in "otg" mode since it's an external port, whereas on Springbank, USB3 is hard-wired to a keyboard controller, so should be marked "host" mode only.
OK. I was seeing it as an SOC capability rather than a board feature.
Related, I assume that any port marked as "otg" needs to have a VBUS GPIO defined so that it can be turned off in device mode, or is VBUS controlled by some other mechanism in some cases? Given that, I /think/ you can't actually mark USB3 as "otg" or "device" on Seaboard since there's no VBUS GPIO.
Done. In principle VBUS can be controlled by a bit in the peripheral controller driving out a VBUS enable line, but that's not how it works in this case.
-- nvpublic
Regards, Simon
We set up two USB ports, one of which can be host or device. For some reason the kernel version does enable both ports.
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v2: - Remove 0x from fdt aliases - Use "okay" instead of "ok" for fdt node status
Changes in v3: - Disable USB2 which is not used on Seaboard - Fix device tree indenting with tabs instead of spaces - Remove "okay" from nodes since this is the default anyway
Changes in v5: - Remove support-host-mode property
board/nvidia/dts/tegra2-seaboard.dts | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts index dde5d03..f53690f 100644 --- a/board/nvidia/dts/tegra2-seaboard.dts +++ b/board/nvidia/dts/tegra2-seaboard.dts @@ -11,6 +11,12 @@ bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; };
+ aliases { + /* This defines the order of our USB ports */ + usb0 = "/usb@c5008000"; + usb1 = "/usb@c5000000"; + }; + memory { device_type = "memory"; reg = < 0x00000000 0x40000000 >; @@ -33,4 +39,8 @@ usb@c5000000 { nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ }; + + usb@c5004000 { + status = "disabled"; + }; };
CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the txfilltuning field in the EHCI controller on reset.
Signed-off-by: Simon Glass sjg@chromium.org Acked-by: Remy Bohmer linux@bohmer.net ---
README | 3 +++ drivers/usb/host/ehci-hcd.c | 7 +++++++ drivers/usb/host/ehci.h | 6 +++++- 3 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/README b/README index 9d713e8..7adf7c7 100644 --- a/README +++ b/README @@ -1135,6 +1135,9 @@ The following options need to be configured: May be defined to allow interrupt polling instead of using asynchronous interrupts
+ CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the + txfilltuning field in the EHCI controller on reset. + - USB Device: Define the below if you wish to use the USB console. Once firmware is rebuilt from a serial console issue the diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 3f7bc2c..d893b2a 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -259,6 +259,13 @@ static int ehci_reset(void) #endif ehci_writel(reg_ptr, tmp); } + +#ifdef CONFIG_USB_EHCI_TXFIFO_THRESH + cmd = ehci_readl(&hcor->or_txfilltuning); + cmd &= ~TXFIFO_THRESH(0x3f); + cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH); + ehci_writel(&hcor->or_txfilltuning, cmd); +#endif out: return ret; } diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 3d0ad0c..cc00ce4 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -80,7 +80,11 @@ struct ehci_hcor { uint32_t or_ctrldssegment; uint32_t or_periodiclistbase; uint32_t or_asynclistaddr; - uint32_t _reserved_[9]; + uint32_t _reserved_0_; + uint32_t or_burstsize; + uint32_t or_txfilltuning; +#define TXFIFO_THRESH(p) ((p & 0x3f) << 16) + uint32_t _reserved_1_[6]; uint32_t or_configflag; #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
A common requirement is to find the clock ID for a peripheral. This is the second cell of the 'clocks' property (the first being the phandle itself).
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v4: - Add fdtdec function to return peripheral ID
include/fdtdec.h | 13 +++++++++++++ lib/fdtdec.c | 13 +++++++++++++ 2 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h index 6c0a2d1..f3115a6 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -272,3 +272,16 @@ int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name, * @return 0 if all ok or gpio was FDT_GPIO_NONE; -1 on error */ int fdtdec_setup_gpio(struct fdt_gpio_state *gpio); + +/** + * Decode a peripheral ID from a device tree node. This may be a temporary + * function depending on what happens with clocks in the Linux fdt. + * + * This works by looking up the peripheral's 'clocks' node and reading out + * the second cell, which is the clock number / peripheral ID. + * + * @param blob FDT blob to use + * @param node Node to look at + * @return + */ +int fdtdec_decode_periph_id(const void *blob, int node); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index c748cac..f999ed0 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -415,3 +415,16 @@ int fdtdec_setup_gpio(struct fdt_gpio_state *gpio) return -1; return 0; } + +int fdtdec_decode_periph_id(const void *blob, int node) +{ + u32 cell[2]; + int err; + + err = fdtdec_get_int_array(blob, node, "clocks", cell, + ARRAY_SIZE(cell)); + if (err) + return -1; + + return cell[1]; +}
This adds basic support for the Tegra2 USB controller. Board files should call board_usb_init() to set things up.
Configuration is performed through the FDT, with aliases used to set the order of the ports, like this fragment:
aliases { /* This defines the order of our USB ports */ usb0 = "/usb@0xc5008000"; usb1 = "/usb@0xc5000000"; };
drivers/usb/host files ONLY: Acked-by: Remy Bohmer linux@bohmer.net Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v2: - Decode USB VBUS GPIO from the fdt - Decode phy type differently (to match new kernel fdt) - Improve debug() printouts in case of failure to init USB - Remove non-fdt operation of USB, since it is not needed - Rename params to timing - Rename tegra20-usb to tegra20-ehcui (to match new kernel fdt) - Store entire fdt config in port list, not just register pointer
Changes in v3: - Remove usbparams properties from fdt and moved them to C code
Changes in v4: - Use peripheral clock node to obtain peripheral ID - Use updated fdtdec alias functiona to get USB aliases
Changes in v5: - Add additional debugging to report active USB ports - Allow any port to operate in otg mode - Correct PTS_MASK value to be unsigned - Implement new device tree properties - Remove checking of peripheral ID and try to use only device tree - Report error if phy clock does not start up
arch/arm/cpu/armv7/tegra2/Makefile | 4 +- arch/arm/cpu/armv7/tegra2/usb.c | 460 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra2/tegra2.h | 2 + arch/arm/include/asm/arch-tegra2/usb.h | 252 ++++++++++++++++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-tegra.c | 62 ++++ include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 8 files changed, 782 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/usb.c create mode 100644 arch/arm/include/asm/arch-tegra2/usb.h create mode 100644 drivers/usb/host/ehci-tegra.c
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index f668a81..e9ac6c9 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -33,8 +33,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o -COBJS := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +COBJS-y := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
+COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/tegra2/usb.c b/arch/arm/cpu/armv7/tegra2/usb.c new file mode 100644 index 0000000..3527b8e --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/usb.c @@ -0,0 +1,460 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/uart.h> +#include <asm/arch/usb.h> +#include <libfdt.h> +#include <fdtdec.h> + +enum { + USB_PORTS_MAX = 4, /* Maximum ports we allow */ +}; + +/* Parameters we need for USB */ +enum { + PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ + PARAM_DIVM, /* PLL INPUT DIVIDER */ + PARAM_DIVP, /* POST DIVIDER (2^N) */ + PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ + PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ + PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ + PARAM_STABLE_COUNT, /* PLL-U STABLE count */ + PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ + PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ + PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ + PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ + + PARAM_COUNT +}; + +/* Possible port types (dual role mode) */ +enum dr_mode { + DR_MODE_NONE = 0, + DR_MODE_HOST, /* supports host operation */ + DR_MODE_DEVICE, /* supports device operation */ + DR_MODE_OTG, /* supports both */ +}; + +/* Information about a USB port */ +struct fdt_usb { + struct usb_ctlr *reg; /* address of registers in physical memory */ + unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ + unsigned enabled:1; /* 1 to enable, 0 to disable */ + unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ + enum dr_mode dr_mode; /* dual role mode */ + enum periph_id periph_id;/* peripheral id */ + struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ +}; + +static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ +static unsigned port_count; /* Number of available ports */ +static int port_current; /* Current port (-1 = none) */ + +/* + * This table has USB timing parameters for each Oscillator frequency we + * support. There are four sets of values: + * + * 1. PLLU configuration information (reference clock is osc/clk_m and + * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). + * + * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz + * ---------------------------------------------------------------------- + * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) + * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) + * Filter frequency (MHz) 1 4.8 6 2 + * CPCON 1100b 0011b 1100b 1100b + * LFCON0 0 0 0 0 + * + * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: + * + * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz + * --------------------------------------------------------------------------- + * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) + * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) + * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) + * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) + * + * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and + * SessEnd. Each of these signals have their own debouncer and for each of + * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or + * BIAS_DEBOUNCE_B). + * + * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: + * 0xffff -> No debouncing at all + * <n> ms = <n> *1000 / (1/19.2MHz) / 4 + * + * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: + * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 + * + * We need to use only DebounceA for BOOTROM. We don't need the DebounceB + * values, so we can keep those to default. + * + * 4. The 20 microsecond delay after bias cell operation. + */ +static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { + /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ + { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, + { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, + { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, + { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } +}; + +/* UTMIP Idle Wait Delay */ +static const u8 utmip_idle_wait_delay = 17; + +/* UTMIP Elastic limit */ +static const u8 utmip_elastic_limit = 16; + +/* UTMIP High Speed Sync Start Delay */ +static const u8 utmip_hs_sync_start_delay = 9; + +/* Put the port into host mode (this only works for OTG ports) */ +static void set_host_mode(struct fdt_usb *config) +{ + if (config->dr_mode == DR_MODE_OTG) { + /* Check whether remote host from USB1 is driving VBus */ + if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS) + return; + + /* + * If not driving, we set the GPIO to enable VBUS. We assume + * that the pinmux is set up correctly for this. + */ + if (fdt_gpio_isvalid(&config->vbus_gpio)) { + fdtdec_setup_gpio(&config->vbus_gpio); + gpio_direction_output(config->vbus_gpio.gpio, 1); + debug("set_host_mode: GPIO %d high\n", + config->vbus_gpio.gpio); + } + } +} + +void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) +{ + /* Reset the USB controller with 2us delay */ + reset_periph(config->periph_id, 2); + + /* + * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under + * base address + */ + if (config->has_legacy_mode) + setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); + + /* Put UTMIP1/3 in reset */ + setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); + + /* Enable the UTMIP PHY */ + if (config->utmi) + setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); + + /* + * TODO: where do we take the USB1 out of reset? The old code would + * take USB3 out of reset, but not USB1. This code doesn't do either. + */ +} + +/* set up the USB controller with the parameters provided */ +static int init_usb_controller(struct fdt_usb *config, + struct usb_ctlr *usbctlr, const u32 timing[]) +{ + u32 val; + int loop_count; + + clock_enable(config->periph_id); + + /* Reset the usb controller */ + usbf_reset_controller(config, usbctlr); + + /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ + clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); + + /* Follow the crystal clock disable by >100ns delay */ + udelay(1); + + /* + * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP + * mux must be switched to actually use a_sess_vld threshold. + */ + if (fdt_gpio_isvalid(&config->vbus_gpio)) { + clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, + VBUS_SENSE_CTL_MASK, + VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); + } + + /* + * PLL Delay CONFIGURATION settings. The following parameters control + * the bring up of the plls. + */ + val = readl(&usbctlr->utmip_misc_cfg1); + clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, + timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT); + clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, + timing[PARAM_ACTIVE_DELAY_COUNT] << + UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); + writel(val, &usbctlr->utmip_misc_cfg1); + + /* Set PLL enable delay count and crystal frequency count */ + val = readl(&usbctlr->utmip_pll_cfg1); + clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, + timing[PARAM_ENABLE_DELAY_COUNT] << + UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); + clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, + timing[PARAM_XTAL_FREQ_COUNT] << + UTMIP_XTAL_FREQ_COUNT_SHIFT); + writel(val, &usbctlr->utmip_pll_cfg1); + + /* Setting the tracking length time */ + clrsetbits_le32(&usbctlr->utmip_bias_cfg1, + UTMIP_BIAS_PDTRK_COUNT_MASK, + timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); + + /* Program debounce time for VBUS to become valid */ + clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, + UTMIP_DEBOUNCE_CFG0_MASK, + timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); + + setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); + + /* Disable battery charge enabling bit */ + setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); + + clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); + setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); + + /* + * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT + * Setting these fields, together with default values of the + * other fields, results in programming the registers below as + * follows: + * UTMIP_HSRX_CFG0 = 0x9168c000 + * UTMIP_HSRX_CFG1 = 0x13 + */ + + /* Set PLL enable delay count and Crystal frequency count */ + val = readl(&usbctlr->utmip_hsrx_cfg0); + clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, + utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); + clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, + utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); + writel(val, &usbctlr->utmip_hsrx_cfg0); + + /* Configure the UTMIP_HS_SYNC_START_DLY */ + clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, + UTMIP_HS_SYNC_START_DLY_MASK, + utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); + + /* Preceed the crystal clock disable by >100ns delay. */ + udelay(1); + + /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ + setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); + + /* Finished the per-controller init. */ + + /* De-assert UTMIP_RESET to bring out of reset. */ + clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); + + /* Wait for the phy clock to become valid in 100 ms */ + for (loop_count = 100000; loop_count != 0; loop_count--) { + if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) + break; + udelay(1); + } + if (loop_count == 100000) + return -1; + + return 0; +} + +static void power_up_port(struct usb_ctlr *usbctlr) +{ + /* Deassert power down state */ + clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | + UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); + clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | + UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); +} + +static void config_clock(const u32 timing[]) +{ + clock_start_pll(CLOCK_ID_USB, + timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], + timing[PARAM_CPCON], timing[PARAM_LFCON]); +} + +/** + * Add a new USB port to the list of available ports. + * + * @param config USB port configuration + * @return 0 if ok, -1 if error (too many ports) + */ +static int add_port(struct fdt_usb *config, const u32 timing[]) +{ + struct usb_ctlr *usbctlr = config->reg; + + if (port_count == USB_PORTS_MAX) { + debug("tegrausb: Cannot register more than %d ports\n", + USB_PORTS_MAX); + return -1; + } + if (init_usb_controller(config, usbctlr, timing)) { + debug("tegrausb: Cannot init port\n"); + return -1; + } + if (config->utmi) { + /* Disable ICUSB FS/LS transceiver */ + clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); + + /* Select UTMI parallel interface */ + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, + PTS_UTMI << PTS_SHIFT); + clrbits_le32(&usbctlr->port_sc1, STS); + power_up_port(usbctlr); + } + port[port_count++] = *config; + + return 0; +} + +int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor) +{ + struct usb_ctlr *usbctlr; + + if (portnum >= port_count) + return -1; + tegrausb_stop_port(); + set_host_mode(&port[portnum]); + + usbctlr = port[portnum].reg; + *hccr = (u32)&usbctlr->cap_length; + *hcor = (u32)&usbctlr->usb_cmd; + port_current = portnum; + return 0; +} + +int tegrausb_stop_port(void) +{ + struct usb_ctlr *usbctlr; + + if (port_current == -1) + return -1; + + usbctlr = port[port_current].reg; + + /* Stop controller */ + writel(0, &usbctlr->usb_cmd); + udelay(1000); + + /* Initiate controller reset */ + writel(2, &usbctlr->usb_cmd); + udelay(1000); + port_current = -1; + return 0; +} + +int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz, + struct fdt_usb *config) +{ + const char *phy, *mode; + + config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode) { + if (0 == strcmp(mode, "host")) + config->dr_mode = DR_MODE_HOST; + else if (0 == strcmp(mode, "peripheral")) + config->dr_mode = DR_MODE_DEVICE; + else if (0 == strcmp(mode, "otg")) + config->dr_mode = DR_MODE_OTG; + else { + debug("%s: Cannot decode dr_mode '%s'\n", __func__, + mode); + return -FDT_ERR_NOTFOUND; + } + } else { + config->dr_mode = DR_MODE_HOST; + } + + phy = fdt_getprop(blob, node, "phy_type", NULL); + config->utmi = phy && 0 == strcmp("utmi", phy); + config->enabled = fdtdec_get_is_enabled(blob, node); + config->has_legacy_mode = fdtdec_get_bool(blob, node, + "nvidia,has-legacy-mode"); + config->periph_id = fdtdec_decode_periph_id(blob, node); + if (config->periph_id == -1) { + debug("%s: Missing peripheral ID\n", __func__); + return -FDT_ERR_NOTFOUND; + } + fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio); + debug("enabled=%d, legacy_mode=%d, utmi=%d, periph_id=%d, vbus=%d, " + "dr_mode=%d\n", config->enabled, config->has_legacy_mode, + config->utmi, config->periph_id, config->vbus_gpio.gpio, + config->dr_mode); + + return 0; +} + +int board_usb_init(const void *blob) +{ + struct fdt_usb config; + unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC); + enum clock_osc_freq freq; + int node_list[USB_PORTS_MAX]; + int node, count, i; + + /* Set up the USB clocks correctly based on our oscillator frequency */ + freq = clock_get_osc_freq(); + config_clock(usb_pll[freq]); + + /* count may return <0 on error */ + count = fdtdec_find_aliases_for_id(blob, "usb", + COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX); + for (i = 0; i < count; i++) { + debug("USB %d: ", i); + node = node_list[i]; + if (!node) + continue; + if (fdt_decode_usb(blob, node, osc_freq, &config)) { + debug("Cannot decode USB node %s\n", + fdt_get_name(blob, node, NULL)); + return -1; + } + + if (add_port(&config, usb_pll[freq])) + return -1; + set_host_mode(&config); + } + port_current = -1; + + return 0; +} diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h index 8941443..baae2eb 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra2.h +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h @@ -41,6 +41,8 @@ #define TEGRA2_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) #define NV_PA_PMC_BASE 0x7000E400 #define NV_PA_CSITE_BASE 0x70040000 +#define TEGRA_USB1_BASE 0xC5000000 +#define TEGRA_USB3_BASE 0xC5008000
#define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE #define LOW_LEVEL_SRAM_STACK 0x4000FFFC diff --git a/arch/arm/include/asm/arch-tegra2/usb.h b/arch/arm/include/asm/arch-tegra2/usb.h new file mode 100644 index 0000000..638033b --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/usb.h @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA_USB_H_ +#define _TEGRA_USB_H_ + + +/* USB Controller (USBx_CONTROLLER_) regs */ +struct usb_ctlr { + /* 0x000 */ + uint id; + uint reserved0; + uint host; + uint device; + + /* 0x010 */ + uint txbuf; + uint rxbuf; + uint reserved1[2]; + + /* 0x020 */ + uint reserved2[56]; + + /* 0x100 */ + u16 cap_length; + u16 hci_version; + uint hcs_params; + uint hcc_params; + uint reserved3[5]; + + /* 0x120 */ + uint dci_version; + uint dcc_params; + uint reserved4[6]; + + /* 0x140 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x150 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint async_tt_sts; + + /* 0x160 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; /* is this port_sc1 on some controllers? */ + uint icusb_ctrl; + + /* 0x170 */ + uint ulpi_viewport; + uint reserved7; + uint endpt_nak; + uint endpt_nak_enable; + + /* 0x180 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x1a0 */ + uint reserved9; + uint otgsc; + uint usb_mode; + uint endpt_setup_stat; + + /* 0x1b0 */ + uint reserved10[20]; + + /* 0x200 */ + uint reserved11[0x80]; + + /* 0x400 */ + uint susp_ctrl; + uint phy_vbus_sensors; + uint phy_vbus_wakeup_id; + uint phy_alt_vbus_sys; + + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[3]; + + /* 0x420 */ + uint reserved13[56]; + + /* 0x500 */ + uint reserved14[64 * 3]; + + /* 0x800 */ + uint utmip_pll_cfg0; + uint utmip_pll_cfg1; + uint utmip_xcvr_cfg0; + uint utmip_bias_cfg0; + + /* 0x810 */ + uint utmip_hsrx_cfg0; + uint utmip_hsrx_cfg1; + uint utmip_fslsrx_cfg0; + uint utmip_fslsrx_cfg1; + + /* 0x820 */ + uint utmip_tx_cfg0; + uint utmip_misc_cfg0; + uint utmip_misc_cfg1; + uint utmip_debounce_cfg0; + + /* 0x830 */ + uint utmip_bat_chrg_cfg0; + uint utmip_spare_cfg0; + uint utmip_xcvr_cfg1; + uint utmip_bias_cfg1; +}; + + +/* USB1_LEGACY_CTRL */ +#define USB1_NO_LEGACY_MODE 1 + +#define VBUS_SENSE_CTL_SHIFT 1 +#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) +#define VBUS_SENSE_CTL_VBUS_WAKEUP 0 +#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 +#define VBUS_SENSE_CTL_AB_SESS_VLD 2 +#define VBUS_SENSE_CTL_A_SESS_VLD 3 + +/* USBx_IF_USB_SUSP_CTRL_0 */ +#define UTMIP_PHY_ENB (1 << 12) +#define UTMIP_RESET (1 << 11) +#define USB_PHY_CLK_VALID (1 << 7) + +/* USBx_UTMIP_MISC_CFG1 */ +#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 +#define UTMIP_PLLU_STABLE_COUNT_MASK \ + (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) +#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 +#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ + (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) +#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) + +/* USBx_UTMIP_PLL_CFG1_0 */ +#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 +#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ + (0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) +#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 +#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff + +/* USBx_UTMIP_BIAS_CFG1_0 */ +#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 +#define UTMIP_BIAS_PDTRK_COUNT_MASK \ + (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) + +#define UTMIP_DEBOUNCE_CFG0_SHIFT 0 +#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff + +/* USBx_UTMIP_TX_CFG0_0 */ +#define UTMIP_FS_PREAMBLE_J (1 << 19) + +/* USBx_UTMIP_BAT_CHRG_CFG0_0 */ +#define UTMIP_PD_CHRG 1 + +/* USBx_UTMIP_XCVR_CFG0_0 */ +#define UTMIP_XCVR_LSBIAS_SE (1 << 21) + +/* USBx_UTMIP_SPARE_CFG0_0 */ +#define FUSE_SETUP_SEL (1 << 3) + +/* USBx_UTMIP_HSRX_CFG0_0 */ +#define UTMIP_IDLE_WAIT_SHIFT 15 +#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) +#define UTMIP_ELASTIC_LIMIT_SHIFT 10 +#define UTMIP_ELASTIC_LIMIT_MASK \ + (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) + +/* USBx_UTMIP_HSRX_CFG0_1 */ +#define UTMIP_HS_SYNC_START_DLY_SHIFT 1 +#define UTMIP_HS_SYNC_START_DLY_MASK \ + (0xf << UTMIP_HS_SYNC_START_DLY_SHIFT) + +/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ +#define IC_ENB1 (1 << 3) + +/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ +#define PTS_SHIFT 30 +#define PTS_MASK (3U << PTS_SHIFT) +#define PTS_UTMI 0 +#define PTS_RESERVED 1 +#define PTS_ULP 2 +#define PTS_ICUSB_SER 3 + +#define STS (1 << 29) + +/* USBx_UTMIP_XCVR_CFG0_0 */ +#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) +#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) +#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) + +/* USBx_UTMIP_XCVR_CFG1_0 */ +#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) +#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) + +/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ +#define VBUS_VLD_STS (1 << 26) + + +/* Change the USB host port into host mode */ +void usb_set_host_mode(void); + +/* Setup USB on the board */ +int board_usb_init(const void *blob); + +/** + * Start up the given port number (ports are numbered from 0 on each board). + * This returns values for the appropriate hccr and hcor addresses to use for + * USB EHCI operations. + * + * @param portnum port number to start + * @param hccr returns start address of EHCI HCCR registers + * @param hcor returns start address of EHCI HCOR registers + * @return 0 if ok, -1 on error (generally invalid port number) + */ +int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor); + +/** + * Stop the current port + * + * @return 0 if ok, -1 if no port was active + */ +int tegrausb_stop_port(void); + +#endif /* _TEGRA_USB_H_ */ diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 77e217f..a11cebb 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -47,6 +47,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o +COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
COBJS := $(COBJS-y) diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c new file mode 100644 index 0000000..a7e105b --- /dev/null +++ b/drivers/usb/host/ehci-tegra.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2009 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <usb.h> + +#include "ehci.h" +#include "ehci-core.h" + +#include <asm/errno.h> +#include <asm/arch/usb.h> + + +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int ehci_hcd_init(void) +{ + u32 our_hccr, our_hcor; + + /* + * Select the first port, as we don't have a way of selecting others + * yet + */ + if (tegrausb_start_port(0, &our_hccr, &our_hcor)) + return -1; + + hccr = (struct ehci_hccr *)our_hccr; + hcor = (struct ehci_hcor *)our_hcor; + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(void) +{ + tegrausb_stop_port(); + return 0; +} diff --git a/include/fdtdec.h b/include/fdtdec.h index f3115a6..bd2222c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -57,6 +57,7 @@ struct fdt_memory { */ enum fdt_compat_id { COMPAT_UNKNOWN, + COMPAT_NVIDIA_TEGRA20_USB, /* Tegra2 USB port */
COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index f999ed0..7260c73 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -37,6 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; #define COMPAT(id, name) name static const char * const compat_names[COMPAT_COUNT] = { COMPAT(UNKNOWN, "<none>"), + COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"), };
const char *fdtdec_get_compatible(enum fdt_compat_id id)
This adds basic USB support for port 0. The other port is not supported yet.
Tegra2 (SeaBoard) # usb start (Re)start USB... USB: Register 10011 NbrPorts 1 USB EHCI 1.00 scanning bus for devices... 5 USB Device(s) found scanning bus for storage devices... 1 Storage Device(s) found Tegra2 (SeaBoard) # ext2load usb 0:3 10000000 /boot/vmlinuz Loading file "/boot/vmlinuz" from usb device 0:3 (ROOT-A) 2932976 bytes read
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v2: - Add setting of pinmux for USB VBUS GPIO
Changes in v5: - Put pinmux setting into a board-specific function
board/nvidia/common/board.c | 12 ++++++++++++ board/nvidia/common/board.h | 6 ++++++ board/nvidia/seaboard/seaboard.c | 6 ++++++ 3 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index e8253a0..72d8630 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -33,6 +33,7 @@ #include <asm/arch/pinmux.h> #include <asm/arch/uart.h> #include <spi.h> +#include <asm/arch/usb.h> #include "board.h"
DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +51,12 @@ int timer_init(void) return 0; }
+void __pin_mux_usb(void) +{ +} + +void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb"))); + /* * Routine: board_init * Description: Early hardware init. @@ -69,6 +76,11 @@ int board_init(void) /* boot param addr */ gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
+#ifdef CONFIG_USB_EHCI_TEGRA + pin_mux_usb(); + board_usb_init(gd->fdt_blob); +#endif + return 0; }
diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h index a638af2..09fb158 100644 --- a/board/nvidia/common/board.h +++ b/board/nvidia/common/board.h @@ -27,4 +27,10 @@ void gpio_config_uart(void); void gpio_early_init_uart(void);
+/* + * Set up any pin muxing needed for USB (for now, since fdt doesn't support + * it). Boards can overwrite the default fucction which does nothing. + */ +void pin_mux_usb(void); + #endif /* BOARD_H */ diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 9ab6825..94efb1e 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -90,3 +90,9 @@ int board_mmc_init(bd_t *bd) return 0; } #endif + +void pin_mux_usb(void) +{ + /* For USB's GPIO PD0. For now, since we have no pinmux in fdt */ + pinmux_tristate_disable(PINGRP_SLXK); +}
All Tegra2 boards should include tegra2-common. This adds the required USB config to that file.
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v5: - Add CONFIG_EHCI_DCACHE which is needed for dcache operation - Drop unused CONFIG_USB_EHCI_DATA_ALIGN option
include/configs/tegra2-common.h | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index e6f385f..266d0e5 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -84,6 +84,16 @@ #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200}
+/* + * This parameter affects a TXFILLTUNING field that controls how much data is + * sent to the latency fifo before it is sent to the wire. Without this + * parameter, the default (2) causes occasional Data Buffer Errors in OUT + * packets depending on the buffer address and size. + */ +#define CONFIG_USB_EHCI_TXFIFO_THRESH 10 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_EHCI_DCACHE + /* include default commands */ #include <config_cmd_default.h>
Seaboard has a top port which is USB host or device, and a side port which is host only.
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v2: - Remove unneeded CONFIG_TEGRA_USBx defines
include/configs/seaboard.h | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 261f952..b6d9f7a 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -72,4 +72,11 @@
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE #define CONFIG_ENV_OFFSET (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + #endif /* __CONFIG_H */
This switches Seaboard over to use FDT for run-time config instead of CONFIG options. USB is the only user at present.
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v3: - Drop Tegra USB alignment patch as we will deal with this another way
include/configs/seaboard.h | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index b6d9f7a..1dc775a 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -27,6 +27,11 @@ #include <asm/sizes.h> #include "tegra2-common.h"
+/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + /* High-level configuration options */ #define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M" #define V_PROMPT "Tegra2 (SeaBoard) # "
On 01/24/2012 04:21 PM, Simon Glass wrote:
This switches Seaboard over to use FDT for run-time config instead of CONFIG options. USB is the only user at present.
Signed-off-by: Simon Glass sjg@chromium.org
Aside from the issues I've just mentioned in my recent emails, and from needing to update to the clock binding we discussed on the Linux mailing lists, the whole series is:
Acked-by: Stephen Warren swarren@nvidia.com
Hi Stephen,
On Thu, Feb 2, 2012 at 2:17 PM, Stephen Warren swarren@nvidia.com wrote:
On 01/24/2012 04:21 PM, Simon Glass wrote:
This switches Seaboard over to use FDT for run-time config instead of CONFIG options. USB is the only user at present.
Signed-off-by: Simon Glass sjg@chromium.org
Aside from the issues I've just mentioned in my recent emails, and from needing to update to the clock binding we discussed on the Linux mailing lists, the whole series is:
Acked-by: Stephen Warren swarren@nvidia.com
Thanks - it would be nice to get this in since it is the first actual use of fdt in U-Boot.
I will resend the two patches that need changing as v6.
-- nvpublic
Regards, Simon
This series brings in the Linux kernel fdt file and provides a working USB driver for Tegra2 Seaboard.
(I have done this in one series since otherwise most of the fdt additions will just look like dead code.)
The driver requires CONFIG_OF_CONTROL and a device tree to operate.
Some enhancements to fdtdec are required to make this easier, and these are included in the series also. I have had to bring in basic GPIO support due to the request to put the USB VBUS into the fdt.
Since the kernel recently got a very minimal USB binding, I have started with that and extended it where appropriate.
Tegra likes to have cache-aligned buffers. I have dropped the patch which implements this since we will solve this problem by making callers align their buffers (as we did with MMC).
Hi,
what's the status of this patch/patchset?
Thanks M
Hi Marek,
On Sun, Feb 26, 2012 at 3:13 PM, Marek Vasut marex@denx.de wrote:
This series brings in the Linux kernel fdt file and provides a working USB driver for Tegra2 Seaboard.
(I have done this in one series since otherwise most of the fdt additions will just look like dead code.)
The driver requires CONFIG_OF_CONTROL and a device tree to operate.
Some enhancements to fdtdec are required to make this easier, and these are included in the series also. I have had to bring in basic GPIO support due to the request to put the USB VBUS into the fdt.
Since the kernel recently got a very minimal USB binding, I have started with that and extended it where appropriate.
Tegra likes to have cache-aligned buffers. I have dropped the patch which implements this since we will solve this problem by making callers align their buffers (as we did with MMC).
Hi,
what's the status of this patch/patchset?
Superceded, v6 is on its way in the next few days.
Thanks M
Regards, Simon
Hi,
On Sun, Feb 26, 2012 at 7:02 PM, Simon Glass sjg@chromium.org wrote:
Hi Marek,
On Sun, Feb 26, 2012 at 3:13 PM, Marek Vasut marex@denx.de wrote:
This series brings in the Linux kernel fdt file and provides a working USB driver for Tegra2 Seaboard.
(I have done this in one series since otherwise most of the fdt additions will just look like dead code.)
The driver requires CONFIG_OF_CONTROL and a device tree to operate.
Some enhancements to fdtdec are required to make this easier, and these are included in the series also. I have had to bring in basic GPIO support due to the request to put the USB VBUS into the fdt.
Since the kernel recently got a very minimal USB binding, I have started with that and extended it where appropriate.
Tegra likes to have cache-aligned buffers. I have dropped the patch which implements this since we will solve this problem by making callers align their buffers (as we did with MMC).
Hi,
what's the status of this patch/patchset?
Superceded, v6 is on its way in the next few days.
I am about to send v6. Due to the way things are organized, 6 of that patches have changed. I have also dropped the fdt alignment one. So I think it is safest to resend the whole 20-patch series again.
Regards, Simon
Thanks M
Regards, Simon
Hi,
On Sun, Feb 26, 2012 at 7:02 PM, Simon Glass sjg@chromium.org wrote:
Hi Marek,
On Sun, Feb 26, 2012 at 3:13 PM, Marek Vasut marex@denx.de wrote:
This series brings in the Linux kernel fdt file and provides a working USB driver for Tegra2 Seaboard.
(I have done this in one series since otherwise most of the fdt additions will just look like dead code.)
The driver requires CONFIG_OF_CONTROL and a device tree to operate.
Some enhancements to fdtdec are required to make this easier, and these are included in the series also. I have had to bring in basic GPIO support due to the request to put the USB VBUS into the fdt.
Since the kernel recently got a very minimal USB binding, I have started with that and extended it where appropriate.
Tegra likes to have cache-aligned buffers. I have dropped the patch which implements this since we will solve this problem by making callers align their buffers (as we did with MMC).
Hi,
what's the status of this patch/patchset?
Superceded, v6 is on its way in the next few days.
I am about to send v6. Due to the way things are organized, 6 of that patches have changed. I have also dropped the fdt alignment one. So I think it is safest to resend the whole 20-patch series again.
Regards, Simon
Please wait until wednesday with the submission until we sort out the usb maintainership and until the most significant USB changes find their way into mainline uboot.
Thanks in advance M
Marek/Simon,
-----Original Message----- From: Marek Vasut [mailto:marek.vasut@gmail.com] Sent: Monday, February 27, 2012 1:55 PM To: u-boot@lists.denx.de Cc: Simon Glass; Tom Warren Subject: Re: [U-Boot] [PATCH v5 0/18] tegra: Add fdt definitions and USB driver
Hi,
On Sun, Feb 26, 2012 at 7:02 PM, Simon Glass sjg@chromium.org wrote:
Hi Marek,
On Sun, Feb 26, 2012 at 3:13 PM, Marek Vasut marex@denx.de wrote:
This series brings in the Linux kernel fdt file and provides a working USB driver for Tegra2 Seaboard.
(I have done this in one series since otherwise most of the fdt additions will just look like dead code.)
The driver requires CONFIG_OF_CONTROL and a device tree to operate.
Some enhancements to fdtdec are required to make this easier, and these are included in the series also. I have had to bring in basic GPIO support due to the request to put the USB VBUS into the
fdt.
Since the kernel recently got a very minimal USB binding, I have started with that and extended it where appropriate.
Tegra likes to have cache-aligned buffers. I have dropped the patch which implements this since we will solve this problem by making callers align their buffers (as we did with MMC).
Hi,
what's the status of this patch/patchset?
Superceded, v6 is on its way in the next few days.
I am about to send v6. Due to the way things are organized, 6 of that patches have changed. I have also dropped the fdt alignment one. So I think it is safest to resend the whole 20-patch series again.
Regards, Simon
Please wait until wednesday with the submission until we sort out the usb maintainership and until the most significant USB changes find their way into mainline uboot.
For those that don't want to wait, I've applied this patch series to u-boot-tegra/test and pushed to denx.
Simon - seems to work fine - USB->NET dongle, USB mouse, and USB stick all detected OK, both directly and behind the hub on the USB->NET dongle (Asix 3-port hub w/Ethernet adapter).
I'll wait a couple of days for the reviews & USB issues to sort themselves out before doing a pull request to Albert for ARM, but I want to get this in so I can move forward with the other Tegra2 drivers (I2C, LCD, kbd, etc.) that depend on fdt/DT.
Tom
Hi Tom,
On Mon, Feb 27, 2012 at 1:44 PM, Tom Warren TWarren@nvidia.com wrote:
Marek/Simon,
-----Original Message----- From: Marek Vasut [mailto:marek.vasut@gmail.com] Sent: Monday, February 27, 2012 1:55 PM To: u-boot@lists.denx.de Cc: Simon Glass; Tom Warren Subject: Re: [U-Boot] [PATCH v5 0/18] tegra: Add fdt definitions and USB driver
Hi,
On Sun, Feb 26, 2012 at 7:02 PM, Simon Glass sjg@chromium.org wrote:
Hi Marek,
On Sun, Feb 26, 2012 at 3:13 PM, Marek Vasut marex@denx.de wrote:
This series brings in the Linux kernel fdt file and provides a working USB driver for Tegra2 Seaboard.
(I have done this in one series since otherwise most of the fdt additions will just look like dead code.)
The driver requires CONFIG_OF_CONTROL and a device tree to operate.
Some enhancements to fdtdec are required to make this easier, and these are included in the series also. I have had to bring in basic GPIO support due to the request to put the USB VBUS into the
fdt.
Since the kernel recently got a very minimal USB binding, I have started with that and extended it where appropriate.
Tegra likes to have cache-aligned buffers. I have dropped the patch which implements this since we will solve this problem by making callers align their buffers (as we did with MMC).
Hi,
what's the status of this patch/patchset?
Superceded, v6 is on its way in the next few days.
I am about to send v6. Due to the way things are organized, 6 of that patches have changed. I have also dropped the fdt alignment one. So I think it is safest to resend the whole 20-patch series again.
Regards, Simon
Please wait until wednesday with the submission until we sort out the usb maintainership and until the most significant USB changes find their way into mainline uboot.
For those that don't want to wait, I've applied this patch series to u-boot-tegra/test and pushed to denx.
Simon - seems to work fine - USB->NET dongle, USB mouse, and USB stick all detected OK, both directly and behind the hub on the USB->NET dongle (Asix 3-port hub w/Ethernet adapter).
OK thanks, good. Hoping that Puneet's alignment fixes can go in soon also.
I'll wait a couple of days for the reviews & USB issues to sort themselves out before doing a pull request to Albert for ARM, but I want to get this in so I can move forward with the other Tegra2 drivers (I2C, LCD, kbd, etc.) that depend on fdt/DT.
I will have to do an update to i2c sorry, due to Stephen's clock binding changes. Yes I know it is acked and ready, but it will not work now. Wil try to do that today. After that is warmboot - have you taken a look at that?
Regards, Simon
Tom
-- nvpublic
Thanks in advance M
participants (5)
-
Marek Vasut -
Marek Vasut -
Simon Glass -
Stephen Warren -
Tom Warren