[U-Boot] [PATCHv4 0/3] Add SPL support for SoCFPGA
From: Dinh Nguyen dinguyen@opensource.altera.com
Hello,
The following 3 patches are updates to SPL patches that Marek has already applied to his tree. I have split out the DDR driver patches into a separate patch series to make it more convenient to review.
Thanks,
Dinh Nguyen (3): arm: socfpga: spl: Add s_init stub arm: socfpga: spl: add board_init_f to SPL arm: socfpga: spl: update peripheral pll for dev kit
arch/arm/cpu/armv7/socfpga/spl.c | 29 +++++++++++++++++++++++++++++ board/altera/socfpga/pll_config.h | 2 +- board/altera/socfpga/socfpga.c | 2 ++ 3 files changed, 32 insertions(+), 1 deletion(-)
From: Dinh Nguyen dinguyen@opensource.altera.com
Add a stub s_init function in the board file. The reason why the stub function is needed is that most of the work is now being done in board_init_f(), there is no need for the SPL to do anything s_init(). However, since lowlevel_init() is still branching to s_init(), we need stub function for now, until lowlevel_init() morphs into s_init().
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- v4: add a more descriptive commit message v3: move the contents of s_init into board_init_f v2: remove redundant code that is already in arch_early_init_r --- board/altera/socfpga/socfpga.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/altera/socfpga/socfpga.c b/board/altera/socfpga/socfpga.c index 20d2216..a1dbc49 100644 --- a/board/altera/socfpga/socfpga.c +++ b/board/altera/socfpga/socfpga.c @@ -18,6 +18,8 @@
DECLARE_GLOBAL_DATA_PTR;
+void s_init(void) {} + /* * Miscellaneous platform dependent initialisations */
From: Dinh Nguyen dinguyen@opensource.altera.com
Remap SDRAM to 0x0, and clear OCRAM's ECC in board_init_f().
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com Reviewed-by: Marek Vasut marex@denx.de --- v4: remove CONFIG_SPL_BUILD and add a comment v3: Move the code from s_init to board_init_f --- arch/arm/cpu/armv7/socfpga/spl.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index d7cedad..f994658 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -6,6 +6,7 @@
#include <common.h> #include <asm/io.h> +#include <asm/pl310.h> #include <asm/u-boot.h> #include <asm/utils.h> #include <image.h> @@ -19,6 +20,9 @@
DECLARE_GLOBAL_DATA_PTR;
+static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + #define MAIN_VCO_BASE ( \ (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \ @@ -44,6 +48,31 @@ DECLARE_GLOBAL_DATA_PTR; CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \ )
+void board_init_f(ulong dummy) +{ + struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + unsigned long reg; + /* + * First C code to run. Clear fake OCRAM ECC first as SBE + * and DBE might triggered during power on + */ + reg = readl(&sysmgr_regs->eccgrp_ocram); + if (reg & SYSMGR_ECC_OCRAM_SERR) + writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, + &sysmgr_regs->eccgrp_ocram); + if (reg & SYSMGR_ECC_OCRAM_DERR) + writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, + &sysmgr_regs->eccgrp_ocram); + + memset(__bss_start, 0, __bss_end - __bss_start); + + /* Remap SDRAM to 0x0 */ + writel(0x1, &pl310->pl310_addr_filter_start); + + board_init_r(NULL, 0); +} + u32 spl_boot_device(void) { return BOOT_DEVICE_RAM;
From: Dinh Nguyen dinguyen@opensource.altera.com
"commit 0d13a0051b2c arm: socfpga: Sync Cyclone V DK PLL configuration" mistakenly changed CONFIG_HPS_MAINPLLGRP_VCO_NUMER to 39, the correct value should be 79.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- board/altera/socfpga/pll_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h index 8130fa4..7cd25df 100644 --- a/board/altera/socfpga/pll_config.h +++ b/board/altera/socfpga/pll_config.h @@ -36,7 +36,7 @@
/* Peripheral PLL */ #define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) /* * To tell where is the VCOs source: * 0 = EOSC1
On Wednesday, April 15, 2015 at 11:44:30 PM, dinguyen@opensource.altera.com wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
Hello,
The following 3 patches are updates to SPL patches that Marek has already applied to his tree. I have split out the DDR driver patches into a separate patch series to make it more convenient to review.
Thanks,
Applied all three to u-boot-socfpga/master, thanks!
Best regards, Marek Vasut
participants (2)
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dinguyen＠opensource.altera.com -
Marek Vasut