[U-Boot] [PATCH 0/4] mailbox: introduce stm32-ipcc driver for stm32mp157
This patchset adds the mailbox ipcc driver for the stm32mp1 SOC and enables it for the stm32mp157 boards.
Fabien Dessenne (4): mailbox: introduce stm32-ipcc driver MAINTAINERS: Add stm32 mailbox IPPC driver configs: stm32mp15: enable IPCC mailbox ARM: dts: stm32: Add ipcc mailbox support on stm32mp1
MAINTAINERS | 1 + arch/arm/dts/stm32mp157a-dk1.dts | 4 + arch/arm/dts/stm32mp157c-ed1.dts | 4 + arch/arm/dts/stm32mp157c.dtsi | 13 +++ configs/stm32mp15_basic_defconfig | 2 + configs/stm32mp15_trusted_defconfig | 2 + drivers/mailbox/Kconfig | 7 ++ drivers/mailbox/Makefile | 1 + drivers/mailbox/stm32-ipcc.c | 167 ++++++++++++++++++++++++++++++++++++ 9 files changed, 201 insertions(+) create mode 100644 drivers/mailbox/stm32-ipcc.c
On STM32 family, the IPCC peripheral allows the communication between 2 processors offering doorbells mechanism.
Signed-off-by: Fabien Dessenne fabien.dessenne@st.com Signed-off-by: Loic Pallardy loic.pallardy@st.com --- drivers/mailbox/Kconfig | 7 ++ drivers/mailbox/Makefile | 1 + drivers/mailbox/stm32-ipcc.c | 167 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 175 insertions(+) create mode 100644 drivers/mailbox/stm32-ipcc.c
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 2836ee4..11bf552 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -24,6 +24,13 @@ config TEGRA_HSP This enables support for the NVIDIA Tegra HSP Hw module, which implements doorbells, mailboxes, semaphores, and shared interrupts.
+config STM32_IPCC + bool "Enable STM32 IPCC controller support" + depends on DM_MAILBOX && ARCH_STM32MP + help + This enables support for the STM32MP IPCC Hw module, which + implements doorbells between 2 processors. + config K3_SEC_PROXY bool "Texas Instruments K3 Secure Proxy Driver" depends on DM_MAILBOX && ARCH_K3 diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index cd23769..a753cc4 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -6,5 +6,6 @@ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox-uclass.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o +obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o obj-$(CONFIG_K3_SEC_PROXY) += k3-sec-proxy.o diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c new file mode 100644 index 0000000..c3df967 --- /dev/null +++ b/drivers/mailbox/stm32-ipcc.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <mailbox-uclass.h> +#include <asm/io.h> + +/* + * IPCC has one set of registers per CPU + * IPCC_PROC_OFFST allows to define cpu registers set base address + * according to the assigned proc_id. + */ + +#define IPCC_PROC_OFFST 0x010 + +#define IPCC_XSCR 0x008 +#define IPCC_XTOYSR 0x00c + +#define IPCC_HWCFGR 0x3f0 +#define IPCFGR_CHAN_MASK GENMASK(7, 0) + +#define RX_BIT_CHAN(chan) BIT(chan) +#define TX_BIT_SHIFT 16 +#define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan)) + +#define STM32_MAX_PROCS 2 + +struct stm32_ipcc { + void __iomem *reg_base; + void __iomem *reg_proc; + u32 proc_id; + u32 n_chans; +}; + +static int stm32_ipcc_request(struct mbox_chan *chan) +{ + struct stm32_ipcc *ipcc = dev_get_priv(chan->dev); + + debug("%s(chan=%p)\n", __func__, chan); + + if (chan->id >= ipcc->n_chans) { + debug("%s failed to request channel: %ld\n", + __func__, chan->id); + return -EINVAL; + } + + return 0; +} + +static int stm32_ipcc_free(struct mbox_chan *chan) +{ + debug("%s(chan=%p)\n", __func__, chan); + + return 0; +} + +static int stm32_ipcc_send(struct mbox_chan *chan, const void *data) +{ + struct stm32_ipcc *ipcc = dev_get_priv(chan->dev); + + debug("%s(chan=%p, data=%p)\n", __func__, chan, data); + + if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) + return -EBUSY; + + /* set channel n occupied */ + setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); + + return 0; +} + +static int stm32_ipcc_recv(struct mbox_chan *chan, void *data) +{ + struct stm32_ipcc *ipcc = dev_get_priv(chan->dev); + u32 val; + int proc_offset; + + debug("%s(chan=%p, data=%p)\n", __func__, chan, data); + + /* read 'channel occupied' status from other proc */ + proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST; + val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); + + if (!(val & BIT(chan->id))) + return -ENODATA; + + setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); + + return 0; +} + +static int stm32_ipcc_probe(struct udevice *dev) +{ + struct stm32_ipcc *ipcc = dev_get_priv(dev); + fdt_addr_t addr; + const fdt32_t *cell; + struct clk clk; + int len, ret; + + debug("%s(dev=%p)\n", __func__, dev); + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + ipcc->reg_base = (void __iomem *)addr; + + /* proc_id */ + cell = dev_read_prop(dev, "st,proc_id", &len); + if (len < sizeof(fdt32_t)) { + dev_dbg(dev, "Missing st,proc_id\n"); + return -EINVAL; + } + + ipcc->proc_id = fdtdec_get_number(cell, 1); + + if (ipcc->proc_id >= STM32_MAX_PROCS) { + dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id); + return -EINVAL; + } + + ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + goto clk_free; + + /* get channel number */ + ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR); + ipcc->n_chans &= IPCFGR_CHAN_MASK; + + return 0; + +clk_free: + clk_free(&clk); + + return ret; +} + +static const struct udevice_id stm32_ipcc_ids[] = { + { .compatible = "st,stm32mp1-ipcc" }, + { } +}; + +struct mbox_ops stm32_ipcc_mbox_ops = { + .request = stm32_ipcc_request, + .free = stm32_ipcc_free, + .send = stm32_ipcc_send, + .recv = stm32_ipcc_recv, +}; + +U_BOOT_DRIVER(stm32_ipcc) = { + .name = "stm32_ipcc", + .id = UCLASS_MAILBOX, + .of_match = stm32_ipcc_ids, + .probe = stm32_ipcc_probe, + .priv_auto_alloc_size = sizeof(struct stm32_ipcc), + .ops = &stm32_ipcc_mbox_ops, +};
Hi Fabien
On 5/14/19 11:20 AM, Fabien Dessenne wrote:
On STM32 family, the IPCC peripheral allows the communication between 2 processors offering doorbells mechanism.
Signed-off-by: Fabien Dessenne fabien.dessenne@st.com Signed-off-by: Loic Pallardy loic.pallardy@st.com
drivers/mailbox/Kconfig | 7 ++ drivers/mailbox/Makefile | 1 + drivers/mailbox/stm32-ipcc.c | 167 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 175 insertions(+) create mode 100644 drivers/mailbox/stm32-ipcc.c
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 2836ee4..11bf552 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -24,6 +24,13 @@ config TEGRA_HSP This enables support for the NVIDIA Tegra HSP Hw module, which implements doorbells, mailboxes, semaphores, and shared interrupts.
+config STM32_IPCC
- bool "Enable STM32 IPCC controller support"
- depends on DM_MAILBOX && ARCH_STM32MP
- help
This enables support for the STM32MP IPCC Hw module, whichimplements doorbells between 2 processors.config K3_SEC_PROXY bool "Texas Instruments K3 Secure Proxy Driver" depends on DM_MAILBOX && ARCH_K3 diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index cd23769..a753cc4 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -6,5 +6,6 @@ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox-uclass.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o +obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o obj-$(CONFIG_K3_SEC_PROXY) += k3-sec-proxy.o diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c new file mode 100644 index 0000000..c3df967 --- /dev/null +++ b/drivers/mailbox/stm32-ipcc.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- */
+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <mailbox-uclass.h> +#include <asm/io.h>
+/*
- IPCC has one set of registers per CPU
- IPCC_PROC_OFFST allows to define cpu registers set base address
- according to the assigned proc_id.
- */
+#define IPCC_PROC_OFFST 0x010
+#define IPCC_XSCR 0x008 +#define IPCC_XTOYSR 0x00c
+#define IPCC_HWCFGR 0x3f0 +#define IPCFGR_CHAN_MASK GENMASK(7, 0)
+#define RX_BIT_CHAN(chan) BIT(chan) +#define TX_BIT_SHIFT 16 +#define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan))
+#define STM32_MAX_PROCS 2
+struct stm32_ipcc {
- void __iomem *reg_base;
- void __iomem *reg_proc;
- u32 proc_id;
- u32 n_chans;
+};
+static int stm32_ipcc_request(struct mbox_chan *chan) +{
- struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
- debug("%s(chan=%p)\n", __func__, chan);
- if (chan->id >= ipcc->n_chans) {
debug("%s failed to request channel: %ld\n",__func__, chan->id);return -EINVAL;- }
- return 0;
+}
+static int stm32_ipcc_free(struct mbox_chan *chan) +{
- debug("%s(chan=%p)\n", __func__, chan);
- return 0;
+}
+static int stm32_ipcc_send(struct mbox_chan *chan, const void *data) +{
- struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
- debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
- if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id))
return -EBUSY;- /* set channel n occupied */
- setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id));
- return 0;
+}
+static int stm32_ipcc_recv(struct mbox_chan *chan, void *data) +{
- struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
- u32 val;
- int proc_offset;
- debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
- /* read 'channel occupied' status from other proc */
- proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
- val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
- if (!(val & BIT(chan->id)))
return -ENODATA;- setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id));
- return 0;
+}
+static int stm32_ipcc_probe(struct udevice *dev) +{
- struct stm32_ipcc *ipcc = dev_get_priv(dev);
- fdt_addr_t addr;
- const fdt32_t *cell;
- struct clk clk;
- int len, ret;
- debug("%s(dev=%p)\n", __func__, dev);
- addr = dev_read_addr(dev);
- if (addr == FDT_ADDR_T_NONE)
return -EINVAL;- ipcc->reg_base = (void __iomem *)addr;
- /* proc_id */
- cell = dev_read_prop(dev, "st,proc_id", &len);
- if (len < sizeof(fdt32_t)) {
dev_dbg(dev, "Missing st,proc_id\n");return -EINVAL;- }
- ipcc->proc_id = fdtdec_get_number(cell, 1);
- if (ipcc->proc_id >= STM32_MAX_PROCS) {
dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);return -EINVAL;- }
- ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
- ret = clk_get_by_index(dev, 0, &clk);
- if (ret)
return ret;- ret = clk_enable(&clk);
- if (ret)
goto clk_free;- /* get channel number */
- ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR);
- ipcc->n_chans &= IPCFGR_CHAN_MASK;
- return 0;
+clk_free:
- clk_free(&clk);
- return ret;
+}
+static const struct udevice_id stm32_ipcc_ids[] = {
- { .compatible = "st,stm32mp1-ipcc" },
- { }
+};
+struct mbox_ops stm32_ipcc_mbox_ops = {
- .request = stm32_ipcc_request,
- .free = stm32_ipcc_free,
- .send = stm32_ipcc_send,
- .recv = stm32_ipcc_recv,
+};
+U_BOOT_DRIVER(stm32_ipcc) = {
- .name = "stm32_ipcc",
- .id = UCLASS_MAILBOX,
- .of_match = stm32_ipcc_ids,
- .probe = stm32_ipcc_probe,
- .priv_auto_alloc_size = sizeof(struct stm32_ipcc),
- .ops = &stm32_ipcc_mbox_ops,
+};
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
Hi,
From: Fabien DESSENNE fabien.dessenne@st.com Sent: mardi 14 mai 2019 11:21
On STM32 family, the IPCC peripheral allows the communication between 2 processors offering doorbells mechanism.
Signed-off-by: Fabien Dessenne fabien.dessenne@st.com Signed-off-by: Loic Pallardy loic.pallardy@st.com
drivers/mailbox/Kconfig | 7 ++ drivers/mailbox/Makefile | 1 + drivers/mailbox/stm32-ipcc.c | 167 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 175 insertions(+) create mode 100644 drivers/mailbox/stm32-ipcc.c
Applied to u-boot-stm32/master, thanks!
Patrick
Signed-off-by: Fabien Dessenne fabien.dessenne@st.com --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS index 33fd465..5523c4a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -301,6 +301,7 @@ S: Maintained F: arch/arm/mach-stm32mp/ F: drivers/clk/clk_stm32mp1.c F: drivers/i2c/stm32f7_i2c.c +F: drivers/mailbox/stm32-ipcc.c F: drivers/misc/stm32mp_fuse.c F: drivers/mmc/stm32_sdmmc2.c F: drivers/phy/phy-stm32-usbphyc.c
On 5/14/19 11:20 AM, Fabien Dessenne wrote:
Signed-off-by: Fabien Dessenne fabien.dessenne@st.com
MAINTAINERS | 1 + 1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS index 33fd465..5523c4a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -301,6 +301,7 @@ S: Maintained F: arch/arm/mach-stm32mp/ F: drivers/clk/clk_stm32mp1.c F: drivers/i2c/stm32f7_i2c.c +F: drivers/mailbox/stm32-ipcc.c F: drivers/misc/stm32mp_fuse.c F: drivers/mmc/stm32_sdmmc2.c F: drivers/phy/phy-stm32-usbphyc.c
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
Hi,
From: Fabien DESSENNE fabien.dessenne@st.com Sent: mardi 14 mai 2019 11:21
Signed-off-by: Fabien Dessenne fabien.dessenne@st.com
MAINTAINERS | 1 + 1 file changed, 1 insertion(+)
Applied to u-boot-stm32/master, thanks!
Patrick
Activate the ipcc mailbox for stm32mp15 configs.
Signed-off-by: Fabien Dessenne fabien.dessenne@st.com --- configs/stm32mp15_basic_defconfig | 2 ++ configs/stm32mp15_trusted_defconfig | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 0ea9dff..f03c72c 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -52,6 +52,8 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_STM32_IPCC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 3c2bb75..525f4c3 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -44,6 +44,8 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_STM32_IPCC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y
On 5/14/19 11:20 AM, Fabien Dessenne wrote:
Activate the ipcc mailbox for stm32mp15 configs.
Signed-off-by: Fabien Dessenne fabien.dessenne@st.com
configs/stm32mp15_basic_defconfig | 2 ++ configs/stm32mp15_trusted_defconfig | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 0ea9dff..f03c72c 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -52,6 +52,8 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_STM32_IPCC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 3c2bb75..525f4c3 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -44,6 +44,8 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_STM32_IPCC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
Hi,
From: Fabien DESSENNE fabien.dessenne@st.com Sent: mardi 14 mai 2019 11:21
Activate the ipcc mailbox for stm32mp15 configs.
Signed-off-by: Fabien Dessenne fabien.dessenne@st.com
configs/stm32mp15_basic_defconfig | 2 ++ configs/stm32mp15_trusted_defconfig | 2 ++ 2 files changed, 4 insertions(+)
Applied to u-boot-stm32/master, thanks!
Patrick
Add IPCC mailbox support on stm32mp157 eval and disco boards.
Signed-off-by: Fabien Dessenne fabien.dessenne@st.com --- arch/arm/dts/stm32mp157a-dk1.dts | 4 ++++ arch/arm/dts/stm32mp157c-ed1.dts | 4 ++++ arch/arm/dts/stm32mp157c.dtsi | 13 +++++++++++++ 3 files changed, 21 insertions(+)
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index e36773d..b8dd4ba 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -228,6 +228,10 @@ }; };
+&ipcc { + status = "okay"; +}; + &iwdg2 { timeout-sec = <32>; status = "okay"; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index b10208f..ab11c83 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -318,6 +318,10 @@ }; };
+&ipcc { + status = "okay"; +}; + &iwdg2 { timeout-sec = <32>; status = "okay"; diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index 9463433..d90028a 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -849,6 +849,19 @@ status = "disabled"; };
+ ipcc: mailbox@4c001000 { + compatible = "st,stm32mp1-ipcc"; + #mbox-cells = <1>; + reg = <0x4c001000 0x400>; + st,proc-id = <0>; + interrupts-extended = + <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; + clocks = <&rcc IPCC>; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>;
On 5/14/19 11:20 AM, Fabien Dessenne wrote:
Add IPCC mailbox support on stm32mp157 eval and disco boards.
Signed-off-by: Fabien Dessenne fabien.dessenne@st.com
arch/arm/dts/stm32mp157a-dk1.dts | 4 ++++ arch/arm/dts/stm32mp157c-ed1.dts | 4 ++++ arch/arm/dts/stm32mp157c.dtsi | 13 +++++++++++++ 3 files changed, 21 insertions(+)
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index e36773d..b8dd4ba 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -228,6 +228,10 @@ }; };
+&ipcc {
- status = "okay";
+};
&iwdg2 { timeout-sec = <32>; status = "okay"; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index b10208f..ab11c83 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -318,6 +318,10 @@ }; };
+&ipcc {
- status = "okay";
+};
&iwdg2 { timeout-sec = <32>; status = "okay"; diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index 9463433..d90028a 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -849,6 +849,19 @@ status = "disabled"; };
ipcc: mailbox@4c001000 {compatible = "st,stm32mp1-ipcc";#mbox-cells = <1>;reg = <0x4c001000 0x400>;st,proc-id = <0>;interrupts-extended =<&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "rx", "tx";clocks = <&rcc IPCC>;status = "disabled";};- rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>;
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
Hi,
From: Fabien DESSENNE fabien.dessenne@st.com Sent: mardi 14 mai 2019 11:21
Add IPCC mailbox support on stm32mp157 eval and disco boards.
Signed-off-by: Fabien Dessenne fabien.dessenne@st.com
arch/arm/dts/stm32mp157a-dk1.dts | 4 ++++ arch/arm/dts/stm32mp157c- ed1.dts | 4 ++++ arch/arm/dts/stm32mp157c.dtsi | 13 +++++++++++++ 3 files changed, 21 insertions(+)
Applied to u-boot-stm32/master, thanks!
Patrick
Hi
Are there any further comments?
BR
Fabien
On 14/05/2019 11:20 AM, Fabien Dessenne wrote:
This patchset adds the mailbox ipcc driver for the stm32mp1 SOC and enables it for the stm32mp157 boards.
Fabien Dessenne (4): mailbox: introduce stm32-ipcc driver MAINTAINERS: Add stm32 mailbox IPPC driver configs: stm32mp15: enable IPCC mailbox ARM: dts: stm32: Add ipcc mailbox support on stm32mp1
MAINTAINERS | 1 + arch/arm/dts/stm32mp157a-dk1.dts | 4 + arch/arm/dts/stm32mp157c-ed1.dts | 4 + arch/arm/dts/stm32mp157c.dtsi | 13 +++ configs/stm32mp15_basic_defconfig | 2 + configs/stm32mp15_trusted_defconfig | 2 + drivers/mailbox/Kconfig | 7 ++ drivers/mailbox/Makefile | 1 + drivers/mailbox/stm32-ipcc.c | 167 ++++++++++++++++++++++++++++++++++++ 9 files changed, 201 insertions(+) create mode 100644 drivers/mailbox/stm32-ipcc.c
participants (4)
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Fabien DESSENNE -
Fabien Dessenne
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Patrice CHOTARD -
Patrick DELAUNAY