Hello,

[POWERPC] Added support for the muas3001 board from IAI, based on a MPC8270 CPU.

Signed-off-by: Heiko Schocher hs@denx.de --- Makefile | 9 + board/muas3001/Makefile | 50 ++++++ board/muas3001/config.mk | 24 +++ board/muas3001/muas3001.c | 388 ++++++++++++++++++++++++++++++++++++++++++++ include/configs/muas3001.h | 382 +++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 853 insertions(+), 0 deletions(-) create mode 100644 board/muas3001/Makefile create mode 100644 board/muas3001/config.mk create mode 100644 board/muas3001/muas3001.c create mode 100644 include/configs/muas3001.h

diff --git a/Makefile b/Makefile index 3179c67..9c3de1c 100644 --- a/Makefile +++ b/Makefile @@ -1672,6 +1672,15 @@ PQ2FADS-ZU_66MHz_lowboot_config \ MPC8266ADS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc8260 mpc8266ads freescale

+muas3001_dev_config \ +muas3001_config : unconfig + @mkdir -p $(obj)include + @mkdir -p $(obj)board/muas3001 + @if [ "$(findstring dev,$@)" ] ; then \ + echo "#define CONFIG_MUAS_DEV_BOARD" > $(obj)include/config.h ; \ + fi + @$(MKCONFIG) -a muas3001 ppc mpc8260 muas3001 + # PM825/PM826 default configuration: small (= 8 MB) Flash / boot from 64-bit flash PM825_config \ PM825_ROMBOOT_config \ diff --git a/board/muas3001/Makefile b/board/muas3001/Makefile new file mode 100644 index 0000000..a4413b2 --- /dev/null +++ b/board/muas3001/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2001-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/muas3001/config.mk b/board/muas3001/config.mk new file mode 100644 index 0000000..cdd0ec9 --- /dev/null +++ b/board/muas3001/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2008 +# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFF000000 diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c new file mode 100644 index 0000000..1c33493 --- /dev/null +++ b/board/muas3001/muas3001.c @@ -0,0 +1,388 @@ +/* + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8260.h> +#include <ioports.h> + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */ + /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ + /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* ETH_PWRDWN */ + /* PA24 */ { 1, 0, 0, 1, 0, 1 }, /* ETH_RESET */ + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ + /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ + /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* ETH_SLEEP */ + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ + /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* MDIO */ + /* PA9 */ { 1, 0, 0, 1, 0, 0 }, /* MDC */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ + }, + + /* Port B */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */ + /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */ + /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */ + /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ + /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */ + /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */ + /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */ + /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */ + /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */ + /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */ + /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */ + /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */ + /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */ + /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ + /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RxD */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB12 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TxD */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 1, 1, 1, 1, 0, 0 }, /* Timer1 OUT */ + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ + /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC RxCLK 11 */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC TxCLK 12 */ + /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ + /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ + /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* TX OUTPUT SLEW1 */ + /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* TX OUTPUT SLEW0 */ + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* SPA_TX_EN */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ + /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ + /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */ + /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ + /* PD15 */ { 1, 1, 1, 0, 0, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C SCL */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + } +}; + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + ulong maxsize, size; + int i; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff))/* / 2*/; + + sdmr_ptr = &memctl->memc_psdmr; + orx_ptr = &memctl->memc_or1; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + size = get_ram_size((long *)base, maxsize); + *orx_ptr = orx | ~(size - 1); + + return (size); +} + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + + long psize; + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + +#ifndef CFG_RAMBOOT + /* 60x SDRAM setup: + */ + psize = try_init (memctl, CFG_PSDMR, CFG_OR1, + (uchar *) CFG_SDRAM_BASE); +#endif /* CFG_RAMBOOT */ + + icache_enable (); + + return (psize); +} + +int checkboard(void) +{ + puts("Board: MUAS3001\n"); + + return 0; +} + +/* + * Early board initalization. + */ +int board_early_init_r(void) +{ + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +/* + * update "memory" property in the blob + */ +void ft_blob_update(void *blob, bd_t *bd) +{ + int ret, nodeoffset = 0; + ulong memory_data[2] = {0}; + ulong flash_data[4] = {0}; + ulong freq = 0; + ulong speed = 0; + + memory_data[0] = cpu_to_be32(bd->bi_memstart); + memory_data[1] = cpu_to_be32(bd->bi_memsize); + + nodeoffset = fdt_path_offset (blob, "/memory"); + if (nodeoffset >= 0) { + ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, + sizeof(memory_data)); + if (ret < 0) + printf("ft_blob_update): cannot set /memory/reg " + "property err:%s\n", fdt_strerror(ret)); + } + else { + /* memory node is required in dts */ + printf("ft_blob_update(): cannot find /memory node " + "err:%s\n", fdt_strerror(nodeoffset)); + } + /* update Flash addr, size */ + flash_data[2] = cpu_to_be32(CFG_FLASH_BASE); + flash_data[3] = cpu_to_be32(CFG_FLASH_SIZE); + nodeoffset = fdt_path_offset (blob, "/localbus"); + if (nodeoffset >= 0) { + ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data, + sizeof(flash_data)); + if (ret < 0) + printf("ft_blob_update): cannot set /localbus/ranges " + "property err:%s\n", fdt_strerror(ret)); + } + else { + /* memory node is required in dts */ + printf("ft_blob_update(): cannot find /localbus node " + "err:%s\n", fdt_strerror(nodeoffset)); + } + /* MAC Adresse */ + nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet"); + if (nodeoffset >= 0) { + ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr, + sizeof(uchar) * 6); + if (ret < 0) + printf("ft_blob_update): cannot set /soc/cpm/ethernet/mac-address " + "property err:%s\n", fdt_strerror(ret)); + } + else { + /* memory node is required in dts */ + printf("ft_blob_update(): cannot find /soc/cpm/ethernet node " + "err:%s\n", fdt_strerror(nodeoffset)); + } + + /* brg clock */ + nodeoffset = fdt_path_offset (blob, "/soc/cpm/brg"); + if (nodeoffset >= 0) { + freq = cpu_to_be32(bd->bi_brgfreq); + ret = fdt_setprop(blob, nodeoffset, "clock-frequency", &freq, + sizeof(unsigned long)); + if (ret < 0) + printf("ft_blob_update): cannot set /soc/cpm/brg/clock-frequency " + "property err:%s\n", fdt_strerror(ret)); + } + else { + /* memory node is required in dts */ + printf("ft_blob_update(): cannot find /soc/cpm/brg/clock-frequency node " + "err:%s\n", fdt_strerror(nodeoffset)); + } + + /* baudrate */ + nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial"); + if (nodeoffset >= 0) { + speed = cpu_to_be32(bd->bi_baudrate); + ret = fdt_setprop(blob, nodeoffset, "current-speed", &speed, + sizeof(unsigned long)); + if (ret < 0) + printf("ft_blob_update): cannot set /soc/cpm/serial/current-speed " + "property err:%s\n", fdt_strerror(ret)); + } + else { + /* baudrate is required in dts */ + printf("ft_blob_update(): cannot find /soc/cpm/smc2/current-speed node " + "err:%s\n", fdt_strerror(nodeoffset)); + } + + +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup( blob, bd); + ft_blob_update(blob, bd); +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h new file mode 100644 index 0000000..f915e55 --- /dev/null +++ b/include/configs/muas3001.h @@ -0,0 +1,382 @@ +/* + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_8260 1 +#define CONFIG_MPC8260 1 +#define CONFIG_MUAS3001 1 + +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +/* Do boardspecific init */ +#define CONFIG_BOARD_EARLY_INIT_R 1 + +/* + * Select serial console configuration + * + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + */ +#define CONFIG_CONS_ON_SMC /* Console is on SMC */ +#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ +#undef CONFIG_CONS_NONE /* It's not on external UART */ +#if defined(CONFIG_MUAS_DEV_BOARD) +#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ +#else +#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ +#endif + +/* + * Select ethernet configuration + * + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, + * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for + * SCC, 1-3 for FCC) + * + * If CONFIG_ETHER_NONE is defined, then either the ethernet routines + * must be defined elsewhere (as for the console), or CONFIG_CMD_NET + * must be unset. + */ +#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ +#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ +#undef CONFIG_ETHER_NONE /* No external Ethernet */ + +#define CONFIG_ETHER_INDEX 1 +#define CONFIG_ETHER_ON_FCC1 +#define FCC_ENET + +/* + * - Rx-CLK is CLK11 + * - Tx-CLK is CLK12 + */ +# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) +# define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) +/* + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + */ +# define CFG_CPMFCR_RAMTYPE (0) +/* know on local Bus */ +//# define CFG_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) +/* + * - Enable Full Duplex in FSMR + */ +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +# define CFG_PHY_ADDR 1 +/* + * GPIO pins used for bit-banged MII communications + */ +#define MDIO_PORT 0 /* Port A */ + +#define CFG_MDIO_PIN 0x00200000 /* PA10 */ +#define CFG_MDC_PIN 0x00400000 /* PA9 */ + +#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) +#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) +#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ + else iop->pdat &= ~CFG_MDIO_PIN + +#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ + else iop->pdat &= ~CFG_MDC_PIN + +#define MIIDELAY udelay(1) + +#ifndef CONFIG_8260_CLKIN +#define CONFIG_8260_CLKIN 66000000 /* in Hz */ +#endif + +#define CONFIG_BAUDRATE 115200 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "u-boot_addr=100000\0" \ + "kernel_addr=200000\0" \ + "fdt_addr=400000\0" \ + "rootpath=/opt/eldk-4.2-2008-04-01/ppc_82xx\0" \ + "u-boot=u-boot.bin\0" \ + "bootfile=uImage\0" \ + "fdt_file=muas3001.dtb\0" \ + "kernel_file=uImage\0" \ + "ramdisk_file=uRamdisk\0" \ + "load=tftp ${u-boot_addr} ${u-boot}\0" \ + "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ + "cp.b ${u-boot_addr} ff000000 ${filesize};" \ + "prot on ff000000 ff03ffff\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off panic=1\0" \ + "net_nfs=tftp ${kernel_addr} ${bootfile}; " \ + "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_self=tftp ${kernel_addr} ${bootfile}; " \ + "tftp ${fdt_addr} ${fdt_file}; " \ + "tftp ${ramdisk_addr} ${ramdisk_file}; " \ + "run ramargs addip; " \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "ramdisk_addr=ff210000\0" \ + "kernel_addr_self=ff050000\0" \ + "fdt_addr_self=ff200000\0" \ + "flash_self=run ramargs addip addcons;bootm ${kernel_addr_self}" \ + " ${ramdisk_addr} ${fdt_addr_self}\0" \ + "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr} ${ramdisk_file};" \ + "cp.b ${kernel_addr} ${ramdisk_addr} ${filesize}\0" \ + "updatekernel=era ${kernel_addr_self} +1b0000;tftpb ${kernel_addr} ${kernel_file};" \ + "cp.b ${kernel_addr} ${kernel_addr_self} ${filesize}\0" \ + "updatefdt=era ${fdt_addr_self} +10000;tftpb ${fdt_addr} ${fdt_file};" \ + "cp.b ${fdt_addr} ${fdt_addr_self} ${filesize}\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_FLASH_SIZE 32 +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */ + +#define CFG_ENV_IS_IN_FLASH + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/* + * I2C Bus + */ +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_IMMR 0xF0000000 +#define CFG_DEFAULT_IMMR 0x0F010000 + +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* Hard reset configuration word */ +#define CFG_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */ + +/* No slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) + +#define CFG_HID2 0 + +#define CFG_SIUMCR 0x00200000 +#define CFG_SYPCR 0xFFFFFFC3 +#define CFG_BCR 0x004c0000 +#define CFG_SCCR 0x0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR 0 + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 32 bit FLASH + * 1 60x SDRAM 64 bit SDRAM + * 4 60x GPCM 16 bit I/O Ctrl + * + */ +/* Bank 0 - FLASH + */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (0xff000020) + +/* Bank 1 - 60x bus SDRAM + */ +#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ +#define CFG_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ + +#define CFG_MPTPR 0x2800 + +/*----------------------------------------------------------------------------- + * Address for Mode Register Set (MRS) command + *----------------------------------------------------------------------------- + */ +#define CFG_MRS_OFFS 0x00000110 +#define CFG_PSRT 0x13 + +#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM CFG_OR1 + +/* SDRAM initialization values +*/ +#define CFG_OR1 0xfe002ec0 +#define CFG_PSDMR 0x004b36a3 + +/* IO on CS4 initialization values +*/ +#define CFG_IO_BASE 0xc0000000 +#define CFG_IO_SIZE 1 + +#define CFG_BR4_PRELIM ((CFG_IO_BASE & BRx_BA_MSK) |\ + BRx_PS_32 | BRx_MS_GPCM_L | BRx_V) + +#define CFG_OR4_PRELIM (0xfff80020) + +#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_CPU "PowerPC,8270@0" +#define OF_SOC "soc@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#if defined(CONFIG_MUAS_DEV_BOARD) +#define OF_STDOUT_PATH "/soc/cpm/serial@11a90" +#else +#define OF_STDOUT_PATH "/soc/cpm/serial@11a80" +#endif + +#endif /* __CONFIG_H */