[PATCH 01/25] arm: Remove xfi3 board
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Marek Vasut marek.vasut@gmail.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-imx/mxs/Kconfig | 1 - board/creative/xfi3/Kconfig | 15 --- board/creative/xfi3/MAINTAINERS | 6 - board/creative/xfi3/Makefile | 10 -- board/creative/xfi3/spl_boot.c | 133 ------------------- board/creative/xfi3/xfi3.c | 226 -------------------------------- configs/xfi3_defconfig | 43 ------ include/configs/xfi3.h | 39 ------ 8 files changed, 473 deletions(-) delete mode 100644 board/creative/xfi3/Kconfig delete mode 100644 board/creative/xfi3/MAINTAINERS delete mode 100644 board/creative/xfi3/Makefile delete mode 100644 board/creative/xfi3/spl_boot.c delete mode 100644 board/creative/xfi3/xfi3.c delete mode 100644 configs/xfi3_defconfig delete mode 100644 include/configs/xfi3.h
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index b90d7b6e4176..fb19e36559ff 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -30,7 +30,6 @@ config SYS_SOC source "board/olimex/mx23_olinuxino/Kconfig" source "board/freescale/mx23evk/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" -source "board/creative/xfi3/Kconfig"
endif
diff --git a/board/creative/xfi3/Kconfig b/board/creative/xfi3/Kconfig deleted file mode 100644 index 7b681cd81b04..000000000000 --- a/board/creative/xfi3/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_XFI3 - -config SYS_BOARD - default "xfi3" - -config SYS_VENDOR - default "creative" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "xfi3" - -endif diff --git a/board/creative/xfi3/MAINTAINERS b/board/creative/xfi3/MAINTAINERS deleted file mode 100644 index fb8235a3295f..000000000000 --- a/board/creative/xfi3/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -XFI3 BOARD -M: Marek Vasut marek.vasut@gmail.com -S: Maintained -F: board/creative/xfi3/ -F: include/configs/xfi3.h -F: configs/xfi3_defconfig diff --git a/board/creative/xfi3/Makefile b/board/creative/xfi3/Makefile deleted file mode 100644 index 67d68dd6218d..000000000000 --- a/board/creative/xfi3/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := xfi3.o -else -obj-y := spl_boot.o -endif diff --git a/board/creative/xfi3/spl_boot.c b/board/creative/xfi3/spl_boot.c deleted file mode 100644 index 67c1e9801b9b..000000000000 --- a/board/creative/xfi3/spl_boot.c +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Creative ZEN X-Fi3 setup - * - * Copyright (C) 2013 Marek Vasut marex@denx.de - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx23.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* EMI */ - MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI, - - MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI, - MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - - MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - - MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, - MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, - MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD, - MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD, - MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, - MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, - MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, - - MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D07__GPIO_0_7 | MUX_CONFIG_SSP, - - MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP, - MX23_PAD_GPMI_WRN__SSP2_SCK | MUX_CONFIG_SSP, - - /* PWM -- FIXME */ - MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP, -}; - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - /* mDDR configuration values */ - const uint32_t regs[] = { - 0x01010001, 0x00010000, 0x01000000, 0x00000001, - 0x00010101, 0x00000001, 0x00010000, 0x01000001, - 0x01010000, 0x00000001, 0x07000200, 0x04070203, - 0x02020002, 0x06070a02, 0x0d000201, 0x0305000d, - 0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313, - 0x03061323, 0x0000000a, 0x00080008, 0x00200020, - 0x00200020, 0x00200020, 0x000003f7, 0x00000000, - 0x00000000, 0x00000000, 0x00000020, 0x00000000, - 0x001023cd, 0x20410010, 0x00006665, 0x00000000, - 0x00000101, 0x00000001, 0x00000000, 0x00000000, - }; - memcpy(dram_vals, regs, sizeof(regs)); -} - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/board/creative/xfi3/xfi3.c b/board/creative/xfi3/xfi3.c deleted file mode 100644 index b5f0d3130745..000000000000 --- a/board/creative/xfi3/xfi3.c +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Creative ZEN X-Fi3 board - * - * Copyright (C) 2013 Marek Vasut marex@denx.de - * - * Hardware investigation done by: - * - * Amaury Pouly amaury.pouly@gmail.com - */ - -#include <common.h> -#include <errno.h> -#include <init.h> -#include <net.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx23.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -#ifdef CONFIG_CMD_MMC -static int xfi3_mmc_cd(int id) -{ - switch (id) { - case 0: - /* The SSP_DETECT is inverted on this board. */ - return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1); - case 1: - /* Phison bridge always present */ - return 1; - default: - return 0; - } -} - -int board_mmc_init(struct bd_info *bis) -{ - int ret; - - /* MicroSD slot */ - gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1); - gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0); - ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd); - if (ret) - return ret; - - /* Phison SD-NAND bridge */ - ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd); - - return ret; -} -#endif - -#ifdef CONFIG_VIDEO_MXS -static int mxsfb_write_byte(uint32_t payload, const unsigned int data) -{ - struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; - const unsigned int timeout = 0x10000; - - if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, - timeout)) - return -ETIMEDOUT; - - writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | - (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET), - ®s->hw_lcdif_transfer_count); - - writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN, - ®s->hw_lcdif_ctrl_clr); - - if (data) - writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set); - - writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); - - if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29, - timeout)) - return -ETIMEDOUT; - - writel(payload, ®s->hw_lcdif_data); - return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, - timeout); -} - -static void mxsfb_write_register(uint32_t reg, uint32_t data) -{ - mxsfb_write_byte(reg, 0); - mxsfb_write_byte(data, 1); -} - -static const struct { - uint8_t reg; - uint8_t delay; - uint16_t val; -} lcd_regs[] = { - { 0x01, 0, 0x001c }, - { 0x02, 0, 0x0100 }, - /* Writing 0x30 to reg. 0x03 flips the LCD */ - { 0x03, 0, 0x1038 }, - { 0x08, 0, 0x0808 }, - /* This can contain 0x111 to rotate the LCD. */ - { 0x0c, 0, 0x0000 }, - { 0x0f, 0, 0x0c01 }, - { 0x20, 0, 0x0000 }, - { 0x21, 30, 0x0000 }, - /* Wait 30 mS here */ - { 0x10, 0, 0x0a00 }, - { 0x11, 30, 0x1038 }, - /* Wait 30 mS here */ - { 0x12, 0, 0x1010 }, - { 0x13, 0, 0x0050 }, - { 0x14, 0, 0x4f58 }, - { 0x30, 0, 0x0000 }, - { 0x31, 0, 0x00db }, - { 0x32, 0, 0x0000 }, - { 0x33, 0, 0x0000 }, - { 0x34, 0, 0x00db }, - { 0x35, 0, 0x0000 }, - { 0x36, 0, 0x00af }, - { 0x37, 0, 0x0000 }, - { 0x38, 0, 0x00db }, - { 0x39, 0, 0x0000 }, - { 0x50, 0, 0x0000 }, - { 0x51, 0, 0x0705 }, - { 0x52, 0, 0x0e0a }, - { 0x53, 0, 0x0300 }, - { 0x54, 0, 0x0a0e }, - { 0x55, 0, 0x0507 }, - { 0x56, 0, 0x0000 }, - { 0x57, 0, 0x0003 }, - { 0x58, 0, 0x090a }, - { 0x59, 30, 0x0a09 }, - /* Wait 30 mS here */ - { 0x07, 30, 0x1017 }, - /* Wait 40 mS here */ - { 0x36, 0, 0x00af }, - { 0x37, 0, 0x0000 }, - { 0x38, 0, 0x00db }, - { 0x39, 0, 0x0000 }, - { 0x20, 0, 0x0000 }, - { 0x21, 0, 0x0000 }, -}; - -void mxsfb_system_setup(void) -{ - struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; - int i; - - /* Switch the LCDIF into System-Mode */ - writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE | - LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr); - - /* Restart the SmartLCD controller */ - mdelay(50); - writel(1, ®s->hw_lcdif_ctrl1_set); - mdelay(50); - writel(1, ®s->hw_lcdif_ctrl1_clr); - mdelay(50); - writel(1, ®s->hw_lcdif_ctrl1_set); - mdelay(50); - - /* Program the SmartLCD controller */ - writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set); - - writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) | - (0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) | - (0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) | - (0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET), - ®s->hw_lcdif_timing); - - /* - * OTM2201A init and configuration sequence. - */ - for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) { - mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val); - if (lcd_regs[i].delay) - mdelay(lcd_regs[i].delay); - } - /* Turn on Framebuffer Upload Mode */ - mxsfb_write_byte(0x22, 0); - - writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT, - ®s->hw_lcdif_ctrl_set); -} -#endif - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - /* Turn on PWM backlight */ - gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - usb_eth_initialize(bis); - return 0; -} diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig deleted file mode 100644 index c49319c3c2f0..000000000000 --- a/configs/xfi3_defconfig +++ /dev/null @@ -1,43 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX23=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_XFI3=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyAMA0,115200n8 " -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_CONS_INDEX=0 -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_GADGET=y -CONFIG_CI_UDC=y -CONFIG_USB_ETHER=y -CONFIG_USB_ETH_CDC=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h deleted file mode 100644 index 80849129b931..000000000000 --- a/include/configs/xfi3.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Marek Vasut marex@denx.de - */ -#ifndef __CONFIGS_XFI3_H__ -#define __CONFIGS_XFI3_H__ - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* LCD */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_FONT_4X6 -#define CONFIG_VIDEO_MXS_MODE_SYSTEM -#define CONFIG_SYS_BLACK_IN_WRITE -#define LCD_BPP LCD_COLOR16 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_XFI3_H__ */
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Otavio Salvador otavio@ossystems.com.br Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-imx/mxs/Kconfig | 8 -- board/freescale/mx23evk/Kconfig | 15 ---- board/freescale/mx23evk/MAINTAINERS | 6 -- board/freescale/mx23evk/Makefile | 10 --- board/freescale/mx23evk/mx23evk.c | 78 ---------------- board/freescale/mx23evk/spl_boot.c | 134 ---------------------------- configs/mx23evk_defconfig | 40 --------- include/configs/mx23evk.h | 102 --------------------- 8 files changed, 393 deletions(-) delete mode 100644 board/freescale/mx23evk/Kconfig delete mode 100644 board/freescale/mx23evk/MAINTAINERS delete mode 100644 board/freescale/mx23evk/Makefile delete mode 100644 board/freescale/mx23evk/mx23evk.c delete mode 100644 board/freescale/mx23evk/spl_boot.c delete mode 100644 configs/mx23evk_defconfig delete mode 100644 include/configs/mx23evk.h
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index fb19e36559ff..c731d01d4ed3 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -12,23 +12,15 @@ config TARGET_MX23_OLINUXINO bool "Support mx23_olinuxino" select BOARD_EARLY_INIT_F
-config TARGET_MX23EVK - bool "Support mx23evk" - select BOARD_EARLY_INIT_F - config TARGET_SANSA_FUZE_PLUS bool "Support sansa_fuze_plus"
-config TARGET_XFI3 - bool "Support xfi3" - endchoice
config SYS_SOC default "mxs"
source "board/olimex/mx23_olinuxino/Kconfig" -source "board/freescale/mx23evk/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig"
endif diff --git a/board/freescale/mx23evk/Kconfig b/board/freescale/mx23evk/Kconfig deleted file mode 100644 index 51a8f9f773cb..000000000000 --- a/board/freescale/mx23evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX23EVK - -config SYS_BOARD - default "mx23evk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "mx23evk" - -endif diff --git a/board/freescale/mx23evk/MAINTAINERS b/board/freescale/mx23evk/MAINTAINERS deleted file mode 100644 index b03ad6ae0af6..000000000000 --- a/board/freescale/mx23evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX23EVK BOARD -M: Otavio Salvador otavio@ossystems.com.br -S: Maintained -F: board/freescale/mx23evk/ -F: include/configs/mx23evk.h -F: configs/mx23evk_defconfig diff --git a/board/freescale/mx23evk/Makefile b/board/freescale/mx23evk/Makefile deleted file mode 100644 index 6fe6992a5fcd..000000000000 --- a/board/freescale/mx23evk/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := mx23evk.o -else -obj-y := spl_boot.o -endif diff --git a/board/freescale/mx23evk/mx23evk.c b/board/freescale/mx23evk/mx23evk.c deleted file mode 100644 index 3fbac6b5cc31..000000000000 --- a/board/freescale/mx23evk/mx23evk.c +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale MX23EVK board - * - * (C) Copyright 2013 O.S. Systems Software LTDA. - * - * Author: Otavio Salvador otavio@ossystems.com.br - * - * Based on m28evk.c: - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <init.h> -#include <asm/gpio.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux-mx23.h> -#include <asm/arch/sys_proto.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - - /* Power on LCD */ - gpio_direction_output(MX23_PAD_LCD_RESET__GPIO_1_18, 1); - - /* Set contrast to maximum */ - gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -#ifdef CONFIG_CMD_MMC -static int mx23evk_mmc_wp(int id) -{ - if (id != 0) { - printf("MXS MMC: Invalid card selected (card id = %d)\n", id); - return 1; - } - - return gpio_get_value(MX23_PAD_PWM4__GPIO_1_30); -} - -int board_mmc_init(struct bd_info *bis) -{ - /* Configure WP as input */ - gpio_direction_input(MX23_PAD_PWM4__GPIO_1_30); - - /* Configure MMC0 Power Enable */ - gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0); - - return mxsmmc_initialize(bis, 0, mx23evk_mmc_wp, NULL); -} -#endif diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c deleted file mode 100644 index 14e9b4a8634f..000000000000 --- a/board/freescale/mx23evk/spl_boot.c +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale MX23EVK Boot setup - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx23.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_SSP1 (MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_LCD (MXS_PAD_4MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* DUART */ - MX23_PAD_PWM0__DUART_RX, - MX23_PAD_PWM1__DUART_TX, - - /* EMI */ - MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI, - - MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI, - MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - - MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - - /* MMC 0 */ - MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP1, - MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP1, - MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP1, - MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP1, - MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP1, - MX23_PAD_SSP1_DETECT__SSP1_DETECT | MUX_CONFIG_SSP1, - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX23_PAD_SSP1_SCK__SSP1_SCK | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* Write Protect Pin */ - MX23_PAD_PWM4__GPIO_1_30 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* Slot Power Enable */ - MX23_PAD_PWM3__GPIO_1_29 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* LCD */ - MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, - MX23_PAD_GPMI_D08__LCD_D18 | MUX_CONFIG_LCD, - MX23_PAD_GPMI_D09__LCD_D19 | MUX_CONFIG_LCD, - MX23_PAD_GPMI_D10__LCD_D20 | MUX_CONFIG_LCD, - MX23_PAD_GPMI_D11__LCD_D21 | MUX_CONFIG_LCD, - MX23_PAD_GPMI_D12__LCD_D22 | MUX_CONFIG_LCD, - MX23_PAD_GPMI_D13__LCD_D23 | MUX_CONFIG_LCD, - MX23_PAD_LCD_DOTCK__LCD_DOTCK | MUX_CONFIG_LCD, - MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, - MX23_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD, - MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, - MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD, /* LCD power */ - MX23_PAD_PWM2__GPIO_1_28 | MUX_CONFIG_LCD, /* LCD contrast */ -}; - -#define HW_DRAM_CTL14 (0x38 >> 2) -#define CS_MAP 0x3 -#define INTAREF 0x2 -#define HW_DRAM_CTL14_CONFIG (INTAREF << 8 | CS_MAP) - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG; -} - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig deleted file mode 100644 index 0e3d9774c591..000000000000 --- a/configs/mx23evk_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX23=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX23EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_NET is not set -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_CONS_INDEX=0 -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_SPLASH_SCREEN=y -CONFIG_VIDEO_BMP_GZIP=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h deleted file mode 100644 index 3f13e60531cf..000000000000 --- a/include/configs/mx23evk.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23 EVK board config - * - * Copyright (C) 2013 Otavio Salvador otavio@ossystems.com.br - * on behalf of O.S. Systems Software LTDA. - */ -#ifndef __CONFIGS_MX23EVK_H__ -#define __CONFIGS_MX23EVK_H__ - -/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_MX23EVK - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* Environment is in MMC */ - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* Framebuffer support */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_LOGO -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) -#endif - -/* Boot Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environments */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_sd_firmware_filename=u-boot.sd\0" \ - "update_sd_firmware=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_sd_firmware_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ - "fi ; " \ - "fi\0" \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttyAMA0\0" \ - "fdt_file=imx23-evk.dtb\0" \ - "fdt_addr=0x41000000\0" \ - "boot_fdt=try\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else " \ - "echo ERR: Fail to boot from MMC; " \ - "fi; " \ - "fi; " \ - "else exit; fi" - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_MX23EVK_H__ */
Hi Tom,
On Tue, Feb 9, 2021 at 10:04 AM Tom Rini trini@konsulko.com wrote:
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
I will convert this board to DM. Please don't remove it.
Thanks
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Marek Vasut marek.vasut@gmail.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-imx/mxs/Kconfig | 1 - board/olimex/mx23_olinuxino/Kconfig | 15 --- board/olimex/mx23_olinuxino/MAINTAINERS | 6 - board/olimex/mx23_olinuxino/Makefile | 10 -- board/olimex/mx23_olinuxino/mx23_olinuxino.c | 81 ------------- board/olimex/mx23_olinuxino/spl_boot.c | 120 ------------------- configs/mx23_olinuxino_defconfig | 47 -------- include/configs/mx23_olinuxino.h | 118 ------------------ 8 files changed, 398 deletions(-) delete mode 100644 board/olimex/mx23_olinuxino/Kconfig delete mode 100644 board/olimex/mx23_olinuxino/MAINTAINERS delete mode 100644 board/olimex/mx23_olinuxino/Makefile delete mode 100644 board/olimex/mx23_olinuxino/mx23_olinuxino.c delete mode 100644 board/olimex/mx23_olinuxino/spl_boot.c delete mode 100644 configs/mx23_olinuxino_defconfig delete mode 100644 include/configs/mx23_olinuxino.h
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index c731d01d4ed3..636c08b26353 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -20,7 +20,6 @@ endchoice config SYS_SOC default "mxs"
-source "board/olimex/mx23_olinuxino/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig"
endif diff --git a/board/olimex/mx23_olinuxino/Kconfig b/board/olimex/mx23_olinuxino/Kconfig deleted file mode 100644 index 0b151c9bb815..000000000000 --- a/board/olimex/mx23_olinuxino/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX23_OLINUXINO - -config SYS_BOARD - default "mx23_olinuxino" - -config SYS_VENDOR - default "olimex" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "mx23_olinuxino" - -endif diff --git a/board/olimex/mx23_olinuxino/MAINTAINERS b/board/olimex/mx23_olinuxino/MAINTAINERS deleted file mode 100644 index 25f4a10e9ae0..000000000000 --- a/board/olimex/mx23_olinuxino/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX23_OLINUXINO BOARD -M: Marek Vasut marek.vasut@gmail.com -S: Maintained -F: board/olimex/mx23_olinuxino/ -F: include/configs/mx23_olinuxino.h -F: configs/mx23_olinuxino_defconfig diff --git a/board/olimex/mx23_olinuxino/Makefile b/board/olimex/mx23_olinuxino/Makefile deleted file mode 100644 index b2ea89743440..000000000000 --- a/board/olimex/mx23_olinuxino/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := mx23_olinuxino.o -else -obj-y := spl_boot.o -endif diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c deleted file mode 100644 index f13fdb8d47e7..000000000000 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Olimex MX23 Olinuxino board - * - * Copyright (C) 2013 Marek Vasut marex@denx.de - */ - -#include <common.h> -#include <init.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx23.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#ifdef CONFIG_LED_STATUS -#include <status_led.h> -#endif -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - - return 0; -} - -#ifdef CONFIG_CMD_USB -int board_ehci_hcd_init(int port) -{ - /* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */ - gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1); - udelay(100); - return 0; -} - -int board_ehci_hcd_exit(int port) -{ - /* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */ - gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 0); - return 0; -} -#endif - -int dram_init(void) -{ - return mxs_dram_init(); -} - -#ifdef CONFIG_CMD_MMC -static int mx23_olx_mmc_cd(int id) -{ - return 1; /* Card always present */ -} - -int board_mmc_init(struct bd_info *bis) -{ - return mxsmmc_initialize(bis, 0, NULL, mx23_olx_mmc_cd); -} -#endif - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_STATE); -#endif - - return 0; -} diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c deleted file mode 100644 index 248176c23cdc..000000000000 --- a/board/olimex/mx23_olinuxino/spl_boot.c +++ /dev/null @@ -1,120 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Olimex MX23 Olinuxino Boot setup - * - * Copyright (C) 2013 Marek Vasut marex@denx.de - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx23.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_SSP (MXS_PAD_8MA | MXS_PAD_PULLUP) - -const iomux_cfg_t iomux_setup[] = { - /* DUART */ - MX23_PAD_PWM0__DUART_RX, - MX23_PAD_PWM1__DUART_TX, - - /* EMI */ - MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI, - - MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI, - MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - - MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - - /* Green LED */ - MX23_PAD_SSP1_DETECT__GPIO_2_1 | - (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL), - - /* MMC 0 */ - MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP, - - /* Ethernet */ - MX23_PAD_GPMI_ALE__GPIO_0_17 | - (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), -}; - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} - -/* Fine-tune the DRAM configuration. */ -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - /* Enable Auto Precharge. */ - dram_vals[3] |= 1 << 8; - /* Enable Fast Writes. */ - dram_vals[5] |= 1 << 8; - /* tEMRS = 3*tCK */ - dram_vals[10] &= ~(0x3 << 8); - dram_vals[10] |= (0x3 << 8); - /* CASLAT = 3*tCK */ - dram_vals[11] &= ~(0x3 << 0); - dram_vals[11] |= (0x3 << 0); - /* tCKE = 1*tCK */ - dram_vals[12] &= ~(0x7 << 0); - dram_vals[12] |= (0x1 << 0); - /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */ - dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0)); - dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0); - /* tDAL = 6*tCK */ - dram_vals[15] &= ~(0xf << 16); - dram_vals[15] |= (0x6 << 16); - /* tREF = 1040*tCK */ - dram_vals[26] &= ~0xffff; - dram_vals[26] |= 0x0410; - /* tRAS_MAX = 9334*tCK */ - dram_vals[32] &= ~0xffff; - dram_vals[32] |= 0x2475; -} diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig deleted file mode 100644 index 0da54c9e7606..000000000000 --- a/configs/mx23_olinuxino_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX23=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX23_OLINUXINO=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_LED_STATUS=y -CONFIG_LED_STATUS_GPIO=y -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=778 -CONFIG_LED_STATUS_STATE=2 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -CONFIG_LED_STATUS_CMD=y -CONFIG_MMC_MXS=y -CONFIG_CONS_INDEX=0 -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h deleted file mode 100644 index 2ee41aeff1b7..000000000000 --- a/include/configs/mx23_olinuxino.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Marek Vasut marex@denx.de - */ -#ifndef __CONFIGS_MX23_OLINUXINO_H__ -#define __CONFIGS_MX23_OLINUXINO_H__ - -/* System configurations */ -#define CONFIG_MACH_TYPE 4105 - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Status LED */ - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* Ethernet */ - -/* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_sd_firmware_filename=u-boot.sd\0" \ - "update_sd_firmware=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_sd_firmware_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ - "fi ; " \ - "fi\0" \ - "script=boot.scr\0" \ - "uimage=uImage\0" \ - "console=ttyAMA0\0" \ - "fdt_file=imx23-olinuxino.dtb\0" \ - "fdt_addr=0x41000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootm; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "usb start; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${uimage}; " \ - "if test ${boot_fdt} = yes; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;" \ - "fi; " \ - "else " \ - "bootm; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_MX23_OLINUXINO_H__ */
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Marek Vasut marek.vasut@gmail.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-imx/mxs/Kconfig | 5 - board/sandisk/sansa_fuze_plus/Kconfig | 15 - board/sandisk/sansa_fuze_plus/MAINTAINERS | 6 - board/sandisk/sansa_fuze_plus/Makefile | 10 - board/sandisk/sansa_fuze_plus/sfp.c | 390 ---------------------- board/sandisk/sansa_fuze_plus/spl_boot.c | 139 -------- configs/sansa_fuze_plus_defconfig | 46 --- include/configs/sansa_fuze_plus.h | 39 --- 8 files changed, 650 deletions(-) delete mode 100644 board/sandisk/sansa_fuze_plus/Kconfig delete mode 100644 board/sandisk/sansa_fuze_plus/MAINTAINERS delete mode 100644 board/sandisk/sansa_fuze_plus/Makefile delete mode 100644 board/sandisk/sansa_fuze_plus/sfp.c delete mode 100644 board/sandisk/sansa_fuze_plus/spl_boot.c delete mode 100644 configs/sansa_fuze_plus_defconfig delete mode 100644 include/configs/sansa_fuze_plus.h
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index 636c08b26353..bd075de2b826 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -8,10 +8,6 @@ choice prompt "MX23 board select" optional
-config TARGET_MX23_OLINUXINO - bool "Support mx23_olinuxino" - select BOARD_EARLY_INIT_F - config TARGET_SANSA_FUZE_PLUS bool "Support sansa_fuze_plus"
@@ -20,7 +16,6 @@ endchoice config SYS_SOC default "mxs"
-source "board/sandisk/sansa_fuze_plus/Kconfig"
endif
diff --git a/board/sandisk/sansa_fuze_plus/Kconfig b/board/sandisk/sansa_fuze_plus/Kconfig deleted file mode 100644 index ab4a29255cca..000000000000 --- a/board/sandisk/sansa_fuze_plus/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_SANSA_FUZE_PLUS - -config SYS_BOARD - default "sansa_fuze_plus" - -config SYS_VENDOR - default "sandisk" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "sansa_fuze_plus" - -endif diff --git a/board/sandisk/sansa_fuze_plus/MAINTAINERS b/board/sandisk/sansa_fuze_plus/MAINTAINERS deleted file mode 100644 index ccfd3997084e..000000000000 --- a/board/sandisk/sansa_fuze_plus/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SANSA_FUZE_PLUS BOARD -M: Marek Vasut marek.vasut@gmail.com -S: Maintained -F: board/sandisk/sansa_fuze_plus/ -F: include/configs/sansa_fuze_plus.h -F: configs/sansa_fuze_plus_defconfig diff --git a/board/sandisk/sansa_fuze_plus/Makefile b/board/sandisk/sansa_fuze_plus/Makefile deleted file mode 100644 index 5ac545dda341..000000000000 --- a/board/sandisk/sansa_fuze_plus/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := sfp.o -else -obj-y := spl_boot.o -endif diff --git a/board/sandisk/sansa_fuze_plus/sfp.c b/board/sandisk/sansa_fuze_plus/sfp.c deleted file mode 100644 index 42004098b377..000000000000 --- a/board/sandisk/sansa_fuze_plus/sfp.c +++ /dev/null @@ -1,390 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SanDisk Sansa Fuze Plus board - * - * Copyright (C) 2013 Marek Vasut marex@denx.de - * - * Hardware investigation done by: - * - * Amaury Pouly amaury.pouly@gmail.com - */ - -#include <common.h> -#include <errno.h> -#include <init.h> -#include <net.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx23.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -#ifdef CONFIG_CMD_MMC -static int xfi3_mmc_cd(int id) -{ - switch (id) { - case 0: - /* The SSP_DETECT is inverted on this board. */ - return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1); - case 1: - /* Internal eMMC always present */ - return 1; - default: - return 0; - } -} - -int board_mmc_init(struct bd_info *bis) -{ - int ret; - - /* MicroSD slot */ - gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1); - gpio_direction_output(MX23_PAD_GPMI_D08__GPIO_0_8, 0); - ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd); - if (ret) - return ret; - - /* Internal eMMC */ - gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0); - ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd); - - return ret; -} -#endif - -#ifdef CONFIG_VIDEO_MXS -#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -const iomux_cfg_t iomux_lcd_gpio[] = { - MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D06__GPIO_1_6 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D07__GPIO_1_7 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D08__GPIO_1_8 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D09__GPIO_1_9 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D10__GPIO_1_10 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D11__GPIO_1_11 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D12__GPIO_1_12 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D13__GPIO_1_13 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D14__GPIO_1_14 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D15__GPIO_1_15 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D16__GPIO_1_16 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D17__GPIO_1_17 | MUX_CONFIG_LCD, - MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD, - MX23_PAD_LCD_RS__GPIO_1_19 | MUX_CONFIG_LCD, - MX23_PAD_LCD_WR__GPIO_1_20 | MUX_CONFIG_LCD, - MX23_PAD_LCD_CS__GPIO_1_21 | MUX_CONFIG_LCD, - MX23_PAD_LCD_ENABLE__GPIO_1_23 | MUX_CONFIG_LCD, -}; - -const iomux_cfg_t iomux_lcd_lcd[] = { - MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, - MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, - MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD, - MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD, - MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, - MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, - MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, -}; - -static int mxsfb_read_register(uint32_t reg, uint32_t *value) -{ - iomux_cfg_t mux; - uint32_t val = 0; - int i; - - /* Mangle the register offset. */ - reg = ((reg & 0xff) << 1) | (((reg >> 8) & 0xff) << 10); - - /* - * The SmartLCD interface on MX233 can only do WRITE operation - * via the LCDIF controller. Implement the READ operation by - * fiddling with bits. - */ - mxs_iomux_setup_multiple_pads(iomux_lcd_gpio, - ARRAY_SIZE(iomux_lcd_gpio)); - - gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 1); - gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 1); - gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 1); - gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1); - - for (i = 0; i < 18; i++) { - mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); - gpio_direction_output(mux, 0); - } - - udelay(2); - gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 0); - udelay(1); - gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 0); - udelay(1); - gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 0); - udelay(1); - - for (i = 0; i < 18; i++) { - mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); - gpio_direction_output(mux, (reg >> i) & 1); - } - udelay(1); - - gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 1); - udelay(3); - - for (i = 0; i < 18; i++) { - mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); - gpio_direction_input(mux); - } - udelay(2); - - gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 0); - udelay(1); - gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 1); - udelay(1); - gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1); - udelay(3); - gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 0); - udelay(2); - - for (i = 0; i < 18; i++) { - mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); - val |= !!gpio_get_value(mux) << i; - } - udelay(1); - - gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1); - udelay(1); - gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 1); - udelay(1); - - mxs_iomux_setup_multiple_pads(iomux_lcd_lcd, - ARRAY_SIZE(iomux_lcd_lcd)); - - /* Demangle the register value. */ - *value = ((val >> 1) & 0xff) | ((val >> 2) & 0xff00); - - writel(val, 0x2000); - return 0; -} - -static int mxsfb_write_byte(uint32_t payload, const unsigned int data) -{ - struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; - const unsigned int timeout = 0x10000; - - /* What is going on here I do not know. FIXME */ - payload = ((payload & 0xff) << 1) | (((payload >> 8) & 0xff) << 10); - - if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, - timeout)) - return -ETIMEDOUT; - - writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | - (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET), - ®s->hw_lcdif_transfer_count); - - writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN, - ®s->hw_lcdif_ctrl_clr); - - if (data) - writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set); - - writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); - - if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29, - timeout)) - return -ETIMEDOUT; - - writel(payload, ®s->hw_lcdif_data); - return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, - timeout); -} - -static void mxsfb_write_register(uint32_t reg, uint32_t data) -{ - mxsfb_write_byte(reg, 0); - mxsfb_write_byte(data, 1); -} - -static const struct { - uint8_t reg; - uint8_t delay; - uint16_t val; -} lcd_regs[] = { - { 0xe5, 0 , 0x78f0 }, - { 0xe3, 0 , 0x3008 }, - { 0xe7, 0 , 0x0012 }, - { 0xef, 0 , 0x1231 }, - { 0x00, 0 , 0x0001 }, - { 0x01, 0 , 0x0100 }, - { 0x02, 0 , 0x0700 }, - { 0x03, 0 , 0x1030 }, - { 0x04, 0 , 0x0000 }, - { 0x08, 0 , 0x0207 }, - { 0x09, 0 , 0x0000 }, - { 0x0a, 0 , 0x0000 }, - { 0x0c, 0 , 0x0000 }, - { 0x0d, 0 , 0x0000 }, - { 0x0f, 0 , 0x0000 }, - { 0x10, 0 , 0x0000 }, - { 0x11, 0 , 0x0007 }, - { 0x12, 0 , 0x0000 }, - { 0x13, 20 , 0x0000 }, - /* Wait 20 mS here. */ - { 0x10, 0 , 0x1290 }, - { 0x11, 50 , 0x0007 }, - /* Wait 50 mS here. */ - { 0x12, 50 , 0x0019 }, - /* Wait 50 mS here. */ - { 0x13, 0 , 0x1700 }, - { 0x29, 50 , 0x0014 }, - /* Wait 50 mS here. */ - { 0x20, 0 , 0x0000 }, - { 0x21, 0 , 0x0000 }, - { 0x30, 0 , 0x0504 }, - { 0x31, 0 , 0x0007 }, - { 0x32, 0 , 0x0006 }, - { 0x35, 0 , 0x0106 }, - { 0x36, 0 , 0x0202 }, - { 0x37, 0 , 0x0504 }, - { 0x38, 0 , 0x0500 }, - { 0x39, 0 , 0x0706 }, - { 0x3c, 0 , 0x0204 }, - { 0x3d, 0 , 0x0202 }, - { 0x50, 0 , 0x0000 }, - { 0x51, 0 , 0x00ef }, - { 0x52, 0 , 0x0000 }, - { 0x53, 0 , 0x013f }, - { 0x60, 0 , 0xa700 }, - { 0x61, 0 , 0x0001 }, - { 0x6a, 0 , 0x0000 }, - { 0x2b, 50 , 0x000d }, - /* Wait 50 mS here. */ - { 0x90, 0 , 0x0011 }, - { 0x92, 0 , 0x0600 }, - { 0x93, 0 , 0x0003 }, - { 0x95, 0 , 0x0110 }, - { 0x97, 0 , 0x0000 }, - { 0x98, 0 , 0x0000 }, - { 0x07, 0 , 0x0173 }, -}; - -void board_mxsfb_system_setup(void) -{ - struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; - uint32_t id; - int i; - - /* Switch the LCDIF into System-Mode */ - writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE | - LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr); - - /* To program the LCD, switch to 18bit bus + 18bit data. */ - clrsetbits_le32(®s->hw_lcdif_ctrl, - LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK, - LCDIF_CTRL_WORD_LENGTH_18BIT | - LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT); - - mxsfb_read_register(0, &id); - writel(id, 0x2004); - - /* Restart the SmartLCD controller */ - mdelay(50); - writel(1, ®s->hw_lcdif_ctrl1_set); - mdelay(50); - writel(1, ®s->hw_lcdif_ctrl1_clr); - mdelay(50); - writel(1, ®s->hw_lcdif_ctrl1_set); - mdelay(50); - - /* Program the SmartLCD controller */ - writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set); - - writel((0x02 << LCDIF_TIMING_CMD_HOLD_OFFSET) | - (0x02 << LCDIF_TIMING_CMD_SETUP_OFFSET) | - (0x02 << LCDIF_TIMING_DATA_HOLD_OFFSET) | - (0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET), - ®s->hw_lcdif_timing); - - /* - * ILI9325 init and configuration sequence. - */ - for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) { - mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val); - if (lcd_regs[i].delay) - mdelay(lcd_regs[i].delay); - } - /* Turn on Framebuffer Upload Mode */ - mxsfb_write_byte(0x22, 0); - - writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT, - ®s->hw_lcdif_ctrl_set); - - /* Operate the framebuffer in 16bit mode. */ - clrsetbits_le32(®s->hw_lcdif_ctrl, - LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK, - LCDIF_CTRL_WORD_LENGTH_16BIT | - LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT); -} -#endif - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - /* Turn on PWM backlight */ - gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - usb_eth_initialize(bis); - return 0; -} diff --git a/board/sandisk/sansa_fuze_plus/spl_boot.c b/board/sandisk/sansa_fuze_plus/spl_boot.c deleted file mode 100644 index 633c77408dd6..000000000000 --- a/board/sandisk/sansa_fuze_plus/spl_boot.c +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SanDisk Sansa Fuze Plus setup - * - * Copyright (C) 2013 Marek Vasut marex@denx.de - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx23.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* EMI */ - MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI, - - MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI, - MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - - MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - - MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, - MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, - MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD, - MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD, - MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, - MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, - MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, - - MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP, - MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D08__GPIO_0_8 | MUX_CONFIG_SSP, - - MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D04__SSP2_DATA4 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D05__SSP2_DATA5 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D06__SSP2_DATA6 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_D07__SSP2_DATA7 | MUX_CONFIG_SSP, - MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP, - MX23_PAD_GPMI_WRN__SSP2_SCK | - (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL), - MX23_PAD_PWM3__GPIO_1_29 | MUX_CONFIG_SSP, - - /* PWM -- FIXME */ - MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP, -}; - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - /* mDDR configuration values */ - const uint32_t regs[] = { - 0x01010001, 0x00010000, 0x01000000, 0x00000001, - 0x00010101, 0x00000001, 0x00010000, 0x01000001, - 0x01010000, 0x00000001, 0x07000200, 0x04070203, - 0x02020002, 0x06070a02, 0x0d000201, 0x0305000d, - 0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313, - 0x03061323, 0x0000000a, 0x00080008, 0x00200020, - 0x00200020, 0x00200020, 0x000003f7, 0x00000000, - 0x00000000, 0x00000000, 0x00000020, 0x00000000, - 0x001023cd, 0x20410010, 0x00006665, 0x00000000, - 0x00000101, 0x00000001, 0x00000000, 0x00000000, - }; - memcpy(dram_vals, regs, sizeof(regs)); -} - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig deleted file mode 100644 index 69fc1b8b8598..000000000000 --- a/configs/sansa_fuze_plus_defconfig +++ /dev/null @@ -1,46 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX23=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_MEMTEST_START=0x40000000 -CONFIG_SYS_MEMTEST_END=0x40400000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_SANSA_FUZE_PLUS=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyAMA0,115200n8 " -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_CONS_INDEX=0 -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_GADGET=y -CONFIG_CI_UDC=y -CONFIG_USB_ETHER=y -CONFIG_USB_ETH_CDC=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h deleted file mode 100644 index 853a89ced129..000000000000 --- a/include/configs/sansa_fuze_plus.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Marek Vasut marex@denx.de - */ -#ifndef __CONFIGS_SANSA_FUZE_PLUS_H__ -#define __CONFIGS_SANSA_FUZE_PLUS_H__ - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* LCD */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_FONT_4X6 -#define CONFIG_VIDEO_MXS_MODE_SYSTEM -#define CONFIG_SYS_BLACK_IN_WRITE -#define LCD_BPP LCD_COLOR16 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_SANSA_FUZE_PLUS_H__ */
As there are now no boards for the MX23 family, remove the general support.
Cc: Stefano Babic sbabic@denx.de Cc: Fabio Estevam festevam@gmail.com Cc: NXP i.MX U-Boot Team uboot-imx@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/Kconfig | 8 +- arch/arm/Makefile | 2 +- arch/arm/cpu/arm926ejs/mxs/Makefile | 1 - arch/arm/cpu/arm926ejs/mxs/clock.c | 31 +- arch/arm/cpu/arm926ejs/mxs/iomux.c | 7 +- .../cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg | 5 - arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg | 7 - arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 31 +- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 85 +---- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 50 +-- arch/arm/cpu/arm926ejs/mxs/timer.c | 12 +- arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd | 18 - arch/arm/include/asm/arch-mxs/imx-regs.h | 5 - arch/arm/include/asm/arch-mxs/iomux-mx23.h | 349 ------------------ arch/arm/include/asm/arch-mxs/regs-base.h | 46 +-- .../include/asm/arch-mxs/regs-clkctrl-mx23.h | 209 ----------- .../include/asm/arch-mxs/regs-power-mx23.h | 344 ----------------- arch/arm/include/asm/arch-mxs/regs-ssp.h | 42 +-- arch/arm/include/asm/arch-mxs/regs-timrot.h | 97 +---- arch/arm/include/asm/arch-mxs/sys_proto.h | 17 +- arch/arm/include/asm/mach-imx/dma.h | 14 +- arch/arm/include/asm/mach-imx/regs-apbh.h | 115 +----- arch/arm/include/asm/mach-imx/regs-lcdif.h | 12 - arch/arm/mach-imx/mxs/Kconfig | 21 -- drivers/dma/apbh_dma.c | 5 +- drivers/gpio/mxs_gpio.c | 12 +- drivers/mmc/mxsmmc.c | 12 +- drivers/spi/mxs_spi.c | 9 +- include/configs/mxs.h | 14 +- tools/Makefile | 5 +- 30 files changed, 44 insertions(+), 1541 deletions(-) delete mode 100644 arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg delete mode 100644 arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg delete mode 100644 arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd delete mode 100644 arch/arm/include/asm/arch-mxs/iomux-mx23.h delete mode 100644 arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h delete mode 100644 arch/arm/include/asm/arch-mxs/regs-power-mx23.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 95557d6ed6bd..f2a87c3caed8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -856,12 +856,6 @@ config ARCH_IMXRT select SUPPORT_SPL imply CMD_DM
-config ARCH_MX23 - bool "NXP i.MX23 family" - select CPU_ARM926EJS - select PL011_SERIAL - select SUPPORT_SPL - config ARCH_MX25 bool "NXP MX25" select CPU_ARM926EJS @@ -2042,6 +2036,6 @@ source "arch/arm/Kconfig.debug" endmenu
config SPL_LDSCRIPT - default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK + default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if ARCH_MX28 && !SPL_FRAMEWORK default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 28b523b37c70..7c1bca7f9269 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -107,7 +107,7 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt)) +ifneq (,$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt)) libs-y += arch/arm/mach-imx/ endif else diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index f60e61e4343f..f846a5400a3d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -12,7 +12,6 @@ obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o endif
# Specify the target for use in elftosb call -MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx23.cfg MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx28.cfg
# Generate HAB-capable IVT diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index 4e1cf3a1e32b..9aa6f83bb395 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -28,9 +28,7 @@ #define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000) #define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
-#if defined(CONFIG_MX23) -#define MXC_SSPCLK_MAX MXC_SSPCLK0 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define MXC_SSPCLK_MAX MXC_SSPCLK3 #endif
@@ -113,10 +111,7 @@ static uint32_t mxs_get_gpmiclk(void) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; -#if defined(CONFIG_MX23) - uint8_t *reg = - &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]; -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) uint8_t *reg = &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]; #endif @@ -319,9 +314,7 @@ void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq) if (freq == 0) return;
-#if defined(CONFIG_MX23) - writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr); -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr); #endif
@@ -367,23 +360,7 @@ void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq)
k_best /= 1000;
-#if defined(CONFIG_MX23) - writeb(CLKCTRL_FRAC_CLKGATE, - &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]); - writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK), - &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]); - writeb(CLKCTRL_FRAC_CLKGATE, - &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]); - - writel(CLKCTRL_PIX_CLKGATE, - &clkctrl_regs->hw_clkctrl_pix_set); - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix, - CLKCTRL_PIX_DIV_MASK | CLKCTRL_PIX_CLKGATE, - k_best << CLKCTRL_PIX_DIV_OFFSET); - - while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY) - ; -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) writeb(CLKCTRL_FRAC_CLKGATE, &clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]); writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK), diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c index 381264b8a18d..d212d0fa529d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/iomux.c +++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c @@ -13,14 +13,11 @@ #include <asm/arch/iomux.h> #include <asm/arch/imx-regs.h>
-#if defined(CONFIG_MX23) -#define DRIVE_OFFSET 0x200 -#define PULL_OFFSET 0x400 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define DRIVE_OFFSET 0x300 #define PULL_OFFSET 0x600 #else -#error "Please select CONFIG_MX23 or CONFIG_MX28" +#error "Please select CONFIG_MX28" #endif
/* diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg deleted file mode 100644 index ab2183ed3795..000000000000 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg +++ /dev/null @@ -1,5 +0,0 @@ -DISPLAYPROGRESS -SECTION 0x0 BOOTABLE - TAG LAST - LOAD 0x1000 spl/u-boot-spl.bin - CALL 0x1000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg deleted file mode 100644 index e7028092a2c3..000000000000 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg +++ /dev/null @@ -1,7 +0,0 @@ -DISPLAYPROGRESS -SECTION 0x0 BOOTABLE - TAG LAST - LOAD 0x1000 spl/u-boot-spl.bin - CALL 0x1000 0x0 - LOAD 0x40002000 u-boot.bin - CALL 0x40002000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 1501d7df0dc6..d44167e4e90c 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -39,42 +39,13 @@ void early_delay(int delay) ; }
-#if defined(CONFIG_MX23) -#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -static const iomux_cfg_t iomux_boot[] = { - MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD, - MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD, - MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD, - MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD, - MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD, - MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, -}; -#endif - static uint8_t mxs_get_bootmode_index(void) { uint8_t bootmode = 0; int i; uint8_t masked;
-#if defined(CONFIG_MX23) - /* Setup IOMUX of bootmode pads to GPIO */ - mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot)); - - /* Setup bootmode pins as GPIO input */ - gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0); - gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1); - gpio_direction_input(MX23_PAD_LCD_D02__GPIO_1_2); - gpio_direction_input(MX23_PAD_LCD_D03__GPIO_1_3); - gpio_direction_input(MX23_PAD_LCD_D05__GPIO_1_5); - - /* Read bootmode pads */ - bootmode |= (gpio_get_value(MX23_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0; - bootmode |= (gpio_get_value(MX23_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1; - bootmode |= (gpio_get_value(MX23_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2; - bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3; - bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) /* The global boot mode will be detected by ROM code and its value * is stored at the fixed address 0x00019BF0 in OCRAM. */ diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index a94803ee93d9..c56b620f1ffa 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -71,21 +71,6 @@ __weak uint32_t mxs_dram_vals[] = { 0x00040004, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffffff
-/* - * i.MX23 DDR at 133MHz - */ -#elif defined(CONFIG_MX23) - 0x01010001, 0x00010100, 0x01000101, 0x00000001, - 0x00000101, 0x00000000, 0x00010000, 0x01000001, - 0x00000000, 0x00000001, 0x07000200, 0x00070202, - 0x02020000, 0x04040a01, 0x00000201, 0x02040000, - 0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313, - 0x02061521, 0x0000000a, 0x00080008, 0x00200020, - 0x00200020, 0x00200020, 0x000003f7, 0x00000000, - 0x00000000, 0x00000020, 0x00000020, 0x00c80000, - 0x000a23cd, 0x000000c8, 0x00006665, 0x00000000, - 0x00000101, 0x00040001, 0x00000000, 0x00000000, - 0x00010000 #else #error Unsupported memory initialization #endif @@ -144,10 +129,7 @@ static void mxs_mem_init_clock(void) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; -#if defined(CONFIG_MX23) - /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */ - const unsigned char divider = 33; -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ const unsigned char divider = 21; #endif @@ -247,67 +229,6 @@ uint32_t mxs_mem_get_size(void) return sz; }
-#ifdef CONFIG_MX23 -static void mx23_mem_setup_vddmem(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - debug("SPL: Setting mx23 VDDMEM\n"); - - /* We must wait before and after disabling the current limiter! */ - early_delay(10000); - - clrbits_le32(&power_regs->hw_power_vddmemctrl, - POWER_VDDMEMCTRL_ENABLE_ILIMIT); - - early_delay(10000); - -} - -static void mx23_mem_init(void) -{ - debug("SPL: Initialising mx23 SDRAM Controller\n"); - - /* - * Reset/ungate the EMI block. This is essential, otherwise the system - * suffers from memory instability. This thing is mx23 specific and is - * no longer present on mx28. - */ - mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE); - - mx23_mem_setup_vddmem(); - - /* - * Configure the DRAM registers - */ - - /* Clear START and SREFRESH bit from DRAM_CTL8 */ - clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8)); - - initialize_dram_values(); - - /* Set START bit in DRAM_CTL8 */ - setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16); - - clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); - - /* Wait for EMI_STAT bit DRAM_HALTED */ - for (;;) { - if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1))) - break; - early_delay(1000); - } - - /* Adjust EMI port priority. */ - clrsetbits_le32(0x80020000, 0x1f << 16, 0x2); - early_delay(20000); - - setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19); - setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11); -} -#endif - #ifdef CONFIG_MX28 static void mx28_mem_init(void) { @@ -349,9 +270,7 @@ void mxs_mem_init(void)
mxs_mem_setup_vdda();
-#if defined(CONFIG_MX23) - mx23_mem_init(); -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) mx28_mem_init(); #endif
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 35ea71a5ba89..095ad9230fa8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -939,13 +939,6 @@ static void mxs_power_configure_power_source(void) mxs_init_batt_bo();
mxs_switch_vddd_to_dcdc_source(); - -#ifdef CONFIG_MX23 - /* Fire up the VDDMEM LinReg now that we're all set. */ - debug("SPL: Enabling mx23 VDDMEM linear regulator\n"); - writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT, - &power_regs->hw_power_vddmemctrl); -#endif }
/** @@ -1065,9 +1058,7 @@ struct mxs_vddx_cfg { static const struct mxs_vddx_cfg mxs_vddio_cfg = { .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> hw_power_vddioctrl), -#if defined(CONFIG_MX23) - .step_mV = 25, -#else +#if defined(CONFIG_MX28) .step_mV = 50, #endif .lowest_mV = 2800, @@ -1092,21 +1083,6 @@ static const struct mxs_vddx_cfg mxs_vddd_cfg = { .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET, };
-#ifdef CONFIG_MX23 -static const struct mxs_vddx_cfg mxs_vddmem_cfg = { - .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> - hw_power_vddmemctrl), - .step_mV = 50, - .lowest_mV = 1700, - .powered_by_linreg = NULL, - .trg_mask = POWER_VDDMEMCTRL_TRG_MASK, - .bo_irq = 0, - .bo_enirq = 0, - .bo_offset_mask = 0, - .bo_offset_offset = 0, -}; -#endif - /** * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail * @cfg: Configuration data of the DC-DC converter rail @@ -1210,24 +1186,6 @@ static void mxs_setup_batt_detect(void) early_delay(10); }
-/** - * mxs_ungate_power() - Ungate the POWER block - * - * This function ungates clock to the power block. In case the power block - * was still gated at this point, it will not be possible to configure the - * block and therefore the power initialization would fail. This function - * is only needed on i.MX233, on i.MX28 the power block is always ungated. - */ -static void mxs_ungate_power(void) -{ -#ifdef CONFIG_MX23 - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr); -#endif -} - /** * mxs_power_init() - The power block init main function * @@ -1241,8 +1199,6 @@ void mxs_power_init(void)
debug("SPL: Initialising Power Block\n");
- mxs_ungate_power(); - mxs_power_clock2xtal(); mxs_power_set_auto_restart(); mxs_power_set_linreg(); @@ -1258,10 +1214,6 @@ void mxs_power_init(void)
debug("SPL: Setting VDDD to 1V55 (brownout @ 1v400)\n"); mxs_power_set_vddx(&mxs_vddd_cfg, 1550, 1400); -#ifdef CONFIG_MX23 - debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n"); - mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700); -#endif writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ | POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c index 5ab4ed0c5a3d..a5dd9a838e87 100644 --- a/arch/arm/cpu/arm926ejs/mxs/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@ -18,9 +18,7 @@ #include <linux/delay.h>
/* Maximum fixed count */ -#if defined(CONFIG_MX23) -#define TIMER_LOAD_VAL 0xffff -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMER_LOAD_VAL 0xffffffff #endif
@@ -59,9 +57,7 @@ int timer_init(void) mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
/* Set fixed_count to 0 */ -#if defined(CONFIG_MX23) - writel(0, &timrot_regs->hw_timrot_timcount0); -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) writel(0, &timrot_regs->hw_timrot_fixed_count0); #endif
@@ -71,9 +67,7 @@ int timer_init(void) &timrot_regs->hw_timrot_timctrl0);
/* Set fixed_count to maximal value */ -#if defined(CONFIG_MX23) - writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0); -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); #endif
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd deleted file mode 100644 index 3a51879d5e4a..000000000000 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd +++ /dev/null @@ -1,18 +0,0 @@ -options { - driveTag = 0x00; - flags = 0x01; -} - -sources { - u_boot_spl="spl/u-boot-spl.bin"; - u_boot="u-boot.bin"; -} - -section (0) { - load u_boot_spl > 0x0000; - load ivt (entry = 0x0014) > 0x8000; - call 0x8000; - - load u_boot > 0x40000100; - call 0x40000100; -} diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h index f853c484be7d..c099c65c9608 100644 --- a/arch/arm/include/asm/arch-mxs/imx-regs.h +++ b/arch/arm/include/asm/arch-mxs/imx-regs.h @@ -25,11 +25,6 @@ #include <asm/arch/regs-usb.h> #include <asm/arch/regs-usbphy.h>
-#ifdef CONFIG_MX23 -#include <asm/arch/regs-clkctrl-mx23.h> -#include <asm/arch/regs-power-mx23.h> -#endif - #ifdef CONFIG_MX28 #include <asm/arch/regs-clkctrl-mx28.h> #include <asm/arch/regs-power-mx28.h> diff --git a/arch/arm/include/asm/arch-mxs/iomux-mx23.h b/arch/arm/include/asm/arch-mxs/iomux-mx23.h deleted file mode 100644 index 2706efa750a2..000000000000 --- a/arch/arm/include/asm/arch-mxs/iomux-mx23.h +++ /dev/null @@ -1,349 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009-2010 Amit Kucheria amit.kucheria@canonical.com - * Copyright (C) 2010 Freescale Semiconductor, Inc. - */ - -#ifndef __MACH_IOMUX_MX23_H__ -#define __MACH_IOMUX_MX23_H__ - -#include <asm/arch/iomux.h> - -/* - * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * See also iomux.h - * - * BANK PIN MUX - */ -/* MUXSEL_0 */ -#define MX23_PAD_GPMI_D00__GPMI_D00 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D01__GPMI_D01 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D02__GPMI_D02 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D03__GPMI_D03 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D04__GPMI_D04 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D05__GPMI_D05 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D06__GPMI_D06 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D08__GPMI_D08 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D09__GPMI_D09 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D10__GPMI_D10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D11__GPMI_D11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D12__GPMI_D12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D13__GPMI_D13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D14__GPMI_D14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D15__GPMI_D15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_WPN__GPMI_WPN MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0) -#define MX23_PAD_I2C_SCL__I2C_SCL MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0) -#define MX23_PAD_I2C_SDA__I2C_SDA MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0) - -#define MX23_PAD_LCD_D00__LCD_D00 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D01__LCD_D01 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D02__LCD_D02 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D03__LCD_D03 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D04__LCD_D04 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D05__LCD_D05 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D06__LCD_D06 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D08__LCD_D08 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D09__LCD_D09 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) -#define MX23_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) -#define MX23_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) -#define MX23_PAD_LCD_WR__LCD_WR MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) -#define MX23_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) -#define MX23_PAD_LCD_DOTCK__LCD_DOTCK MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) -#define MX23_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) -#define MX23_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) -#define MX23_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) -#define MX23_PAD_PWM0__PWM0 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) -#define MX23_PAD_PWM1__PWM1 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) -#define MX23_PAD_PWM2__PWM2 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) -#define MX23_PAD_PWM3__PWM3 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) -#define MX23_PAD_PWM4__PWM4 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) - -#define MX23_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DETECT__SSP1_DETECT MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) -#define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) -#define MX23_PAD_ROTARYB__ROTARYB MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A00__EMI_A00 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A01__EMI_A01 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A02__EMI_A02 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A03__EMI_A03 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A04__EMI_A04 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A05__EMI_A05 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A06__EMI_A06 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A07__EMI_A07 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A08__EMI_A08 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A09__EMI_A09 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A10__EMI_A10 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A11__EMI_A11 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A12__EMI_A12 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) -#define MX23_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0) -#define MX23_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0) -#define MX23_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0) -#define MX23_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0) - -#define MX23_PAD_EMI_D00__EMI_D00 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D01__EMI_D01 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D02__EMI_D02 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D03__EMI_D03 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D04__EMI_D04 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D05__EMI_D05 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D06__EMI_D06 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D08__EMI_D08 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D09__EMI_D09 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D10__EMI_D10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D11__EMI_D11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D12__EMI_D12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D13__EMI_D13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D14__EMI_D14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D15__EMI_D15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CLKN__EMI_CLKN MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) - -/* MUXSEL_1 */ -#define MX23_PAD_GPMI_D00__LCD_D8 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D01__LCD_D9 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D02__LCD_D10 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D03__LCD_D11 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D04__LCD_D12 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D05__LCD_D13 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D06__LCD_D14 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D08__LCD_D18 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D09__LCD_D19 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D10__LCD_D20 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D11__LCD_D21 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D12__LCD_D22 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D13__LCD_D23 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D14__AUART2_RX MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D15__AUART2_TX MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_CLE__LCD_D16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_ALE__LCD_D17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_CE2N__ATA_A2 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_RTS__IR_CLK MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_RX__IR_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_TX__IR_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1) -#define MX23_PAD_I2C_SCL__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1) -#define MX23_PAD_I2C_SDA__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1) - -#define MX23_PAD_LCD_D00__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D01__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D02__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D03__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D04__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D05__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D06__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D08__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D09__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D10__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D11__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D12__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D13__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D14__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D15__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1) -#define MX23_PAD_LCD_RESET__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1) -#define MX23_PAD_LCD_RS__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1) -#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) -#define MX23_PAD_LCD_ENABLE__I2C_SCL MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) -#define MX23_PAD_LCD_HSYNC__I2C_SDA MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) -#define MX23_PAD_LCD_VSYNC__LCD_BUSY MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) -#define MX23_PAD_PWM0__ROTARYA MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) -#define MX23_PAD_PWM1__ROTARYB MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) -#define MX23_PAD_PWM2__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) -#define MX23_PAD_PWM3__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) -#define MX23_PAD_PWM4__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) - -#define MX23_PAD_SSP1_DETECT__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_1) -#define MX23_PAD_SSP1_DATA1__I2C_SCL MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_1) -#define MX23_PAD_SSP1_DATA2__I2C_SDA MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) -#define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) -#define MX23_PAD_ROTARYB__AUART2_CTS MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_1) - -/* MUXSEL_2 */ -#define MX23_PAD_GPMI_D00__SSP2_DATA0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D01__SSP2_DATA1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D02__SSP2_DATA2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D03__SSP2_DATA3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D04__SSP2_DATA4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D05__SSP2_DATA5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D06__SSP2_DATA6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D08__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D09__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D10__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D11__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D15__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_RDY0__SSP2_DETECT MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_RDY1__SSP2_CMD MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_WRN__SSP2_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_CTS__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_RTS__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_RX__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_TX__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2) -#define MX23_PAD_I2C_SCL__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2) -#define MX23_PAD_I2C_SDA__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2) - -#define MX23_PAD_LCD_D08__SAIF2_SDATA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D09__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D11__SAIF_LRCLK MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D12__SAIF2_SDATA1 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D13__SAIF2_SDATA2 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D14__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D15__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) -#define MX23_PAD_LCD_RESET__GPMI_CE3N MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) -#define MX23_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2) -#define MX23_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2) -#define MX23_PAD_PWM3__AUART1_CTS MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) -#define MX23_PAD_PWM4__AUART1_RTS MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) - -#define MX23_PAD_SSP1_CMD__JTAG_TDO MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DETECT__USB_OTG_ID MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA0__JTAG_TDI MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA1__JTAG_TCLK MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA2__JTAG_RTCK MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA3__JTAG_TMS MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_SCK__JTAG_TRST MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_2) -#define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2) -#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) - -/* MUXSEL_GPIO */ -#define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) - -#define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) - -#define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) - -#endif /* __MACH_IOMUX_MX23_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-base.h b/arch/arm/include/asm/arch-mxs/regs-base.h index 44d40cade879..c016d1b25534 100644 --- a/arch/arm/include/asm/arch-mxs/regs-base.h +++ b/arch/arm/include/asm/arch-mxs/regs-base.h @@ -14,52 +14,10 @@ #ifndef __MXS_REGS_BASE_H__ #define __MXS_REGS_BASE_H__
-/* - * Register base addresses for i.MX23 - */ -#if defined(CONFIG_MX23) -#define MXS_ICOLL_BASE 0x80000000 -#define MXS_APBH_BASE 0x80004000 -#define MXS_ECC8_BASE 0x80008000 -#define MXS_BCH_BASE 0x8000A000 -#define MXS_GPMI_BASE 0x8000C000 -#define MXS_SSP0_BASE 0x80010000 -#define MXS_SSP1_BASE 0x80034000 -#define MXS_ETM_BASE 0x80014000 -#define MXS_PINCTRL_BASE 0x80018000 -#define MXS_DIGCTL_BASE 0x8001C000 -#define MXS_EMI_BASE 0x80020000 -#define MXS_APBX_BASE 0x80024000 -#define MXS_DCP_BASE 0x80028000 -#define MXS_PXP_BASE 0x8002A000 -#define MXS_OCOTP_BASE 0x8002C000 -#define MXS_AXI_BASE 0x8002E000 -#define MXS_LCDIF_BASE 0x80030000 -#define MXS_SSP1_BASE 0x80034000 -#define MXS_TVENC_BASE 0x80038000 -#define MXS_CLKCTRL_BASE 0x80040000 -#define MXS_SAIF0_BASE 0x80042000 -#define MXS_POWER_BASE 0x80044000 -#define MXS_SAIF1_BASE 0x80046000 -#define MXS_AUDIOOUT_BASE 0x80048000 -#define MXS_AUDIOIN_BASE 0x8004C000 -#define MXS_LRADC_BASE 0x80050000 -#define MXS_SPDIF_BASE 0x80054000 -#define MXS_I2C0_BASE 0x80058000 -#define MXS_RTC_BASE 0x8005C000 -#define MXS_PWM_BASE 0x80064000 -#define MXS_TIMROT_BASE 0x80068000 -#define MXS_UARTAPP0_BASE 0x8006C000 -#define MXS_UARTAPP1_BASE 0x8006E000 -#define MXS_UARTDBG_BASE 0x80070000 -#define MXS_USBPHY0_BASE 0x8007C000 -#define MXS_USBCTRL0_BASE 0x80080000 -#define MXS_DRAM_BASE 0x800E0000 - /* * Register base addresses for i.MX28 */ -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define MXS_ICOL_BASE 0x80000000 #define MXS_HSADC_BASE 0x80002000 #define MXS_APBH_BASE 0x80004000 @@ -114,7 +72,7 @@ #define MXS_ENET0_BASE 0x800F0000 #define MXS_ENET1_BASE 0x800F4000 #else -#error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28 +#error Unkown SoC. Please set CONFIG_MX28 #endif
#endif /* __MXS_REGS_BASE_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h deleted file mode 100644 index 50fdc9cd0326..000000000000 --- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h +++ /dev/null @@ -1,209 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23 CLKCTRL Register Definitions - * - * Copyright (C) 2012 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX23_REGS_CLKCTRL_H__ -#define __MX23_REGS_CLKCTRL_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_clkctrl_regs { - mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ - uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */ - uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */ - mxs_reg_32(hw_clkctrl_cpu) /* 0x20 */ - mxs_reg_32(hw_clkctrl_hbus) /* 0x30 */ - mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */ - mxs_reg_32(hw_clkctrl_xtal) /* 0x50 */ - mxs_reg_32(hw_clkctrl_pix) /* 0x60 */ - uint32_t hw_clkctrl_ssp0; /* 0x70 */ - uint32_t reserved_ssp0[3]; /* 0x74-0x7c */ - uint32_t hw_clkctrl_gpmi; /* 0x80 */ - uint32_t reserved_gpmi[3]; /* 0x84-0x8c */ - mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */ - mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */ - - uint32_t reserved1[4]; - - mxs_reg_32(hw_clkctrl_saif0) /* 0xc0 */ - mxs_reg_32(hw_clkctrl_tv) /* 0xd0 */ - mxs_reg_32(hw_clkctrl_etm) /* 0xe0 */ - mxs_reg_8(hw_clkctrl_frac0) /* 0xf0 */ - mxs_reg_8(hw_clkctrl_frac1) /* 0x100 */ - mxs_reg_32(hw_clkctrl_clkseq) /* 0x110 */ - mxs_reg_32(hw_clkctrl_reset) /* 0x120 */ - mxs_reg_32(hw_clkctrl_status) /* 0x130 */ - mxs_reg_32(hw_clkctrl_version) /* 0x140 */ -}; -#endif - -#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL0CTRL0_POWER (1 << 16) - -#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 - -#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) -#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) -#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) -#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 -#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) -#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) -#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f -#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 - -#define CLKCTRL_HBUS_BUSY (1 << 29) -#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 28) -#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 27) -#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) -#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) -#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) -#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) -#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) -#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) -#define CLKCTRL_HBUS_AUTO_SLOW_MODE (1 << 20) -#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 -#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) -#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) -#define CLKCTRL_HBUS_DIV_MASK 0x1f -#define CLKCTRL_HBUS_DIV_OFFSET 0 - -#define CLKCTRL_XBUS_BUSY (1 << 31) -#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_XBUS_DIV_MASK 0x3ff -#define CLKCTRL_XBUS_DIV_OFFSET 0 - -#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) -#define CLKCTRL_XTAL_FILT_CLK24M_GATE (1 << 30) -#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) -#define CLKCTRL_XTAL_DRI_CLK24M_GATE (1 << 28) -#define CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE (1 << 27) -#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) -#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 -#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 - -#define CLKCTRL_PIX_CLKGATE (1 << 31) -#define CLKCTRL_PIX_BUSY (1 << 29) -#define CLKCTRL_PIX_DIV_FRAC_EN (1 << 12) -#define CLKCTRL_PIX_DIV_MASK 0xfff -#define CLKCTRL_PIX_DIV_OFFSET 0 - -#define CLKCTRL_SSP_CLKGATE (1 << 31) -#define CLKCTRL_SSP_BUSY (1 << 29) -#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) -#define CLKCTRL_SSP_DIV_MASK 0x1ff -#define CLKCTRL_SSP_DIV_OFFSET 0 - -#define CLKCTRL_GPMI_CLKGATE (1 << 31) -#define CLKCTRL_GPMI_BUSY (1 << 29) -#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_GPMI_DIV_MASK 0x3ff -#define CLKCTRL_GPMI_DIV_OFFSET 0 - -#define CLKCTRL_SPDIF_CLKGATE (1 << 31) - -#define CLKCTRL_EMI_CLKGATE (1 << 31) -#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) -#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) -#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) -#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) -#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) -#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) -#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) -#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 -#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f -#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 - -#define CLKCTRL_IR_CLKGATE (1 << 31) -#define CLKCTRL_IR_AUTO_DIV (1 << 29) -#define CLKCTRL_IR_IR_BUSY (1 << 28) -#define CLKCTRL_IR_IROV_BUSY (1 << 27) -#define CLKCTRL_IR_IROV_DIV_MASK (0x1ff << 16) -#define CLKCTRL_IR_IROV_DIV_OFFSET 16 -#define CLKCTRL_IR_IR_DIV_MASK 0x3ff -#define CLKCTRL_IR_IR_DIV_OFFSET 0 - -#define CLKCTRL_SAIF0_CLKGATE (1 << 31) -#define CLKCTRL_SAIF0_BUSY (1 << 29) -#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF0_DIV_MASK 0xffff -#define CLKCTRL_SAIF0_DIV_OFFSET 0 - -#define CLKCTRL_TV_CLK_TV108M_GATE (1 << 31) -#define CLKCTRL_TV_CLK_TV_GATE (1 << 30) - -#define CLKCTRL_ETM_CLKGATE (1 << 31) -#define CLKCTRL_ETM_BUSY (1 << 29) -#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 6) -#define CLKCTRL_ETM_DIV_MASK 0x3f -#define CLKCTRL_ETM_DIV_OFFSET 0 - -#define CLKCTRL_FRAC_CLKGATE (1 << 7) -#define CLKCTRL_FRAC_STABLE (1 << 6) -#define CLKCTRL_FRAC_FRAC_MASK 0x3f -#define CLKCTRL_FRAC_FRAC_OFFSET 0 -#define CLKCTRL_FRAC0_CPU 0 -#define CLKCTRL_FRAC0_EMI 1 -#define CLKCTRL_FRAC0_PIX 2 -#define CLKCTRL_FRAC0_IO0 3 -#define CLKCTRL_FRAC1_VID 3 - -#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) -#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7) -#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6) -#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 5) -#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4) -#define CLKCTRL_CLKSEQ_BYPASS_IR (1 << 3) -#define CLKCTRL_CLKSEQ_BYPASS_PIX (1 << 1) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF (1 << 0) - -#define CLKCTRL_RESET_CHIP (1 << 1) -#define CLKCTRL_RESET_DIG (1 << 0) - -#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) -#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 - -#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) -#define CLKCTRL_VERSION_MAJOR_OFFSET 24 -#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) -#define CLKCTRL_VERSION_MINOR_OFFSET 16 -#define CLKCTRL_VERSION_STEP_MASK 0xffff -#define CLKCTRL_VERSION_STEP_OFFSET 0 - -#endif /* __MX23_REGS_CLKCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h deleted file mode 100644 index a0dc78102301..000000000000 --- a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h +++ /dev/null @@ -1,344 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23 Power Controller Register Definitions - * - * Copyright (C) 2012 Marek Vasut marex@denx.de - */ - -#ifndef __MX23_REGS_POWER_H__ -#define __MX23_REGS_POWER_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_power_regs { - mxs_reg_32(hw_power_ctrl) - mxs_reg_32(hw_power_5vctrl) - mxs_reg_32(hw_power_minpwr) - mxs_reg_32(hw_power_charge) - uint32_t hw_power_vdddctrl; - uint32_t reserved_vddd[3]; - uint32_t hw_power_vddactrl; - uint32_t reserved_vdda[3]; - uint32_t hw_power_vddioctrl; - uint32_t reserved_vddio[3]; - uint32_t hw_power_vddmemctrl; - uint32_t reserved_vddmem[3]; - uint32_t hw_power_dcdc4p2; - uint32_t reserved_dcdc4p2[3]; - uint32_t hw_power_misc; - uint32_t reserved_misc[3]; - uint32_t hw_power_dclimits; - uint32_t reserved_dclimits[3]; - mxs_reg_32(hw_power_loopctrl) - uint32_t hw_power_sts; - uint32_t reserved_sts[3]; - mxs_reg_32(hw_power_speed) - uint32_t hw_power_battmonitor; - uint32_t reserved_battmonitor[3]; - - uint32_t reserved1[4]; - - mxs_reg_32(hw_power_reset) - - uint32_t reserved2[4]; - - mxs_reg_32(hw_power_special) - mxs_reg_32(hw_power_version) -}; -#endif - -#define POWER_CTRL_CLKGATE (1 << 30) -#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) -#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) -#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) -#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) -#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) -#define POWER_CTRL_PSWITCH_IRQ (1 << 20) -#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) -#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) -#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) -#define POWER_CTRL_POLARITY_DC_OK (1 << 16) -#define POWER_CTRL_DC_OK_IRQ (1 << 15) -#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) -#define POWER_CTRL_BATT_BO_IRQ (1 << 13) -#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) -#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) -#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) -#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) -#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) -#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) -#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) -#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) -#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) -#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) -#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) -#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) -#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) - -#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 28 -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 28) -#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) -#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 -#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x1 << 20) -#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 -#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 -#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) -#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) -#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) -#define POWER_5VCTRL_DCDC_XFER (1 << 5) -#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) -#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) -#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) -#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) -#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) - -#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) -#define POWER_MINPWR_VDAC_DUMP_CTRL (1 << 13) -#define POWER_MINPWR_PWD_BO (1 << 12) -#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) -#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) -#define POWER_MINPWR_ENABLE_OSC (1 << 9) -#define POWER_MINPWR_SELECT_OSC (1 << 8) -#define POWER_MINPWR_VBG_OFF (1 << 7) -#define POWER_MINPWR_DOUBLE_FETS (1 << 6) -#define POWER_MINPWR_HALFFETS (1 << 5) -#define POWER_MINPWR_LESSANA_I (1 << 4) -#define POWER_MINPWR_PWD_XTAL24 (1 << 3) -#define POWER_MINPWR_DC_STOPCLK (1 << 2) -#define POWER_MINPWR_EN_DC_PFM (1 << 1) -#define POWER_MINPWR_DC_HALFCLK (1 << 0) - -#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) -#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 -#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) -#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) -#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) -#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) -#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) -#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) -#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) -#define POWER_CHARGE_ENABLE_LOAD (1 << 22) -#define POWER_CHARGE_ENABLE_CHARGER_RESISTORS (1 << 21) -#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) -#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) -#define POWER_CHARGE_USE_EXTERN_R (1 << 17) -#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) -#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) -#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 -#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) -#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) -#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) -#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) -#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f -#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 -#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 -#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 -#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 -#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 -#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 -#define POWER_CHARGE_BATTCHRG_I_400MA 0x20 - -#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) -#define POWER_VDDDCTRL_ADJTN_OFFSET 28 -#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) -#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) -#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) -#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) -#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 -#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) -#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDDCTRL_TRG_MASK 0x1f -#define POWER_VDDDCTRL_TRG_OFFSET 0 - -#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) -#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) -#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) -#define POWER_VDDACTRL_DISABLE_FET (1 << 16) -#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDACTRL_TRG_MASK 0x1f -#define POWER_VDDACTRL_TRG_OFFSET 0 - -#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) -#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 -#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) -#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) -#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) -#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDIOCTRL_TRG_MASK 0x1f -#define POWER_VDDIOCTRL_TRG_OFFSET 0 - -#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) -#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) -#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) -#define POWER_VDDMEMCTRL_TRG_MASK 0x1f -#define POWER_VDDMEMCTRL_TRG_OFFSET 0 - -#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 -#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) -#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) -#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 -#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) -#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) -#define POWER_DCDC4P2_HYST_DIR (1 << 21) -#define POWER_DCDC4P2_HYST_THRESH (1 << 20) -#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) -#define POWER_DCDC4P2_TRG_OFFSET 16 -#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) -#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) -#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) -#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) -#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) -#define POWER_DCDC4P2_BO_MASK (0x1f << 8) -#define POWER_DCDC4P2_BO_OFFSET 8 -#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f -#define POWER_DCDC4P2_CMPTRIP_OFFSET 0 - -#define POWER_MISC_FREQSEL_MASK (0x7 << 4) -#define POWER_MISC_FREQSEL_OFFSET 4 -#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) -#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) -#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) -#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) -#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) -#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) -#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) -#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) -#define POWER_MISC_DELAY_TIMING (1 << 2) -#define POWER_MISC_TEST (1 << 1) -#define POWER_MISC_SEL_PLLCLK (1 << 0) - -#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) -#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 -#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f -#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 - -#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) -#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) -#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) -#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) -#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) -#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) -#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) -#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 -#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) -#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) -#define POWER_LOOPCTRL_DC_FF_OFFSET 8 -#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) -#define POWER_LOOPCTRL_DC_R_OFFSET 4 -#define POWER_LOOPCTRL_DC_C_MASK 0x3 -#define POWER_LOOPCTRL_DC_C_OFFSET 0 -#define POWER_LOOPCTRL_DC_C_MAX 0x0 -#define POWER_LOOPCTRL_DC_C_2X 0x1 -#define POWER_LOOPCTRL_DC_C_4X 0x2 -#define POWER_LOOPCTRL_DC_C_MIN 0x3 - -#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) -#define POWER_STS_PWRUP_SOURCE_OFFSET 24 -#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) -#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) -#define POWER_STS_PSWITCH_MASK (0x3 << 20) -#define POWER_STS_PSWITCH_OFFSET 20 -#define POWER_STS_AVALID0_STATUS (1 << 17) -#define POWER_STS_BVALID0_STATUS (1 << 16) -#define POWER_STS_VBUSVALID0_STATUS (1 << 15) -#define POWER_STS_SESSEND0_STATUS (1 << 14) -#define POWER_STS_BATT_BO (1 << 13) -#define POWER_STS_VDD5V_FAULT (1 << 12) -#define POWER_STS_CHRGSTS (1 << 11) -#define POWER_STS_DCDC_4P2_BO (1 << 10) -#define POWER_STS_DC_OK (1 << 9) -#define POWER_STS_VDDIO_BO (1 << 8) -#define POWER_STS_VDDA_BO (1 << 7) -#define POWER_STS_VDDD_BO (1 << 6) -#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) -#define POWER_STS_VDD5V_DROOP (1 << 4) -#define POWER_STS_AVALID0 (1 << 3) -#define POWER_STS_BVALID0 (1 << 2) -#define POWER_STS_VBUSVALID0 (1 << 1) -#define POWER_STS_SESSEND0 (1 << 0) - -#define POWER_SPEED_STATUS_MASK (0xff << 16) -#define POWER_SPEED_STATUS_OFFSET 16 -#define POWER_SPEED_CTRL_MASK 0x3 -#define POWER_SPEED_CTRL_OFFSET 0 -#define POWER_SPEED_CTRL_SS_OFF 0x0 -#define POWER_SPEED_CTRL_SS_ON 0x1 -#define POWER_SPEED_CTRL_SS_ENABLE 0x3 - -#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) -#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 -#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) -#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) -#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f -#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 - -#define POWER_RESET_UNLOCK_MASK (0xffff << 16) -#define POWER_RESET_UNLOCK_OFFSET 16 -#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) -#define POWER_RESET_PWD_OFF (1 << 1) -#define POWER_RESET_PWD (1 << 0) - -#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) -#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) -#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) -#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) - -#define POWER_SPECIAL_TEST_MASK 0xffffffff -#define POWER_SPECIAL_TEST_OFFSET 0 - -#define POWER_VERSION_MAJOR_MASK (0xff << 24) -#define POWER_VERSION_MAJOR_OFFSET 24 -#define POWER_VERSION_MINOR_MASK (0xff << 16) -#define POWER_VERSION_MINOR_OFFSET 16 -#define POWER_VERSION_STEP_MASK 0xffff -#define POWER_VERSION_STEP_OFFSET 0 - -#endif /* __MX23_REGS_POWER_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h index eeb7e7f44c06..26e620f93802 100644 --- a/arch/arm/include/asm/arch-mxs/regs-ssp.h +++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h @@ -14,28 +14,7 @@ #include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__ -#if defined(CONFIG_MX23) -struct mxs_ssp_regs { - mxs_reg_32(hw_ssp_ctrl0) - mxs_reg_32(hw_ssp_cmd0) - mxs_reg_32(hw_ssp_cmd1) - mxs_reg_32(hw_ssp_compref) - mxs_reg_32(hw_ssp_compmask) - mxs_reg_32(hw_ssp_timing) - mxs_reg_32(hw_ssp_ctrl1) - mxs_reg_32(hw_ssp_data) - mxs_reg_32(hw_ssp_sdresp0) - mxs_reg_32(hw_ssp_sdresp1) - mxs_reg_32(hw_ssp_sdresp2) - mxs_reg_32(hw_ssp_sdresp3) - mxs_reg_32(hw_ssp_status) - - uint32_t reserved1[12]; - - mxs_reg_32(hw_ssp_debug) - mxs_reg_32(hw_ssp_version) -}; -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) struct mxs_ssp_regs { mxs_reg_32(hw_ssp_ctrl0) mxs_reg_32(hw_ssp_cmd0) @@ -62,9 +41,7 @@ struct mxs_ssp_regs {
static inline int mxs_ssp_bus_id_valid(int bus) { -#if defined(CONFIG_MX23) - const unsigned int mxs_ssp_chan_count = 2; -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) const unsigned int mxs_ssp_chan_count = 4; #endif
@@ -79,9 +56,7 @@ static inline int mxs_ssp_bus_id_valid(int bus)
static inline int mxs_ssp_clock_by_bus(unsigned int clock) { -#if defined(CONFIG_MX23) - return 0; -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) return clock; #endif } @@ -125,11 +100,6 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) #define SSP_CTRL0_GET_RESP (1 << 17) #define SSP_CTRL0_ENABLE (1 << 16)
-#ifdef CONFIG_MX23 -#define SSP_CTRL0_XFER_COUNT_OFFSET 0 -#define SSP_CTRL0_XFER_COUNT_MASK 0xffff -#endif - #define SSP_CMD0_SOFT_TERMINATE (1 << 26) #define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) #define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) @@ -137,12 +107,6 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) #define SSP_CMD0_SLOW_CLKING_EN (1 << 22) #define SSP_CMD0_CONT_CLKING_EN (1 << 21) #define SSP_CMD0_APPEND_8CYC (1 << 20) -#if defined(CONFIG_MX23) -#define SSP_CMD0_BLOCK_SIZE_MASK (0xf << 16) -#define SSP_CMD0_BLOCK_SIZE_OFFSET 16 -#define SSP_CMD0_BLOCK_COUNT_MASK (0xff << 8) -#define SSP_CMD0_BLOCK_COUNT_OFFSET 8 -#endif #define SSP_CMD0_CMD_MASK 0xff #define SSP_CMD0_CMD_OFFSET 0 #define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00 diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h index 9e19aabf114a..83ac268f70c0 100644 --- a/arch/arm/include/asm/arch-mxs/regs-timrot.h +++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h @@ -17,16 +17,7 @@ struct mxs_timrot_regs { mxs_reg_32(hw_timrot_rotctrl) mxs_reg_32(hw_timrot_rotcount) -#if defined(CONFIG_MX23) - mxs_reg_32(hw_timrot_timctrl0) - mxs_reg_32(hw_timrot_timcount0) - mxs_reg_32(hw_timrot_timctrl1) - mxs_reg_32(hw_timrot_timcount1) - mxs_reg_32(hw_timrot_timctrl2) - mxs_reg_32(hw_timrot_timcount2) - mxs_reg_32(hw_timrot_timctrl3) - mxs_reg_32(hw_timrot_timcount3) -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) mxs_reg_32(hw_timrot_timctrl0) mxs_reg_32(hw_timrot_running_count0) mxs_reg_32(hw_timrot_fixed_count0) @@ -68,9 +59,7 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) #define TIMROT_ROTCTRL_POLARITY_B (1 << 9) #define TIMROT_ROTCTRL_POLARITY_A (1 << 8) -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4) -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) #endif #define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 @@ -80,19 +69,14 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4) -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) #define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) #define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) #endif -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_A_MASK 0x7 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_A_MASK 0xf #endif #define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 @@ -102,10 +86,7 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 #define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 #define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6 -#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 #define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 #define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 @@ -138,15 +119,7 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 #define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 #define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6 -#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7 -#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8 -#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9 -#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa -#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb -#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 #define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 #define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 @@ -159,18 +132,12 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf #endif
-#if defined(CONFIG_MX23) -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16) -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 #endif
-#if defined(CONFIG_MX23) -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff #define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 #endif @@ -188,15 +155,7 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16) -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) @@ -208,45 +167,7 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) #endif -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_IRQ (1 << 15) -#define TIMROT_TIMCTRL3_IRQ_EN (1 << 14) -#define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10) -#endif #define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8) -#define TIMROT_TIMCTRL3_POLARITY_OFFSET 8 -#define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8) -#define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8) -#define TIMROT_TIMCTRL3_UPDATE (1 << 7) -#define TIMROT_TIMCTRL3_RELOAD (1 << 6) -#define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4 -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4) -#define TIMROT_TIMCTRL3_SELECT_MASK 0xf -#define TIMROT_TIMCTRL3_SELECT_OFFSET 0 -#define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0 -#define TIMROT_TIMCTRL3_SELECT_PWM0 0x1 -#define TIMROT_TIMCTRL3_SELECT_PWM1 0x2 -#define TIMROT_TIMCTRL3_SELECT_PWM2 0x3 -#define TIMROT_TIMCTRL3_SELECT_PWM3 0x4 -#define TIMROT_TIMCTRL3_SELECT_PWM4 0x5 -#define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6 -#define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7 -#define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8 -#define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9 -#define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa -#define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb -#define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc -#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16) -#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16 -#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff -#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0 -#endif
#define TIMROT_VERSION_MAJOR_MASK (0xff << 24) #define TIMROT_VERSION_MAJOR_OFFSET 24 diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 20ee863ac7e7..5d86d6b28312 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -16,9 +16,7 @@ int mxsmmc_initialize(struct bd_info *bis, int id, int (*wp)(int),
#ifdef CONFIG_SPL_BUILD
-#if defined(CONFIG_MX23) -#include <asm/arch/iomux-mx23.h> -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #include <asm/arch/iomux-mx28.h> #endif
@@ -36,18 +34,7 @@ struct mxs_pair { };
static const struct mxs_pair mxs_boot_modes[] = { -#if defined(CONFIG_MX23) - { 0x00, 0x0f, "USB" }, - { 0x01, 0x1f, "I2C, master" }, - { 0x02, 0x1f, "SSP SPI #1, master, NOR" }, - { 0x03, 0x1f, "SSP SPI #2, master, NOR" }, - { 0x04, 0x1f, "NAND" }, - { 0x06, 0x1f, "JTAG" }, - { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" }, - { 0x09, 0x1f, "SSP SD/MMC #0" }, - { 0x0a, 0x1f, "SSP SD/MMC #1" }, - { 0x00, 0x00, "Reserved/Unknown/Wrong" }, -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) { 0x00, 0x0f, "USB #0" }, { 0x01, 0x1f, "I2C #0, master, 3V3" }, { 0x11, 0x1f, "I2C #0, master, 1V8" }, diff --git a/arch/arm/include/asm/mach-imx/dma.h b/arch/arm/include/asm/mach-imx/dma.h index 55eb84cb8e7e..30a0fc057f2a 100644 --- a/arch/arm/include/asm/mach-imx/dma.h +++ b/arch/arm/include/asm/mach-imx/dma.h @@ -23,19 +23,7 @@ /* * MXS DMA channels */ -#if defined(CONFIG_MX23) -enum { - MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0, - MXS_DMA_CHANNEL_AHB_APBH_SSP0, - MXS_DMA_CHANNEL_AHB_APBH_SSP1, - MXS_DMA_CHANNEL_AHB_APBH_RESERVED0, - MXS_DMA_CHANNEL_AHB_APBH_GPMI0, - MXS_DMA_CHANNEL_AHB_APBH_GPMI1, - MXS_DMA_CHANNEL_AHB_APBH_GPMI2, - MXS_DMA_CHANNEL_AHB_APBH_GPMI3, - MXS_MAX_DMA_CHANNELS, -}; -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) enum { MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0, MXS_DMA_CHANNEL_AHB_APBH_SSP1, diff --git a/arch/arm/include/asm/mach-imx/regs-apbh.h b/arch/arm/include/asm/mach-imx/regs-apbh.h index 94c330c7f928..c751eab99164 100644 --- a/arch/arm/include/asm/mach-imx/regs-apbh.h +++ b/arch/arm/include/asm/mach-imx/regs-apbh.h @@ -17,86 +17,6 @@
#ifndef __ASSEMBLY__
-#if defined(CONFIG_MX23) -struct mxs_apbh_regs { - mxs_reg_32(hw_apbh_ctrl0) - mxs_reg_32(hw_apbh_ctrl1) - mxs_reg_32(hw_apbh_ctrl2) - mxs_reg_32(hw_apbh_channel_ctrl) - - union { - struct { - mxs_reg_32(hw_apbh_ch_curcmdar) - mxs_reg_32(hw_apbh_ch_nxtcmdar) - mxs_reg_32(hw_apbh_ch_cmd) - mxs_reg_32(hw_apbh_ch_bar) - mxs_reg_32(hw_apbh_ch_sema) - mxs_reg_32(hw_apbh_ch_debug1) - mxs_reg_32(hw_apbh_ch_debug2) - } ch[8]; - struct { - mxs_reg_32(hw_apbh_ch0_curcmdar) - mxs_reg_32(hw_apbh_ch0_nxtcmdar) - mxs_reg_32(hw_apbh_ch0_cmd) - mxs_reg_32(hw_apbh_ch0_bar) - mxs_reg_32(hw_apbh_ch0_sema) - mxs_reg_32(hw_apbh_ch0_debug1) - mxs_reg_32(hw_apbh_ch0_debug2) - mxs_reg_32(hw_apbh_ch1_curcmdar) - mxs_reg_32(hw_apbh_ch1_nxtcmdar) - mxs_reg_32(hw_apbh_ch1_cmd) - mxs_reg_32(hw_apbh_ch1_bar) - mxs_reg_32(hw_apbh_ch1_sema) - mxs_reg_32(hw_apbh_ch1_debug1) - mxs_reg_32(hw_apbh_ch1_debug2) - mxs_reg_32(hw_apbh_ch2_curcmdar) - mxs_reg_32(hw_apbh_ch2_nxtcmdar) - mxs_reg_32(hw_apbh_ch2_cmd) - mxs_reg_32(hw_apbh_ch2_bar) - mxs_reg_32(hw_apbh_ch2_sema) - mxs_reg_32(hw_apbh_ch2_debug1) - mxs_reg_32(hw_apbh_ch2_debug2) - mxs_reg_32(hw_apbh_ch3_curcmdar) - mxs_reg_32(hw_apbh_ch3_nxtcmdar) - mxs_reg_32(hw_apbh_ch3_cmd) - mxs_reg_32(hw_apbh_ch3_bar) - mxs_reg_32(hw_apbh_ch3_sema) - mxs_reg_32(hw_apbh_ch3_debug1) - mxs_reg_32(hw_apbh_ch3_debug2) - mxs_reg_32(hw_apbh_ch4_curcmdar) - mxs_reg_32(hw_apbh_ch4_nxtcmdar) - mxs_reg_32(hw_apbh_ch4_cmd) - mxs_reg_32(hw_apbh_ch4_bar) - mxs_reg_32(hw_apbh_ch4_sema) - mxs_reg_32(hw_apbh_ch4_debug1) - mxs_reg_32(hw_apbh_ch4_debug2) - mxs_reg_32(hw_apbh_ch5_curcmdar) - mxs_reg_32(hw_apbh_ch5_nxtcmdar) - mxs_reg_32(hw_apbh_ch5_cmd) - mxs_reg_32(hw_apbh_ch5_bar) - mxs_reg_32(hw_apbh_ch5_sema) - mxs_reg_32(hw_apbh_ch5_debug1) - mxs_reg_32(hw_apbh_ch5_debug2) - mxs_reg_32(hw_apbh_ch6_curcmdar) - mxs_reg_32(hw_apbh_ch6_nxtcmdar) - mxs_reg_32(hw_apbh_ch6_cmd) - mxs_reg_32(hw_apbh_ch6_bar) - mxs_reg_32(hw_apbh_ch6_sema) - mxs_reg_32(hw_apbh_ch6_debug1) - mxs_reg_32(hw_apbh_ch6_debug2) - mxs_reg_32(hw_apbh_ch7_curcmdar) - mxs_reg_32(hw_apbh_ch7_nxtcmdar) - mxs_reg_32(hw_apbh_ch7_cmd) - mxs_reg_32(hw_apbh_ch7_bar) - mxs_reg_32(hw_apbh_ch7_sema) - mxs_reg_32(hw_apbh_ch7_debug1) - mxs_reg_32(hw_apbh_ch7_debug2) - }; - }; - mxs_reg_32(hw_apbh_version) -}; - -#else struct mxs_apbh_regs { mxs_reg_32(hw_apbh_ctrl0) mxs_reg_32(hw_apbh_ctrl1) @@ -235,7 +155,6 @@ struct mxs_apbh_regs { }; mxs_reg_32(hw_apbh_version) }; -#endif
#endif
@@ -243,20 +162,7 @@ struct mxs_apbh_regs { #define APBH_CTRL0_CLKGATE (1 << 30) #define APBH_CTRL0_AHB_BURST8_EN (1 << 29) #define APBH_CTRL0_APB_BURST_EN (1 << 28) -#if defined(CONFIG_MX23) -#define APBH_CTRL0_RSVD0_MASK (0xf << 24) -#define APBH_CTRL0_RSVD0_OFFSET 24 -#define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16) -#define APBH_CTRL0_RESET_CHANNEL_OFFSET 16 -#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xff << 8) -#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 8 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x02 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x04 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x10 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define APBH_CTRL0_RSVD0_MASK (0xfff << 16) #define APBH_CTRL0_RSVD0_OFFSET 16 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff @@ -393,24 +299,7 @@ struct mxs_apbh_regs { /* Not on i.MX23 */ #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
-#if defined(CONFIG_MX23) -#define APBH_DEVSEL_CH7_MASK (0xf << 28) -#define APBH_DEVSEL_CH7_OFFSET 28 -#define APBH_DEVSEL_CH6_MASK (0xf << 24) -#define APBH_DEVSEL_CH6_OFFSET 24 -#define APBH_DEVSEL_CH5_MASK (0xf << 20) -#define APBH_DEVSEL_CH5_OFFSET 20 -#define APBH_DEVSEL_CH4_MASK (0xf << 16) -#define APBH_DEVSEL_CH4_OFFSET 16 -#define APBH_DEVSEL_CH3_MASK (0xf << 12) -#define APBH_DEVSEL_CH3_OFFSET 12 -#define APBH_DEVSEL_CH2_MASK (0xf << 8) -#define APBH_DEVSEL_CH2_OFFSET 8 -#define APBH_DEVSEL_CH1_MASK (0xf << 4) -#define APBH_DEVSEL_CH1_OFFSET 4 -#define APBH_DEVSEL_CH0_MASK (0xf << 0) -#define APBH_DEVSEL_CH0_OFFSET 0 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define APBH_DEVSEL_CH15_MASK (0x3 << 30) #define APBH_DEVSEL_CH15_OFFSET 30 #define APBH_DEVSEL_CH14_MASK (0x3 << 28) diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h index 587463879661..12e0faad91d6 100644 --- a/arch/arm/include/asm/mach-imx/regs-lcdif.h +++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h @@ -29,10 +29,6 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */ mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */
-#if defined(CONFIG_MX23) - uint32_t reserved1[4]; -#endif - mxs_reg_32(hw_lcdif_timing) /* 0x60 */ mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */ mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */ @@ -52,9 +48,6 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */ mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
-#if defined(CONFIG_MX23) - uint32_t reserved2[12]; -#endif mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */ mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */ #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \ @@ -214,13 +207,8 @@ struct mxs_lcdif_regs { #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
-#if defined(CONFIG_MX23) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24 -#else #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 -#endif #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index bd075de2b826..e04b0dc10f6c 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -1,24 +1,3 @@ -if ARCH_MX23 - -config MX23 - bool - default y - -choice - prompt "MX23 board select" - optional - -config TARGET_SANSA_FUZE_PLUS - bool "Support sansa_fuze_plus" - -endchoice - -config SYS_SOC - default "mxs" - - -endif - if ARCH_MX28
config MX28 diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index da988f6bb667..e05415d2d502 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -215,10 +215,7 @@ static int mxs_dma_reset(int channel) struct mxs_apbh_regs *apbh_regs = (struct mxs_apbh_regs *)MXS_APBH_BASE; int ret; -#if defined(CONFIG_MX23) - uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set); - uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET; -#elif defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ +#if defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) u32 setreg = (uintptr_t)(&apbh_regs->hw_apbh_channel_ctrl_set); u32 offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET; diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index 4b2b18fdb538..22e50dd21ca9 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -15,15 +15,7 @@ #include <asm/arch/iomux.h> #include <asm/arch/imx-regs.h>
-#if defined(CONFIG_MX23) -#define PINCTRL_BANKS 3 -#define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10)) -#define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10)) -#define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10)) -#define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10)) -#define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10)) -#define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10)) -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define PINCTRL_BANKS 5 #define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10)) #define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10)) @@ -32,7 +24,7 @@ #define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10)) #define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10)) #else -#error "Please select CONFIG_MX23 or CONFIG_MX28" +#error "Please select CONFIG_MX28" #endif
#define GPIO_INT_FALL_EDGE 0x0 diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 8fd41764152f..863e67f10c52 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -391,15 +391,7 @@ mxsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) ctrl0 |= SSP_CTRL0_DATA_XFER;
reg = data->blocksize * data->blocks; -#if defined(CONFIG_MX23) - ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK; - - clrsetbits_le32(&ssp_regs->hw_ssp_cmd0, - SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK, - ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) | - ((ffs(data->blocksize) - 1) << - SSP_CMD0_BLOCK_SIZE_OFFSET)); -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) writel(reg, &ssp_regs->hw_ssp_xfer_size);
reg = ((data->blocks - 1) << @@ -595,8 +587,6 @@ static int mxsmmc_probe(struct udevice *dev)
#ifdef CONFIG_MX28 priv->clkid = clkid - MXS_SSP_IMX28_CLKID_SSP0; -#else /* CONFIG_MX23 */ - priv->clkid = clkid - MXS_SSP_IMX23_CLKID_SSP0; #endif mmc = &plat->mmc; mmc->cfg = &plat->cfg; diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index d41352a0bb8c..45b541fe1668 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -83,10 +83,7 @@ static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
while (length--) { /* We transfer 1 byte */ -#if defined(CONFIG_MX23) - writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr); - writel(1, &ssp_regs->hw_ssp_ctrl0_set); -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) writel(1, &ssp_regs->hw_ssp_xfer_size); #endif
@@ -146,9 +143,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv, int tl; int ret = 0;
-#if defined(CONFIG_MX23) - const int mxs_spi_pio_words = 1; -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) const int mxs_spi_pio_words = 4; #endif
diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 325c3ee00ce3..3db3e18066e7 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -23,17 +23,9 @@ * Includes */
-#if defined(CONFIG_MX23) && defined(CONFIG_MX28) -#error Select either CONFIG_MX23 or CONFIG_MX28 , never both! -#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28) -#error Select one of CONFIG_MX23 or CONFIG_MX28 ! -#endif - #include <asm/arch/regs-base.h>
-#if defined(CONFIG_MX23) -#include <asm/arch/iomux-mx23.h> -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #include <asm/arch/iomux-mx28.h> #endif
@@ -54,9 +46,7 @@
/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ #define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#if defined(CONFIG_MX23) -#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024) -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) #endif
diff --git a/tools/Makefile b/tools/Makefile index 2d550432ba5a..ce8faeb85249 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -127,7 +127,7 @@ fit_info-objs := $(dumpimage-mkimage-objs) fit_info.o fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o file2include-objs := file2include.o
-ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),) +ifneq ($(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),) # Add CONFIG_MXS into host CFLAGS, so we can check whether or not register # the mxsimage support within tools/mxsimage.c . HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS @@ -155,7 +155,7 @@ HOSTCFLAGS_kwbimage.o += -DCONFIG_KWB_SECURE endif
# MXSImage needs LibSSL -ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE)$(CONFIG_FIT_CIPHER),) +ifneq ($(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE)$(CONFIG_FIT_CIPHER),) HOSTCFLAGS_kwbimage.o += \ $(shell pkg-config --cflags libssl libcrypto 2> /dev/null || echo "") HOSTLDLIBS_mkimage += \ @@ -186,7 +186,6 @@ hostprogs-$(CONFIG_X86) += ifdtool ifwitool-objs := ifwitool.o hostprogs-$(CONFIG_X86)$(CONFIG_SANDBOX) += ifwitool
-hostprogs-$(CONFIG_MX23) += mxsboot hostprogs-$(CONFIG_MX28) += mxsboot HOSTCFLAGS_mxsboot.o := -pedantic
On 09.02.21 14:02, Tom Rini wrote:
As there are now no boards for the MX23 family, remove the general support.
I am fine to drop it.
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano
Cc: Stefano Babic sbabic@denx.de Cc: Fabio Estevam festevam@gmail.com Cc: NXP i.MX U-Boot Team uboot-imx@nxp.com Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/Kconfig | 8 +- arch/arm/Makefile | 2 +- arch/arm/cpu/arm926ejs/mxs/Makefile | 1 - arch/arm/cpu/arm926ejs/mxs/clock.c | 31 +- arch/arm/cpu/arm926ejs/mxs/iomux.c | 7 +- .../cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg | 5 - arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg | 7 - arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 31 +- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 85 +---- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 50 +-- arch/arm/cpu/arm926ejs/mxs/timer.c | 12 +- arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd | 18 - arch/arm/include/asm/arch-mxs/imx-regs.h | 5 - arch/arm/include/asm/arch-mxs/iomux-mx23.h | 349 ------------------ arch/arm/include/asm/arch-mxs/regs-base.h | 46 +-- .../include/asm/arch-mxs/regs-clkctrl-mx23.h | 209 ----------- .../include/asm/arch-mxs/regs-power-mx23.h | 344 ----------------- arch/arm/include/asm/arch-mxs/regs-ssp.h | 42 +-- arch/arm/include/asm/arch-mxs/regs-timrot.h | 97 +---- arch/arm/include/asm/arch-mxs/sys_proto.h | 17 +- arch/arm/include/asm/mach-imx/dma.h | 14 +- arch/arm/include/asm/mach-imx/regs-apbh.h | 115 +----- arch/arm/include/asm/mach-imx/regs-lcdif.h | 12 - arch/arm/mach-imx/mxs/Kconfig | 21 -- drivers/dma/apbh_dma.c | 5 +- drivers/gpio/mxs_gpio.c | 12 +- drivers/mmc/mxsmmc.c | 12 +- drivers/spi/mxs_spi.c | 9 +- include/configs/mxs.h | 14 +- tools/Makefile | 5 +- 30 files changed, 44 insertions(+), 1541 deletions(-) delete mode 100644 arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg delete mode 100644 arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg delete mode 100644 arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd delete mode 100644 arch/arm/include/asm/arch-mxs/iomux-mx23.h delete mode 100644 arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h delete mode 100644 arch/arm/include/asm/arch-mxs/regs-power-mx23.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 95557d6ed6bd..f2a87c3caed8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -856,12 +856,6 @@ config ARCH_IMXRT select SUPPORT_SPL imply CMD_DM
-config ARCH_MX23
- bool "NXP i.MX23 family"
- select CPU_ARM926EJS
- select PL011_SERIAL
- select SUPPORT_SPL
config ARCH_MX25 bool "NXP MX25" select CPU_ARM926EJS @@ -2042,6 +2036,6 @@ source "arch/arm/Kconfig.debug" endmenu
config SPL_LDSCRIPT
- default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
- default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if ARCH_MX28 && !SPL_FRAMEWORK default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 28b523b37c70..7c1bca7f9269 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -107,7 +107,7 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt)) +ifneq (,$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt)) libs-y += arch/arm/mach-imx/ endif else diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index f60e61e4343f..f846a5400a3d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -12,7 +12,6 @@ obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o endif
# Specify the target for use in elftosb call -MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx23.cfg MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx28.cfg
# Generate HAB-capable IVT diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index 4e1cf3a1e32b..9aa6f83bb395 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -28,9 +28,7 @@ #define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000) #define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
-#if defined(CONFIG_MX23) -#define MXC_SSPCLK_MAX MXC_SSPCLK0 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define MXC_SSPCLK_MAX MXC_SSPCLK3 #endif
@@ -113,10 +111,7 @@ static uint32_t mxs_get_gpmiclk(void) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; -#if defined(CONFIG_MX23)
- uint8_t *reg =
&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) uint8_t *reg = &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]; #endif @@ -319,9 +314,7 @@ void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq) if (freq == 0) return;
-#if defined(CONFIG_MX23)
- writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr);
-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr); #endif
@@ -367,23 +360,7 @@ void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq)
k_best /= 1000;
-#if defined(CONFIG_MX23)
- writeb(CLKCTRL_FRAC_CLKGATE,
&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]);- writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]);- writeb(CLKCTRL_FRAC_CLKGATE,
&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]);- writel(CLKCTRL_PIX_CLKGATE,
&clkctrl_regs->hw_clkctrl_pix_set);- clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix,
CLKCTRL_PIX_DIV_MASK | CLKCTRL_PIX_CLKGATE,k_best << CLKCTRL_PIX_DIV_OFFSET);- while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY)
;-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) writeb(CLKCTRL_FRAC_CLKGATE, &clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]); writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK), diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c index 381264b8a18d..d212d0fa529d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/iomux.c +++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c @@ -13,14 +13,11 @@ #include <asm/arch/iomux.h> #include <asm/arch/imx-regs.h>
-#if defined(CONFIG_MX23) -#define DRIVE_OFFSET 0x200 -#define PULL_OFFSET 0x400 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define DRIVE_OFFSET 0x300 #define PULL_OFFSET 0x600 #else -#error "Please select CONFIG_MX23 or CONFIG_MX28" +#error "Please select CONFIG_MX28" #endif
/* diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg deleted file mode 100644 index ab2183ed3795..000000000000 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg +++ /dev/null @@ -1,5 +0,0 @@ -DISPLAYPROGRESS -SECTION 0x0 BOOTABLE
- TAG LAST
- LOAD 0x1000 spl/u-boot-spl.bin
- CALL 0x1000 0x0
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg deleted file mode 100644 index e7028092a2c3..000000000000 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg +++ /dev/null @@ -1,7 +0,0 @@ -DISPLAYPROGRESS -SECTION 0x0 BOOTABLE
- TAG LAST
- LOAD 0x1000 spl/u-boot-spl.bin
- CALL 0x1000 0x0
- LOAD 0x40002000 u-boot.bin
- CALL 0x40002000 0x0
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 1501d7df0dc6..d44167e4e90c 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -39,42 +39,13 @@ void early_delay(int delay) ; }
-#if defined(CONFIG_MX23) -#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -static const iomux_cfg_t iomux_boot[] = {
- MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
- MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
- MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
- MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
- MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
- MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
-}; -#endif
static uint8_t mxs_get_bootmode_index(void) { uint8_t bootmode = 0; int i; uint8_t masked;
-#if defined(CONFIG_MX23)
- /* Setup IOMUX of bootmode pads to GPIO */
- mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot));
- /* Setup bootmode pins as GPIO input */
- gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0);
- gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1);
- gpio_direction_input(MX23_PAD_LCD_D02__GPIO_1_2);
- gpio_direction_input(MX23_PAD_LCD_D03__GPIO_1_3);
- gpio_direction_input(MX23_PAD_LCD_D05__GPIO_1_5);
- /* Read bootmode pads */
- bootmode |= (gpio_get_value(MX23_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0;
- bootmode |= (gpio_get_value(MX23_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1;
- bootmode |= (gpio_get_value(MX23_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
- bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
- bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) /* The global boot mode will be detected by ROM code and its value * is stored at the fixed address 0x00019BF0 in OCRAM. */ diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index a94803ee93d9..c56b620f1ffa 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -71,21 +71,6 @@ __weak uint32_t mxs_dram_vals[] = { 0x00040004, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffffff
-/*
- i.MX23 DDR at 133MHz
- */
-#elif defined(CONFIG_MX23)
- 0x01010001, 0x00010100, 0x01000101, 0x00000001,
- 0x00000101, 0x00000000, 0x00010000, 0x01000001,
- 0x00000000, 0x00000001, 0x07000200, 0x00070202,
- 0x02020000, 0x04040a01, 0x00000201, 0x02040000,
- 0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313,
- 0x02061521, 0x0000000a, 0x00080008, 0x00200020,
- 0x00200020, 0x00200020, 0x000003f7, 0x00000000,
- 0x00000000, 0x00000020, 0x00000020, 0x00c80000,
- 0x000a23cd, 0x000000c8, 0x00006665, 0x00000000,
- 0x00000101, 0x00040001, 0x00000000, 0x00000000,
- 0x00010000
#else #error Unsupported memory initialization #endif @@ -144,10 +129,7 @@ static void mxs_mem_init_clock(void) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; -#if defined(CONFIG_MX23)
- /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
- const unsigned char divider = 33;
-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ const unsigned char divider = 21; #endif @@ -247,67 +229,6 @@ uint32_t mxs_mem_get_size(void) return sz; }
-#ifdef CONFIG_MX23 -static void mx23_mem_setup_vddmem(void) -{
- struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;- debug("SPL: Setting mx23 VDDMEM\n");
- /* We must wait before and after disabling the current limiter! */
- early_delay(10000);
- clrbits_le32(&power_regs->hw_power_vddmemctrl,
POWER_VDDMEMCTRL_ENABLE_ILIMIT);- early_delay(10000);
-}
-static void mx23_mem_init(void) -{
- debug("SPL: Initialising mx23 SDRAM Controller\n");
- /*
* Reset/ungate the EMI block. This is essential, otherwise the system* suffers from memory instability. This thing is mx23 specific and is* no longer present on mx28.*/- mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE);
- mx23_mem_setup_vddmem();
- /*
* Configure the DRAM registers*/- /* Clear START and SREFRESH bit from DRAM_CTL8 */
- clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
- initialize_dram_values();
- /* Set START bit in DRAM_CTL8 */
- setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
- clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
- /* Wait for EMI_STAT bit DRAM_HALTED */
- for (;;) {
if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1)))break;early_delay(1000);- }
- /* Adjust EMI port priority. */
- clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
- early_delay(20000);
- setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
- setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
-} -#endif
#ifdef CONFIG_MX28 static void mx28_mem_init(void) { @@ -349,9 +270,7 @@ void mxs_mem_init(void)
mxs_mem_setup_vdda();
-#if defined(CONFIG_MX23)
- mx23_mem_init();
-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) mx28_mem_init(); #endif
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 35ea71a5ba89..095ad9230fa8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -939,13 +939,6 @@ static void mxs_power_configure_power_source(void) mxs_init_batt_bo();
mxs_switch_vddd_to_dcdc_source();
-#ifdef CONFIG_MX23
- /* Fire up the VDDMEM LinReg now that we're all set. */
- debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
- writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
&power_regs->hw_power_vddmemctrl);-#endif }
/** @@ -1065,9 +1058,7 @@ struct mxs_vddx_cfg { static const struct mxs_vddx_cfg mxs_vddio_cfg = { .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> hw_power_vddioctrl), -#if defined(CONFIG_MX23)
- .step_mV = 25,
-#else +#if defined(CONFIG_MX28) .step_mV = 50, #endif .lowest_mV = 2800, @@ -1092,21 +1083,6 @@ static const struct mxs_vddx_cfg mxs_vddd_cfg = { .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET, };
-#ifdef CONFIG_MX23 -static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
- .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
hw_power_vddmemctrl),- .step_mV = 50,
- .lowest_mV = 1700,
- .powered_by_linreg = NULL,
- .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
- .bo_irq = 0,
- .bo_enirq = 0,
- .bo_offset_mask = 0,
- .bo_offset_offset = 0,
-}; -#endif
/**
- mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
- @cfg: Configuration data of the DC-DC converter rail
@@ -1210,24 +1186,6 @@ static void mxs_setup_batt_detect(void) early_delay(10); }
-/**
- mxs_ungate_power() - Ungate the POWER block
- This function ungates clock to the power block. In case the power block
- was still gated at this point, it will not be possible to configure the
- block and therefore the power initialization would fail. This function
- is only needed on i.MX233, on i.MX28 the power block is always ungated.
- */
-static void mxs_ungate_power(void) -{ -#ifdef CONFIG_MX23
- struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;- writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
-#endif -}
/**
- mxs_power_init() - The power block init main function
@@ -1241,8 +1199,6 @@ void mxs_power_init(void)
debug("SPL: Initialising Power Block\n");
- mxs_ungate_power();
- mxs_power_clock2xtal(); mxs_power_set_auto_restart(); mxs_power_set_linreg();
@@ -1258,10 +1214,6 @@ void mxs_power_init(void)
debug("SPL: Setting VDDD to 1V55 (brownout @ 1v400)\n"); mxs_power_set_vddx(&mxs_vddd_cfg, 1550, 1400); -#ifdef CONFIG_MX23
- debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n");
- mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
-#endif writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ | POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c index 5ab4ed0c5a3d..a5dd9a838e87 100644 --- a/arch/arm/cpu/arm926ejs/mxs/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@ -18,9 +18,7 @@ #include <linux/delay.h>
/* Maximum fixed count */ -#if defined(CONFIG_MX23) -#define TIMER_LOAD_VAL 0xffff -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMER_LOAD_VAL 0xffffffff #endif
@@ -59,9 +57,7 @@ int timer_init(void) mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
/* Set fixed_count to 0 */ -#if defined(CONFIG_MX23)
- writel(0, &timrot_regs->hw_timrot_timcount0);
-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) writel(0, &timrot_regs->hw_timrot_fixed_count0); #endif
@@ -71,9 +67,7 @@ int timer_init(void) &timrot_regs->hw_timrot_timctrl0);
/* Set fixed_count to maximal value */ -#if defined(CONFIG_MX23)
- writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); #endif
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd deleted file mode 100644 index 3a51879d5e4a..000000000000 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd +++ /dev/null @@ -1,18 +0,0 @@ -options {
- driveTag = 0x00;
- flags = 0x01;
-}
-sources {
- u_boot_spl="spl/u-boot-spl.bin";
- u_boot="u-boot.bin";
-}
-section (0) {
- load u_boot_spl > 0x0000;
- load ivt (entry = 0x0014) > 0x8000;
- call 0x8000;
- load u_boot > 0x40000100;
- call 0x40000100;
-} diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h index f853c484be7d..c099c65c9608 100644 --- a/arch/arm/include/asm/arch-mxs/imx-regs.h +++ b/arch/arm/include/asm/arch-mxs/imx-regs.h @@ -25,11 +25,6 @@ #include <asm/arch/regs-usb.h> #include <asm/arch/regs-usbphy.h>
-#ifdef CONFIG_MX23 -#include <asm/arch/regs-clkctrl-mx23.h> -#include <asm/arch/regs-power-mx23.h> -#endif
#ifdef CONFIG_MX28 #include <asm/arch/regs-clkctrl-mx28.h> #include <asm/arch/regs-power-mx28.h> diff --git a/arch/arm/include/asm/arch-mxs/iomux-mx23.h b/arch/arm/include/asm/arch-mxs/iomux-mx23.h deleted file mode 100644 index 2706efa750a2..000000000000 --- a/arch/arm/include/asm/arch-mxs/iomux-mx23.h +++ /dev/null @@ -1,349 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- Copyright (C) 2009-2010 Amit Kucheria amit.kucheria@canonical.com
- Copyright (C) 2010 Freescale Semiconductor, Inc.
- */
-#ifndef __MACH_IOMUX_MX23_H__ -#define __MACH_IOMUX_MX23_H__
-#include <asm/arch/iomux.h>
-/*
- The naming convention for the pad modes is MX23_PAD_<padname>__<padmode>
- If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
- See also iomux.h
BANK PIN MUX- */
-/* MUXSEL_0 */ -#define MX23_PAD_GPMI_D00__GPMI_D00 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D01__GPMI_D01 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D02__GPMI_D02 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D03__GPMI_D03 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D04__GPMI_D04 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D05__GPMI_D05 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D06__GPMI_D06 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D08__GPMI_D08 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D09__GPMI_D09 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D10__GPMI_D10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D11__GPMI_D11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D12__GPMI_D12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D13__GPMI_D13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D14__GPMI_D14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D15__GPMI_D15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_WPN__GPMI_WPN MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0) -#define MX23_PAD_I2C_SCL__I2C_SCL MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0) -#define MX23_PAD_I2C_SDA__I2C_SDA MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D00__LCD_D00 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D01__LCD_D01 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D02__LCD_D02 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D03__LCD_D03 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D04__LCD_D04 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D05__LCD_D05 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D06__LCD_D06 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D08__LCD_D08 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D09__LCD_D09 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) -#define MX23_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) -#define MX23_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) -#define MX23_PAD_LCD_WR__LCD_WR MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) -#define MX23_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) -#define MX23_PAD_LCD_DOTCK__LCD_DOTCK MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) -#define MX23_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) -#define MX23_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) -#define MX23_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) -#define MX23_PAD_PWM0__PWM0 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) -#define MX23_PAD_PWM1__PWM1 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) -#define MX23_PAD_PWM2__PWM2 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) -#define MX23_PAD_PWM3__PWM3 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) -#define MX23_PAD_PWM4__PWM4 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DETECT__SSP1_DETECT MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) -#define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) -#define MX23_PAD_ROTARYB__ROTARYB MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A00__EMI_A00 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A01__EMI_A01 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A02__EMI_A02 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A03__EMI_A03 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A04__EMI_A04 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A05__EMI_A05 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A06__EMI_A06 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A07__EMI_A07 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A08__EMI_A08 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A09__EMI_A09 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A10__EMI_A10 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A11__EMI_A11 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A12__EMI_A12 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) -#define MX23_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0) -#define MX23_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0) -#define MX23_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0) -#define MX23_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D00__EMI_D00 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D01__EMI_D01 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D02__EMI_D02 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D03__EMI_D03 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D04__EMI_D04 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D05__EMI_D05 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D06__EMI_D06 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D08__EMI_D08 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D09__EMI_D09 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D10__EMI_D10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D11__EMI_D11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D12__EMI_D12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D13__EMI_D13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D14__EMI_D14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D15__EMI_D15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CLKN__EMI_CLKN MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
-/* MUXSEL_1 */ -#define MX23_PAD_GPMI_D00__LCD_D8 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D01__LCD_D9 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D02__LCD_D10 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D03__LCD_D11 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D04__LCD_D12 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D05__LCD_D13 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D06__LCD_D14 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D08__LCD_D18 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D09__LCD_D19 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D10__LCD_D20 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D11__LCD_D21 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D12__LCD_D22 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D13__LCD_D23 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D14__AUART2_RX MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D15__AUART2_TX MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_CLE__LCD_D16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_ALE__LCD_D17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_CE2N__ATA_A2 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_RTS__IR_CLK MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_RX__IR_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_TX__IR_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1) -#define MX23_PAD_I2C_SCL__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1) -#define MX23_PAD_I2C_SDA__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D00__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D01__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D02__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D03__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D04__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D05__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D06__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D08__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D09__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D10__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D11__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D12__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D13__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D14__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D15__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1) -#define MX23_PAD_LCD_RESET__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1) -#define MX23_PAD_LCD_RS__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1) -#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) -#define MX23_PAD_LCD_ENABLE__I2C_SCL MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) -#define MX23_PAD_LCD_HSYNC__I2C_SDA MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) -#define MX23_PAD_LCD_VSYNC__LCD_BUSY MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) -#define MX23_PAD_PWM0__ROTARYA MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) -#define MX23_PAD_PWM1__ROTARYB MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) -#define MX23_PAD_PWM2__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) -#define MX23_PAD_PWM3__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) -#define MX23_PAD_PWM4__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
-#define MX23_PAD_SSP1_DETECT__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_1) -#define MX23_PAD_SSP1_DATA1__I2C_SCL MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_1) -#define MX23_PAD_SSP1_DATA2__I2C_SDA MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) -#define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) -#define MX23_PAD_ROTARYB__AUART2_CTS MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_1)
-/* MUXSEL_2 */ -#define MX23_PAD_GPMI_D00__SSP2_DATA0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D01__SSP2_DATA1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D02__SSP2_DATA2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D03__SSP2_DATA3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D04__SSP2_DATA4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D05__SSP2_DATA5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D06__SSP2_DATA6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D08__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D09__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D10__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D11__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D15__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_RDY0__SSP2_DETECT MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_RDY1__SSP2_CMD MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_WRN__SSP2_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_CTS__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_RTS__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_RX__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_TX__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2) -#define MX23_PAD_I2C_SCL__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2) -#define MX23_PAD_I2C_SDA__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D08__SAIF2_SDATA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D09__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D11__SAIF_LRCLK MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D12__SAIF2_SDATA1 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D13__SAIF2_SDATA2 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D14__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D15__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) -#define MX23_PAD_LCD_RESET__GPMI_CE3N MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) -#define MX23_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2) -#define MX23_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2) -#define MX23_PAD_PWM3__AUART1_CTS MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) -#define MX23_PAD_PWM4__AUART1_RTS MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_CMD__JTAG_TDO MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DETECT__USB_OTG_ID MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA0__JTAG_TDI MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA1__JTAG_TCLK MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA2__JTAG_RTCK MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA3__JTAG_TMS MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_SCK__JTAG_TRST MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_2) -#define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2) -#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2)
-/* MUXSEL_GPIO */ -#define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
-#endif /* __MACH_IOMUX_MX23_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-base.h b/arch/arm/include/asm/arch-mxs/regs-base.h index 44d40cade879..c016d1b25534 100644 --- a/arch/arm/include/asm/arch-mxs/regs-base.h +++ b/arch/arm/include/asm/arch-mxs/regs-base.h @@ -14,52 +14,10 @@ #ifndef __MXS_REGS_BASE_H__ #define __MXS_REGS_BASE_H__
-/*
- Register base addresses for i.MX23
- */
-#if defined(CONFIG_MX23) -#define MXS_ICOLL_BASE 0x80000000 -#define MXS_APBH_BASE 0x80004000 -#define MXS_ECC8_BASE 0x80008000 -#define MXS_BCH_BASE 0x8000A000 -#define MXS_GPMI_BASE 0x8000C000 -#define MXS_SSP0_BASE 0x80010000 -#define MXS_SSP1_BASE 0x80034000 -#define MXS_ETM_BASE 0x80014000 -#define MXS_PINCTRL_BASE 0x80018000 -#define MXS_DIGCTL_BASE 0x8001C000 -#define MXS_EMI_BASE 0x80020000 -#define MXS_APBX_BASE 0x80024000 -#define MXS_DCP_BASE 0x80028000 -#define MXS_PXP_BASE 0x8002A000 -#define MXS_OCOTP_BASE 0x8002C000 -#define MXS_AXI_BASE 0x8002E000 -#define MXS_LCDIF_BASE 0x80030000 -#define MXS_SSP1_BASE 0x80034000 -#define MXS_TVENC_BASE 0x80038000 -#define MXS_CLKCTRL_BASE 0x80040000 -#define MXS_SAIF0_BASE 0x80042000 -#define MXS_POWER_BASE 0x80044000 -#define MXS_SAIF1_BASE 0x80046000 -#define MXS_AUDIOOUT_BASE 0x80048000 -#define MXS_AUDIOIN_BASE 0x8004C000 -#define MXS_LRADC_BASE 0x80050000 -#define MXS_SPDIF_BASE 0x80054000 -#define MXS_I2C0_BASE 0x80058000 -#define MXS_RTC_BASE 0x8005C000 -#define MXS_PWM_BASE 0x80064000 -#define MXS_TIMROT_BASE 0x80068000 -#define MXS_UARTAPP0_BASE 0x8006C000 -#define MXS_UARTAPP1_BASE 0x8006E000 -#define MXS_UARTDBG_BASE 0x80070000 -#define MXS_USBPHY0_BASE 0x8007C000 -#define MXS_USBCTRL0_BASE 0x80080000 -#define MXS_DRAM_BASE 0x800E0000
/*
- Register base addresses for i.MX28
*/ -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define MXS_ICOL_BASE 0x80000000 #define MXS_HSADC_BASE 0x80002000 #define MXS_APBH_BASE 0x80004000 @@ -114,7 +72,7 @@ #define MXS_ENET0_BASE 0x800F0000 #define MXS_ENET1_BASE 0x800F4000 #else -#error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28 +#error Unkown SoC. Please set CONFIG_MX28 #endif
#endif /* __MXS_REGS_BASE_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h deleted file mode 100644 index 50fdc9cd0326..000000000000 --- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h +++ /dev/null @@ -1,209 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- Freescale i.MX23 CLKCTRL Register Definitions
- Copyright (C) 2012 Marek Vasut marek.vasut@gmail.com
- on behalf of DENX Software Engineering GmbH
- Based on code from LTIB:
- Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-#ifndef __MX23_REGS_CLKCTRL_H__ -#define __MX23_REGS_CLKCTRL_H__
-#include <asm/mach-imx/regs-common.h>
-#ifndef __ASSEMBLY__ -struct mxs_clkctrl_regs {
- mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
- uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */
- uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */
- mxs_reg_32(hw_clkctrl_cpu) /* 0x20 */
- mxs_reg_32(hw_clkctrl_hbus) /* 0x30 */
- mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */
- mxs_reg_32(hw_clkctrl_xtal) /* 0x50 */
- mxs_reg_32(hw_clkctrl_pix) /* 0x60 */
- uint32_t hw_clkctrl_ssp0; /* 0x70 */
- uint32_t reserved_ssp0[3]; /* 0x74-0x7c */
- uint32_t hw_clkctrl_gpmi; /* 0x80 */
- uint32_t reserved_gpmi[3]; /* 0x84-0x8c */
- mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */
- mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */
- uint32_t reserved1[4];
- mxs_reg_32(hw_clkctrl_saif0) /* 0xc0 */
- mxs_reg_32(hw_clkctrl_tv) /* 0xd0 */
- mxs_reg_32(hw_clkctrl_etm) /* 0xe0 */
- mxs_reg_8(hw_clkctrl_frac0) /* 0xf0 */
- mxs_reg_8(hw_clkctrl_frac1) /* 0x100 */
- mxs_reg_32(hw_clkctrl_clkseq) /* 0x110 */
- mxs_reg_32(hw_clkctrl_reset) /* 0x120 */
- mxs_reg_32(hw_clkctrl_status) /* 0x130 */
- mxs_reg_32(hw_clkctrl_version) /* 0x140 */
-}; -#endif
-#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL0CTRL0_POWER (1 << 16)
-#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0
-#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) -#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) -#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) -#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 -#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) -#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) -#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f -#define CLKCTRL_CPU_DIV_CPU_OFFSET 0
-#define CLKCTRL_HBUS_BUSY (1 << 29) -#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 28) -#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 27) -#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) -#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) -#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) -#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) -#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) -#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) -#define CLKCTRL_HBUS_AUTO_SLOW_MODE (1 << 20) -#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 -#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) -#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) -#define CLKCTRL_HBUS_DIV_MASK 0x1f -#define CLKCTRL_HBUS_DIV_OFFSET 0
-#define CLKCTRL_XBUS_BUSY (1 << 31) -#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_XBUS_DIV_MASK 0x3ff -#define CLKCTRL_XBUS_DIV_OFFSET 0
-#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) -#define CLKCTRL_XTAL_FILT_CLK24M_GATE (1 << 30) -#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) -#define CLKCTRL_XTAL_DRI_CLK24M_GATE (1 << 28) -#define CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE (1 << 27) -#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) -#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 -#define CLKCTRL_XTAL_DIV_UART_OFFSET 0
-#define CLKCTRL_PIX_CLKGATE (1 << 31) -#define CLKCTRL_PIX_BUSY (1 << 29) -#define CLKCTRL_PIX_DIV_FRAC_EN (1 << 12) -#define CLKCTRL_PIX_DIV_MASK 0xfff -#define CLKCTRL_PIX_DIV_OFFSET 0
-#define CLKCTRL_SSP_CLKGATE (1 << 31) -#define CLKCTRL_SSP_BUSY (1 << 29) -#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) -#define CLKCTRL_SSP_DIV_MASK 0x1ff -#define CLKCTRL_SSP_DIV_OFFSET 0
-#define CLKCTRL_GPMI_CLKGATE (1 << 31) -#define CLKCTRL_GPMI_BUSY (1 << 29) -#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_GPMI_DIV_MASK 0x3ff -#define CLKCTRL_GPMI_DIV_OFFSET 0
-#define CLKCTRL_SPDIF_CLKGATE (1 << 31)
-#define CLKCTRL_EMI_CLKGATE (1 << 31) -#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) -#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) -#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) -#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) -#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) -#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) -#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) -#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 -#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f -#define CLKCTRL_EMI_DIV_EMI_OFFSET 0
-#define CLKCTRL_IR_CLKGATE (1 << 31) -#define CLKCTRL_IR_AUTO_DIV (1 << 29) -#define CLKCTRL_IR_IR_BUSY (1 << 28) -#define CLKCTRL_IR_IROV_BUSY (1 << 27) -#define CLKCTRL_IR_IROV_DIV_MASK (0x1ff << 16) -#define CLKCTRL_IR_IROV_DIV_OFFSET 16 -#define CLKCTRL_IR_IR_DIV_MASK 0x3ff -#define CLKCTRL_IR_IR_DIV_OFFSET 0
-#define CLKCTRL_SAIF0_CLKGATE (1 << 31) -#define CLKCTRL_SAIF0_BUSY (1 << 29) -#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF0_DIV_MASK 0xffff -#define CLKCTRL_SAIF0_DIV_OFFSET 0
-#define CLKCTRL_TV_CLK_TV108M_GATE (1 << 31) -#define CLKCTRL_TV_CLK_TV_GATE (1 << 30)
-#define CLKCTRL_ETM_CLKGATE (1 << 31) -#define CLKCTRL_ETM_BUSY (1 << 29) -#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 6) -#define CLKCTRL_ETM_DIV_MASK 0x3f -#define CLKCTRL_ETM_DIV_OFFSET 0
-#define CLKCTRL_FRAC_CLKGATE (1 << 7) -#define CLKCTRL_FRAC_STABLE (1 << 6) -#define CLKCTRL_FRAC_FRAC_MASK 0x3f -#define CLKCTRL_FRAC_FRAC_OFFSET 0 -#define CLKCTRL_FRAC0_CPU 0 -#define CLKCTRL_FRAC0_EMI 1 -#define CLKCTRL_FRAC0_PIX 2 -#define CLKCTRL_FRAC0_IO0 3 -#define CLKCTRL_FRAC1_VID 3
-#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) -#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7) -#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6) -#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 5) -#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4) -#define CLKCTRL_CLKSEQ_BYPASS_IR (1 << 3) -#define CLKCTRL_CLKSEQ_BYPASS_PIX (1 << 1) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF (1 << 0)
-#define CLKCTRL_RESET_CHIP (1 << 1) -#define CLKCTRL_RESET_DIG (1 << 0)
-#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) -#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30
-#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) -#define CLKCTRL_VERSION_MAJOR_OFFSET 24 -#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) -#define CLKCTRL_VERSION_MINOR_OFFSET 16 -#define CLKCTRL_VERSION_STEP_MASK 0xffff -#define CLKCTRL_VERSION_STEP_OFFSET 0
-#endif /* __MX23_REGS_CLKCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h deleted file mode 100644 index a0dc78102301..000000000000 --- a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h +++ /dev/null @@ -1,344 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- Freescale i.MX23 Power Controller Register Definitions
- Copyright (C) 2012 Marek Vasut marex@denx.de
- */
-#ifndef __MX23_REGS_POWER_H__ -#define __MX23_REGS_POWER_H__
-#include <asm/mach-imx/regs-common.h>
-#ifndef __ASSEMBLY__ -struct mxs_power_regs {
- mxs_reg_32(hw_power_ctrl)
- mxs_reg_32(hw_power_5vctrl)
- mxs_reg_32(hw_power_minpwr)
- mxs_reg_32(hw_power_charge)
- uint32_t hw_power_vdddctrl;
- uint32_t reserved_vddd[3];
- uint32_t hw_power_vddactrl;
- uint32_t reserved_vdda[3];
- uint32_t hw_power_vddioctrl;
- uint32_t reserved_vddio[3];
- uint32_t hw_power_vddmemctrl;
- uint32_t reserved_vddmem[3];
- uint32_t hw_power_dcdc4p2;
- uint32_t reserved_dcdc4p2[3];
- uint32_t hw_power_misc;
- uint32_t reserved_misc[3];
- uint32_t hw_power_dclimits;
- uint32_t reserved_dclimits[3];
- mxs_reg_32(hw_power_loopctrl)
- uint32_t hw_power_sts;
- uint32_t reserved_sts[3];
- mxs_reg_32(hw_power_speed)
- uint32_t hw_power_battmonitor;
- uint32_t reserved_battmonitor[3];
- uint32_t reserved1[4];
- mxs_reg_32(hw_power_reset)
- uint32_t reserved2[4];
- mxs_reg_32(hw_power_special)
- mxs_reg_32(hw_power_version)
-}; -#endif
-#define POWER_CTRL_CLKGATE (1 << 30) -#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) -#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) -#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) -#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) -#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) -#define POWER_CTRL_PSWITCH_IRQ (1 << 20) -#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) -#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) -#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) -#define POWER_CTRL_POLARITY_DC_OK (1 << 16) -#define POWER_CTRL_DC_OK_IRQ (1 << 15) -#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) -#define POWER_CTRL_BATT_BO_IRQ (1 << 13) -#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) -#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) -#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) -#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) -#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) -#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) -#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) -#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) -#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) -#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) -#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) -#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) -#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0)
-#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 28 -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 28) -#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) -#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 -#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x1 << 20) -#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 -#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 -#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) -#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) -#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) -#define POWER_5VCTRL_DCDC_XFER (1 << 5) -#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) -#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) -#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) -#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) -#define POWER_5VCTRL_ENABLE_DCDC (1 << 0)
-#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) -#define POWER_MINPWR_VDAC_DUMP_CTRL (1 << 13) -#define POWER_MINPWR_PWD_BO (1 << 12) -#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) -#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) -#define POWER_MINPWR_ENABLE_OSC (1 << 9) -#define POWER_MINPWR_SELECT_OSC (1 << 8) -#define POWER_MINPWR_VBG_OFF (1 << 7) -#define POWER_MINPWR_DOUBLE_FETS (1 << 6) -#define POWER_MINPWR_HALFFETS (1 << 5) -#define POWER_MINPWR_LESSANA_I (1 << 4) -#define POWER_MINPWR_PWD_XTAL24 (1 << 3) -#define POWER_MINPWR_DC_STOPCLK (1 << 2) -#define POWER_MINPWR_EN_DC_PFM (1 << 1) -#define POWER_MINPWR_DC_HALFCLK (1 << 0)
-#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) -#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 -#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) -#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) -#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) -#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) -#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) -#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) -#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) -#define POWER_CHARGE_ENABLE_LOAD (1 << 22) -#define POWER_CHARGE_ENABLE_CHARGER_RESISTORS (1 << 21) -#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) -#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) -#define POWER_CHARGE_USE_EXTERN_R (1 << 17) -#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) -#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) -#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 -#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) -#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) -#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) -#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) -#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f -#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 -#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 -#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 -#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 -#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 -#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 -#define POWER_CHARGE_BATTCHRG_I_400MA 0x20
-#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) -#define POWER_VDDDCTRL_ADJTN_OFFSET 28 -#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) -#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) -#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) -#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) -#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 -#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) -#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDDCTRL_TRG_MASK 0x1f -#define POWER_VDDDCTRL_TRG_OFFSET 0
-#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) -#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) -#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) -#define POWER_VDDACTRL_DISABLE_FET (1 << 16) -#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDACTRL_TRG_MASK 0x1f -#define POWER_VDDACTRL_TRG_OFFSET 0
-#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) -#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 -#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) -#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) -#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) -#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDIOCTRL_TRG_MASK 0x1f -#define POWER_VDDIOCTRL_TRG_OFFSET 0
-#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) -#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) -#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) -#define POWER_VDDMEMCTRL_TRG_MASK 0x1f -#define POWER_VDDMEMCTRL_TRG_OFFSET 0
-#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 -#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) -#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) -#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 -#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) -#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) -#define POWER_DCDC4P2_HYST_DIR (1 << 21) -#define POWER_DCDC4P2_HYST_THRESH (1 << 20) -#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) -#define POWER_DCDC4P2_TRG_OFFSET 16 -#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) -#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) -#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) -#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) -#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) -#define POWER_DCDC4P2_BO_MASK (0x1f << 8) -#define POWER_DCDC4P2_BO_OFFSET 8 -#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f -#define POWER_DCDC4P2_CMPTRIP_OFFSET 0
-#define POWER_MISC_FREQSEL_MASK (0x7 << 4) -#define POWER_MISC_FREQSEL_OFFSET 4 -#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) -#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) -#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) -#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) -#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) -#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) -#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) -#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) -#define POWER_MISC_DELAY_TIMING (1 << 2) -#define POWER_MISC_TEST (1 << 1) -#define POWER_MISC_SEL_PLLCLK (1 << 0)
-#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) -#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 -#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f -#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0
-#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) -#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) -#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) -#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) -#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) -#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) -#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) -#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 -#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) -#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) -#define POWER_LOOPCTRL_DC_FF_OFFSET 8 -#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) -#define POWER_LOOPCTRL_DC_R_OFFSET 4 -#define POWER_LOOPCTRL_DC_C_MASK 0x3 -#define POWER_LOOPCTRL_DC_C_OFFSET 0 -#define POWER_LOOPCTRL_DC_C_MAX 0x0 -#define POWER_LOOPCTRL_DC_C_2X 0x1 -#define POWER_LOOPCTRL_DC_C_4X 0x2 -#define POWER_LOOPCTRL_DC_C_MIN 0x3
-#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) -#define POWER_STS_PWRUP_SOURCE_OFFSET 24 -#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) -#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) -#define POWER_STS_PSWITCH_MASK (0x3 << 20) -#define POWER_STS_PSWITCH_OFFSET 20 -#define POWER_STS_AVALID0_STATUS (1 << 17) -#define POWER_STS_BVALID0_STATUS (1 << 16) -#define POWER_STS_VBUSVALID0_STATUS (1 << 15) -#define POWER_STS_SESSEND0_STATUS (1 << 14) -#define POWER_STS_BATT_BO (1 << 13) -#define POWER_STS_VDD5V_FAULT (1 << 12) -#define POWER_STS_CHRGSTS (1 << 11) -#define POWER_STS_DCDC_4P2_BO (1 << 10) -#define POWER_STS_DC_OK (1 << 9) -#define POWER_STS_VDDIO_BO (1 << 8) -#define POWER_STS_VDDA_BO (1 << 7) -#define POWER_STS_VDDD_BO (1 << 6) -#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) -#define POWER_STS_VDD5V_DROOP (1 << 4) -#define POWER_STS_AVALID0 (1 << 3) -#define POWER_STS_BVALID0 (1 << 2) -#define POWER_STS_VBUSVALID0 (1 << 1) -#define POWER_STS_SESSEND0 (1 << 0)
-#define POWER_SPEED_STATUS_MASK (0xff << 16) -#define POWER_SPEED_STATUS_OFFSET 16 -#define POWER_SPEED_CTRL_MASK 0x3 -#define POWER_SPEED_CTRL_OFFSET 0 -#define POWER_SPEED_CTRL_SS_OFF 0x0 -#define POWER_SPEED_CTRL_SS_ON 0x1 -#define POWER_SPEED_CTRL_SS_ENABLE 0x3
-#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) -#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 -#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) -#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) -#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f -#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0
-#define POWER_RESET_UNLOCK_MASK (0xffff << 16) -#define POWER_RESET_UNLOCK_OFFSET 16 -#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) -#define POWER_RESET_PWD_OFF (1 << 1) -#define POWER_RESET_PWD (1 << 0)
-#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) -#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) -#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) -#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0)
-#define POWER_SPECIAL_TEST_MASK 0xffffffff -#define POWER_SPECIAL_TEST_OFFSET 0
-#define POWER_VERSION_MAJOR_MASK (0xff << 24) -#define POWER_VERSION_MAJOR_OFFSET 24 -#define POWER_VERSION_MINOR_MASK (0xff << 16) -#define POWER_VERSION_MINOR_OFFSET 16 -#define POWER_VERSION_STEP_MASK 0xffff -#define POWER_VERSION_STEP_OFFSET 0
-#endif /* __MX23_REGS_POWER_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h index eeb7e7f44c06..26e620f93802 100644 --- a/arch/arm/include/asm/arch-mxs/regs-ssp.h +++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h @@ -14,28 +14,7 @@ #include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__ -#if defined(CONFIG_MX23) -struct mxs_ssp_regs {
- mxs_reg_32(hw_ssp_ctrl0)
- mxs_reg_32(hw_ssp_cmd0)
- mxs_reg_32(hw_ssp_cmd1)
- mxs_reg_32(hw_ssp_compref)
- mxs_reg_32(hw_ssp_compmask)
- mxs_reg_32(hw_ssp_timing)
- mxs_reg_32(hw_ssp_ctrl1)
- mxs_reg_32(hw_ssp_data)
- mxs_reg_32(hw_ssp_sdresp0)
- mxs_reg_32(hw_ssp_sdresp1)
- mxs_reg_32(hw_ssp_sdresp2)
- mxs_reg_32(hw_ssp_sdresp3)
- mxs_reg_32(hw_ssp_status)
- uint32_t reserved1[12];
- mxs_reg_32(hw_ssp_debug)
- mxs_reg_32(hw_ssp_version)
-}; -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) struct mxs_ssp_regs { mxs_reg_32(hw_ssp_ctrl0) mxs_reg_32(hw_ssp_cmd0) @@ -62,9 +41,7 @@ struct mxs_ssp_regs {
static inline int mxs_ssp_bus_id_valid(int bus) { -#if defined(CONFIG_MX23)
- const unsigned int mxs_ssp_chan_count = 2;
-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) const unsigned int mxs_ssp_chan_count = 4; #endif
@@ -79,9 +56,7 @@ static inline int mxs_ssp_bus_id_valid(int bus)
static inline int mxs_ssp_clock_by_bus(unsigned int clock) { -#if defined(CONFIG_MX23)
- return 0;
-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) return clock; #endif } @@ -125,11 +100,6 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) #define SSP_CTRL0_GET_RESP (1 << 17) #define SSP_CTRL0_ENABLE (1 << 16)
-#ifdef CONFIG_MX23 -#define SSP_CTRL0_XFER_COUNT_OFFSET 0 -#define SSP_CTRL0_XFER_COUNT_MASK 0xffff -#endif
#define SSP_CMD0_SOFT_TERMINATE (1 << 26) #define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) #define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) @@ -137,12 +107,6 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) #define SSP_CMD0_SLOW_CLKING_EN (1 << 22) #define SSP_CMD0_CONT_CLKING_EN (1 << 21) #define SSP_CMD0_APPEND_8CYC (1 << 20) -#if defined(CONFIG_MX23) -#define SSP_CMD0_BLOCK_SIZE_MASK (0xf << 16) -#define SSP_CMD0_BLOCK_SIZE_OFFSET 16 -#define SSP_CMD0_BLOCK_COUNT_MASK (0xff << 8) -#define SSP_CMD0_BLOCK_COUNT_OFFSET 8 -#endif #define SSP_CMD0_CMD_MASK 0xff #define SSP_CMD0_CMD_OFFSET 0 #define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00 diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h index 9e19aabf114a..83ac268f70c0 100644 --- a/arch/arm/include/asm/arch-mxs/regs-timrot.h +++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h @@ -17,16 +17,7 @@ struct mxs_timrot_regs { mxs_reg_32(hw_timrot_rotctrl) mxs_reg_32(hw_timrot_rotcount) -#if defined(CONFIG_MX23)
- mxs_reg_32(hw_timrot_timctrl0)
- mxs_reg_32(hw_timrot_timcount0)
- mxs_reg_32(hw_timrot_timctrl1)
- mxs_reg_32(hw_timrot_timcount1)
- mxs_reg_32(hw_timrot_timctrl2)
- mxs_reg_32(hw_timrot_timcount2)
- mxs_reg_32(hw_timrot_timctrl3)
- mxs_reg_32(hw_timrot_timcount3)
-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) mxs_reg_32(hw_timrot_timctrl0) mxs_reg_32(hw_timrot_running_count0) mxs_reg_32(hw_timrot_fixed_count0) @@ -68,9 +59,7 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) #define TIMROT_ROTCTRL_POLARITY_B (1 << 9) #define TIMROT_ROTCTRL_POLARITY_A (1 << 8) -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4) -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) #endif #define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 @@ -80,19 +69,14 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4) -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) #define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) #define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) #endif -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_A_MASK 0x7 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_A_MASK 0xf #endif #define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 @@ -102,10 +86,7 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 #define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 #define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6 -#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 #define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 #define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 @@ -138,15 +119,7 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 #define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 #define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6 -#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7 -#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8 -#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9 -#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa -#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb -#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 #define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 #define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 @@ -159,18 +132,12 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf #endif
-#if defined(CONFIG_MX23) -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16) -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 #endif
-#if defined(CONFIG_MX23) -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff #define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 #endif @@ -188,15 +155,7 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16) -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) @@ -208,45 +167,7 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) #endif -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_IRQ (1 << 15) -#define TIMROT_TIMCTRL3_IRQ_EN (1 << 14) -#define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10) -#endif #define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8) -#define TIMROT_TIMCTRL3_POLARITY_OFFSET 8 -#define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8) -#define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8) -#define TIMROT_TIMCTRL3_UPDATE (1 << 7) -#define TIMROT_TIMCTRL3_RELOAD (1 << 6) -#define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4 -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4) -#define TIMROT_TIMCTRL3_SELECT_MASK 0xf -#define TIMROT_TIMCTRL3_SELECT_OFFSET 0 -#define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0 -#define TIMROT_TIMCTRL3_SELECT_PWM0 0x1 -#define TIMROT_TIMCTRL3_SELECT_PWM1 0x2 -#define TIMROT_TIMCTRL3_SELECT_PWM2 0x3 -#define TIMROT_TIMCTRL3_SELECT_PWM3 0x4 -#define TIMROT_TIMCTRL3_SELECT_PWM4 0x5 -#define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6 -#define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7 -#define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8 -#define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9 -#define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa -#define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb -#define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc -#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16) -#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16 -#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff -#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0 -#endif
#define TIMROT_VERSION_MAJOR_MASK (0xff << 24) #define TIMROT_VERSION_MAJOR_OFFSET 24 diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 20ee863ac7e7..5d86d6b28312 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -16,9 +16,7 @@ int mxsmmc_initialize(struct bd_info *bis, int id, int (*wp)(int),
#ifdef CONFIG_SPL_BUILD
-#if defined(CONFIG_MX23) -#include <asm/arch/iomux-mx23.h> -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #include <asm/arch/iomux-mx28.h> #endif
@@ -36,18 +34,7 @@ struct mxs_pair { };
static const struct mxs_pair mxs_boot_modes[] = { -#if defined(CONFIG_MX23)
- { 0x00, 0x0f, "USB" },
- { 0x01, 0x1f, "I2C, master" },
- { 0x02, 0x1f, "SSP SPI #1, master, NOR" },
- { 0x03, 0x1f, "SSP SPI #2, master, NOR" },
- { 0x04, 0x1f, "NAND" },
- { 0x06, 0x1f, "JTAG" },
- { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
- { 0x09, 0x1f, "SSP SD/MMC #0" },
- { 0x0a, 0x1f, "SSP SD/MMC #1" },
- { 0x00, 0x00, "Reserved/Unknown/Wrong" },
-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) { 0x00, 0x0f, "USB #0" }, { 0x01, 0x1f, "I2C #0, master, 3V3" }, { 0x11, 0x1f, "I2C #0, master, 1V8" }, diff --git a/arch/arm/include/asm/mach-imx/dma.h b/arch/arm/include/asm/mach-imx/dma.h index 55eb84cb8e7e..30a0fc057f2a 100644 --- a/arch/arm/include/asm/mach-imx/dma.h +++ b/arch/arm/include/asm/mach-imx/dma.h @@ -23,19 +23,7 @@ /*
- MXS DMA channels
*/ -#if defined(CONFIG_MX23) -enum {
- MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
- MXS_DMA_CHANNEL_AHB_APBH_SSP0,
- MXS_DMA_CHANNEL_AHB_APBH_SSP1,
- MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
- MXS_MAX_DMA_CHANNELS,
-}; -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) enum { MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0, MXS_DMA_CHANNEL_AHB_APBH_SSP1, diff --git a/arch/arm/include/asm/mach-imx/regs-apbh.h b/arch/arm/include/asm/mach-imx/regs-apbh.h index 94c330c7f928..c751eab99164 100644 --- a/arch/arm/include/asm/mach-imx/regs-apbh.h +++ b/arch/arm/include/asm/mach-imx/regs-apbh.h @@ -17,86 +17,6 @@
#ifndef __ASSEMBLY__
-#if defined(CONFIG_MX23) -struct mxs_apbh_regs {
- mxs_reg_32(hw_apbh_ctrl0)
- mxs_reg_32(hw_apbh_ctrl1)
- mxs_reg_32(hw_apbh_ctrl2)
- mxs_reg_32(hw_apbh_channel_ctrl)
- union {
- struct {
mxs_reg_32(hw_apbh_ch_curcmdar)mxs_reg_32(hw_apbh_ch_nxtcmdar)mxs_reg_32(hw_apbh_ch_cmd)mxs_reg_32(hw_apbh_ch_bar)mxs_reg_32(hw_apbh_ch_sema)mxs_reg_32(hw_apbh_ch_debug1)mxs_reg_32(hw_apbh_ch_debug2)- } ch[8];
- struct {
mxs_reg_32(hw_apbh_ch0_curcmdar)mxs_reg_32(hw_apbh_ch0_nxtcmdar)mxs_reg_32(hw_apbh_ch0_cmd)mxs_reg_32(hw_apbh_ch0_bar)mxs_reg_32(hw_apbh_ch0_sema)mxs_reg_32(hw_apbh_ch0_debug1)mxs_reg_32(hw_apbh_ch0_debug2)mxs_reg_32(hw_apbh_ch1_curcmdar)mxs_reg_32(hw_apbh_ch1_nxtcmdar)mxs_reg_32(hw_apbh_ch1_cmd)mxs_reg_32(hw_apbh_ch1_bar)mxs_reg_32(hw_apbh_ch1_sema)mxs_reg_32(hw_apbh_ch1_debug1)mxs_reg_32(hw_apbh_ch1_debug2)mxs_reg_32(hw_apbh_ch2_curcmdar)mxs_reg_32(hw_apbh_ch2_nxtcmdar)mxs_reg_32(hw_apbh_ch2_cmd)mxs_reg_32(hw_apbh_ch2_bar)mxs_reg_32(hw_apbh_ch2_sema)mxs_reg_32(hw_apbh_ch2_debug1)mxs_reg_32(hw_apbh_ch2_debug2)mxs_reg_32(hw_apbh_ch3_curcmdar)mxs_reg_32(hw_apbh_ch3_nxtcmdar)mxs_reg_32(hw_apbh_ch3_cmd)mxs_reg_32(hw_apbh_ch3_bar)mxs_reg_32(hw_apbh_ch3_sema)mxs_reg_32(hw_apbh_ch3_debug1)mxs_reg_32(hw_apbh_ch3_debug2)mxs_reg_32(hw_apbh_ch4_curcmdar)mxs_reg_32(hw_apbh_ch4_nxtcmdar)mxs_reg_32(hw_apbh_ch4_cmd)mxs_reg_32(hw_apbh_ch4_bar)mxs_reg_32(hw_apbh_ch4_sema)mxs_reg_32(hw_apbh_ch4_debug1)mxs_reg_32(hw_apbh_ch4_debug2)mxs_reg_32(hw_apbh_ch5_curcmdar)mxs_reg_32(hw_apbh_ch5_nxtcmdar)mxs_reg_32(hw_apbh_ch5_cmd)mxs_reg_32(hw_apbh_ch5_bar)mxs_reg_32(hw_apbh_ch5_sema)mxs_reg_32(hw_apbh_ch5_debug1)mxs_reg_32(hw_apbh_ch5_debug2)mxs_reg_32(hw_apbh_ch6_curcmdar)mxs_reg_32(hw_apbh_ch6_nxtcmdar)mxs_reg_32(hw_apbh_ch6_cmd)mxs_reg_32(hw_apbh_ch6_bar)mxs_reg_32(hw_apbh_ch6_sema)mxs_reg_32(hw_apbh_ch6_debug1)mxs_reg_32(hw_apbh_ch6_debug2)mxs_reg_32(hw_apbh_ch7_curcmdar)mxs_reg_32(hw_apbh_ch7_nxtcmdar)mxs_reg_32(hw_apbh_ch7_cmd)mxs_reg_32(hw_apbh_ch7_bar)mxs_reg_32(hw_apbh_ch7_sema)mxs_reg_32(hw_apbh_ch7_debug1)mxs_reg_32(hw_apbh_ch7_debug2)- };
- };
- mxs_reg_32(hw_apbh_version)
-};
-#else struct mxs_apbh_regs { mxs_reg_32(hw_apbh_ctrl0) mxs_reg_32(hw_apbh_ctrl1) @@ -235,7 +155,6 @@ struct mxs_apbh_regs { }; mxs_reg_32(hw_apbh_version) }; -#endif
#endif
@@ -243,20 +162,7 @@ struct mxs_apbh_regs { #define APBH_CTRL0_CLKGATE (1 << 30) #define APBH_CTRL0_AHB_BURST8_EN (1 << 29) #define APBH_CTRL0_APB_BURST_EN (1 << 28) -#if defined(CONFIG_MX23) -#define APBH_CTRL0_RSVD0_MASK (0xf << 24) -#define APBH_CTRL0_RSVD0_OFFSET 24 -#define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16) -#define APBH_CTRL0_RESET_CHANNEL_OFFSET 16 -#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xff << 8) -#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 8 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x02 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x04 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x10 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define APBH_CTRL0_RSVD0_MASK (0xfff << 16) #define APBH_CTRL0_RSVD0_OFFSET 16 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff @@ -393,24 +299,7 @@ struct mxs_apbh_regs { /* Not on i.MX23 */ #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
-#if defined(CONFIG_MX23) -#define APBH_DEVSEL_CH7_MASK (0xf << 28) -#define APBH_DEVSEL_CH7_OFFSET 28 -#define APBH_DEVSEL_CH6_MASK (0xf << 24) -#define APBH_DEVSEL_CH6_OFFSET 24 -#define APBH_DEVSEL_CH5_MASK (0xf << 20) -#define APBH_DEVSEL_CH5_OFFSET 20 -#define APBH_DEVSEL_CH4_MASK (0xf << 16) -#define APBH_DEVSEL_CH4_OFFSET 16 -#define APBH_DEVSEL_CH3_MASK (0xf << 12) -#define APBH_DEVSEL_CH3_OFFSET 12 -#define APBH_DEVSEL_CH2_MASK (0xf << 8) -#define APBH_DEVSEL_CH2_OFFSET 8 -#define APBH_DEVSEL_CH1_MASK (0xf << 4) -#define APBH_DEVSEL_CH1_OFFSET 4 -#define APBH_DEVSEL_CH0_MASK (0xf << 0) -#define APBH_DEVSEL_CH0_OFFSET 0 -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define APBH_DEVSEL_CH15_MASK (0x3 << 30) #define APBH_DEVSEL_CH15_OFFSET 30 #define APBH_DEVSEL_CH14_MASK (0x3 << 28) diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h index 587463879661..12e0faad91d6 100644 --- a/arch/arm/include/asm/mach-imx/regs-lcdif.h +++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h @@ -29,10 +29,6 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */ mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */
-#if defined(CONFIG_MX23)
- uint32_t reserved1[4];
-#endif
- mxs_reg_32(hw_lcdif_timing) /* 0x60 */ mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */ mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
@@ -52,9 +48,6 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */ mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
-#if defined(CONFIG_MX23)
- uint32_t reserved2[12];
-#endif mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */ mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */ #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \ @@ -214,13 +207,8 @@ struct mxs_lcdif_regs { #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
-#if defined(CONFIG_MX23) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24 -#else #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 -#endif #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index bd075de2b826..e04b0dc10f6c 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -1,24 +1,3 @@ -if ARCH_MX23
-config MX23
- bool
- default y
-choice
- prompt "MX23 board select"
- optional
-config TARGET_SANSA_FUZE_PLUS
- bool "Support sansa_fuze_plus"
-endchoice
-config SYS_SOC
- default "mxs"
-endif
if ARCH_MX28
config MX28 diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index da988f6bb667..e05415d2d502 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -215,10 +215,7 @@ static int mxs_dma_reset(int channel) struct mxs_apbh_regs *apbh_regs = (struct mxs_apbh_regs *)MXS_APBH_BASE; int ret; -#if defined(CONFIG_MX23)
- uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
- uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
-#elif defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ +#if defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) u32 setreg = (uintptr_t)(&apbh_regs->hw_apbh_channel_ctrl_set); u32 offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET; diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index 4b2b18fdb538..22e50dd21ca9 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -15,15 +15,7 @@ #include <asm/arch/iomux.h> #include <asm/arch/imx-regs.h>
-#if defined(CONFIG_MX23) -#define PINCTRL_BANKS 3 -#define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10)) -#define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10)) -#define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10)) -#define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10)) -#define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10)) -#define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10)) -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define PINCTRL_BANKS 5 #define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10)) #define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10)) @@ -32,7 +24,7 @@ #define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10)) #define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10)) #else -#error "Please select CONFIG_MX23 or CONFIG_MX28" +#error "Please select CONFIG_MX28" #endif
#define GPIO_INT_FALL_EDGE 0x0 diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 8fd41764152f..863e67f10c52 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -391,15 +391,7 @@ mxsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) ctrl0 |= SSP_CTRL0_DATA_XFER;
reg = data->blocksize * data->blocks;-#if defined(CONFIG_MX23)
ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |((ffs(data->blocksize) - 1) <<SSP_CMD0_BLOCK_SIZE_OFFSET));-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) writel(reg, &ssp_regs->hw_ssp_xfer_size);
reg = ((data->blocks - 1) <<@@ -595,8 +587,6 @@ static int mxsmmc_probe(struct udevice *dev)
#ifdef CONFIG_MX28 priv->clkid = clkid - MXS_SSP_IMX28_CLKID_SSP0; -#else /* CONFIG_MX23 */
- priv->clkid = clkid - MXS_SSP_IMX23_CLKID_SSP0;
#endif mmc = &plat->mmc; mmc->cfg = &plat->cfg; diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index d41352a0bb8c..45b541fe1668 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -83,10 +83,7 @@ static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
while (length--) { /* We transfer 1 byte */ -#if defined(CONFIG_MX23)
writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);writel(1, &ssp_regs->hw_ssp_ctrl0_set);-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) writel(1, &ssp_regs->hw_ssp_xfer_size); #endif
@@ -146,9 +143,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv, int tl; int ret = 0;
-#if defined(CONFIG_MX23)
- const int mxs_spi_pio_words = 1;
-#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) const int mxs_spi_pio_words = 4; #endif
diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 325c3ee00ce3..3db3e18066e7 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -23,17 +23,9 @@
- Includes
*/
-#if defined(CONFIG_MX23) && defined(CONFIG_MX28) -#error Select either CONFIG_MX23 or CONFIG_MX28 , never both! -#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28) -#error Select one of CONFIG_MX23 or CONFIG_MX28 ! -#endif
#include <asm/arch/regs-base.h>
-#if defined(CONFIG_MX23) -#include <asm/arch/iomux-mx23.h> -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #include <asm/arch/iomux-mx28.h> #endif
@@ -54,9 +46,7 @@
/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ #define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#if defined(CONFIG_MX23) -#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024) -#elif defined(CONFIG_MX28) +#if defined(CONFIG_MX28) #define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) #endif
diff --git a/tools/Makefile b/tools/Makefile index 2d550432ba5a..ce8faeb85249 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -127,7 +127,7 @@ fit_info-objs := $(dumpimage-mkimage-objs) fit_info.o fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o file2include-objs := file2include.o
-ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),) +ifneq ($(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),) # Add CONFIG_MXS into host CFLAGS, so we can check whether or not register # the mxsimage support within tools/mxsimage.c . HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS @@ -155,7 +155,7 @@ HOSTCFLAGS_kwbimage.o += -DCONFIG_KWB_SECURE endif
# MXSImage needs LibSSL -ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE)$(CONFIG_FIT_CIPHER),) +ifneq ($(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE)$(CONFIG_FIT_CIPHER),) HOSTCFLAGS_kwbimage.o += \ $(shell pkg-config --cflags libssl libcrypto 2> /dev/null || echo "") HOSTLDLIBS_mkimage += \ @@ -186,7 +186,6 @@ hostprogs-$(CONFIG_X86) += ifdtool ifwitool-objs := ifwitool.o hostprogs-$(CONFIG_X86)$(CONFIG_SANDBOX) += ifwitool
-hostprogs-$(CONFIG_MX23) += mxsboot hostprogs-$(CONFIG_MX28) += mxsboot HOSTCFLAGS_mxsboot.o := -pedantic
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Fabio Estevam fabio.estevam@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-imx/mxs/Kconfig | 5 - board/freescale/mx28evk/Kconfig | 15 -- board/freescale/mx28evk/MAINTAINERS | 9 - board/freescale/mx28evk/Makefile | 10 -- board/freescale/mx28evk/README | 62 ------- board/freescale/mx28evk/iomux.c | 205 --------------------- board/freescale/mx28evk/mx28evk.c | 150 ---------------- configs/mx28evk_auart_console_defconfig | 63 ------- configs/mx28evk_defconfig | 63 ------- configs/mx28evk_nand_defconfig | 64 ------- configs/mx28evk_spi_defconfig | 60 ------- include/configs/mx28evk.h | 226 ------------------------ 12 files changed, 932 deletions(-) delete mode 100644 board/freescale/mx28evk/Kconfig delete mode 100644 board/freescale/mx28evk/MAINTAINERS delete mode 100644 board/freescale/mx28evk/Makefile delete mode 100644 board/freescale/mx28evk/README delete mode 100644 board/freescale/mx28evk/iomux.c delete mode 100644 board/freescale/mx28evk/mx28evk.c delete mode 100644 configs/mx28evk_auart_console_defconfig delete mode 100644 configs/mx28evk_defconfig delete mode 100644 configs/mx28evk_nand_defconfig delete mode 100644 configs/mx28evk_spi_defconfig delete mode 100644 include/configs/mx28evk.h
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index e04b0dc10f6c..6a6e6ebecf0b 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -14,10 +14,6 @@ config TARGET_APX4DEVKIT config TARGET_BG0900 bool "Support bg0900"
-config TARGET_MX28EVK - bool "Support mx28evk" - select BOARD_EARLY_INIT_F - config TARGET_SC_SPS_1 bool "Support sc_sps_1"
@@ -33,7 +29,6 @@ config SYS_SOC default "mxs"
source "board/bluegiga/apx4devkit/Kconfig" -source "board/freescale/mx28evk/Kconfig" source "board/liebherr/xea/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/schulercontrol/sc_sps_1/Kconfig" diff --git a/board/freescale/mx28evk/Kconfig b/board/freescale/mx28evk/Kconfig deleted file mode 100644 index 39777bd70fae..000000000000 --- a/board/freescale/mx28evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX28EVK - -config SYS_BOARD - default "mx28evk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "mx28evk" - -endif diff --git a/board/freescale/mx28evk/MAINTAINERS b/board/freescale/mx28evk/MAINTAINERS deleted file mode 100644 index a98a70558a72..000000000000 --- a/board/freescale/mx28evk/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -MX28EVK BOARD -M: Fabio Estevam fabio.estevam@nxp.com -S: Maintained -F: board/freescale/mx28evk/ -F: include/configs/mx28evk.h -F: configs/mx28evk_defconfig -F: configs/mx28evk_auart_console_defconfig -F: configs/mx28evk_nand_defconfig -F: configs/mx28evk_spi_defconfig diff --git a/board/freescale/mx28evk/Makefile b/board/freescale/mx28evk/Makefile deleted file mode 100644 index 057760433da9..000000000000 --- a/board/freescale/mx28evk/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := mx28evk.o -else -obj-y := iomux.o -endif diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README deleted file mode 100644 index d32f0efb3326..000000000000 --- a/board/freescale/mx28evk/README +++ /dev/null @@ -1,62 +0,0 @@ -FREESCALE MX28EVK -================== - -Supported hardware: MX28EVK rev C and D are supported in U-Boot. - -Files of the MX28EVK port --------------------------- - -arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28 -arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28 -board/freescale/mx28evk/ - MX28EVK board specific files -include/configs/mx28evk.h - MX28EVK configuration file - -Jumper configuration ---------------------- - -To boot MX28EVK from an SD card, set the boot mode DIP switches as: - - * Boot Mode Select: 1 0 0 1 (Boot from SD card Slot 0 - U42) - * JTAG PSWITCH RESET: To the right (reset disabled) - * Battery Source: Down - * Wall 5V: Up - * VDD 5V: To the left (off) - * Hold Button: Down (off) - -To boot MX28EVK from SPI NOR flash, set the boot mode DIP switches as: - - * Boot Mode Select: 0 0 1 0 (Boot from SSP2) - * JTAG PSWITCH RESET: To the right (reset disabled) - * Battery Source: Down - * Wall 5V: Up - * VDD 5V: To the left (off) - * Hold Button: Down (off) - -Environment Storage -------------------- - -There are three targets for mx28evk: - -"make mx28evk_config" - store environment variables into MMC - -or - -"make mx28evk_nand_config" - store environment variables into NAND flash - -or - -"make mx28evk_spi_config" - store environment variables into SPI NOR flash - -Choose the target accordingly. - -Note: The mx28evk board does not come with a NAND flash populated from the -factory. It comes with an empty slot (U23), which allows the insertion of a -48-pin TSOP flash device. - -mx28evk does not come with SPI NOR flash populated from the factory either. -It is possible to solder a SOIC memory on U49 or use a DIP8 on J89. -To get SPI communication to work R320, R321,R322 and C178 need to be populated. -Look in the schematics for the proper component values. - -Follow the instructions from doc/imx/common/mxs.txt to generate a bootable -SD card or to generate a binary to be flashed into SPI NOR. diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c deleted file mode 100644 index cc0c85885446..000000000000 --- a/board/freescale/mx28evk/iomux.c +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale MX28EVK IOMUX setup - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* DUART */ - MX28_PAD_PWM0__DUART_RX, - MX28_PAD_PWM1__DUART_TX, - - /* MMC0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* write protect */ - MX28_PAD_SSP1_SCK__GPIO_2_12, - /* MMC0 slot power enable */ - MX28_PAD_PWM3__GPIO_3_28 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - -#ifdef CONFIG_NAND_MXS - /* GPMI NAND */ - MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDN__GPMI_RDN | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), - MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, -#endif - - /* FEC0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, - /* FEC0 Enable */ - MX28_PAD_SSP1_DATA3__GPIO_2_15 | - (MXS_PAD_12MA | MXS_PAD_3V3), - /* FEC0 Reset */ - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - - /* FEC1 */ - MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, - - /* EMI */ - MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, - MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, - - MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - - /* SPI2 (for SPI flash) */ - MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_SS0__SSP2_D3 | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* LCD */ - MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, - MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, - MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD, - MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD, - MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD, - MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, /* LCD power */ - MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_LCD, /* LCD contrast */ -}; - -#define HW_DRAM_CTL29 (0x74 >> 2) -#define CS_MAP 0xf -#define COLUMN_SIZE 0x2 -#define ADDR_PINS 0x1 -#define APREBIT 0xa - -#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ - ADDR_PINS << 8 | APREBIT) - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; -} - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c deleted file mode 100644 index a6b66d99ccb1..000000000000 --- a/board/freescale/mx28evk/mx28evk.c +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale MX28EVK board - * - * (C) Copyright 2011 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam fabio.estevam@freescale.com - * - * Based on m28evk.c: - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <linux/delay.h> -#include <linux/mii.h> -#include <miiphy.h> -#include <netdev.h> -#include <errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - /* IO1 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK1, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - /* SSP2 clock at 160MHz */ - mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); - -#ifdef CONFIG_CMD_USB - mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); - mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 | - MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL); - gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1); -#endif - - /* Power on LCD */ - gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1); - - /* Set contrast to maximum */ - gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -#ifdef CONFIG_CMD_MMC -static int mx28evk_mmc_wp(int id) -{ - if (id != 0) { - printf("MXS MMC: Invalid card selected (card id = %d)\n", id); - return 1; - } - - return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12); -} - -int board_mmc_init(struct bd_info *bis) -{ - /* Configure WP as input */ - gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12); - - /* Configure MMC0 Power Enable */ - gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); - - return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, NULL); -} -#endif - -#ifdef CONFIG_CMD_NET - -int board_eth_init(struct bd_info *bis) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - struct eth_device *dev; - int ret; - - ret = cpu_eth_init(bis); - if (ret) - return ret; - - /* MX28EVK uses ENET_CLK PAD to drive FEC clock */ - writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, - &clkctrl_regs->hw_clkctrl_enet); - - /* Power-on FECs */ - gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0); - - /* Reset FEC PHYs */ - gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); - udelay(200); - gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); - - ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); - if (ret) { - puts("FEC MXS: Unable to init FEC0\n"); - return ret; - } - - ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE); - if (ret) { - puts("FEC MXS: Unable to init FEC1\n"); - return ret; - } - - dev = eth_get_dev_by_name("FEC0"); - if (!dev) { - puts("FEC MXS: Unable to get FEC0 device entry\n"); - return -EINVAL; - } - - dev = eth_get_dev_by_name("FEC1"); - if (!dev) { - puts("FEC MXS: Unable to get FEC1 device entry\n"); - return -EINVAL; - } - - return ret; -} - -#endif diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig deleted file mode 100644 index ec4fd6585ee5..000000000000 --- a/configs/mx28evk_auart_console_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_VIDEO=y -CONFIG_SPLASH_SCREEN=y -CONFIG_VIDEO_BMP_GZIP=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig deleted file mode 100644 index 4f0ed83bc1f0..000000000000 --- a/configs/mx28evk_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_FIT=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_VIDEO=y -CONFIG_SPLASH_SCREEN=y -CONFIG_VIDEO_BMP_GZIP=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig deleted file mode 100644 index 7d95b8fc52de..000000000000 --- a/configs/mx28evk_nand_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x380000 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_VIDEO=y -CONFIG_SPLASH_SCREEN=y -CONFIG_VIDEO_BMP_GZIP=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig deleted file mode 100644 index e969d50af7fe..000000000000 --- a/configs/mx28evk_spi_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_VIDEO=y -CONFIG_SPLASH_SCREEN=y -CONFIG_VIDEO_BMP_GZIP=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h deleted file mode 100644 index a65df4860810..000000000000 --- a/include/configs/mx28evk.h +++ /dev/null @@ -1,226 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Freescale Semiconductor, Inc. - * Author: Fabio Estevam fabio.estevam@freescale.com - * - * Based on m28evk.h: - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - */ -#ifndef __CONFIGS_MX28EVK_H__ -#define __CONFIGS_MX28EVK_H__ - -/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* Environment is in MMC */ - -/* Environment is in NAND */ -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_RANGE (512 * 1024) -#endif - -/* Environment is in SPI flash */ - -/* UBI and NAND partitioning */ - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_MDIO_BASE MXS_ENET0_BASE -#define CONFIG_MX28_FEC_MAC_IN_OCOTP -#endif - -/* RTC */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_MXS -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* Framebuffer support */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_LOGO -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) -#endif - -/* Boot Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ubifs_file=filesystem.ubifs\0" \ - "update_nand_full_filename=u-boot.nand\0" \ - "update_nand_firmware_filename=u-boot.sb\0" \ - "update_nand_firmware_maxsz=0x100000\0" \ - "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ - "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ - "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \ - "nand device 0 ; " \ - "nand info ; " \ - "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \ - "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \ - "update_nand_firmware_full=" /* Update FCB, DBBT and FW */ \ - "if tftp ${update_nand_full_filename} ; then " \ - "run update_nand_get_fcb_size ; " \ - "nand scrub -y 0x0 ${filesize} ; " \ - "nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \ - "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \ - "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \ - "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \ - "fi\0" \ - "update_nand_firmware=" /* Update only firmware */ \ - "if tftp ${update_nand_firmware_filename} ; then " \ - "run update_nand_get_fcb_size ; " \ - "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \ - "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \ - "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \ - "nand erase ${fcb_sz} ${fw_sz} ; " \ - "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ - "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ - "fi\0" \ - "update_nand_kernel=" /* Update kernel */ \ - "mtdparts default; " \ - "nand erase.part kernel; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "nand write ${loadaddr} kernel ${filesize}\0" \ - "update_nand_fdt=" /* Update fdt */ \ - "mtdparts default; " \ - "nand erase.part fdt; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${fdt_file}; " \ - "nand write ${loadaddr} fdt ${filesize}\0" \ - "update_nand_filesystem=" /* Update filesystem */ \ - "mtdparts default; " \ - "nand erase.part filesystem; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${ubifs_file}; " \ - "ubi part filesystem; " \ - "ubi create filesystem; " \ - "ubi write ${loadaddr} filesystem ${filesize}\0" \ - "nandargs=setenv bootargs console=${console_mainline},${baudrate} " \ - "rootfstype=ubifs ubi.mtd=6 root=ubi0_0 ${mtdparts}\0" \ - "nandboot=" /* Boot from NAND */ \ - "mtdparts default; " \ - "run nandargs; " \ - "nand read ${loadaddr} kernel 0x00400000; " \ - "if test ${boot_fdt} = yes; then " \ - "nand read ${fdt_addr} fdt 0x00080000; " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = no; then " \ - "bootz; " \ - "else " \ - "echo "ERROR: Set boot_fdt to yes or no."; " \ - "fi; " \ - "fi\0" \ - "update_sd_firmware_filename=u-boot.sd\0" \ - "update_sd_firmware=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_sd_firmware_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ - "fi ; " \ - "fi\0" \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console_fsl=ttyAM0\0" \ - "console_mainline=ttyAMA0\0" \ - "fdt_file=imx28-evk.dtb\0" \ - "fdt_addr=0x41000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \ - "mmcargs=setenv bootargs console=${console_mainline},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console_mainline},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;" \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_MX28EVK_H__ */
Hi Tom,
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
This is very strange as imx28 SoC is still in active production (and will be for some years from now on).
I think that this board shall stay in U-Boot, as it is the official EVK board from NXP.
I've added Peng to this mail, so maybe NXP will find some time to convert it.
Cc: Fabio Estevam fabio.estevam@nxp.com Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/mach-imx/mxs/Kconfig | 5 - board/freescale/mx28evk/Kconfig | 15 -- board/freescale/mx28evk/MAINTAINERS | 9 - board/freescale/mx28evk/Makefile | 10 -- board/freescale/mx28evk/README | 62 ------- board/freescale/mx28evk/iomux.c | 205 --------------------- board/freescale/mx28evk/mx28evk.c | 150 ---------------- configs/mx28evk_auart_console_defconfig | 63 ------- configs/mx28evk_defconfig | 63 ------- configs/mx28evk_nand_defconfig | 64 ------- configs/mx28evk_spi_defconfig | 60 ------- include/configs/mx28evk.h | 226 ------------------------ 12 files changed, 932 deletions(-) delete mode 100644 board/freescale/mx28evk/Kconfig delete mode 100644 board/freescale/mx28evk/MAINTAINERS delete mode 100644 board/freescale/mx28evk/Makefile delete mode 100644 board/freescale/mx28evk/README delete mode 100644 board/freescale/mx28evk/iomux.c delete mode 100644 board/freescale/mx28evk/mx28evk.c delete mode 100644 configs/mx28evk_auart_console_defconfig delete mode 100644 configs/mx28evk_defconfig delete mode 100644 configs/mx28evk_nand_defconfig delete mode 100644 configs/mx28evk_spi_defconfig delete mode 100644 include/configs/mx28evk.h
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index e04b0dc10f6c..6a6e6ebecf0b 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -14,10 +14,6 @@ config TARGET_APX4DEVKIT config TARGET_BG0900 bool "Support bg0900"
-config TARGET_MX28EVK
- bool "Support mx28evk"
- select BOARD_EARLY_INIT_F
config TARGET_SC_SPS_1 bool "Support sc_sps_1"
@@ -33,7 +29,6 @@ config SYS_SOC default "mxs"
source "board/bluegiga/apx4devkit/Kconfig" -source "board/freescale/mx28evk/Kconfig" source "board/liebherr/xea/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/schulercontrol/sc_sps_1/Kconfig" diff --git a/board/freescale/mx28evk/Kconfig b/board/freescale/mx28evk/Kconfig deleted file mode 100644 index 39777bd70fae..000000000000 --- a/board/freescale/mx28evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX28EVK
-config SYS_BOARD
- default "mx28evk"
-config SYS_VENDOR
- default "freescale"
-config SYS_SOC
- default "mxs"
-config SYS_CONFIG_NAME
- default "mx28evk"
-endif diff --git a/board/freescale/mx28evk/MAINTAINERS b/board/freescale/mx28evk/MAINTAINERS deleted file mode 100644 index a98a70558a72..000000000000 --- a/board/freescale/mx28evk/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -MX28EVK BOARD -M: Fabio Estevam fabio.estevam@nxp.com -S: Maintained -F: board/freescale/mx28evk/ -F: include/configs/mx28evk.h -F: configs/mx28evk_defconfig -F: configs/mx28evk_auart_console_defconfig -F: configs/mx28evk_nand_defconfig -F: configs/mx28evk_spi_defconfig diff --git a/board/freescale/mx28evk/Makefile b/board/freescale/mx28evk/Makefile deleted file mode 100644 index 057760433da9..000000000000 --- a/board/freescale/mx28evk/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifndef CONFIG_SPL_BUILD -obj-y := mx28evk.o -else -obj-y := iomux.o -endif diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README deleted file mode 100644 index d32f0efb3326..000000000000 --- a/board/freescale/mx28evk/README +++ /dev/null @@ -1,62 +0,0 @@
-FREESCALE MX28EVK
-Supported hardware: MX28EVK rev C and D are supported in U-Boot.
-Files of the MX28EVK port
-arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28 -arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28 -board/freescale/mx28evk/ - MX28EVK board specific files -include/configs/mx28evk.h - MX28EVK configuration file -
-Jumper configuration
-To boot MX28EVK from an SD card, set the boot mode DIP switches as:
- Boot Mode Select: 1 0 0 1 (Boot from SD card Slot 0 - U42)
- JTAG PSWITCH RESET: To the right (reset disabled)
- Battery Source: Down
- Wall 5V: Up
- VDD 5V: To the left (off)
- Hold Button: Down (off)
-To boot MX28EVK from SPI NOR flash, set the boot mode DIP switches as: -
- Boot Mode Select: 0 0 1 0 (Boot from SSP2)
- JTAG PSWITCH RESET: To the right (reset disabled)
- Battery Source: Down
- Wall 5V: Up
- VDD 5V: To the left (off)
- Hold Button: Down (off)
-Environment Storage
-There are three targets for mx28evk:
-"make mx28evk_config" - store environment variables into MMC - -or
-"make mx28evk_nand_config" - store environment variables into NAND flash - -or
-"make mx28evk_spi_config" - store environment variables into SPI NOR flash - -Choose the target accordingly.
-Note: The mx28evk board does not come with a NAND flash populated from the -factory. It comes with an empty slot (U23), which allows the insertion of a -48-pin TSOP flash device.
-mx28evk does not come with SPI NOR flash populated from the factory either. -It is possible to solder a SOIC memory on U49 or use a DIP8 on J89. -To get SPI communication to work R320, R321,R322 and C178 need to be populated. -Look in the schematics for the proper component values. - -Follow the instructions from doc/imx/common/mxs.txt to generate a bootable -SD card or to generate a binary to be flashed into SPI NOR. diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c deleted file mode 100644 index cc0c85885446..000000000000 --- a/board/freescale/mx28evk/iomux.c +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- Freescale MX28EVK IOMUX setup
- Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com
- on behalf of DENX Software Engineering GmbH
- */
-#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h>
-#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = {
- /* DUART */
- MX28_PAD_PWM0__DUART_RX,
- MX28_PAD_PWM1__DUART_TX,
- /* MMC0 */
- MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),- MX28_PAD_SSP0_SCK__SSP0_SCK |
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),- /* write protect */
- MX28_PAD_SSP1_SCK__GPIO_2_12,
- /* MMC0 slot power enable */
- MX28_PAD_PWM3__GPIO_3_28 |
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),-#ifdef CONFIG_NAND_MXS
- /* GPMI NAND */
- MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RDN__GPMI_RDN |
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),- MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
-#endif
- /* FEC0 */
- MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
- MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
- /* FEC0 Enable */
- MX28_PAD_SSP1_DATA3__GPIO_2_15 |
(MXS_PAD_12MA | MXS_PAD_3V3),- /* FEC0 Reset */
- MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),- /* FEC1 */
- MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
- /* EMI */
- MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK |
MUX_CONFIG_EMI,
- MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
- /* SPI2 (for SPI flash) */
- MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
- MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
- MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
- MX28_PAD_SSP2_SS0__SSP2_D3 |
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),- /* I2C */
- MX28_PAD_I2C0_SCL__I2C0_SCL,
- MX28_PAD_I2C0_SDA__I2C0_SDA,
- /* LCD */
- MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
- MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
- MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
- MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD,
- MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, /* LCD power
*/
- MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_LCD, /* LCD contrast */
-};
-#define HW_DRAM_CTL29 (0x74 >> 2) -#define CS_MAP 0xf -#define COLUMN_SIZE 0x2 -#define ADDR_PINS 0x1 -#define APREBIT 0xa
-#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \
ADDR_PINS << 8 | APREBIT)-void mxs_adjust_memory_params(uint32_t *dram_vals) -{
- dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
-}
-void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{
- mxs_common_spl_init(arg, resptr, iomux_setup,
ARRAY_SIZE(iomux_setup)); -} diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c deleted file mode 100644 index a6b66d99ccb1..000000000000 --- a/board/freescale/mx28evk/mx28evk.c +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- Freescale MX28EVK board
- (C) Copyright 2011 Freescale Semiconductor, Inc.
- Author: Fabio Estevam fabio.estevam@freescale.com
- Based on m28evk.c:
- Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com
- on behalf of DENX Software Engineering GmbH
- */
-#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <linux/delay.h> -#include <linux/mii.h> -#include <miiphy.h> -#include <netdev.h> -#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-/*
- Functions
- */
-int board_early_init_f(void) -{
- /* IO0 clock at 480MHz */
- mxs_set_ioclk(MXC_IOCLK0, 480000);
- /* IO1 clock at 480MHz */
- mxs_set_ioclk(MXC_IOCLK1, 480000);
- /* SSP0 clock at 96MHz */
- mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
- /* SSP2 clock at 160MHz */
- mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
-#ifdef CONFIG_CMD_USB
- mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
- mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 |
MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);- gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
-#endif
- /* Power on LCD */
- gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1);
- /* Set contrast to maximum */
- gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1);
- return 0;
-}
-int dram_init(void) -{
- return mxs_dram_init();
-}
-int board_init(void) -{
- /* Adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- return 0;
-}
-#ifdef CONFIG_CMD_MMC -static int mx28evk_mmc_wp(int id) -{
- if (id != 0) {
printf("MXS MMC: Invalid card selected (card id =%d)\n", id);
return 1;- }
- return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12);
-}
-int board_mmc_init(struct bd_info *bis) -{
- /* Configure WP as input */
- gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12);
- /* Configure MMC0 Power Enable */
- gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
- return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, NULL);
-} -#endif
-#ifdef CONFIG_CMD_NET
-int board_eth_init(struct bd_info *bis) -{
- struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;- struct eth_device *dev;
- int ret;
- ret = cpu_eth_init(bis);
- if (ret)
return ret;- /* MX28EVK uses ENET_CLK PAD to drive FEC clock */
- writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK |
CLKCTRL_ENET_CLK_OUT_EN,
&clkctrl_regs->hw_clkctrl_enet);- /* Power-on FECs */
- gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
- /* Reset FEC PHYs */
- gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
- udelay(200);
- gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
- ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
- if (ret) {
puts("FEC MXS: Unable to init FEC0\n");return ret;- }
- ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
- if (ret) {
puts("FEC MXS: Unable to init FEC1\n");return ret;- }
- dev = eth_get_dev_by_name("FEC0");
- if (!dev) {
puts("FEC MXS: Unable to get FEC0 device entry\n");return -EINVAL;- }
- dev = eth_get_dev_by_name("FEC1");
- if (!dev) {
puts("FEC MXS: Unable to get FEC1 device entry\n");return -EINVAL;- }
- return ret;
-}
-#endif diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig deleted file mode 100644 index ec4fd6585ee5..000000000000 --- a/configs/mx28evk_auart_console_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_VIDEO=y -CONFIG_SPLASH_SCREEN=y -CONFIG_VIDEO_BMP_GZIP=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig deleted file mode 100644 index 4f0ed83bc1f0..000000000000 --- a/configs/mx28evk_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_FIT=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_VIDEO=y -CONFIG_SPLASH_SCREEN=y -CONFIG_VIDEO_BMP_GZIP=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig deleted file mode 100644 index 7d95b8fc52de..000000000000 --- a/configs/mx28evk_nand_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x380000 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_VIDEO=y -CONFIG_SPLASH_SCREEN=y -CONFIG_VIDEO_BMP_GZIP=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig deleted file mode 100644 index e969d50af7fe..000000000000 --- a/configs/mx28evk_spi_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_VIDEO=y -CONFIG_SPLASH_SCREEN=y -CONFIG_VIDEO_BMP_GZIP=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h deleted file mode 100644 index a65df4860810..000000000000 --- a/include/configs/mx28evk.h +++ /dev/null @@ -1,226 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- (C) Copyright 2011 Freescale Semiconductor, Inc.
- Author: Fabio Estevam fabio.estevam@freescale.com
- Based on m28evk.h:
- Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com
- on behalf of DENX Software Engineering GmbH
- */
-#ifndef __CONFIGS_MX28EVK_H__ -#define __CONFIGS_MX28EVK_H__
-/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK
-/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */
-/* Environment is in MMC */
-/* Environment is in NAND */ -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_RANGE (512 * 1024) -#endif
-/* Environment is in SPI flash */
-/* UBI and NAND partitioning */
-/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_MDIO_BASE MXS_ENET0_BASE -#define CONFIG_MX28_FEC_MAC_IN_OCOTP -#endif
-/* RTC */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_MXS -#endif
-/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif
-/* Framebuffer support */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_LOGO -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) -#endif
-/* Boot Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \
- "ubifs_file=filesystem.ubifs\0" \
- "update_nand_full_filename=u-boot.nand\0" \
- "update_nand_firmware_filename=u-boot.sb\0" \
- "update_nand_firmware_maxsz=0x100000\0" \
- "update_nand_stride=0x40\0" /* MX28 datasheet ch.
12.12 */ \
- "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12
*/ \
- "update_nand_get_fcb_size=" /* Get size of FCB blocks
*/ \
"nand device 0 ; " \"nand info ; " \"setexpr fcb_sz ${update_nand_stride} *${update_nand_count};" \
"setexpr update_nand_fcb ${fcb_sz} *${nand_writesize}\0" \
- "update_nand_firmware_full=" /* Update FCB, DBBT and FW */ \
"if tftp ${update_nand_full_filename} ; then " \"run update_nand_get_fcb_size ; " \"nand scrub -y 0x0 ${filesize} ; " \"nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \"setexpr update_off ${loadaddr} + ${update_nand_fcb}; " \
"setexpr update_sz ${filesize} - ${update_nand_fcb}; " \
"nand write ${update_off} ${update_nand_fcb}${update_sz} ; " \
"fi\0" \- "update_nand_firmware=" /* Update only
firmware */ \
"if tftp ${update_nand_firmware_filename} ; then " \"run update_nand_get_fcb_size ; " \"setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB +DBBT */ \
"setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; "\
"setexpr fw_off ${fcb_sz} +${update_nand_firmware_maxsz};" \
"nand erase ${fcb_sz} ${fw_sz} ; " \"nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \"nand write ${loadaddr} ${fw_off} ${filesize} ; " \"fi\0" \- "update_nand_kernel=" /* Update kernel */ \
"mtdparts default; " \"nand erase.part kernel; " \"if test ${ip_dyn} = yes; then " \"setenv get_cmd dhcp; " \"else " \"setenv get_cmd tftp; " \"fi; " \"${get_cmd} ${image}; " \"nand write ${loadaddr} kernel ${filesize}\0" \- "update_nand_fdt=" /* Update fdt */ \
"mtdparts default; " \"nand erase.part fdt; " \"if test ${ip_dyn} = yes; then " \"setenv get_cmd dhcp; " \"else " \"setenv get_cmd tftp; " \"fi; " \"${get_cmd} ${fdt_file}; " \"nand write ${loadaddr} fdt ${filesize}\0" \- "update_nand_filesystem=" /* Update
filesystem */ \
"mtdparts default; " \"nand erase.part filesystem; " \"if test ${ip_dyn} = yes; then " \"setenv get_cmd dhcp; " \"else " \"setenv get_cmd tftp; " \"fi; " \"${get_cmd} ${ubifs_file}; " \"ubi part filesystem; " \"ubi create filesystem; " \"ubi write ${loadaddr} filesystem ${filesize}\0" \- "nandargs=setenv bootargs
console=${console_mainline},${baudrate} " \
"rootfstype=ubifs ubi.mtd=6 root=ubi0_0${mtdparts}\0" \
- "nandboot=" /* Boot from NAND */ \
"mtdparts default; " \"run nandargs; " \"nand read ${loadaddr} kernel 0x00400000; " \"if test ${boot_fdt} = yes; then " \"nand read ${fdt_addr} fdt 0x00080000; " \"bootz ${loadaddr} - ${fdt_addr}; " \"else " \"if test ${boot_fdt} = no; then " \"bootz; " \"else " \"echo \"ERROR: Set boot_fdt to yesor no."; " \
"fi; " \"fi\0" \- "update_sd_firmware_filename=u-boot.sd\0" \
- "update_sd_firmware=" /* Update the SD
firmware partition */ \
"if mmc rescan ; then " \"if tftp ${update_sd_firmware_filename} ; then " \"setexpr fw_sz ${filesize} / 0x200 ; " /* SDblock size */ \
"setexpr fw_sz ${fw_sz} + 1 ; " \"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \"fi ; " \"fi\0" \- "script=boot.scr\0" \
- "image=zImage\0" \
- "console_fsl=ttyAM0\0" \
- "console_mainline=ttyAMA0\0" \
- "fdt_file=imx28-evk.dtb\0" \
- "fdt_addr=0x41000000\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
- "mmcdev=0\0" \
- "mmcpart=2\0" \
- "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
- "mmcargs=setenv bootargs
console=${console_mainline},${baudrate} " \
"root=${mmcroot}\0" \- "loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
"source\0" \- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \"if test ${boot_fdt} = yes || test ${boot_fdt} =try; then " \
"if run loadfdt; then " \"bootz ${loadaddr} - ${fdt_addr}; " \"else " \"if test ${boot_fdt} = try; then " \"bootz; " \"else " \"echo WARN: Cannot load theDT; " \
"fi; " \"fi; " \"else " \"bootz; " \"fi;\0" \- "netargs=setenv bootargs
console=${console_mainline},${baudrate} " \
"root=/dev/nfs " \"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \- "netboot=echo Booting from net ...; " \
"run netargs; " \"if test ${ip_dyn} = yes; then " \"setenv get_cmd dhcp; " \"else " \"setenv get_cmd tftp; " \"fi; " \"${get_cmd} ${image}; " \"if test ${boot_fdt} = yes; then " \"if ${get_cmd} ${fdt_addr} ${fdt_file}; then" \
"bootz ${loadaddr} - ${fdt_addr}; " \"else " \"if test ${boot_fdt} = try; then " \"bootz; " \"else " \"echo WARN: Cannot load theDT; " \
"fi;" \"fi; " \"else " \"bootz; " \"fi;\0"-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \"run bootscript; " \"else " \"if run loadimage; then " \"run mmcboot; " \"else run netboot; " \"fi; " \"fi; " \- "else run netboot; fi"
-/* The rest of the configuration is shared */ -#include <configs/mxs.h>
-#endif /* __CONFIGS_MX28EVK_H__ */
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
On Tue, Feb 09, 2021 at 02:11:54PM +0100, Lukasz Majewski wrote:
Hi Tom,
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
This is very strange as imx28 SoC is still in active production (and will be for some years from now on).
I think that this board shall stay in U-Boot, as it is the official EVK board from NXP.
I've added Peng to this mail, so maybe NXP will find some time to convert it.
It can stay so long as someone converts it. It's also missing the CONFIG_DM conversion (v2020.01), CONFIG_DM_USB (v2019.07), CONFIG_DM_VIDEO (v2019.07) and CONFIG_DM_ETH (v2020.07) conversions.
Hi Tom,
On Tue, Feb 9, 2021 at 10:34 AM Tom Rini trini@konsulko.com wrote:
It can stay so long as someone converts it. It's also missing the CONFIG_DM conversion (v2020.01), CONFIG_DM_USB (v2019.07), CONFIG_DM_VIDEO (v2019.07) and CONFIG_DM_ETH (v2020.07) conversions.
I will work on converting this board to DM. I will try to finish the conversion in the following weeks.
These are the boards that I want to convert to DM: imx53-qsb, imx51-evk, imx28-evk.
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Lauri Hintsala lauri.hintsala@bluegiga.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-imx/mxs/Kconfig | 4 - board/bluegiga/apx4devkit/Kconfig | 15 --- board/bluegiga/apx4devkit/MAINTAINERS | 6 - board/bluegiga/apx4devkit/Makefile | 10 -- board/bluegiga/apx4devkit/apx4devkit.c | 142 ----------------------- board/bluegiga/apx4devkit/spl_boot.c | 152 ------------------------- configs/apx4devkit_defconfig | 50 -------- include/configs/apx4devkit.h | 77 ------------- 8 files changed, 456 deletions(-) delete mode 100644 board/bluegiga/apx4devkit/Kconfig delete mode 100644 board/bluegiga/apx4devkit/MAINTAINERS delete mode 100644 board/bluegiga/apx4devkit/Makefile delete mode 100644 board/bluegiga/apx4devkit/apx4devkit.c delete mode 100644 board/bluegiga/apx4devkit/spl_boot.c delete mode 100644 configs/apx4devkit_defconfig delete mode 100644 include/configs/apx4devkit.h
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index 6a6e6ebecf0b..40d74c93b305 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -8,9 +8,6 @@ choice prompt "MX28 board select" optional
-config TARGET_APX4DEVKIT - bool "Support apx4devkit" - config TARGET_BG0900 bool "Support bg0900"
@@ -28,7 +25,6 @@ endchoice config SYS_SOC default "mxs"
-source "board/bluegiga/apx4devkit/Kconfig" source "board/liebherr/xea/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/schulercontrol/sc_sps_1/Kconfig" diff --git a/board/bluegiga/apx4devkit/Kconfig b/board/bluegiga/apx4devkit/Kconfig deleted file mode 100644 index f327fa15cf07..000000000000 --- a/board/bluegiga/apx4devkit/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_APX4DEVKIT - -config SYS_BOARD - default "apx4devkit" - -config SYS_VENDOR - default "bluegiga" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "apx4devkit" - -endif diff --git a/board/bluegiga/apx4devkit/MAINTAINERS b/board/bluegiga/apx4devkit/MAINTAINERS deleted file mode 100644 index 286e9e9f063e..000000000000 --- a/board/bluegiga/apx4devkit/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -APX4DEVKIT BOARD -M: Lauri Hintsala lauri.hintsala@bluegiga.com -S: Maintained -F: board/bluegiga/apx4devkit/ -F: include/configs/apx4devkit.h -F: configs/apx4devkit_defconfig diff --git a/board/bluegiga/apx4devkit/Makefile b/board/bluegiga/apx4devkit/Makefile deleted file mode 100644 index 039d62dda2ad..000000000000 --- a/board/bluegiga/apx4devkit/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := apx4devkit.o -else -obj-y := spl_boot.o -endif diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c deleted file mode 100644 index 739f71f5c4d1..000000000000 --- a/board/bluegiga/apx4devkit/apx4devkit.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Bluegiga APX4 Development Kit - * - * Copyright (C) 2012 Bluegiga Technologies Oy - * - * Authors: - * Veli-Pekka Peltola veli-pekka.peltola@bluegiga.com - * Lauri Hintsala lauri.hintsala@bluegiga.com - * - * Based on m28evk.c: - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/setup.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <env.h> -#include <linux/mii.h> -#include <miiphy.h> -#include <netdev.h> -#include <errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* Functions */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - /* IO1 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK1, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(struct bd_info *bis) -{ - return mxsmmc_initialize(bis, 0, NULL, NULL); -} -#endif - - -#ifdef CONFIG_CMD_NET - -#define MII_PHY_CTRL2 0x1f -int fecmxc_mii_postcall(int phy) -{ - /* change PHY RMII clock to 50MHz */ - miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - int ret; - struct eth_device *dev; - - ret = cpu_eth_init(bis); - if (ret) { - printf("FEC MXS: Unable to init FEC clocks\n"); - return ret; - } - - ret = fecmxc_initialize(bis); - if (ret) { - printf("FEC MXS: Unable to init FEC\n"); - return ret; - } - - dev = eth_get_dev_by_name("FEC"); - if (!dev) { - printf("FEC MXS: Unable to get FEC device entry\n"); - return -EINVAL; - } - - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXS: Unable to register FEC MII postcall\n"); - return ret; - } - - return ret; -} -#endif - -#ifdef CONFIG_SERIAL_TAG -#define MXS_OCOTP_MAX_TIMEOUT 1000000 -void get_board_serial(struct tag_serialnr *serialnr) -{ - struct mxs_ocotp_regs *ocotp_regs = - (struct mxs_ocotp_regs *)MXS_OCOTP_BASE; - - serialnr->high = 0; - serialnr->low = 0; - - writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); - - if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, - MXS_OCOTP_MAX_TIMEOUT)) { - printf("MXS: Can't get serial number from OCOTP\n"); - return; - } - - serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3); -} -#endif - -#ifdef CONFIG_REVISION_TAG -u32 get_board_rev(void) -{ - if (env_get("revision#") != NULL) - return simple_strtoul(env_get("revision#"), NULL, 10); - return 0; -} -#endif diff --git a/board/bluegiga/apx4devkit/spl_boot.c b/board/bluegiga/apx4devkit/spl_boot.c deleted file mode 100644 index e5d5c4637b0c..000000000000 --- a/board/bluegiga/apx4devkit/spl_boot.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Bluegiga APX4 Development Kit - * - * Copyright (C) 2012 Bluegiga Technologies Oy - * - * Authors: - * Veli-Pekka Peltola veli-pekka.peltola@bluegiga.com - * Lauri Hintsala lauri.hintsala@bluegiga.com - * - * Based on spl_boot.c: - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <config.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* DUART */ - MX28_PAD_PWM0__DUART_RX, - MX28_PAD_PWM1__DUART_TX, - - /* LED */ - MX28_PAD_PWM3__GPIO_3_28, - - /* MMC0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* GPMI NAND */ - MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDN__GPMI_RDN | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), - MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, - - /* FEC0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* EMI */ - MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, - MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, - - MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, -}; - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); - - /* switch LED on */ - gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); -} - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - /* - * All address lines are routed from CPU to memory chip. - * ADDR_PINS field is set to zero. - */ - dram_vals[0x74 >> 2] = 0x0f02000a; - - /* Used memory has 4 banks. EIGHT_BANK_MODE bit is disabled. */ - dram_vals[0x7c >> 2] = 0x00000101; -} diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig deleted file mode 100644 index 2ada946e5281..000000000000 --- a/configs/apx4devkit_defconfig +++ /dev/null @@ -1,50 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x120000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_APX4DEVKIT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x180000 -CONFIG_BOOTDELAY=1 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env),-(root)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h deleted file mode 100644 index bcd55bb8689e..000000000000 --- a/include/configs/apx4devkit.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Bluegiga Technologies Oy - * - * Authors: - * Veli-Pekka Peltola veli-pekka.peltola@bluegiga.com - * Lauri Hintsala lauri.hintsala@bluegiga.com - * - * Based on m28evk.h: - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - */ -#ifndef __CONFIGS_APX4DEVKIT_H__ -#define __CONFIGS_APX4DEVKIT_H__ - -/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment is in NAND */ -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_RANGE (384 * 1024) -#endif - -/* UBI and NAND partitioning */ - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 -#define IMX_FEC_BASE MXS_ENET0_BASE -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* Boot Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTCOMMAND "run bootcmd_nand" -#define CONFIG_LOADADDR 0x41000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SERIAL_TAG -#define CONFIG_REVISION_TAG - -/* Extra Environments */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "verify=no\0" \ - "bootcmd=run bootcmd_nand\0" \ - "kernelargs=console=tty0 console=ttyAMA0,115200 consoleblank=0\0" \ - "bootargs_nand=" \ - "setenv bootargs ${kernelargs} ubi.mtd=3,2048 " \ - "root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \ - "bootcmd_nand=" \ - "run bootargs_nand && ubi part root 2048 && " \ - "ubifsmount ubi:rootfs && ubifsload 41000000 boot/uImage && " \ - "bootm 41000000\0" \ - "bootargs_mmc=" \ - "setenv bootargs ${kernelargs} " \ - "root=/dev/mmcblk0p2 rootwait ${mtdparts} rw\0" \ - "bootcmd_mmc=" \ - "run bootargs_mmc && mmc rescan && " \ - "ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \ -"" - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_APX4DEVKIT_H__ */
That's fine. apx4devkit is not under active development.
Best regards, Lauri Hintsala
On 9 Feb 2021, at 15.02, Tom Rini trini@konsulko.com wrote:
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Lauri Hintsala lauri.hintsala@bluegiga.com Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/mach-imx/mxs/Kconfig | 4 - board/bluegiga/apx4devkit/Kconfig | 15 --- board/bluegiga/apx4devkit/MAINTAINERS | 6 - board/bluegiga/apx4devkit/Makefile | 10 -- board/bluegiga/apx4devkit/apx4devkit.c | 142 ----------------------- board/bluegiga/apx4devkit/spl_boot.c | 152 ------------------------- configs/apx4devkit_defconfig | 50 -------- include/configs/apx4devkit.h | 77 ------------- 8 files changed, 456 deletions(-) delete mode 100644 board/bluegiga/apx4devkit/Kconfig delete mode 100644 board/bluegiga/apx4devkit/MAINTAINERS delete mode 100644 board/bluegiga/apx4devkit/Makefile delete mode 100644 board/bluegiga/apx4devkit/apx4devkit.c delete mode 100644 board/bluegiga/apx4devkit/spl_boot.c delete mode 100644 configs/apx4devkit_defconfig delete mode 100644 include/configs/apx4devkit.h
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index 6a6e6ebecf0b..40d74c93b305 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -8,9 +8,6 @@ choice prompt "MX28 board select" optional
-config TARGET_APX4DEVKIT
bool "Support apx4devkit"config TARGET_BG0900 bool "Support bg0900"
@@ -28,7 +25,6 @@ endchoice config SYS_SOC default "mxs"
-source "board/bluegiga/apx4devkit/Kconfig" source "board/liebherr/xea/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/schulercontrol/sc_sps_1/Kconfig" diff --git a/board/bluegiga/apx4devkit/Kconfig b/board/bluegiga/apx4devkit/Kconfig deleted file mode 100644 index f327fa15cf07..000000000000 --- a/board/bluegiga/apx4devkit/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_APX4DEVKIT
-config SYS_BOARD
default "apx4devkit"-config SYS_VENDOR
default "bluegiga"-config SYS_SOC
default "mxs"-config SYS_CONFIG_NAME
default "apx4devkit"-endif diff --git a/board/bluegiga/apx4devkit/MAINTAINERS b/board/bluegiga/apx4devkit/MAINTAINERS deleted file mode 100644 index 286e9e9f063e..000000000000 --- a/board/bluegiga/apx4devkit/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -APX4DEVKIT BOARD -M: Lauri Hintsala lauri.hintsala@bluegiga.com -S: Maintained -F: board/bluegiga/apx4devkit/ -F: include/configs/apx4devkit.h -F: configs/apx4devkit_defconfig diff --git a/board/bluegiga/apx4devkit/Makefile b/board/bluegiga/apx4devkit/Makefile deleted file mode 100644 index 039d62dda2ad..000000000000 --- a/board/bluegiga/apx4devkit/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifndef CONFIG_SPL_BUILD -obj-y := apx4devkit.o -else -obj-y := spl_boot.o -endif diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c deleted file mode 100644 index 739f71f5c4d1..000000000000 --- a/board/bluegiga/apx4devkit/apx4devkit.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- Bluegiga APX4 Development Kit
- Copyright (C) 2012 Bluegiga Technologies Oy
- Authors:
- Veli-Pekka Peltola veli-pekka.peltola@bluegiga.com
- Lauri Hintsala lauri.hintsala@bluegiga.com
- Based on m28evk.c:
- Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com
- on behalf of DENX Software Engineering GmbH
- */
-#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/setup.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <env.h> -#include <linux/mii.h> -#include <miiphy.h> -#include <netdev.h> -#include <errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-/* Functions */ -int board_early_init_f(void) -{
/* IO0 clock at 480MHz */mxs_set_ioclk(MXC_IOCLK0, 480000);/* IO1 clock at 480MHz */mxs_set_ioclk(MXC_IOCLK1, 480000);/* SSP0 clock at 96MHz */mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);return 0;-}
-int dram_init(void) -{
return mxs_dram_init();-}
-int board_init(void) -{
/* Adress of boot parameters */gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;return 0;-}
-#ifdef CONFIG_CMD_MMC -int board_mmc_init(struct bd_info *bis) -{
return mxsmmc_initialize(bis, 0, NULL, NULL);-} -#endif
-#ifdef CONFIG_CMD_NET
-#define MII_PHY_CTRL2 0x1f -int fecmxc_mii_postcall(int phy) -{
/* change PHY RMII clock to 50MHz */miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180);return 0;-}
-int board_eth_init(struct bd_info *bis) -{
int ret;struct eth_device *dev;ret = cpu_eth_init(bis);if (ret) {printf("FEC MXS: Unable to init FEC clocks\n");return ret;}ret = fecmxc_initialize(bis);if (ret) {printf("FEC MXS: Unable to init FEC\n");return ret;}dev = eth_get_dev_by_name("FEC");if (!dev) {printf("FEC MXS: Unable to get FEC device entry\n");return -EINVAL;}ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);if (ret) {printf("FEC MXS: Unable to register FEC MII postcall\n");return ret;}return ret;-} -#endif
-#ifdef CONFIG_SERIAL_TAG -#define MXS_OCOTP_MAX_TIMEOUT 1000000 -void get_board_serial(struct tag_serialnr *serialnr) -{
struct mxs_ocotp_regs *ocotp_regs =(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;serialnr->high = 0;serialnr->low = 0;writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,MXS_OCOTP_MAX_TIMEOUT)) {printf("MXS: Can't get serial number from OCOTP\n");return;}serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3);-} -#endif
-#ifdef CONFIG_REVISION_TAG -u32 get_board_rev(void) -{
if (env_get("revision#") != NULL)return simple_strtoul(env_get("revision#"), NULL, 10);return 0;-} -#endif diff --git a/board/bluegiga/apx4devkit/spl_boot.c b/board/bluegiga/apx4devkit/spl_boot.c deleted file mode 100644 index e5d5c4637b0c..000000000000 --- a/board/bluegiga/apx4devkit/spl_boot.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- Bluegiga APX4 Development Kit
- Copyright (C) 2012 Bluegiga Technologies Oy
- Authors:
- Veli-Pekka Peltola veli-pekka.peltola@bluegiga.com
- Lauri Hintsala lauri.hintsala@bluegiga.com
- Based on spl_boot.c:
- Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com
- on behalf of DENX Software Engineering GmbH
- */
-#include <common.h> -#include <config.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h>
-#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
-const iomux_cfg_t iomux_setup[] = {
/* DUART */MX28_PAD_PWM0__DUART_RX,MX28_PAD_PWM1__DUART_TX,/* LED */MX28_PAD_PWM3__GPIO_3_28,/* MMC0 */MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL),MX28_PAD_SSP0_SCK__SSP0_SCK |(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),/* GPMI NAND */MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,MX28_PAD_GPMI_RDN__GPMI_RDN |(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,/* FEC0 */MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,/* I2C */MX28_PAD_I2C0_SCL__I2C0_SCL,MX28_PAD_I2C0_SDA__I2C0_SDA,/* EMI */MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,-};
-void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{
mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));/* switch LED on */gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);-}
-void mxs_adjust_memory_params(uint32_t *dram_vals) -{
/** All address lines are routed from CPU to memory chip.* ADDR_PINS field is set to zero.*/dram_vals[0x74 >> 2] = 0x0f02000a;/* Used memory has 4 banks. EIGHT_BANK_MODE bit is disabled. */dram_vals[0x7c >> 2] = 0x00000101;-} diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig deleted file mode 100644 index 2ada946e5281..000000000000 --- a/configs/apx4devkit_defconfig +++ /dev/null @@ -1,50 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x120000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_APX4DEVKIT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x180000 -CONFIG_BOOTDELAY=1 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env),-(root)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h deleted file mode 100644 index bcd55bb8689e..000000000000 --- a/include/configs/apx4devkit.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- Copyright (C) 2012 Bluegiga Technologies Oy
- Authors:
- Veli-Pekka Peltola veli-pekka.peltola@bluegiga.com
- Lauri Hintsala lauri.hintsala@bluegiga.com
- Based on m28evk.h:
- Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com
- on behalf of DENX Software Engineering GmbH
- */
-#ifndef __CONFIGS_APX4DEVKIT_H__ -#define __CONFIGS_APX4DEVKIT_H__
-/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT
-/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-/* Environment is in NAND */ -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_RANGE (384 * 1024) -#endif
-/* UBI and NAND partitioning */
-/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 -#define IMX_FEC_BASE MXS_ENET0_BASE -#endif
-/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif
-/* Boot Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTCOMMAND "run bootcmd_nand" -#define CONFIG_LOADADDR 0x41000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SERIAL_TAG -#define CONFIG_REVISION_TAG
-/* Extra Environments */ -#define CONFIG_EXTRA_ENV_SETTINGS \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \"verify=no\0" \"bootcmd=run bootcmd_nand\0" \"kernelargs=console=tty0 console=ttyAMA0,115200 consoleblank=0\0" \"bootargs_nand=" \"setenv bootargs ${kernelargs} ubi.mtd=3,2048 " \"root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \"bootcmd_nand=" \"run bootargs_nand && ubi part root 2048 && " \"ubifsmount ubi:rootfs && ubifsload 41000000 boot/uImage && " \"bootm 41000000\0" \"bootargs_mmc=" \"setenv bootargs ${kernelargs} " \"root=/dev/mmcblk0p2 rootwait ${mtdparts} rw\0" \"bootcmd_mmc=" \"run bootargs_mmc && mmc rescan && " \"ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \-""
-/* The rest of the configuration is shared */ -#include <configs/mxs.h>
-#endif /* __CONFIGS_APX4DEVKIT_H__ */
2.17.1
Acked-by: Lauri Hintsala <lauri.hintsala@silabs.commailto:lauri.hintsala@silabs.com>
On 9 Feb 2021, at 15.02, Tom Rini <trini@konsulko.commailto:trini@konsulko.com> wrote:
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Lauri Hintsala <lauri.hintsala@bluegiga.commailto:lauri.hintsala@bluegiga.com> Signed-off-by: Tom Rini <trini@konsulko.commailto:trini@konsulko.com> --- arch/arm/mach-imx/mxs/Kconfig | 4 - board/bluegiga/apx4devkit/Kconfig | 15 --- board/bluegiga/apx4devkit/MAINTAINERS | 6 - board/bluegiga/apx4devkit/Makefile | 10 -- board/bluegiga/apx4devkit/apx4devkit.c | 142 ----------------------- board/bluegiga/apx4devkit/spl_boot.c | 152 ------------------------- configs/apx4devkit_defconfig | 50 -------- include/configs/apx4devkit.h | 77 ------------- 8 files changed, 456 deletions(-) delete mode 100644 board/bluegiga/apx4devkit/Kconfig delete mode 100644 board/bluegiga/apx4devkit/MAINTAINERS delete mode 100644 board/bluegiga/apx4devkit/Makefile delete mode 100644 board/bluegiga/apx4devkit/apx4devkit.c delete mode 100644 board/bluegiga/apx4devkit/spl_boot.c delete mode 100644 configs/apx4devkit_defconfig delete mode 100644 include/configs/apx4devkit.h
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index 6a6e6ebecf0b..40d74c93b305 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -8,9 +8,6 @@ choice prompt "MX28 board select" optional
-config TARGET_APX4DEVKIT - bool "Support apx4devkit" - config TARGET_BG0900 bool "Support bg0900"
@@ -28,7 +25,6 @@ endchoice config SYS_SOC default "mxs"
-source "board/bluegiga/apx4devkit/Kconfig" source "board/liebherr/xea/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/schulercontrol/sc_sps_1/Kconfig" diff --git a/board/bluegiga/apx4devkit/Kconfig b/board/bluegiga/apx4devkit/Kconfig deleted file mode 100644 index f327fa15cf07..000000000000 --- a/board/bluegiga/apx4devkit/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_APX4DEVKIT - -config SYS_BOARD - default "apx4devkit" - -config SYS_VENDOR - default "bluegiga" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "apx4devkit" - -endif diff --git a/board/bluegiga/apx4devkit/MAINTAINERS b/board/bluegiga/apx4devkit/MAINTAINERS deleted file mode 100644 index 286e9e9f063e..000000000000 --- a/board/bluegiga/apx4devkit/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -APX4DEVKIT BOARD -M: Lauri Hintsala <lauri.hintsala@bluegiga.commailto:lauri.hintsala@bluegiga.com> -S: Maintained -F: board/bluegiga/apx4devkit/ -F: include/configs/apx4devkit.h -F: configs/apx4devkit_defconfig diff --git a/board/bluegiga/apx4devkit/Makefile b/board/bluegiga/apx4devkit/Makefile deleted file mode 100644 index 039d62dda2ad..000000000000 --- a/board/bluegiga/apx4devkit/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.demailto:wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := apx4devkit.o -else -obj-y := spl_boot.o -endif diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c deleted file mode 100644 index 739f71f5c4d1..000000000000 --- a/board/bluegiga/apx4devkit/apx4devkit.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Bluegiga APX4 Development Kit - * - * Copyright (C) 2012 Bluegiga Technologies Oy - * - * Authors: - * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.commailto:veli-pekka.peltola@bluegiga.com> - * Lauri Hintsala <lauri.hintsala@bluegiga.commailto:lauri.hintsala@bluegiga.com> - * - * Based on m28evk.c: - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.commailto:marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/setup.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <env.h> -#include <linux/mii.h> -#include <miiphy.h> -#include <netdev.h> -#include <errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* Functions */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - /* IO1 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK1, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(struct bd_info *bis) -{ - return mxsmmc_initialize(bis, 0, NULL, NULL); -} -#endif - - -#ifdef CONFIG_CMD_NET - -#define MII_PHY_CTRL2 0x1f -int fecmxc_mii_postcall(int phy) -{ - /* change PHY RMII clock to 50MHz */ - miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - int ret; - struct eth_device *dev; - - ret = cpu_eth_init(bis); - if (ret) { - printf("FEC MXS: Unable to init FEC clocks\n"); - return ret; - } - - ret = fecmxc_initialize(bis); - if (ret) { - printf("FEC MXS: Unable to init FEC\n"); - return ret; - } - - dev = eth_get_dev_by_name("FEC"); - if (!dev) { - printf("FEC MXS: Unable to get FEC device entry\n"); - return -EINVAL; - } - - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXS: Unable to register FEC MII postcall\n"); - return ret; - } - - return ret; -} -#endif - -#ifdef CONFIG_SERIAL_TAG -#define MXS_OCOTP_MAX_TIMEOUT 1000000 -void get_board_serial(struct tag_serialnr *serialnr) -{ - struct mxs_ocotp_regs *ocotp_regs = - (struct mxs_ocotp_regs *)MXS_OCOTP_BASE; - - serialnr->high = 0; - serialnr->low = 0; - - writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); - - if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, - MXS_OCOTP_MAX_TIMEOUT)) { - printf("MXS: Can't get serial number from OCOTP\n"); - return; - } - - serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3); -} -#endif - -#ifdef CONFIG_REVISION_TAG -u32 get_board_rev(void) -{ - if (env_get("revision#") != NULL) - return simple_strtoul(env_get("revision#"), NULL, 10); - return 0; -} -#endif diff --git a/board/bluegiga/apx4devkit/spl_boot.c b/board/bluegiga/apx4devkit/spl_boot.c deleted file mode 100644 index e5d5c4637b0c..000000000000 --- a/board/bluegiga/apx4devkit/spl_boot.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Bluegiga APX4 Development Kit - * - * Copyright (C) 2012 Bluegiga Technologies Oy - * - * Authors: - * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.commailto:veli-pekka.peltola@bluegiga.com> - * Lauri Hintsala <lauri.hintsala@bluegiga.commailto:lauri.hintsala@bluegiga.com> - * - * Based on spl_boot.c: - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.commailto:marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <config.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* DUART */ - MX28_PAD_PWM0__DUART_RX, - MX28_PAD_PWM1__DUART_TX, - - /* LED */ - MX28_PAD_PWM3__GPIO_3_28, - - /* MMC0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* GPMI NAND */ - MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDN__GPMI_RDN | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), - MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, - - /* FEC0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* EMI */ - MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, - MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, - - MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, -}; - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); - - /* switch LED on */ - gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); -} - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - /* - * All address lines are routed from CPU to memory chip. - * ADDR_PINS field is set to zero. - */ - dram_vals[0x74 >> 2] = 0x0f02000a; - - /* Used memory has 4 banks. EIGHT_BANK_MODE bit is disabled. */ - dram_vals[0x7c >> 2] = 0x00000101; -} diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig deleted file mode 100644 index 2ada946e5281..000000000000 --- a/configs/apx4devkit_defconfig +++ /dev/null @@ -1,50 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x120000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_APX4DEVKIT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x180000 -CONFIG_BOOTDELAY=1 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env),-(root)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h deleted file mode 100644 index bcd55bb8689e..000000000000 --- a/include/configs/apx4devkit.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Bluegiga Technologies Oy - * - * Authors: - * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.commailto:veli-pekka.peltola@bluegiga.com> - * Lauri Hintsala <lauri.hintsala@bluegiga.commailto:lauri.hintsala@bluegiga.com> - * - * Based on m28evk.h: - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.commailto:marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ -#ifndef __CONFIGS_APX4DEVKIT_H__ -#define __CONFIGS_APX4DEVKIT_H__ - -/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment is in NAND */ -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_RANGE (384 * 1024) -#endif - -/* UBI and NAND partitioning */ - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 -#define IMX_FEC_BASE MXS_ENET0_BASE -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* Boot Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTCOMMAND "run bootcmd_nand" -#define CONFIG_LOADADDR 0x41000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SERIAL_TAG -#define CONFIG_REVISION_TAG - -/* Extra Environments */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "verify=no\0" \ - "bootcmd=run bootcmd_nand\0" \ - "kernelargs=console=tty0 console=ttyAMA0,115200 consoleblank=0\0" \ - "bootargs_nand=" \ - "setenv bootargs ${kernelargs} ubi.mtd=3,2048 " \ - "root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \ - "bootcmd_nand=" \ - "run bootargs_nand && ubi part root 2048 && " \ - "ubifsmount ubi:rootfs && ubifsload 41000000 boot/uImage && " \ - "bootm 41000000\0" \ - "bootargs_mmc=" \ - "setenv bootargs ${kernelargs} " \ - "root=/dev/mmcblk0p2 rootwait ${mtdparts} rw\0" \ - "bootcmd_mmc=" \ - "run bootargs_mmc && mmc rescan && " \ - "ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \ -"" - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_APX4DEVKIT_H__ */ -- 2.17.1
On Tue, Feb 09, 2021 at 08:02:59AM -0500, Tom Rini wrote:
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Lauri Hintsala lauri.hintsala@bluegiga.com Signed-off-by: Tom Rini trini@konsulko.com Acked-by: Lauri Hintsala <lauri.hintsala@silabs.commailto:lauri.hintsala@silabs.com> Signed-off-by: Tom Rini <trini@konsulko.commailto:trini@konsulko.com>
Applied to u-boot/master, thanks!
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Marek Vasut marek.vasut@gmail.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-imx/mxs/Kconfig | 4 - board/schulercontrol/sc_sps_1/Kconfig | 15 --- board/schulercontrol/sc_sps_1/MAINTAINERS | 6 - board/schulercontrol/sc_sps_1/Makefile | 10 -- board/schulercontrol/sc_sps_1/sc_sps_1.c | 98 -------------- board/schulercontrol/sc_sps_1/spl_boot.c | 148 ---------------------- configs/sc_sps_1_defconfig | 43 ------- include/configs/sc_sps_1.h | 57 --------- 8 files changed, 381 deletions(-) delete mode 100644 board/schulercontrol/sc_sps_1/Kconfig delete mode 100644 board/schulercontrol/sc_sps_1/MAINTAINERS delete mode 100644 board/schulercontrol/sc_sps_1/Makefile delete mode 100644 board/schulercontrol/sc_sps_1/sc_sps_1.c delete mode 100644 board/schulercontrol/sc_sps_1/spl_boot.c delete mode 100644 configs/sc_sps_1_defconfig delete mode 100644 include/configs/sc_sps_1.h
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index 40d74c93b305..ce81eeb38d46 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -11,9 +11,6 @@ choice config TARGET_BG0900 bool "Support bg0900"
-config TARGET_SC_SPS_1 - bool "Support sc_sps_1" - config TARGET_TS4600 bool "Support TS4600"
@@ -27,7 +24,6 @@ config SYS_SOC
source "board/liebherr/xea/Kconfig" source "board/ppcag/bg0900/Kconfig" -source "board/schulercontrol/sc_sps_1/Kconfig" source "board/technologic/ts4600/Kconfig"
endif diff --git a/board/schulercontrol/sc_sps_1/Kconfig b/board/schulercontrol/sc_sps_1/Kconfig deleted file mode 100644 index 2461d0cc5046..000000000000 --- a/board/schulercontrol/sc_sps_1/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_SC_SPS_1 - -config SYS_BOARD - default "sc_sps_1" - -config SYS_VENDOR - default "schulercontrol" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "sc_sps_1" - -endif diff --git a/board/schulercontrol/sc_sps_1/MAINTAINERS b/board/schulercontrol/sc_sps_1/MAINTAINERS deleted file mode 100644 index 74849cdfaf20..000000000000 --- a/board/schulercontrol/sc_sps_1/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SC_SPS_1 BOARD -M: Marek Vasut marek.vasut@gmail.com -S: Maintained -F: board/schulercontrol/sc_sps_1/ -F: include/configs/sc_sps_1.h -F: configs/sc_sps_1_defconfig diff --git a/board/schulercontrol/sc_sps_1/Makefile b/board/schulercontrol/sc_sps_1/Makefile deleted file mode 100644 index 4fb32de6e8e8..000000000000 --- a/board/schulercontrol/sc_sps_1/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2012 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := sc_sps_1.o -else -obj-y := spl_boot.o -endif diff --git a/board/schulercontrol/sc_sps_1/sc_sps_1.c b/board/schulercontrol/sc_sps_1/sc_sps_1.c deleted file mode 100644 index 8011871fc8fb..000000000000 --- a/board/schulercontrol/sc_sps_1/sc_sps_1.c +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SchulerControl GmbH, SC_SPS_1 module - * - * Copyright (C) 2012 Marek Vasut marex@denx.de - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <linux/mii.h> -#include <miiphy.h> -#include <netdev.h> -#include <errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - /* IO1 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK1, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - /* SSP2 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK2, 96000, 0); - -#ifdef CONFIG_CMD_USB - mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT); - mxs_iomux_setup_pad(MX28_PAD_AUART2_TX__GPIO_3_9 | - MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL); - gpio_direction_output(MX28_PAD_AUART2_TX__GPIO_3_9, 1); -#endif - - return 0; -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(struct bd_info *bis) -{ - return mxsmmc_initialize(bis, 0, NULL, NULL); -} -#endif - -#ifdef CONFIG_CMD_NET -int board_eth_init(struct bd_info *bis) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - int ret; - - ret = cpu_eth_init(bis); - - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, - CLKCTRL_ENET_TIME_SEL_MASK, - CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN); - - ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); - if (ret) { - printf("FEC MXS: Unable to init FEC0\n"); - return ret; - } - - ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE); - if (ret) { - printf("FEC MXS: Unable to init FEC1\n"); - return ret; - } - - return ret; -} - -#endif diff --git a/board/schulercontrol/sc_sps_1/spl_boot.c b/board/schulercontrol/sc_sps_1/spl_boot.c deleted file mode 100644 index 68758eb99701..000000000000 --- a/board/schulercontrol/sc_sps_1/spl_boot.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SchulerControl GmbH, SC_SPS_1 module setup - * - * Copyright (C) 2012 Marek Vasut marex@denx.de - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* -- Strick 3 -- */ - - /* FEC Ethernet */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, - - MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* ENET INT */ - - MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, - - /* -- Strick 4 -- */ - - /* EMI */ - MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, - - MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - - MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, - - MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - - MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, - - /* -- Strick 5 -- */ - - /* MMC0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), - - /* SPI2 (for flash) */ - MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_SS0__SSP2_D3 | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), - - /* -- Strick 6 -- */ - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* AUART0 */ - MX28_PAD_AUART0_TX__AUART0_TX, - MX28_PAD_AUART0_RX__AUART0_RX, - - /* MEGA interface */ - - /* Debug UART */ - MX28_PAD_PWM0__DUART_RX, - MX28_PAD_PWM1__DUART_TX, - - /* LED */ - MX28_PAD_GPMI_D00__GPIO_0_0 | MUX_CONFIG_LED, - MX28_PAD_GPMI_D03__GPIO_0_3 | MUX_CONFIG_LED, - MX28_PAD_GPMI_D06__GPIO_0_6 | MUX_CONFIG_LED, -}; - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - dram_vals[0x74 >> 2] = 0x0f02010a; -} diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig deleted file mode 100644 index 6b50170951ea..000000000000 --- a/configs/sc_sps_1_defconfig +++ /dev/null @@ -1,43 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_SC_SPS_1=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyAMA0,115200" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_PHYLIB=y -CONFIG_PHY_SMSC=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h deleted file mode 100644 index 6011fb7d522d..000000000000 --- a/include/configs/sc_sps_1.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * SchulerControl GmbH, SC_SPS_1 module config - * - * Copyright (C) 2012 Marek Vasut marex@denx.de - * on behalf of DENX Software Engineering GmbH - */ -#ifndef __CONFIGS_SC_SPS_1_H__ -#define __CONFIGS_SC_SPS_1_H__ - -/* System configuration */ -#define CONFIG_MACH_TYPE MACH_TYPE_SC_SPS_1 - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* Environment is in MMC */ - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTCOMMAND "bootm" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_sd_firmware_filename=u-boot.sd\0" \ - "update_sd_firmware=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_sd_firmware_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ - "fi ; " \ - "fi\0" - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_SC_SPS_1_H__ */
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Sebastien Bourdelin sebastien.bourdelin@savoirfairelinux.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-imx/mxs/Kconfig | 4 - board/technologic/ts4600/Kconfig | 15 --- board/technologic/ts4600/MAINTAINERS | 6 -- board/technologic/ts4600/Makefile | 9 -- board/technologic/ts4600/iomux.c | 148 --------------------------- board/technologic/ts4600/ts4600.c | 90 ---------------- configs/ts4600_defconfig | 30 ------ include/configs/ts4600.h | 58 ----------- 8 files changed, 360 deletions(-) delete mode 100644 board/technologic/ts4600/Kconfig delete mode 100644 board/technologic/ts4600/MAINTAINERS delete mode 100644 board/technologic/ts4600/Makefile delete mode 100644 board/technologic/ts4600/iomux.c delete mode 100644 board/technologic/ts4600/ts4600.c delete mode 100644 configs/ts4600_defconfig delete mode 100644 include/configs/ts4600.h
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index ce81eeb38d46..34aae07d4222 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -11,9 +11,6 @@ choice config TARGET_BG0900 bool "Support bg0900"
-config TARGET_TS4600 - bool "Support TS4600" - config TARGET_XEA bool "Support XEA"
@@ -24,6 +21,5 @@ config SYS_SOC
source "board/liebherr/xea/Kconfig" source "board/ppcag/bg0900/Kconfig" -source "board/technologic/ts4600/Kconfig"
endif diff --git a/board/technologic/ts4600/Kconfig b/board/technologic/ts4600/Kconfig deleted file mode 100644 index d0dc2e1b7340..000000000000 --- a/board/technologic/ts4600/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_TS4600 - -config SYS_BOARD - default "ts4600" - -config SYS_VENDOR - default "technologic" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "ts4600" - -endif diff --git a/board/technologic/ts4600/MAINTAINERS b/board/technologic/ts4600/MAINTAINERS deleted file mode 100644 index 6f683b5995ef..000000000000 --- a/board/technologic/ts4600/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TS4600 BOARD -M: Sebastien Bourdelin sebastien.bourdelin@savoirfairelinux.com -S: Maintained -F: board/technologic/ts4600/ -F: include/configs/ts4600.h -F: configs/ts4600_defconfig diff --git a/board/technologic/ts4600/Makefile b/board/technologic/ts4600/Makefile deleted file mode 100644 index ddf4a8ee1eeb..000000000000 --- a/board/technologic/ts4600/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2016 Savoir-faire Linux - -ifndef CONFIG_SPL_BUILD -obj-y := ts4600.o -else -obj-y := iomux.o -endif diff --git a/board/technologic/ts4600/iomux.c b/board/technologic/ts4600/iomux.c deleted file mode 100644 index 9bd3eacb0bdc..000000000000 --- a/board/technologic/ts4600/iomux.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Savoir-faire Linux Inc. - * - * Author: Sebastien Bourdelin sebastien.bourdelin@savoirfairelinux.com - * - * Based on work from TS7680 code by: - * Kris Bahnsen kris@embeddedarm.com - * Mark Featherston mark@embeddedarm.com - * https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680 - * - * Derived from MX28EVK code by - * Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* DUART */ - MX28_PAD_PWM0__DUART_RX, - MX28_PAD_PWM1__DUART_TX, - - /* MMC0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* MMC0 slot power enable */ - MX28_PAD_PWM3__GPIO_3_28 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - - /* EMI */ - MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, - MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - -}; - -#define HW_DRAM_CTL29 (0x74 >> 2) -#define CS_MAP 0xf -#define COLUMN_SIZE 0x2 -#define ADDR_PINS 0x1 -#define APREBIT 0xa - -#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ - ADDR_PINS << 8 | APREBIT) - -#define HW_DRAM_CTL39 (0x9c >> 2) -#define TFAW 0xb -#define TDLL 0xc8 - -#define HW_DRAM_CTL39_CONFIG (TFAW << 24 | TDLL) - -#define HW_DRAM_CTL41 (0xa4 >> 2) -#define TPDEX 0x2 -#define TRCD_INT 0x4 -#define TRC 0xd - -#define HW_DRAM_CTL41_CONFIG (TPDEX << 24 | TRCD_INT << 8 | TRC) - -#define HW_DRAM_CTL42 (0xa8 >> 2) -#define TRAS_MAX 0x36a6 -#define TRAS_MIN 0xa - -#define HW_DRAM_CTL42_CONFIG (TRAS_MAX << 8 | TRAS_MIN) - -#define HW_DRAM_CTL43 (0xac >> 2) -#define TRP 0x4 -#define TRFC 0x27 -#define TREF 0x2a0 - -#define HW_DRAM_CTL43_CONFIG (TRP << 24 | TRFC << 16 | TREF) - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; - dram_vals[HW_DRAM_CTL39] = HW_DRAM_CTL39_CONFIG; - dram_vals[HW_DRAM_CTL41] = HW_DRAM_CTL41_CONFIG; - dram_vals[HW_DRAM_CTL42] = HW_DRAM_CTL42_CONFIG; - dram_vals[HW_DRAM_CTL43] = HW_DRAM_CTL43_CONFIG; -} - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/board/technologic/ts4600/ts4600.c b/board/technologic/ts4600/ts4600.c deleted file mode 100644 index 0ef306d58a27..000000000000 --- a/board/technologic/ts4600/ts4600.c +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Savoir-faire Linux Inc. - * - * Author: Sebastien Bourdelin sebastien.bourdelin@savoirfairelinux.com - * - * Based on work from TS7680 code by: - * Kris Bahnsen kris@embeddedarm.com - * Mark Featherston mark@embeddedarm.com - * https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680 - * - * Derived from MX28EVK code by - * Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <linux/delay.h> -#include <linux/mii.h> -#include <miiphy.h> -#include <netdev.h> -#include <errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - /* IO1 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK1, 480000); - - /* SSP0 clocks at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -#ifdef CONFIG_CMD_MMC -static int ts4600_mmc_cd(int id) -{ - return 1; -} - -int board_mmc_init(struct bd_info *bis) -{ - int ret; - - mxs_iomux_setup_pad(MX28_PAD_PWM3__GPIO_3_28); - - /* Power-on SD */ - gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 1); - udelay(1000); - gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); - - /* SD card */ - ret = mxsmmc_initialize(bis, 0, NULL, ts4600_mmc_cd); - if(ret != 0) { - printf("SD controller initialized with %d\n", ret); - } - - return ret; -} -#endif - -int checkboard(void) -{ - puts("Board: TS4600\n"); - - return 0; -} diff --git a/configs/ts4600_defconfig b/configs/ts4600_defconfig deleted file mode 100644 index 806cbc668426..000000000000 --- a/configs/ts4600_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_TS4600=y -CONFIG_SPL=y -CONFIG_FIT=y -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MMC=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_CONS_INDEX=0 -CONFIG_OF_LIBFDT=y diff --git a/include/configs/ts4600.h b/include/configs/ts4600.h deleted file mode 100644 index ae9352f5b9ad..000000000000 --- a/include/configs/ts4600.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Savoir-faire Linux Inc. - * - * Author: Sebastien Bourdelin sebastien.bourdelin@savoirfairelinux.com - * - * Derived from MX28EVK code by - * Fabio Estevam fabio.estevam@freescale.com - * Freescale Semiconductor, Inc. - * - * Configuration settings for the TS4600 Board - */ -#ifndef __CONFIGS_TS4600_H__ -#define __CONFIGS_TS4600_H__ - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* Environment is in MMC */ - -/* Boot Linux */ -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_addr=0x41000000\0" \ - "loadkernel=load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} imx28-ts4600.dtb\0" \ - "loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot.ub\0" \ - "bootscript=echo Running bootscript from mmc...; " \ - "setenv mmcdev 0; " \ - "setenv mmcpart 2; " \ - "run loadbootscript && source ${loadaddr}; \0" \ - "sdboot=echo Booting from SD card ...; " \ - "setenv mmcdev 0; " \ - "setenv mmcpart 2; " \ - "setenv root /dev/mmcblk0p3; " \ - "run loadkernel && run loadfdt; \0" \ - "startbootsequence=run bootscript || run sdboot \0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan; " \ - "run startbootsequence; " \ - "setenv cmdline_append console=ttyAMA0,115200; " \ - "setenv bootargs root=${root} rootwait rw ${cmdline_append}; " \ - "bootz ${loadaddr} - ${fdt_addr}; " - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_TS4600_H__ */
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Stefano Babic sbabic@denx.de Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/Kconfig | 6 - board/freescale/mx35pdk/Kconfig | 15 -- board/freescale/mx35pdk/MAINTAINERS | 6 - board/freescale/mx35pdk/Makefile | 8 - board/freescale/mx35pdk/README | 114 --------- board/freescale/mx35pdk/lowlevel_init.S | 239 ------------------- board/freescale/mx35pdk/mx35pdk.c | 293 ------------------------ board/freescale/mx35pdk/mx35pdk.h | 41 ---- configs/mx35pdk_defconfig | 54 ----- drivers/serial/Kconfig | 2 +- include/configs/mx35pdk.h | 206 ----------------- 11 files changed, 1 insertion(+), 983 deletions(-) delete mode 100644 board/freescale/mx35pdk/Kconfig delete mode 100644 board/freescale/mx35pdk/MAINTAINERS delete mode 100644 board/freescale/mx35pdk/Makefile delete mode 100644 board/freescale/mx35pdk/README delete mode 100644 board/freescale/mx35pdk/lowlevel_init.S delete mode 100644 board/freescale/mx35pdk/mx35pdk.c delete mode 100644 board/freescale/mx35pdk/mx35pdk.h delete mode 100644 configs/mx35pdk_defconfig delete mode 100644 include/configs/mx35pdk.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f2a87c3caed8..9969da161e9c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -621,11 +621,6 @@ config TARGET_FLEA3 bool "Support flea3" select CPU_ARM1136
-config TARGET_MX35PDK - bool "Support mx35pdk" - select BOARD_LATE_INIT - select CPU_ARM1136 - config ARCH_BCM283X bool "Broadcom BCM283X family" select DM @@ -2009,7 +2004,6 @@ source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" source "board/freescale/lx2160a/Kconfig" -source "board/freescale/mx35pdk/Kconfig" source "board/freescale/s32v234evb/Kconfig" source "board/grinn/chiliboard/Kconfig" source "board/hisilicon/hikey/Kconfig" diff --git a/board/freescale/mx35pdk/Kconfig b/board/freescale/mx35pdk/Kconfig deleted file mode 100644 index 021d19e5511c..000000000000 --- a/board/freescale/mx35pdk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX35PDK - -config SYS_BOARD - default "mx35pdk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx35" - -config SYS_CONFIG_NAME - default "mx35pdk" - -endif diff --git a/board/freescale/mx35pdk/MAINTAINERS b/board/freescale/mx35pdk/MAINTAINERS deleted file mode 100644 index 540e9436912b..000000000000 --- a/board/freescale/mx35pdk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX35PDK BOARD -M: Stefano Babic sbabic@denx.de -S: Maintained -F: board/freescale/mx35pdk/ -F: include/configs/mx35pdk.h -F: configs/mx35pdk_defconfig diff --git a/board/freescale/mx35pdk/Makefile b/board/freescale/mx35pdk/Makefile deleted file mode 100644 index 6a60fad0cc8d..000000000000 --- a/board/freescale/mx35pdk/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de -# -# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - -obj-y := mx35pdk.o -obj-y += lowlevel_init.o diff --git a/board/freescale/mx35pdk/README b/board/freescale/mx35pdk/README deleted file mode 100644 index 6f6841f0993b..000000000000 --- a/board/freescale/mx35pdk/README +++ /dev/null @@ -1,114 +0,0 @@ -Overview --------------- - -mx35pdk (known als as mx35_3stack) is a development board by Freescale. -It consists of three pluggable board: - - CPU module, with CPU, RAM, flash - - Personality board, with most interfaces (USB, Network,..) - - Debug board with JTAG header. - -The board is usually delivered with redboot. This howto explains how to boot -a linux kernel and how to replace the original bootloader with U-Boot. - -The board is delivered with Redboot on the NAND flash. It is possible to -switch the boot device with the switches SW1-SW2 on the Personality board, -and with SW5-SW10 on the Debug board. - -Delivered Redboot script to start the kernel ---------------------------------------------------- - -In redboot the following script is stored: - -fis load kernel -exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76" - -Kernel is taken from flash. The image is in zImage format. - -Booting from NET, rootfs on NFS: ------------------------------------ - -To change the script in redboot: - -load -r -b 0x100000 <path_to_zImage> -exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp" - -If the ip address is not set, you can set it with : - -ip_address -l <board_ip/netmask> -h <server_ip> - -Linux partitions: ---------------------------- - -As default, the board is shipped with these partition tables for NAND -and for NOR: - -Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit": -0x00000000-0x00100000 : "nand.bootloader" -0x00100000-0x00600000 : "nand.kernel" -0x00600000-0x06600000 : "nand.rootfs" -0x06600000-0x06e00000 : "nand.configure" -0x06e00000-0x80000000 : "nand.userfs" - -Creating 6 MTD partitions on "mxc_nor_flash.0": -0x00000000-0x00080000 : "Bootloader" -0x00080000-0x00480000 : "nor.Kernel" -0x00480000-0x02280000 : "nor.userfs" -0x02280000-0x03e80000 : "nor.rootfs" -0x01fe0000-0x01fe3000 : "FIS directory" -0x01fff000-0x04000000 : "Redboot config" - -NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS. -For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2. - -However, the setup in redboot is not correct and does not use the whole flash. - -Better solution is to use the kernel parameter mtdparts. -Here the resulting script to be defined in RedBoot with fconfig: - -load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37 -exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)" - -Flashing U-Boot --------------------------------- - -U-Boot should be stored on the NOR flash. - -The boot storage can be select using the switches on the personality board -(SW1-SW2) and on the DEBUG board (SW4-SW10). - -If something goes wrong flashing the bootloader, it is always possible to -recover the board booting from the other device. - -Saving U-Boot in the NOR flash ---------------------------------- - -Check the partition for boot in the NOR flash. Setting the mtdparts as reported, -the boot partition should be /dev/mtd0. - -Creating 6 MTD partitions on "mxc_nor_flash.0": -0x00000000-0x00080000 : "Bootloader" -0x00080000-0x00480000 : "nor.Kernel" -0x00480000-0x02280000 : "nor.userfs" -0x02280000-0x03e80000 : "nor.rootfs" -0x01fe0000-0x01fe3000 : "FIS directory" -0x01fff000-0x04000000 : "Redboot config" - -To erase the whole partition: -$ flash_eraseall /dev/mtd0 - -Writing U-Boot: -dd if=u-boot.bin of=/dev/mtd0 - -To boot from NOR, you have to select the switches as follows: - -Personality board - SW2 all off - SW1 all off - -Debug Board: - SW5 0 - SW6 0 - SW7 0 - SW8 1 - SW9 1 - SW10 0 diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S deleted file mode 100644 index 5dae5597fb69..000000000000 --- a/board/freescale/mx35pdk/lowlevel_init.S +++ /dev/null @@ -1,239 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - */ - -#include <config.h> -#include <asm/arch/imx-regs.h> -#include <generated/asm-offsets.h> -#include "mx35pdk.h" -#include <asm/arch/lowlevel_macro.S> - -/* - * return soc version - * 0x10: TO1 - * 0x20: TO2 - * 0x30: TO3 - */ -.macro check_soc_version ret, tmp - ldr \tmp, =IIM_BASE_ADDR - ldr \ret, [\tmp, #IIM_SREV] - cmp \ret, #0x00 - moveq \tmp, #ROMPATCH_REV - ldreq \ret, [\tmp] - moveq \ret, \ret, lsl #4 - addne \ret, \ret, #0x10 -.endm - -/* CPLD on CS5 setup */ -.macro init_debug_board - ldr r0, =DBG_BASE_ADDR - ldr r1, =DBG_CSCR_U_CONFIG - str r1, [r0, #0x00] - ldr r1, =DBG_CSCR_L_CONFIG - str r1, [r0, #0x04] - ldr r1, =DBG_CSCR_A_CONFIG - str r1, [r0, #0x08] -.endm - -/* clock setup */ -.macro init_clock - ldr r0, =CCM_BASE_ADDR - - /* default CLKO to 1/32 of the ARM core*/ - ldr r1, [r0, #CLKCTL_COSR] - bic r1, r1, #0x00000FF00 - bic r1, r1, #0x0000000FF - mov r2, #0x00006C00 - add r2, r2, #0x67 - orr r1, r1, r2 - str r1, [r0, #CLKCTL_COSR] - - ldr r2, =CCM_CCMR_CONFIG - str r2, [r0, #CLKCTL_CCMR] - - check_soc_version r1, r2 - cmp r1, #CHIP_REV_2_0 - ldrhs r3, =CCM_MPLL_532_HZ - bhs 1f - ldr r2, [r0, #CLKCTL_PDR0] - tst r2, #CLKMODE_CONSUMER - ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/ - ldreq r3, =CCM_MPLL_399_HZ /* auto path*/ -1: - str r3, [r0, #CLKCTL_MPCTL] - - ldr r1, =CCM_PPLL_300_HZ - str r1, [r0, #CLKCTL_PPCTL] - - ldr r1, =CCM_PDR0_CONFIG - bic r1, r1, #0x800000 - str r1, [r0, #CLKCTL_PDR0] - - ldr r1, [r0, #CLKCTL_CGR0] - orr r1, r1, #0x0C300000 - str r1, [r0, #CLKCTL_CGR0] - - ldr r1, [r0, #CLKCTL_CGR1] - orr r1, r1, #0x00000C00 - orr r1, r1, #0x00000003 - str r1, [r0, #CLKCTL_CGR1] - - ldr r1, [r0, #CLKCTL_CGR2] - orr r1, r1, #0x00C00000 - str r1, [r0, #CLKCTL_CGR2] -.endm - -.macro setup_sdram - ldr r0, =ESDCTL_BASE_ADDR - mov r3, #0x2000 - str r3, [r0, #0x0] - str r3, [r0, #0x8] - - /*ip(r12) has used to save lr register in upper calling*/ - mov fp, lr - - mov r5, #0x00 - mov r2, #0x00 - mov r1, #CSD0_BASE_ADDR - bl setup_sdram_bank - - mov r5, #0x00 - mov r2, #0x00 - mov r1, #CSD1_BASE_ADDR - bl setup_sdram_bank - - mov lr, fp - -1: - ldr r3, =ESDCTL_DELAY_LINE5 - str r3, [r0, #0x30] -.endm - -.globl lowlevel_init -lowlevel_init: - mov r10, lr - - core_init - - init_aips - - init_max - - init_m3if - - init_clock - init_debug_board - - cmp pc, #PHYS_SDRAM_1 - blo init_sdram_start - cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) - blo skip_sdram_setup - -init_sdram_start: - /*init_sdram*/ - setup_sdram - -skip_sdram_setup: - mov lr, r10 - mov pc, lr - - -/* - * r0: ESDCTL control base, r1: sdram slot base - * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base - */ -setup_sdram_bank: - mov r3, #0xE - tst r2, #0x1 - orreq r3, r3, #0x300 /*DDR2*/ - str r3, [r0, #0x10] - bic r3, r3, #0x00A - str r3, [r0, #0x10] - beq 2f - - mov r3, #0x20000 -1: subs r3, r3, #1 - bne 1b - -2: tst r2, #0x1 - ldreq r3, =ESDCTL_DDR2_CONFIG - ldrne r3, =ESDCTL_MDDR_CONFIG - cmp r1, #CSD1_BASE_ADDR - strlo r3, [r0, #0x4] - strhs r3, [r0, #0xC] - - ldr r3, =ESDCTL_0x92220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_PRECHARGE - strb r3, [r1, r4] - - tst r2, #0x1 - bne skip_set_mode - - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0xB2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_DDR2_EMR2 - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_EMR3 - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_EN_DLL - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_RESET_DLL - strb r3, [r1, r4] - - ldr r3, =ESDCTL_0x92220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_PRECHARGE - strb r3, [r1, r4] - -skip_set_mode: - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0xA2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - strb r3, [r1] - strb r3, [r1] - - ldr r3, =ESDCTL_0xB2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - tst r2, #0x1 - ldreq r4, =ESDCTL_DDR2_MR - ldrne r4, =ESDCTL_MDDR_MR - mov r3, #0xDA - strb r3, [r1, r4] - ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT - streqb r3, [r1, r4] - ldreq r4, =ESDCTL_DDR2_EN_DLL - ldrne r4, =ESDCTL_MDDR_EMR - strb r3, [r1, r4] - - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0x82228080 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - - tst r2, #0x1 - moveq r4, #0x20000 - movne r4, #0x200 -1: subs r4, r4, #1 - bne 1b - - str r3, [r1, #0x100] - ldr r4, [r1, #0x100] - cmp r3, r4 - movne r3, #1 - moveq r3, #0 - - mov pc, lr diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c deleted file mode 100644 index fc024c47dbdd..000000000000 --- a/board/freescale/mx35pdk/mx35pdk.c +++ /dev/null @@ -1,293 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux-mx35.h> -#include <i2c.h> -#include <power/pmic.h> -#include <fsl_pmic.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <mc9sdz60.h> -#include <mc13892.h> -#include <linux/types.h> -#include <asm/gpio.h> -#include <asm/arch/sys_proto.h> -#include <netdev.h> -#include <asm/mach-types.h> - -#ifndef CONFIG_BOARD_LATE_INIT -#error "CONFIG_BOARD_LATE_INIT must be set for this board" -#endif - -#ifndef CONFIG_BOARD_EARLY_INIT_F -#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - u32 size1, size2; - - size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - gd->ram_size = size1 + size2; - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - - return 0; -} - -#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE) - -static void setup_iomux_i2c(void) -{ - static const iomux_v3_cfg_t i2c1_pads[] = { - NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL), - }; - - /* setup pins for I2C1 */ - imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); -} - - -static void setup_iomux_spi(void) -{ - static const iomux_v3_cfg_t spi_pads[] = { - MX35_PAD_CSPI1_MOSI__CSPI1_MOSI, - MX35_PAD_CSPI1_MISO__CSPI1_MISO, - MX35_PAD_CSPI1_SS0__CSPI1_SS0, - MX35_PAD_CSPI1_SS1__CSPI1_SS1, - MX35_PAD_CSPI1_SCLK__CSPI1_SCLK, - }; - - imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); -} - -#define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \ - PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) -#define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) - -static void setup_iomux_usbotg(void) -{ - static const iomux_v3_cfg_t usbotg_pads[] = { - NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, - USBOTG_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, - USBOTG_IN_PAD_CTRL), - }; - - /* Set up pins for USBOTG. */ - imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads)); -} - -#define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) - -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_22K_UP), - NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL), - }; - - /* setup pins for FEC */ - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -int board_early_init_f(void) -{ - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - - /* enable clocks */ - writel(readl(&ccm->cgr0) | - MXC_CCM_CGR0_EMI_MASK | - MXC_CCM_CGR0_EDIO_MASK | - MXC_CCM_CGR0_EPIT1_MASK, - &ccm->cgr0); - - writel(readl(&ccm->cgr1) | - MXC_CCM_CGR1_FEC_MASK | - MXC_CCM_CGR1_GPIO1_MASK | - MXC_CCM_CGR1_GPIO2_MASK | - MXC_CCM_CGR1_GPIO3_MASK | - MXC_CCM_CGR1_I2C1_MASK | - MXC_CCM_CGR1_I2C2_MASK | - MXC_CCM_CGR1_IPU_MASK, - &ccm->cgr1); - - /* Setup NAND */ - __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); - - setup_iomux_i2c(); - setup_iomux_usbotg(); - setup_iomux_fec(); - setup_iomux_spi(); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -static inline int pmic_detect(void) -{ - unsigned int id; - struct pmic *p = pmic_get("FSL_PMIC"); - if (!p) - return -ENODEV; - - pmic_reg_read(p, REG_IDENTIFICATION, &id); - - id = (id >> 6) & 0x7; - if (id == 0x7) - return 1; - return 0; -} - -u32 get_board_rev(void) -{ - int rev; - - rev = pmic_detect(); - - return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; -} - -int board_late_init(void) -{ - u8 val; - u32 pmic_val; - struct pmic *p; - int ret; - - ret = pmic_init(I2C_0); - if (ret) - return ret; - - if (pmic_detect()) { - p = pmic_get("FSL_PMIC"); - imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B); - - pmic_reg_read(p, REG_SETTING_0, &pmic_val); - pmic_reg_write(p, REG_SETTING_0, - pmic_val | VO_1_30V | VO_1_50V); - pmic_reg_read(p, REG_MODE_0, &pmic_val); - pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN); - - imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5); - - gpio_direction_output(IMX_GPIO_NR(1, 5), 1); - } - - val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; - mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val); - mdelay(200); - - val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F; - mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); - mdelay(200); - - val |= 0x80; - mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); - - /* Print board revision */ - printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_SMC911X) - int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); - if (rc) - return rc; -#endif - return cpu_eth_init(bis); -} - -#if defined(CONFIG_FSL_ESDHC_IMX) - -struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; - -int board_mmc_init(struct bd_info *bis) -{ - static const iomux_v3_cfg_t sdhc1_pads[] = { - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - }; - - /* configure pins for SDHC1 only */ - imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); - - esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); - return fsl_esdhc_initialize(bis, &esdhc_cfg); -} - -int board_mmc_getcd(struct mmc *mmc) -{ - return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4); -} -#endif diff --git a/board/freescale/mx35pdk/mx35pdk.h b/board/freescale/mx35pdk/mx35pdk.h deleted file mode 100644 index 0af4b88bfbee..000000000000 --- a/board/freescale/mx35pdk/mx35pdk.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer s.hauer@pengutronix.de - * - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - */ - -#ifndef __BOARD_MX35_3STACK_H -#define __BOARD_MX35_3STACK_H - -#define DBG_BASE_ADDR WEIM_CTRL_CS5 -#define DBG_CSCR_U_CONFIG 0x0000D843 -#define DBG_CSCR_L_CONFIG 0x22252521 -#define DBG_CSCR_A_CONFIG 0x22220A00 - -#define CCM_CCMR_CONFIG 0x003F4208 -#define CCM_PDR0_CONFIG 0x00801000 - -/* MEMORY SETTING */ -#define ESDCTL_0x92220000 0x92220000 -#define ESDCTL_0xA2220000 0xA2220000 -#define ESDCTL_0xB2220000 0xB2220000 -#define ESDCTL_0x82228080 0x82228080 - -#define ESDCTL_PRECHARGE 0x00000400 - -#define ESDCTL_MDDR_CONFIG 0x007FFC3F -#define ESDCTL_MDDR_MR 0x00000033 -#define ESDCTL_MDDR_EMR 0x02000000 - -#define ESDCTL_DDR2_CONFIG 0x007FFC3F -#define ESDCTL_DDR2_EMR2 0x04000000 -#define ESDCTL_DDR2_EMR3 0x06000000 -#define ESDCTL_DDR2_EN_DLL 0x02000400 -#define ESDCTL_DDR2_RESET_DLL 0x00000333 -#define ESDCTL_DDR2_MR 0x00000233 -#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 - -#define ESDCTL_DELAY_LINE5 0x00F49F00 -#endif /* __BOARD_MX35_3STACK_H */ diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig deleted file mode 100644 index ab77fb5c06c2..000000000000 --- a/configs/mx35pdk_defconfig +++ /dev/null @@ -1,54 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_MX35PDK=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)" -CONFIG_EFI_PARTITION=y -# CONFIG_PARTITION_UUIDS is not set -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xA0080000 -CONFIG_ENV_ADDR_REDUND=0xA00A0000 -CONFIG_MXC_GPIO=y -CONFIG_FSL_ESDHC_IMX=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXC=y -CONFIG_MII=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0xB6000000 -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 9db4cae1df18..79ad0a1b3435 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -635,7 +635,7 @@ config MCFUART
config MXC_UART bool "IMX serial port support" - depends on ARCH_MX25 || ARCH_MX31 || TARGET_APF27 || TARGET_FLEA3 || TARGET_MX35PDK \ + depends on ARCH_MX25 || ARCH_MX31 || TARGET_APF27 || TARGET_FLEA3 \ || MX5 || MX6 || MX7 || IMX8M help If you have a machine based on a Motorola IMX CPU you diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h deleted file mode 100644 index d2dcc8179b14..000000000000 --- a/include/configs/mx35pdk.h +++ /dev/null @@ -1,206 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010, Stefano Babic sbabic@denx.de - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de - * - * Configuration for the MX35pdk Freescale board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - - /* High Level Configuration Options */ -#define CONFIG_MX35 - -#define CONFIG_SYS_FSL_CLK - -/* Set TEXT at the beginning of the NOR flash */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - -/* - * Hardware drivers - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -/* - * PMIC Configs - */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_FSL -#define CONFIG_POWER_FSL_MC13892 -#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08 -#define CONFIG_RTC_MC13XXX - -/* - * MFD MC9SDZ60 - */ -#define CONFIG_FSL_MC9SDZ60 -#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69 - -/* - * UART (console) - */ -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* - * Command definition - */ - -#define CONFIG_NET_RETRY_COUNT 100 - - -#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ - -/* - * Ethernet on the debug board (SMC911) - */ -#define CONFIG_HAS_ETH1 -#define CONFIG_ETHPRIME - -/* - * Ethernet on SOC (FEC) - */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1F - -#define CONFIG_ARP_TIMEOUT 200UL - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/* - * MTD Command for mtdparts - */ - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -/* Address and size of Redundant Environment Sector */ - -/* - * CFI FLASH driver setup - */ - -/* A non-standard buffered write algorithm */ -#define CONFIG_FLASH_SPANSION_S29WS_N - -/* - * NAND FLASH driver setup - */ -#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE - -/* EHCI driver */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_MXC -#define CONFIG_MXC_USB_PORT 0 -#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \ - MXC_EHCI_POWER_PINS_ENABLED | \ - MXC_EHCI_OC_PIN_ACTIVE_LOW) -#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI) - -/* mmc driver */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -/* - * Default environment and default scripts - * to update uboot and load kernel - */ - -#define CONFIG_HOSTNAME "mx35pdk" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth1\0" \ - "ethprime=smc911x\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip_sta=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test -n ${ipdyn};then run addip_dyn;" \ - "else run addip_sta;fi\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ - "loadaddr=80800000\0" \ - "kernel_addr_r=80800000\0" \ - "hostname=" CONFIG_HOSTNAME "\0" \ - "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ - "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ - "update=protect off ${uboot_addr} +80000;" \ - "erase ${uboot_addr} +80000;" \ - "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ - "upd=if run load;then echo Updating u-boot;if run update;" \ - "then echo U-Boot updated;" \ - "else echo Error updating u-boot !;" \ - "echo Board without bootloader !!;" \ - "fi;" \ - "else echo U-Boot not downloaded..exiting;fi\0" \ - "bootcmd=run net_nfs\0" - -#endif /* __CONFIG_H */
On 09.02.21 14:03, Tom Rini wrote:
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
This is a very old board, I am fine to remove it.
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano
Cc: Stefano Babic sbabic@denx.de Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/Kconfig | 6 - board/freescale/mx35pdk/Kconfig | 15 -- board/freescale/mx35pdk/MAINTAINERS | 6 - board/freescale/mx35pdk/Makefile | 8 - board/freescale/mx35pdk/README | 114 --------- board/freescale/mx35pdk/lowlevel_init.S | 239 ------------------- board/freescale/mx35pdk/mx35pdk.c | 293 ------------------------ board/freescale/mx35pdk/mx35pdk.h | 41 ---- configs/mx35pdk_defconfig | 54 ----- drivers/serial/Kconfig | 2 +- include/configs/mx35pdk.h | 206 ----------------- 11 files changed, 1 insertion(+), 983 deletions(-) delete mode 100644 board/freescale/mx35pdk/Kconfig delete mode 100644 board/freescale/mx35pdk/MAINTAINERS delete mode 100644 board/freescale/mx35pdk/Makefile delete mode 100644 board/freescale/mx35pdk/README delete mode 100644 board/freescale/mx35pdk/lowlevel_init.S delete mode 100644 board/freescale/mx35pdk/mx35pdk.c delete mode 100644 board/freescale/mx35pdk/mx35pdk.h delete mode 100644 configs/mx35pdk_defconfig delete mode 100644 include/configs/mx35pdk.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f2a87c3caed8..9969da161e9c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -621,11 +621,6 @@ config TARGET_FLEA3 bool "Support flea3" select CPU_ARM1136
-config TARGET_MX35PDK
- bool "Support mx35pdk"
- select BOARD_LATE_INIT
- select CPU_ARM1136
config ARCH_BCM283X bool "Broadcom BCM283X family" select DM @@ -2009,7 +2004,6 @@ source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" source "board/freescale/lx2160a/Kconfig" -source "board/freescale/mx35pdk/Kconfig" source "board/freescale/s32v234evb/Kconfig" source "board/grinn/chiliboard/Kconfig" source "board/hisilicon/hikey/Kconfig" diff --git a/board/freescale/mx35pdk/Kconfig b/board/freescale/mx35pdk/Kconfig deleted file mode 100644 index 021d19e5511c..000000000000 --- a/board/freescale/mx35pdk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX35PDK
-config SYS_BOARD
- default "mx35pdk"
-config SYS_VENDOR
- default "freescale"
-config SYS_SOC
- default "mx35"
-config SYS_CONFIG_NAME
- default "mx35pdk"
-endif diff --git a/board/freescale/mx35pdk/MAINTAINERS b/board/freescale/mx35pdk/MAINTAINERS deleted file mode 100644 index 540e9436912b..000000000000 --- a/board/freescale/mx35pdk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX35PDK BOARD -M: Stefano Babic sbabic@denx.de -S: Maintained -F: board/freescale/mx35pdk/ -F: include/configs/mx35pdk.h -F: configs/mx35pdk_defconfig diff --git a/board/freescale/mx35pdk/Makefile b/board/freescale/mx35pdk/Makefile deleted file mode 100644 index 6a60fad0cc8d..000000000000 --- a/board/freescale/mx35pdk/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de -# -# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-obj-y := mx35pdk.o -obj-y += lowlevel_init.o diff --git a/board/freescale/mx35pdk/README b/board/freescale/mx35pdk/README deleted file mode 100644 index 6f6841f0993b..000000000000 --- a/board/freescale/mx35pdk/README +++ /dev/null @@ -1,114 +0,0 @@
-Overview
-mx35pdk (known als as mx35_3stack) is a development board by Freescale. -It consists of three pluggable board:
- CPU module, with CPU, RAM, flash
- Personality board, with most interfaces (USB, Network,..)
- Debug board with JTAG header.
-The board is usually delivered with redboot. This howto explains how to boot -a linux kernel and how to replace the original bootloader with U-Boot.
-The board is delivered with Redboot on the NAND flash. It is possible to -switch the boot device with the switches SW1-SW2 on the Personality board, -and with SW5-SW10 on the Debug board.
-Delivered Redboot script to start the kernel
-In redboot the following script is stored:
-fis load kernel -exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76"
-Kernel is taken from flash. The image is in zImage format.
-Booting from NET, rootfs on NFS:
-To change the script in redboot:
-load -r -b 0x100000 <path_to_zImage> -exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp"
-If the ip address is not set, you can set it with :
-ip_address -l <board_ip/netmask> -h <server_ip>
-Linux partitions:
-As default, the board is shipped with these partition tables for NAND -and for NOR:
-Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit": -0x00000000-0x00100000 : "nand.bootloader" -0x00100000-0x00600000 : "nand.kernel" -0x00600000-0x06600000 : "nand.rootfs" -0x06600000-0x06e00000 : "nand.configure" -0x06e00000-0x80000000 : "nand.userfs"
-Creating 6 MTD partitions on "mxc_nor_flash.0": -0x00000000-0x00080000 : "Bootloader" -0x00080000-0x00480000 : "nor.Kernel" -0x00480000-0x02280000 : "nor.userfs" -0x02280000-0x03e80000 : "nor.rootfs" -0x01fe0000-0x01fe3000 : "FIS directory" -0x01fff000-0x04000000 : "Redboot config"
-NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS. -For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2.
-However, the setup in redboot is not correct and does not use the whole flash.
-Better solution is to use the kernel parameter mtdparts. -Here the resulting script to be defined in RedBoot with fconfig:
-load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37 -exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
-Flashing U-Boot
-U-Boot should be stored on the NOR flash.
-The boot storage can be select using the switches on the personality board -(SW1-SW2) and on the DEBUG board (SW4-SW10).
-If something goes wrong flashing the bootloader, it is always possible to -recover the board booting from the other device.
-Saving U-Boot in the NOR flash
-Check the partition for boot in the NOR flash. Setting the mtdparts as reported, -the boot partition should be /dev/mtd0.
-Creating 6 MTD partitions on "mxc_nor_flash.0": -0x00000000-0x00080000 : "Bootloader" -0x00080000-0x00480000 : "nor.Kernel" -0x00480000-0x02280000 : "nor.userfs" -0x02280000-0x03e80000 : "nor.rootfs" -0x01fe0000-0x01fe3000 : "FIS directory" -0x01fff000-0x04000000 : "Redboot config"
-To erase the whole partition: -$ flash_eraseall /dev/mtd0
-Writing U-Boot: -dd if=u-boot.bin of=/dev/mtd0
-To boot from NOR, you have to select the switches as follows:
-Personality board
- SW2 all off
- SW1 all off
-Debug Board:
- SW5 0
- SW6 0
- SW7 0
- SW8 1
- SW9 1
- SW10 0
diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S deleted file mode 100644 index 5dae5597fb69..000000000000 --- a/board/freescale/mx35pdk/lowlevel_init.S +++ /dev/null @@ -1,239 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de
- (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- */
-#include <config.h> -#include <asm/arch/imx-regs.h> -#include <generated/asm-offsets.h> -#include "mx35pdk.h" -#include <asm/arch/lowlevel_macro.S>
-/*
- return soc version
- 0x10: TO1
- 0x20: TO2
- 0x30: TO3
- */
-.macro check_soc_version ret, tmp
- ldr \tmp, =IIM_BASE_ADDR
- ldr \ret, [\tmp, #IIM_SREV]
- cmp \ret, #0x00
- moveq \tmp, #ROMPATCH_REV
- ldreq \ret, [\tmp]
- moveq \ret, \ret, lsl #4
- addne \ret, \ret, #0x10
-.endm
-/* CPLD on CS5 setup */ -.macro init_debug_board
- ldr r0, =DBG_BASE_ADDR
- ldr r1, =DBG_CSCR_U_CONFIG
- str r1, [r0, #0x00]
- ldr r1, =DBG_CSCR_L_CONFIG
- str r1, [r0, #0x04]
- ldr r1, =DBG_CSCR_A_CONFIG
- str r1, [r0, #0x08]
-.endm
-/* clock setup */ -.macro init_clock
- ldr r0, =CCM_BASE_ADDR
- /* default CLKO to 1/32 of the ARM core*/
- ldr r1, [r0, #CLKCTL_COSR]
- bic r1, r1, #0x00000FF00
- bic r1, r1, #0x0000000FF
- mov r2, #0x00006C00
- add r2, r2, #0x67
- orr r1, r1, r2
- str r1, [r0, #CLKCTL_COSR]
- ldr r2, =CCM_CCMR_CONFIG
- str r2, [r0, #CLKCTL_CCMR]
- check_soc_version r1, r2
- cmp r1, #CHIP_REV_2_0
- ldrhs r3, =CCM_MPLL_532_HZ
- bhs 1f
- ldr r2, [r0, #CLKCTL_PDR0]
- tst r2, #CLKMODE_CONSUMER
- ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
- ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
-1:
- str r3, [r0, #CLKCTL_MPCTL]
- ldr r1, =CCM_PPLL_300_HZ
- str r1, [r0, #CLKCTL_PPCTL]
- ldr r1, =CCM_PDR0_CONFIG
- bic r1, r1, #0x800000
- str r1, [r0, #CLKCTL_PDR0]
- ldr r1, [r0, #CLKCTL_CGR0]
- orr r1, r1, #0x0C300000
- str r1, [r0, #CLKCTL_CGR0]
- ldr r1, [r0, #CLKCTL_CGR1]
- orr r1, r1, #0x00000C00
- orr r1, r1, #0x00000003
- str r1, [r0, #CLKCTL_CGR1]
- ldr r1, [r0, #CLKCTL_CGR2]
- orr r1, r1, #0x00C00000
- str r1, [r0, #CLKCTL_CGR2]
-.endm
-.macro setup_sdram
- ldr r0, =ESDCTL_BASE_ADDR
- mov r3, #0x2000
- str r3, [r0, #0x0]
- str r3, [r0, #0x8]
- /*ip(r12) has used to save lr register in upper calling*/
- mov fp, lr
- mov r5, #0x00
- mov r2, #0x00
- mov r1, #CSD0_BASE_ADDR
- bl setup_sdram_bank
- mov r5, #0x00
- mov r2, #0x00
- mov r1, #CSD1_BASE_ADDR
- bl setup_sdram_bank
- mov lr, fp
-1:
- ldr r3, =ESDCTL_DELAY_LINE5
- str r3, [r0, #0x30]
-.endm
-.globl lowlevel_init -lowlevel_init:
- mov r10, lr
- core_init
- init_aips
- init_max
- init_m3if
- init_clock
- init_debug_board
- cmp pc, #PHYS_SDRAM_1
- blo init_sdram_start
- cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
- blo skip_sdram_setup
-init_sdram_start:
- /*init_sdram*/
- setup_sdram
-skip_sdram_setup:
- mov lr, r10
- mov pc, lr
-/*
- r0: ESDCTL control base, r1: sdram slot base
- r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
- */
-setup_sdram_bank:
- mov r3, #0xE
- tst r2, #0x1
- orreq r3, r3, #0x300 /*DDR2*/
- str r3, [r0, #0x10]
- bic r3, r3, #0x00A
- str r3, [r0, #0x10]
- beq 2f
- mov r3, #0x20000
-1: subs r3, r3, #1
- bne 1b
-2: tst r2, #0x1
- ldreq r3, =ESDCTL_DDR2_CONFIG
- ldrne r3, =ESDCTL_MDDR_CONFIG
- cmp r1, #CSD1_BASE_ADDR
- strlo r3, [r0, #0x4]
- strhs r3, [r0, #0xC]
- ldr r3, =ESDCTL_0x92220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_PRECHARGE
- strb r3, [r1, r4]
- tst r2, #0x1
- bne skip_set_mode
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0xB2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_DDR2_EMR2
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_EMR3
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_EN_DLL
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_RESET_DLL
- strb r3, [r1, r4]
- ldr r3, =ESDCTL_0x92220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_PRECHARGE
- strb r3, [r1, r4]
-skip_set_mode:
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0xA2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- strb r3, [r1]
- strb r3, [r1]
- ldr r3, =ESDCTL_0xB2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- tst r2, #0x1
- ldreq r4, =ESDCTL_DDR2_MR
- ldrne r4, =ESDCTL_MDDR_MR
- mov r3, #0xDA
- strb r3, [r1, r4]
- ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
- streqb r3, [r1, r4]
- ldreq r4, =ESDCTL_DDR2_EN_DLL
- ldrne r4, =ESDCTL_MDDR_EMR
- strb r3, [r1, r4]
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0x82228080
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- tst r2, #0x1
- moveq r4, #0x20000
- movne r4, #0x200
-1: subs r4, r4, #1
- bne 1b
- str r3, [r1, #0x100]
- ldr r4, [r1, #0x100]
- cmp r3, r4
- movne r3, #1
- moveq r3, #0
- mov pc, lr
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c deleted file mode 100644 index fc024c47dbdd..000000000000 --- a/board/freescale/mx35pdk/mx35pdk.c +++ /dev/null @@ -1,293 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de
- (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- */
-#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux-mx35.h> -#include <i2c.h> -#include <power/pmic.h> -#include <fsl_pmic.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <mc9sdz60.h> -#include <mc13892.h> -#include <linux/types.h> -#include <asm/gpio.h> -#include <asm/arch/sys_proto.h> -#include <netdev.h> -#include <asm/mach-types.h>
-#ifndef CONFIG_BOARD_LATE_INIT -#error "CONFIG_BOARD_LATE_INIT must be set for this board" -#endif
-#ifndef CONFIG_BOARD_EARLY_INIT_F -#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" -#endif
-DECLARE_GLOBAL_DATA_PTR;
-int dram_init(void) -{
- u32 size1, size2;
- size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
- gd->ram_size = size1 + size2;
- return 0;
-}
-int dram_init_banksize(void) -{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- return 0;
-}
-#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
-static void setup_iomux_i2c(void) -{
- static const iomux_v3_cfg_t i2c1_pads[] = {
NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),- };
- /* setup pins for I2C1 */
- imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
-}
-static void setup_iomux_spi(void) -{
- static const iomux_v3_cfg_t spi_pads[] = {
MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,MX35_PAD_CSPI1_MISO__CSPI1_MISO,MX35_PAD_CSPI1_SS0__CSPI1_SS0,MX35_PAD_CSPI1_SS1__CSPI1_SS1,MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,- };
- imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
-}
-#define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)-#define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
-static void setup_iomux_usbotg(void) -{
- static const iomux_v3_cfg_t usbotg_pads[] = {
NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,USBOTG_OUT_PAD_CTRL),NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,USBOTG_IN_PAD_CTRL),- };
- /* Set up pins for USBOTG. */
- imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
-}
-#define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
-static void setup_iomux_fec(void) -{
- static const iomux_v3_cfg_t fec_pads[] = {
NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),- };
- /* setup pins for FEC */
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-int board_early_init_f(void) -{
- struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;- /* enable clocks */
- writel(readl(&ccm->cgr0) |
MXC_CCM_CGR0_EMI_MASK |MXC_CCM_CGR0_EDIO_MASK |MXC_CCM_CGR0_EPIT1_MASK,&ccm->cgr0);- writel(readl(&ccm->cgr1) |
MXC_CCM_CGR1_FEC_MASK |MXC_CCM_CGR1_GPIO1_MASK |MXC_CCM_CGR1_GPIO2_MASK |MXC_CCM_CGR1_GPIO3_MASK |MXC_CCM_CGR1_I2C1_MASK |MXC_CCM_CGR1_I2C2_MASK |MXC_CCM_CGR1_IPU_MASK,&ccm->cgr1);- /* Setup NAND */
- __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
- setup_iomux_i2c();
- setup_iomux_usbotg();
- setup_iomux_fec();
- setup_iomux_spi();
- return 0;
-}
-int board_init(void) -{
- gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- return 0;
-}
-static inline int pmic_detect(void) -{
- unsigned int id;
- struct pmic *p = pmic_get("FSL_PMIC");
- if (!p)
return -ENODEV;- pmic_reg_read(p, REG_IDENTIFICATION, &id);
- id = (id >> 6) & 0x7;
- if (id == 0x7)
return 1;- return 0;
-}
-u32 get_board_rev(void) -{
- int rev;
- rev = pmic_detect();
- return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
-}
-int board_late_init(void) -{
- u8 val;
- u32 pmic_val;
- struct pmic *p;
- int ret;
- ret = pmic_init(I2C_0);
- if (ret)
return ret;- if (pmic_detect()) {
p = pmic_get("FSL_PMIC");imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);pmic_reg_read(p, REG_SETTING_0, &pmic_val);pmic_reg_write(p, REG_SETTING_0,pmic_val | VO_1_30V | VO_1_50V);pmic_reg_read(p, REG_MODE_0, &pmic_val);pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);gpio_direction_output(IMX_GPIO_NR(1, 5), 1);- }
- val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
- mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
- mdelay(200);
- val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
- mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
- mdelay(200);
- val |= 0x80;
- mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
- /* Print board revision */
- printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
- return 0;
-}
-int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_SMC911X)
- int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
- if (rc)
return rc;-#endif
- return cpu_eth_init(bis);
-}
-#if defined(CONFIG_FSL_ESDHC_IMX)
-struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
-int board_mmc_init(struct bd_info *bis) -{
- static const iomux_v3_cfg_t sdhc1_pads[] = {
MX35_PAD_SD1_CMD__ESDHC1_CMD,MX35_PAD_SD1_CLK__ESDHC1_CLK,MX35_PAD_SD1_DATA0__ESDHC1_DAT0,MX35_PAD_SD1_DATA1__ESDHC1_DAT1,MX35_PAD_SD1_DATA2__ESDHC1_DAT2,MX35_PAD_SD1_DATA3__ESDHC1_DAT3,- };
- /* configure pins for SDHC1 only */
- imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
- esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
- return fsl_esdhc_initialize(bis, &esdhc_cfg);
-}
-int board_mmc_getcd(struct mmc *mmc) -{
- return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
-} -#endif diff --git a/board/freescale/mx35pdk/mx35pdk.h b/board/freescale/mx35pdk/mx35pdk.h deleted file mode 100644 index 0af4b88bfbee..000000000000 --- a/board/freescale/mx35pdk/mx35pdk.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- (c) 2007 Pengutronix, Sascha Hauer s.hauer@pengutronix.de
- (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- */
-#ifndef __BOARD_MX35_3STACK_H -#define __BOARD_MX35_3STACK_H
-#define DBG_BASE_ADDR WEIM_CTRL_CS5 -#define DBG_CSCR_U_CONFIG 0x0000D843 -#define DBG_CSCR_L_CONFIG 0x22252521 -#define DBG_CSCR_A_CONFIG 0x22220A00
-#define CCM_CCMR_CONFIG 0x003F4208 -#define CCM_PDR0_CONFIG 0x00801000
-/* MEMORY SETTING */ -#define ESDCTL_0x92220000 0x92220000 -#define ESDCTL_0xA2220000 0xA2220000 -#define ESDCTL_0xB2220000 0xB2220000 -#define ESDCTL_0x82228080 0x82228080
-#define ESDCTL_PRECHARGE 0x00000400
-#define ESDCTL_MDDR_CONFIG 0x007FFC3F -#define ESDCTL_MDDR_MR 0x00000033 -#define ESDCTL_MDDR_EMR 0x02000000
-#define ESDCTL_DDR2_CONFIG 0x007FFC3F -#define ESDCTL_DDR2_EMR2 0x04000000 -#define ESDCTL_DDR2_EMR3 0x06000000 -#define ESDCTL_DDR2_EN_DLL 0x02000400 -#define ESDCTL_DDR2_RESET_DLL 0x00000333 -#define ESDCTL_DDR2_MR 0x00000233 -#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-#define ESDCTL_DELAY_LINE5 0x00F49F00 -#endif /* __BOARD_MX35_3STACK_H */ diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig deleted file mode 100644 index ab77fb5c06c2..000000000000 --- a/configs/mx35pdk_defconfig +++ /dev/null @@ -1,54 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_MX35PDK=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)" -CONFIG_EFI_PARTITION=y -# CONFIG_PARTITION_UUIDS is not set -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xA0080000 -CONFIG_ENV_ADDR_REDUND=0xA00A0000 -CONFIG_MXC_GPIO=y -CONFIG_FSL_ESDHC_IMX=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXC=y -CONFIG_MII=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0xB6000000 -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 9db4cae1df18..79ad0a1b3435 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -635,7 +635,7 @@ config MCFUART
config MXC_UART bool "IMX serial port support"
- depends on ARCH_MX25 || ARCH_MX31 || TARGET_APF27 || TARGET_FLEA3 || TARGET_MX35PDK \
- depends on ARCH_MX25 || ARCH_MX31 || TARGET_APF27 || TARGET_FLEA3 \ || MX5 || MX6 || MX7 || IMX8M help If you have a machine based on a Motorola IMX CPU you
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h deleted file mode 100644 index d2dcc8179b14..000000000000 --- a/include/configs/mx35pdk.h +++ /dev/null @@ -1,206 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- (C) Copyright 2010, Stefano Babic sbabic@denx.de
- (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de
- Configuration for the MX35pdk Freescale board.
- */
-#ifndef __CONFIG_H -#define __CONFIG_H
-#include <asm/arch/imx-regs.h>
- /* High Level Configuration Options */
-#define CONFIG_MX35
-#define CONFIG_SYS_FSL_CLK
-/* Set TEXT at the beginning of the NOR flash */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG
-/*
- Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
-/*
- Hardware drivers
- */
-#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-/*
- PMIC Configs
- */
-#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_FSL -#define CONFIG_POWER_FSL_MC13892 -#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08 -#define CONFIG_RTC_MC13XXX
-/*
- MFD MC9SDZ60
- */
-#define CONFIG_FSL_MC9SDZ60 -#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69
-/*
- UART (console)
- */
-#define CONFIG_MXC_UART_BASE UART1_BASE
-/*
- Command definition
- */
-#define CONFIG_NET_RETRY_COUNT 100
-#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
-/*
- Ethernet on the debug board (SMC911)
- */
-#define CONFIG_HAS_ETH1 -#define CONFIG_ETHPRIME
-/*
- Ethernet on SOC (FEC)
- */
-#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1F
-#define CONFIG_ARP_TIMEOUT 200UL
-/*
- Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-/*
- Physical Memory Map
- */
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_GBL_DATA_OFFSET)-/*
- MTD Command for mtdparts
- */
-/*
- FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-/* Address and size of Redundant Environment Sector */
-/*
- CFI FLASH driver setup
- */
-/* A non-standard buffered write algorithm */ -#define CONFIG_FLASH_SPANSION_S29WS_N
-/*
- NAND FLASH driver setup
- */
-#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE
-/* EHCI driver */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_MXC -#define CONFIG_MXC_USB_PORT 0 -#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \
MXC_EHCI_POWER_PINS_ENABLED | \MXC_EHCI_OC_PIN_ACTIVE_LOW)-#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
-/* mmc driver */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1
-/*
- Default environment and default scripts
- to update uboot and load kernel
- */
-#define CONFIG_HOSTNAME "mx35pdk" -#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth1\0" \
- "ethprime=smc911x\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip_sta=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \":${hostname}:${netdev}:off panic=1\0" \- "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
- "addip=if test -n ${ipdyn};then run addip_dyn;" \
"else run addip_sta;fi\0" \- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addtty=setenv bootargs ${bootargs}" \
" console=ttymxc0,${baudrate}\0" \- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
- "loadaddr=80800000\0" \
- "kernel_addr_r=80800000\0" \
- "hostname=" CONFIG_HOSTNAME "\0" \
- "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
- "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr}\0" \- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
"run nfsargs addip addtty addmtd addmisc;" \"bootm ${kernel_addr_r}\0" \- "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \- "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
- "update=protect off ${uboot_addr} +80000;" \
"erase ${uboot_addr} +80000;" \"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \- "upd=if run load;then echo Updating u-boot;if run update;" \
"then echo U-Boot updated;" \"else echo Error updating u-boot !;" \"echo Board without bootloader !!;" \"fi;" \"else echo U-Boot not downloaded..exiting;fi\0" \- "bootcmd=run net_nfs\0"
-#endif /* __CONFIG_H */
On Tue, Feb 09, 2021 at 08:03:02AM -0500, Tom Rini wrote:
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Stefano Babic sbabic@denx.de Signed-off-by: Tom Rini trini@konsulko.com Acked-by: Stefano Babic sbabic@denx.de
Applied to u-boot/master, thanks!
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Philippe Reynes tremyfr@yahoo.fr Cc: Eric Jarrige eric.jarrige@armadeus.org Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/Kconfig | 6 - board/armadeus/apf27/Kconfig | 15 - board/armadeus/apf27/MAINTAINERS | 7 - board/armadeus/apf27/Makefile | 12 - board/armadeus/apf27/apf27.c | 258 -------------- board/armadeus/apf27/apf27.h | 488 --------------------------- board/armadeus/apf27/fpga.c | 226 ------------- board/armadeus/apf27/fpga.h | 24 -- board/armadeus/apf27/lowlevel_init.S | 166 --------- configs/apf27_defconfig | 59 ---- drivers/serial/Kconfig | 2 +- include/configs/apf27.h | 266 --------------- 12 files changed, 1 insertion(+), 1528 deletions(-) delete mode 100644 board/armadeus/apf27/Kconfig delete mode 100644 board/armadeus/apf27/MAINTAINERS delete mode 100644 board/armadeus/apf27/Makefile delete mode 100644 board/armadeus/apf27/apf27.c delete mode 100644 board/armadeus/apf27/apf27.h delete mode 100644 board/armadeus/apf27/fpga.c delete mode 100644 board/armadeus/apf27/fpga.h delete mode 100644 board/armadeus/apf27/lowlevel_init.S delete mode 100644 configs/apf27_defconfig delete mode 100644 include/configs/apf27.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9969da161e9c..acffdc6a1ed8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -561,11 +561,6 @@ config ARCH_MVEBU select SPI imply CMD_DM
-config TARGET_APF27 - bool "Support apf27" - select CPU_ARM926EJS - select SUPPORT_SPL - config ARCH_ORION5X bool "Marvell Orion" select CPU_ARM926EJS @@ -1969,7 +1964,6 @@ source "board/Marvell/aspenite/Kconfig" source "board/Marvell/gplugd/Kconfig" source "board/Marvell/octeontx/Kconfig" source "board/Marvell/octeontx2/Kconfig" -source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" source "board/cortina/presidio-asic/Kconfig" diff --git a/board/armadeus/apf27/Kconfig b/board/armadeus/apf27/Kconfig deleted file mode 100644 index 65544a844834..000000000000 --- a/board/armadeus/apf27/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_APF27 - -config SYS_BOARD - default "apf27" - -config SYS_VENDOR - default "armadeus" - -config SYS_SOC - default "mx27" - -config SYS_CONFIG_NAME - default "apf27" - -endif diff --git a/board/armadeus/apf27/MAINTAINERS b/board/armadeus/apf27/MAINTAINERS deleted file mode 100644 index 09f0525c51b9..000000000000 --- a/board/armadeus/apf27/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -APF27 BOARD -M: Philippe Reynes tremyfr@yahoo.fr -M: Eric Jarrige eric.jarrige@armadeus.org -S: Maintained -F: board/armadeus/apf27/ -F: include/configs/apf27.h -F: configs/apf27_defconfig diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile deleted file mode 100644 index 57129718d5c5..000000000000 --- a/board/armadeus/apf27/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# (C) Copyright 2012-2013 -# Eric Jarrige eric.jarrige@armadeus.org -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := apf27.o -obj-y += lowlevel_init.o -obj-$(CONFIG_FPGA) += fpga.o diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c deleted file mode 100644 index 29e0bf388d07..000000000000 --- a/board/armadeus/apf27/apf27.c +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008-2013 Eric Jarrige eric.jarrige@armadeus.org - * - * based on the files by - * Sascha Hauer, Pengutronix - */ - -#include <common.h> -#include <hang.h> -#include <init.h> -#include <jffs2/jffs2.h> -#include <nand.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/gpio.h> -#include <asm/gpio.h> -#include <linux/errno.h> -#include <u-boot/crc.h> -#include "apf27.h" -#include "fpga.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Fuse bank 1 row 8 is "reserved for future use" and therefore available for - * customer use. The APF27 board uses this fuse to store the board revision: - * 0: initial board revision - * 1: first revision - Presence of the second RAM chip on the board is blown in - * fuse bank 1 row 9 bit 0 - No hardware change - * N: to be defined - */ -static u32 get_board_rev(void) -{ - struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; - - return readl(&iim->bank[1].fuse_regs[8]); -} - -/* - * Fuse bank 1 row 9 is "reserved for future use" and therefore available for - * customer use. The APF27 board revision 1 uses the bit 0 to permanently store - * the presence of the second RAM chip - * 0: AFP27 with 1 RAM of 64 MiB - * 1: AFP27 with 2 RAM chips of 64 MiB each (128MB) - */ -static int get_num_ram_bank(void) -{ - struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; - int nr_dram_banks = 1; - - if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1)) - nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01; - else - nr_dram_banks = CONFIG_NR_DRAM_POPULATED; - - return nr_dram_banks; -} - -static void apf27_port_init(int port, u32 gpio_dr, u32 ocr1, u32 ocr2, - u32 iconfa1, u32 iconfa2, u32 iconfb1, u32 iconfb2, - u32 icr1, u32 icr2, u32 imr, u32 gpio_dir, u32 gpr, - u32 puen, u32 gius) -{ - struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE; - - writel(gpio_dr, ®s->port[port].gpio_dr); - writel(ocr1, ®s->port[port].ocr1); - writel(ocr2, ®s->port[port].ocr2); - writel(iconfa1, ®s->port[port].iconfa1); - writel(iconfa2, ®s->port[port].iconfa2); - writel(iconfb1, ®s->port[port].iconfb1); - writel(iconfb2, ®s->port[port].iconfb2); - writel(icr1, ®s->port[port].icr1); - writel(icr2, ®s->port[port].icr2); - writel(imr, ®s->port[port].imr); - writel(gpio_dir, ®s->port[port].gpio_dir); - writel(gpr, ®s->port[port].gpr); - writel(puen, ®s->port[port].puen); - writel(gius, ®s->port[port].gius); -} - -#define APF27_PORT_INIT(n) apf27_port_init(PORT##n, ACFG_DR_##n##_VAL, \ - ACFG_OCR1_##n##_VAL, ACFG_OCR2_##n##_VAL, ACFG_ICFA1_##n##_VAL, \ - ACFG_ICFA2_##n##_VAL, ACFG_ICFB1_##n##_VAL, ACFG_ICFB2_##n##_VAL, \ - ACFG_ICR1_##n##_VAL, ACFG_ICR2_##n##_VAL, ACFG_IMR_##n##_VAL, \ - ACFG_DDIR_##n##_VAL, ACFG_GPR_##n##_VAL, ACFG_PUEN_##n##_VAL, \ - ACFG_GIUS_##n##_VAL) - -static void apf27_iomux_init(void) -{ - APF27_PORT_INIT(A); - APF27_PORT_INIT(B); - APF27_PORT_INIT(C); - APF27_PORT_INIT(D); - APF27_PORT_INIT(E); - APF27_PORT_INIT(F); -} - -static int apf27_devices_init(void) -{ - int i; - unsigned int mode[] = { - PC5_PF_I2C2_DATA, - PC6_PF_I2C2_CLK, - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - -#ifdef CONFIG_MXC_UART - mx27_uart1_init_pins(); -#endif - -#ifdef CONFIG_FEC_MXC - mx27_fec_init_pins(); -#endif - -#ifdef CONFIG_MMC_MXC - mx27_sd2_init_pins(); - imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16)); - gpio_request(PC_PWRON, "pc_pwron"); - gpio_set_value(PC_PWRON, 1); -#endif - return 0; -} - -static void apf27_setup_csx(void) -{ - struct weim_regs *weim = (struct weim_regs *)IMX_WEIM_BASE; - - writel(ACFG_CS0U_VAL, &weim->cs0u); - writel(ACFG_CS0L_VAL, &weim->cs0l); - writel(ACFG_CS0A_VAL, &weim->cs0a); - - writel(ACFG_CS1U_VAL, &weim->cs1u); - writel(ACFG_CS1L_VAL, &weim->cs1l); - writel(ACFG_CS1A_VAL, &weim->cs1a); - - writel(ACFG_CS2U_VAL, &weim->cs2u); - writel(ACFG_CS2L_VAL, &weim->cs2l); - writel(ACFG_CS2A_VAL, &weim->cs2a); - - writel(ACFG_CS3U_VAL, &weim->cs3u); - writel(ACFG_CS3L_VAL, &weim->cs3l); - writel(ACFG_CS3A_VAL, &weim->cs3a); - - writel(ACFG_CS4U_VAL, &weim->cs4u); - writel(ACFG_CS4L_VAL, &weim->cs4l); - writel(ACFG_CS4A_VAL, &weim->cs4a); - - writel(ACFG_CS5U_VAL, &weim->cs5u); - writel(ACFG_CS5L_VAL, &weim->cs5l); - writel(ACFG_CS5A_VAL, &weim->cs5a); - - writel(ACFG_EIM_VAL, &weim->eim); -} - -static void apf27_setup_port(void) -{ - struct system_control_regs *system = - (struct system_control_regs *)IMX_SYSTEM_CTL_BASE; - - writel(ACFG_FMCR_VAL, &system->fmcr); -} - -int board_init(void) -{ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - apf27_setup_csx(); - apf27_setup_port(); - apf27_iomux_init(); - apf27_devices_init(); -#if defined(CONFIG_FPGA) - APF27_init_fpga(); -#endif - - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - if (get_num_ram_bank() > 1) - gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - if (get_num_ram_bank() > 1) - gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); - else - gd->bd->bi_dram[1].size = 0; - - return 0; -} - -ulong board_get_usable_ram_top(ulong total_size) -{ - ulong ramtop; - - if (get_num_ram_bank() > 1) - ramtop = PHYS_SDRAM_2 + get_ram_size((void *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); - else - ramtop = PHYS_SDRAM_1 + get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - - return ramtop; -} - -int checkboard(void) -{ - printf("Board: Armadeus APF27 revision %d\n", get_board_rev()); - return 0; -} - -#ifdef CONFIG_SPL_BUILD -inline void hang(void) -{ - for (;;) - ; -} - -void board_init_f(ulong bootflag) -{ - /* - * copy ourselves from where we are running to where we were - * linked at. Use ulong pointers as all addresses involved - * are 4-byte-aligned. - */ - ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst; - asm volatile ("ldr %0, =_start" : "=r"(start_ptr)); - asm volatile ("ldr %0, =_end" : "=r"(end_ptr)); - asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr)); - asm volatile ("adr %0, board_init_f" : "=r"(run_ptr)); - for (dst = start_ptr; dst < end_ptr; dst++) - *dst = *(dst+(run_ptr-link_ptr)); - - /* - * branch to nand_boot's link-time address. - */ - asm volatile("ldr pc, =nand_boot"); -} -#endif /* CONFIG_SPL_BUILD */ diff --git a/board/armadeus/apf27/apf27.h b/board/armadeus/apf27/apf27.h deleted file mode 100644 index 9c3cfd3cf4bd..000000000000 --- a/board/armadeus/apf27/apf27.h +++ /dev/null @@ -1,488 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2008-2013 Eric Jarrige eric.jarrige@armadeus.org - */ - -#ifndef __APF27_H -#define __APF27_H - -/* FPGA program pin configuration */ -#define ACFG_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */ -#define ACFG_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */ -#define ACFG_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */ -#define ACFG_FPGA_RDATA 0xD6000000 /* FPGA data addr */ -#define ACFG_FPGA_WDATA 0xD6000000 /* FPGA data addr */ -#define ACFG_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */ -#define ACFG_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */ -#define ACFG_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */ -#define ACFG_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */ -#define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */ -#define ACFG_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */ - -/* MMC pin */ -#define PC_PWRON (GPIO_PORTF | 16) - -/* - * MPU CLOCK source before PLL - * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ) - */ -#define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */ -#define ACFG_MPCTL1_VAL 0 -#define CONFIG_MPLL_FREQ 399 - -#define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */ - -/* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/ -#define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */ -#define ACFG_SPCTL1_VAL 0 -#define CONFIG_SPLL_FREQ 300 /* MHz */ - -/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */ -#define CONFIG_ARM_FREQ 399 /* up to 400 MHz */ - -/* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */ -#define CONFIG_HCLK_FREQ 133 /* (ACFG_CLK_FREQ/2) */ - -#define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */ -#define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */ -#define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */ -#define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */ -#define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1 */ -#define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2 */ -#define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC */ -#define CONFIG_H264_FREQ 66 /* 66.50 MHz H264 */ -#define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */ -#define CONFIG_CLK0_EN 1 /* CLK0 enabled */ - -/* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */ -#define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh 133MHz */ - -/* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */ -#define CONFIG_USB_FREQ 60 /* 60 MHz */ - -/* - * SDRAM - */ -#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ -/* micron 64MB */ -#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 - * column address bits - */ -#define ACFG_SDRAM_NUM_ROW 13 /* 11, 12 or 13 - * row address bits - */ -#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 - * 2=4096 3=8192 refresh - */ -#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power - * down delay - */ -#define ACFG_SDRAM_W2R_DELAY 1 /* write to read - * cycle delay > 0 - */ -#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ -#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register - * cycle delay 1..4 - */ -#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck - * SDRAM: 0=1ck 1=2ck - */ -#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ -#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ -#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ -#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC - * refresh to command) - */ -#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time - * estimated fo CL=1 - * 0=force 3 for lpddr - */ -#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater - * 3=Eighth 4=Sixteenth - */ -#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half - * 2=quater 3=Eighth - */ -#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ -#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access - * 0 = Burst mode - */ -#endif - -#if (ACFG_SDRAM_MBYTE_SYZE == 128) -/* micron 128MB */ -#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 - * column address bits - */ -#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 - * row address bits - */ -#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 - * 2=4096 3=8192 refresh - */ -#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power - * down delay - */ -#define ACFG_SDRAM_W2R_DELAY 1 /* write to read - * cycle delay > 0 - */ -#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ -#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register - * cycle delay 1..4 - */ -#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck - * SDRAM: 0=1ck 1=2ck - */ -#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ -#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ -#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ -#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC - * refresh to command) - */ -#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time - * estimated fo CL=1 - * 0=force 3 for lpddr - */ -#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater - * 3=Eighth 4=Sixteenth - */ -#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half - * 2=quater 3=Eighth - */ -#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ -#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access - * 0 = Burst mode - */ -#endif - -#if (ACFG_SDRAM_MBYTE_SYZE == 256) -/* micron 256MB */ -#define ACFG_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 - * column address bits - */ -#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 - * row address bits - */ -#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 - * 2=4096 3=8192 refresh - */ -#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power - * down delay - */ -#define ACFG_SDRAM_W2R_DELAY 1 /* write to read cycle - * delay > 0 - */ -#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ -#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register - * cycle delay 1..4 - */ -#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck - * SDRAM: 0=1ck 1=2ck - */ -#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ -#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ -#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ -#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC - * refresh to command) - */ -#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time - * estimated fo CL=1 - * 0=force 3 for lpddr - */ -#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater - * 3=Eighth 4=Sixteenth - */ -#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength - * 1=half - * 2=quater - * 3=Eighth - */ -#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ -#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access - * 0 = Burst mode - */ -#endif - -/* - * External interface - */ -/* - * CSCRxU_VAL: - * 31| x | x | x x |x x x x| x x | x | x |x x x x|16 - * |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL | - * - * 15| x x | x x x x x x | x | x x x x | x x x x |0 - * | CNC | WSC |EW | WWS | EDC | - * - * CSCRxL_VAL: - * 31| x x x x | x x x x | x x x x | x x x x |16 - * | OEA | OEN | EBWA | EBWN | - * 15|x x x x| x |x x x |x x x x| x | x | x | x | 0 - * | CSA |EBC| DSZ | CSN |PSR|CRE|WRAP|CSEN| - * - * CSCRxA_VAL: - * 31| x x x x | x x x x | x x x x | x x x x |16 - * | EBRA | EBRN | RWA | RWN | - * 15| x | x x |x x x|x x|x x|x x| x | x | x | x | 0 - * |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE| - */ - -/* CS0 configuration for 16 bit nor flash */ -#define ACFG_CS0U_VAL 0x0000CC03 -#define ACFG_CS0L_VAL 0xa0330D01 -#define ACFG_CS0A_VAL 0x00220800 - -#define ACFG_CS1U_VAL 0x00000f00 -#define ACFG_CS1L_VAL 0x00000D01 -#define ACFG_CS1A_VAL 0 - -#define ACFG_CS2U_VAL 0 -#define ACFG_CS2L_VAL 0 -#define ACFG_CS2A_VAL 0 - -#define ACFG_CS3U_VAL 0 -#define ACFG_CS3L_VAL 0 -#define ACFG_CS3A_VAL 0 - -#define ACFG_CS4U_VAL 0 -#define ACFG_CS4L_VAL 0 -#define ACFG_CS4A_VAL 0 - -/* FPGA 16 bit data bus */ -#define ACFG_CS5U_VAL 0x00000600 -#define ACFG_CS5L_VAL 0x00000D01 -#define ACFG_CS5A_VAL 0 - -#define ACFG_EIM_VAL 0x00002200 - - -/* - * FPGA specific settings - */ - -/* CLKO */ -#define ACFG_CCSR_VAL 0x00000305 -/* drive strength CLKO set to 2 */ -#define ACFG_DSCR10_VAL 0x00020000 -/* drive strength A1..A12 set to 2 */ -#define ACFG_DSCR3_VAL 0x02AAAAA8 -/* drive strength ctrl */ -#define ACFG_DSCR7_VAL 0x00020880 -/* drive strength data */ -#define ACFG_DSCR2_VAL 0xAAAAAAAA - - -/* - * Default configuration for GPIOs and peripherals - */ -#define ACFG_DDIR_A_VAL 0x00000000 -#define ACFG_OCR1_A_VAL 0x00000000 -#define ACFG_OCR2_A_VAL 0x00000000 -#define ACFG_ICFA1_A_VAL 0xFFFFFFFF -#define ACFG_ICFA2_A_VAL 0xFFFFFFFF -#define ACFG_ICFB1_A_VAL 0xFFFFFFFF -#define ACFG_ICFB2_A_VAL 0xFFFFFFFF -#define ACFG_DR_A_VAL 0x00000000 -#define ACFG_GIUS_A_VAL 0xFFFFFFFF -#define ACFG_ICR1_A_VAL 0x00000000 -#define ACFG_ICR2_A_VAL 0x00000000 -#define ACFG_IMR_A_VAL 0x00000000 -#define ACFG_GPR_A_VAL 0x00000000 -#define ACFG_PUEN_A_VAL 0xFFFFFFFF - -#define ACFG_DDIR_B_VAL 0x00000000 -#define ACFG_OCR1_B_VAL 0x00000000 -#define ACFG_OCR2_B_VAL 0x00000000 -#define ACFG_ICFA1_B_VAL 0xFFFFFFFF -#define ACFG_ICFA2_B_VAL 0xFFFFFFFF -#define ACFG_ICFB1_B_VAL 0xFFFFFFFF -#define ACFG_ICFB2_B_VAL 0xFFFFFFFF -#define ACFG_DR_B_VAL 0x00000000 -#define ACFG_GIUS_B_VAL 0xFF3FFFF0 -#define ACFG_ICR1_B_VAL 0x00000000 -#define ACFG_ICR2_B_VAL 0x00000000 -#define ACFG_IMR_B_VAL 0x00000000 -#define ACFG_GPR_B_VAL 0x00000000 -#define ACFG_PUEN_B_VAL 0xFFFFFFFF - -#define ACFG_DDIR_C_VAL 0x00000000 -#define ACFG_OCR1_C_VAL 0x00000000 -#define ACFG_OCR2_C_VAL 0x00000000 -#define ACFG_ICFA1_C_VAL 0xFFFFFFFF -#define ACFG_ICFA2_C_VAL 0xFFFFFFFF -#define ACFG_ICFB1_C_VAL 0xFFFFFFFF -#define ACFG_ICFB2_C_VAL 0xFFFFFFFF -#define ACFG_DR_C_VAL 0x00000000 -#define ACFG_GIUS_C_VAL 0xFFFFC07F -#define ACFG_ICR1_C_VAL 0x00000000 -#define ACFG_ICR2_C_VAL 0x00000000 -#define ACFG_IMR_C_VAL 0x00000000 -#define ACFG_GPR_C_VAL 0x00000000 -#define ACFG_PUEN_C_VAL 0xFFFFFF87 - -#define ACFG_DDIR_D_VAL 0x00000000 -#define ACFG_OCR1_D_VAL 0x00000000 -#define ACFG_OCR2_D_VAL 0x00000000 -#define ACFG_ICFA1_D_VAL 0xFFFFFFFF -#define ACFG_ICFA2_D_VAL 0xFFFFFFFF -#define ACFG_ICFB1_D_VAL 0xFFFFFFFF -#define ACFG_ICFB2_D_VAL 0xFFFFFFFF -#define ACFG_DR_D_VAL 0x00000000 -#define ACFG_GIUS_D_VAL 0xFFFFFFFF -#define ACFG_ICR1_D_VAL 0x00000000 -#define ACFG_ICR2_D_VAL 0x00000000 -#define ACFG_IMR_D_VAL 0x00000000 -#define ACFG_GPR_D_VAL 0x00000000 -#define ACFG_PUEN_D_VAL 0xFFFFFFFF - -#define ACFG_DDIR_E_VAL 0x00000000 -#define ACFG_OCR1_E_VAL 0x00000000 -#define ACFG_OCR2_E_VAL 0x00000000 -#define ACFG_ICFA1_E_VAL 0xFFFFFFFF -#define ACFG_ICFA2_E_VAL 0xFFFFFFFF -#define ACFG_ICFB1_E_VAL 0xFFFFFFFF -#define ACFG_ICFB2_E_VAL 0xFFFFFFFF -#define ACFG_DR_E_VAL 0x00000000 -#define ACFG_GIUS_E_VAL 0xFCFFCCF8 -#define ACFG_ICR1_E_VAL 0x00000000 -#define ACFG_ICR2_E_VAL 0x00000000 -#define ACFG_IMR_E_VAL 0x00000000 -#define ACFG_GPR_E_VAL 0x00000000 -#define ACFG_PUEN_E_VAL 0xFFFFFFFF - -#define ACFG_DDIR_F_VAL 0x00000000 -#define ACFG_OCR1_F_VAL 0x00000000 -#define ACFG_OCR2_F_VAL 0x00000000 -#define ACFG_ICFA1_F_VAL 0xFFFFFFFF -#define ACFG_ICFA2_F_VAL 0xFFFFFFFF -#define ACFG_ICFB1_F_VAL 0xFFFFFFFF -#define ACFG_ICFB2_F_VAL 0xFFFFFFFF -#define ACFG_DR_F_VAL 0x00000000 -#define ACFG_GIUS_F_VAL 0xFF7F8000 -#define ACFG_ICR1_F_VAL 0x00000000 -#define ACFG_ICR2_F_VAL 0x00000000 -#define ACFG_IMR_F_VAL 0x00000000 -#define ACFG_GPR_F_VAL 0x00000000 -#define ACFG_PUEN_F_VAL 0xFFFFFFFF - -/* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */ -#define ACFG_GPCR_VAL 0x0003000F - -#define ACFG_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN - -/* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */ -#if (CONFIG_NR_DRAM_BANKS == 1) -#define ACFG_FMCR_VAL 0xFFFFFFF9 -#elif (CONFIG_NR_DRAM_BANKS == 2) -#define ACFG_FMCR_VAL 0xFFFFFFFB -#endif - -#define ACFG_AIPI1_PSR0_VAL 0x20040304 -#define ACFG_AIPI1_PSR1_VAL 0xDFFBFCFB -#define ACFG_AIPI2_PSR0_VAL 0x00000000 -#define ACFG_AIPI2_PSR1_VAL 0xFFFFFFFF - -/* PCCR enable DMA FEC I2C1 IIM SDHC1 */ -#define ACFG_PCCR0_VAL 0x05070410 -#define ACFG_PCCR1_VAL 0xA14A0608 - -/* - * From here, there should not be any user configuration. - * All Equations are automatic - */ - -/* fixme none integer value (7.5ns) => 2*hclock = 15ns */ -#define ACFG_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */ - -/* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/ -#define CSCR_MASK 0x0300800D - -#define ACFG_CSCR_VAL \ - (CSCR_MASK \ - |((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28) \ - |((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12) \ - |((((ACFG_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8)) - -/* SSIx CLKO NFC H264 MSHC */ -#define ACFG_PCDR0_VAL\ - (((((ACFG_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0) \ - |((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6) \ - |(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\ - |(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\ - |(((CONFIG_CLK0_DIV)&0x07)<<22)\ - |(((CONFIG_CLK0_EN)&0x01)<<25)\ - |(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26)) - -/* PERCLKx */ -#define ACFG_PCDR1_VAL\ - (((((ACFG_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0) \ - |((((ACFG_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8) \ - |((((ACFG_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16) \ - |((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24)) - -/* SDRAM controller programming Values */ -#if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \ - (ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1)) -#define REG_FIELD_SCL_VAL 3 -#define REG_FIELD_SCLIMX_VAL 0 -#else -#define REG_FIELD_SCL_VAL\ - ((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \ - ACFG_2XHCLK_LGTH) -#define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL -#endif - -#if ((2*ACFG_SDRAM_RC_DELAY) > (16*ACFG_2XHCLK_LGTH)) -#define REG_FIELD_SRC_VAL 0 -#else -#define REG_FIELD_SRC_VAL\ - ((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \ - ACFG_2XHCLK_LGTH) -#endif - -/* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/ -#define REG_ESDCTL_BASE_CONFIG (0x80020485\ - | (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\ - | (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20)\ - | (((ACFG_SDRAM_REFRESH)&0x7)<<13)) - -#define ACFG_NORMAL_RW_CMD ((0x0<<28)+REG_ESDCTL_BASE_CONFIG) -#define ACFG_PRECHARGE_CMD ((0x1<<28)+REG_ESDCTL_BASE_CONFIG) -#define ACFG_AUTOREFRESH_CMD ((0x2<<28)+REG_ESDCTL_BASE_CONFIG) -#define ACFG_SET_MODE_REG_CMD ((0x3<<28)+REG_ESDCTL_BASE_CONFIG) - -/* ESDRAMC Configuration Registers : force CL=3 to lpddr */ -#define ACFG_SDRAM_ESDCFG_REGISTER_VAL (0x0\ - | (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \ - ACFG_2XHCLK_LGTH)-1)&0x3)<<21)\ - | (((ACFG_SDRAM_W2R_DELAY-1)&0x1)<<20)\ - | (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+ \ - ACFG_2XHCLK_LGTH-1)/ACFG_2XHCLK_LGTH)-1)&0x3)<<18) \ - | (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\ - | (((ACFG_SDRAM_TWR_DELAY)&0x1)<<15)\ - | (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \ - ACFG_2XHCLK_LGTH)-1)&0x7)<<12) \ - | (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ - ACFG_2XHCLK_LGTH)-1)&0x3)<<10) \ - | (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\ - | (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ - ACFG_2XHCLK_LGTH)-1)&0x7)<<4) \ - | (((REG_FIELD_SRC_VAL)&0x0F)<<0)) - -/* Issue Mode register Command to SDRAM */ -#define ACFG_SDRAM_MODE_REGISTER_VAL\ - ((((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\ - | (((REG_FIELD_SCL_VAL)&0x7)<<(4))\ - | ((0)<<(3)) /* sequentiql access */ \ - /*| (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/) - -/* Issue Extended Mode register Command to SDRAM */ -#define ACFG_SDRAM_EXT_MODE_REGISTER_VAL\ - ((ACFG_SDRAM_PARTIAL_ARRAY_SR<<0)\ - | (ACFG_SDRAM_DRIVE_STRENGH<<(5))\ - | (1<<(ACFG_SDRAM_NUM_COL+ACFG_SDRAM_NUM_ROW+1+2))) - -/* Issue Precharge all Command to SDRAM */ -#define ACFG_SDRAM_PRECHARGE_ALL_VAL (1<<10) - -#endif /* __APF27_H */ diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c deleted file mode 100644 index 9e2f39f9814f..000000000000 --- a/board/armadeus/apf27/fpga.c +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002-2013 - * Eric Jarrige eric.jarrige@armadeus.org - * - * based on the files by - * Rich Ireland, Enterasys Networks, rireland@enterasys.com - * and - * Keith Outwater, keith_outwater@mvis.com - */ -#include <common.h> -#include <log.h> -#include <linux/delay.h> - -#include <asm/arch/imx-regs.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <command.h> -#include <config.h> -#include "fpga.h" -#include <spartan3.h> -#include "apf27.h" - -/* - * Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - * Spartan2 code is used to download our Spartan 3 :) code is compatible. - * Just take care about the file size - */ -xilinx_spartan3_slave_parallel_fns fpga_fns = { - fpga_pre_fn, - fpga_pgm_fn, - fpga_init_fn, - NULL, - fpga_done_fn, - fpga_clk_fn, - fpga_cs_fn, - fpga_wr_fn, - fpga_rdata_fn, - fpga_wdata_fn, - fpga_busy_fn, - fpga_abort_fn, - fpga_post_fn, -}; - -xilinx_desc fpga[CONFIG_FPGA_COUNT] = { - {xilinx_spartan3, - slave_parallel, - 1196128l/8, - (void *)&fpga_fns, - 0, - &spartan3_op, - "3s200aft256"} -}; - -/* - * Initialize GPIO port B before download - */ -int fpga_pre_fn(int cookie) -{ - /* Initialize GPIO pins */ - gpio_set_value(ACFG_FPGA_PWR, 1); - imx_gpio_mode(ACFG_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO); - imx_gpio_mode(ACFG_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO); - imx_gpio_mode(ACFG_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); - imx_gpio_mode(ACFG_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); - imx_gpio_mode(ACFG_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); - imx_gpio_mode(ACFG_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); - imx_gpio_mode(ACFG_FPGA_SUSPEND|GPIO_OUT|GPIO_PUEN|GPIO_GPIO); - gpio_set_value(ACFG_FPGA_RESET, 1); - imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); - imx_gpio_mode(ACFG_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); - gpio_set_value(ACFG_FPGA_PRG, 1); - gpio_set_value(ACFG_FPGA_CLK, 1); - gpio_set_value(ACFG_FPGA_RW, 1); - gpio_set_value(ACFG_FPGA_CS, 1); - gpio_set_value(ACFG_FPGA_SUSPEND, 0); - gpio_set_value(ACFG_FPGA_PWR, 0); - udelay(30000); /*wait until supply started*/ - - return cookie; -} - -/* - * Set the FPGA's active-low program line to the specified level - */ -int fpga_pgm_fn(int assert, int flush, int cookie) -{ - debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__, - assert ? "high" : "low"); - gpio_set_value(ACFG_FPGA_PRG, !assert); - return assert; -} - -/* - * Set the FPGA's active-high clock line to the specified level - */ -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__, - assert_clk ? "high" : "low"); - gpio_set_value(ACFG_FPGA_CLK, !assert_clk); - return assert_clk; -} - -/* - * Test the state of the active-low FPGA INIT line. Return 1 on INIT - * asserted (low). - */ -int fpga_init_fn(int cookie) -{ - int value; - debug("%s:%d: INIT check... ", __func__, __LINE__); - value = gpio_get_value(ACFG_FPGA_INIT); - /* printf("init value read %x",value); */ -#ifdef CONFIG_SYS_FPGA_IS_PROTO - return value; -#else - return !value; -#endif -} - -/* - * Test the state of the active-high FPGA DONE pin - */ -int fpga_done_fn(int cookie) -{ - debug("%s:%d: DONE check... %s", __func__, __LINE__, - gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low"); - return gpio_get_value(ACFG_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL; -} - -/* - * Set the FPGA's wr line to the specified level - */ -int fpga_wr_fn(int assert_write, int flush, int cookie) -{ - debug("%s:%d: FPGA RW... %s ", __func__, __LINE__, - assert_write ? "high" : "low"); - gpio_set_value(ACFG_FPGA_RW, !assert_write); - return assert_write; -} - -int fpga_cs_fn(int assert_cs, int flush, int cookie) -{ - debug("%s:%d: FPGA CS %s ", __func__, __LINE__, - assert_cs ? "high" : "low"); - gpio_set_value(ACFG_FPGA_CS, !assert_cs); - return assert_cs; -} - -int fpga_rdata_fn(unsigned char *data, int cookie) -{ - debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__, - *((char *)ACFG_FPGA_RDATA)); - *data = (unsigned char) - ((*((unsigned short *)ACFG_FPGA_RDATA))&0x00FF); - return *data; -} - -int fpga_wdata_fn(unsigned char data, int flush, int cookie) -{ - debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__, - data); - *((unsigned short *)ACFG_FPGA_WDATA) = data; - return data; -} - -int fpga_abort_fn(int cookie) -{ - return fpga_post_fn(cookie); -} - - -int fpga_busy_fn(int cookie) -{ - return 1; -} - -int fpga_post_fn(int cookie) -{ - debug("%s:%d: FPGA POST ", __func__, __LINE__); - - imx_gpio_mode(ACFG_FPGA_RW | GPIO_PF | GPIO_PUEN); - imx_gpio_mode(ACFG_FPGA_CS | GPIO_PF | GPIO_PUEN); - imx_gpio_mode(ACFG_FPGA_CLK | GPIO_PF | GPIO_PUEN); - gpio_set_value(ACFG_FPGA_PRG, 1); - gpio_set_value(ACFG_FPGA_RESET, 0); - imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); - return cookie; -} - -void apf27_fpga_setup(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - struct system_control_regs *system = - (struct system_control_regs *)IMX_SYSTEM_CTL_BASE; - - /* Configure FPGA CLKO */ - writel(ACFG_CCSR_VAL, &pll->ccsr); - - /* Configure strentgh for FPGA */ - writel(ACFG_DSCR10_VAL, &system->dscr10); - writel(ACFG_DSCR3_VAL, &system->dscr3); - writel(ACFG_DSCR7_VAL, &system->dscr7); - writel(ACFG_DSCR2_VAL, &system->dscr2); -} - -/* - * Initialize the fpga. Return 1 on success, 0 on failure. - */ -void APF27_init_fpga(void) -{ - int i; - - apf27_fpga_setup(); - - fpga_init(); - - for (i = 0; i < CONFIG_FPGA_COUNT; i++) { - debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i); - fpga_add(fpga_xilinx, &fpga[i]); - } - - return; -} diff --git a/board/armadeus/apf27/fpga.h b/board/armadeus/apf27/fpga.h deleted file mode 100644 index d6394e976a85..000000000000 --- a/board/armadeus/apf27/fpga.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2002-2013 - * Eric Jarrige eric.jarrige@armadeus.org - * - * based on the files by - * Rich Ireland, Enterasys Networks, rireland@enterasys.com - * and - * Keith Outwater, keith_outwater@mvis.com - */ -extern void APF27_init_fpga(void); - -extern int fpga_pre_fn(int cookie); -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_cs_fn(int assert_cs, int flush, int cookie); -extern int fpga_init_fn(int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(int assert_write, int flush, int cookie); -extern int fpga_rdata_fn(unsigned char *data, int cookie); -extern int fpga_wdata_fn(unsigned char data, int flush, int cookie); -extern int fpga_abort_fn(int cookie); -extern int fpga_post_fn(int cookie); -extern int fpga_busy_fn(int cookie); diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S deleted file mode 100644 index 0991b7ddf499..000000000000 --- a/board/armadeus/apf27/lowlevel_init.S +++ /dev/null @@ -1,166 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Philippe Reynes tremyfr@yahoo.fr - */ - -#include <config.h> -#include <generated/asm-offsets.h> -#include <asm/macro.h> -#include <asm/arch/imx-regs.h> -#include "apf27.h" - - .macro init_aipi - /* - * setup AIPI1 and AIPI2 - */ - write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL - write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL - write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL - write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL - - /* Change SDRAM signal strengh */ - ldr r0, =GPCR - ldr r1, =ACFG_GPCR_VAL - ldr r5, [r0] - orr r5, r5, r1 - str r5, [r0] - - .endm /* init_aipi */ - - .macro init_clock - ldr r0, =CSCR - /* disable MPLL/SPLL first */ - ldr r1, [r0] - bic r1, r1, #(CSCR_MPEN|CSCR_SPEN) - str r1, [r0] - - /* - * pll clock initialization predefined in apf27.h - */ - write32 MPCTL0, ACFG_MPCTL0_VAL - write32 SPCTL0, ACFG_SPCTL0_VAL - - write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART - - /* - * add some delay here - */ - mov r1, #0x1000 - 1: subs r1, r1, #0x1 - bne 1b - - /* peripheral clock divider */ - write32 PCDR0, ACFG_PCDR0_VAL - write32 PCDR1, ACFG_PCDR1_VAL - - /* Configure PCCR0 and PCCR1 */ - write32 PCCR0, ACFG_PCCR0_VAL - write32 PCCR1, ACFG_PCCR1_VAL - - .endm /* init_clock */ - - .macro init_ddr - /* wait for SDRAM/LPDDR ready (SDRAMRDY) */ - ldr r0, =IMX_ESD_BASE - ldr r4, =ESDMISC_SDRAM_RDY -2: ldr r1, [r0, #ESDMISC_ROF] - ands r1, r1, r4 - bpl 2b - - /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */ - ldr r0, =IMX_ESD_BASE - ldr r4, =ACFG_ESDMISC_VAL - orr r1, r4, #ESDMISC_MDDR_DL_RST - str r1, [r0, #ESDMISC_ROF] - - /* Hold for more than 200ns */ - ldr r1, =0x10000 -1: subs r1, r1, #0x1 - bne 1b - - str r4, [r0] - - ldr r0, =IMX_ESD_BASE - ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL - str r1, [r0, #ESDCFG0_ROF] - - ldr r0, =IMX_ESD_BASE - ldr r1, =ACFG_PRECHARGE_CMD - str r1, [r0, #ESDCTL0_ROF] - - /* write8(0xA0001000, any value) */ - ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL - strb r2, [r1] - - ldr r1, =ACFG_AUTOREFRESH_CMD - str r1, [r0, #ESDCTL0_ROF] - - ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */ - - ldr r6,=0x7 /* load loop counter */ -1: str r5,[r4] /* run auto-refresh cycle to array 0 */ - subs r6,r6,#1 - bne 1b - - ldr r1, =ACFG_SET_MODE_REG_CMD - str r1, [r0, #ESDCTL0_ROF] - - /* set standard mode register */ - ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL - strb r2, [r4] - - /* set extended mode register */ - ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL - strb r5, [r4] - - ldr r1, =ACFG_NORMAL_RW_CMD - str r1, [r0, #ESDCTL0_ROF] - - /* 2nd sdram */ - ldr r0, =IMX_ESD_BASE - ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL - str r1, [r0, #ESDCFG1_ROF] - - ldr r0, =IMX_ESD_BASE - ldr r1, =ACFG_PRECHARGE_CMD - str r1, [r0, #ESDCTL1_ROF] - - /* write8(0xB0001000, any value) */ - ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL - strb r2, [r1] - - ldr r1, =ACFG_AUTOREFRESH_CMD - str r1, [r0, #ESDCTL1_ROF] - - ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */ - - ldr r6,=0x7 /* load loop counter */ -1: str r5,[r4] /* run auto-refresh cycle to array 0 */ - subs r6,r6,#1 - bne 1b - - ldr r1, =ACFG_SET_MODE_REG_CMD - str r1, [r0, #ESDCTL1_ROF] - - /* set standard mode register */ - ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL - strb r2, [r4] - - /* set extended mode register */ - ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL - strb r2, [r4] - - ldr r1, =ACFG_NORMAL_RW_CMD - str r1, [r0, #ESDCTL1_ROF] - .endm /* init_ddr */ - -.globl lowlevel_init -lowlevel_init: - - init_aipi - init_clock -#ifdef CONFIG_SPL_BUILD - init_ddr -#endif - - mov pc, lr diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig deleted file mode 100644 index edb8c2b47732..000000000000 --- a/configs/apf27_defconfig +++ /dev/null @@ -1,59 +0,0 @@ -CONFIG_ARM=y -# CONFIG_SPL_USE_ARCH_MEMCPY is not set -CONFIG_TARGET_APF27=y -CONFIG_SYS_TEXT_BASE=0xA0000800 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_TEXT_BASE=0xA0000000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x180000 -CONFIG_IDENT_STRING=" apf27 patch 3.10" -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_BOOTDELAY=5 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySMX0,115200 mtdparts=mxc_nand.0:1M(u-boot)ro,512K(env),512K(env2),512K(firmware),512K(dtb),5M(kernel),-(rootfs) ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs " -CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="run check_flash check_env;" -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="BIOS> " -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_NAND_LOCK_UNLOCK=y -CONFIG_CMD_DHCP=y -CONFIG_BOOTP_DNS2=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DNS=y -CONFIG_CMD_BSP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand.0:1M(u-boot)ro,512K(env),512K(env2),512K(firmware),512K(dtb),5M(kernel),-(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_SPARTAN3=y -CONFIG_MXC_GPIO=y -CONFIG_MMC_MXC=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXC=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_OF_LIBFDT=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 79ad0a1b3435..404cc6b7d703 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -635,7 +635,7 @@ config MCFUART
config MXC_UART bool "IMX serial port support" - depends on ARCH_MX25 || ARCH_MX31 || TARGET_APF27 || TARGET_FLEA3 \ + depends on ARCH_MX25 || ARCH_MX31 || TARGET_FLEA3 \ || MX5 || MX6 || MX7 || IMX8M help If you have a machine based on a Motorola IMX CPU you diff --git a/include/configs/apf27.h b/include/configs/apf27.h deleted file mode 100644 index b69e5772a68e..000000000000 --- a/include/configs/apf27.h +++ /dev/null @@ -1,266 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * Configuration settings for the Armadeus Project motherboard APF27 - * - * Copyright (C) 2008-2013 Eric Jarrige eric.jarrige@armadeus.org - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -#define CONFIG_ENV_VERSION 10 -#define CONFIG_BOARD_NAME apf27 - -/* - * SoC configurations - */ -#define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */ -#define CONFIG_MACH_TYPE 1698 /* APF27 */ - -/* - * Enable the call to miscellaneous platform dependent initialization. - */ - -/* - * SPL - */ -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_MAX_SIZE 2048 - -/* NAND boot config */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_HOSTNAME "apf27" -#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" - -/* - * Memory configurations - */ -#define CONFIG_NR_DRAM_POPULATED 1 - -#define ACFG_SDRAM_MBYTE_SYZE 64 - -#define PHYS_SDRAM_1 0xA0000000 -#define PHYS_SDRAM_2 0xB0000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ - + PHYS_SDRAM_1_SIZE - 0x0100000) - -/* - * FLASH organization - */ -#define ACFG_MONITOR_OFFSET 0x00000000 -#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */ -#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */ -#define CONFIG_FIRMWARE_OFFSET 0x00200000 -#define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */ -#define CONFIG_KERNEL_OFFSET 0x00300000 -#define CONFIG_ROOTFS_OFFSET 0x00800000 - -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ - -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ -#define CONFIG_INITRD_TAG /* send initrd params */ - -#define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin" - -#define ACFG_CONSOLE_DEV ttySMX0 -#define CONFIG_BOOTCOMMAND "run ubifsboot" -#define CONFIG_SYS_AUTOLOAD "no" -/* - * Default load address for user programs and kernel - */ -#define CONFIG_LOADADDR 0xA0000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * Extra Environments - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ - "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "partition=nand0,6\0" \ - "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \ - "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \ - "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \ - "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \ - "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \ - "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \ - "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ - "kernel_addr_r=A0000000\0" \ - "check_env=if test -n ${flash_env_version}; " \ - "then env default env_version; " \ - "else env set flash_env_version ${env_version}; env save; "\ - "fi; " \ - "if itest ${flash_env_version} < ${env_version}; then " \ - "echo "*** Warning - Environment version" \ - " change suggests: run flash_reset_env; reset"; "\ - "env default flash_reset_env; "\ - "fi; \0" \ - "check_flash=nand lock; nand unlock ${env_addr}; \0" \ - "flash_reset_env=env default -f -a; saveenv; run update_env;" \ - "echo Flash environment variables erased!\0" \ - "download_uboot=tftpboot ${loadaddr} ${board_name}" \ - "-u-boot-with-spl.bin\0" \ - "flash_uboot=nand unlock ${u-boot_addr} ;" \ - "nand erase.part u-boot;" \ - "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\ - "then nand lock; nand unlock ${env_addr};" \ - "echo Flashing of uboot succeed;" \ - "else echo Flashing of uboot failed;" \ - "fi; \0" \ - "update_uboot=run download_uboot flash_uboot\0" \ - "download_env=tftpboot ${loadaddr} ${board_name}" \ - "-u-boot-env.txt\0" \ - "flash_env=env import -t ${loadaddr}; env save; \0" \ - "update_env=run download_env flash_env\0" \ - "update_all=run update_env update_uboot\0" \ - "unlock_regs=mw 10000008 0; mw 10020008 0\0" \ - -/* - * Serial Driver - */ -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* - * NOR - */ - -/* - * NAND - */ - -#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000 -#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE -#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 11 -#define NAND_MAX_CHIPS 1 - -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_NAND_QUIET 1 - -/* - * Partitions & Filsystems - */ - -/* - * Ethernet (on SOC imx FEC) - */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x1f - -/* - * FPGA - */ -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ -#define CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_SYS_FPGA_CHECK_CTRLC -#define CONFIG_SYS_FPGA_CHECK_ERROR - -/* - * Fuses - IIM - */ -#ifdef CONFIG_CMD_IMX_FUSE -#define IIM_MAC_BANK 0 -#define IIM_MAC_ROW 5 -#define IIM0_SCC_KEY 11 -#define IIM1_SUID 1 -#endif - -/* - * I2C - */ - -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F -#define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES { } - -#ifdef CONFIG_CMD_EEPROM -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */ -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */ -#endif /* CONFIG_CMD_EEPROM */ -#endif /* CONFIG_CMD_I2C */ - -/* - * SD/MMC - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MXC_MCI_REGS_BASE 0x10014000 -#endif - -/* - * RTC - */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1374 -#define CONFIG_SYS_RTC_BUS_NUM 0 -#endif /* CONFIG_CMD_DATE */ - -/* - * PLL - * - * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0 - * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------| - */ -#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */ - -#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ -/* micron 64MB */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ -#endif - -#if (ACFG_SDRAM_MBYTE_SYZE == 128) -/* micron 128MB */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ -#endif - -#if (ACFG_SDRAM_MBYTE_SYZE == 256) -/* micron 256MB */ -#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ -#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */ -#endif - -#endif /* __CONFIG_H */
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Fabio Estevam fabio.estevam@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-imx/mx2/Kconfig | 7 - board/freescale/mx25pdk/Kconfig | 15 -- board/freescale/mx25pdk/MAINTAINERS | 6 - board/freescale/mx25pdk/Makefile | 7 - board/freescale/mx25pdk/imximage.cfg | 64 --------- board/freescale/mx25pdk/mx25pdk.c | 198 --------------------------- configs/mx25pdk_defconfig | 31 ----- include/configs/mx25pdk.h | 178 ------------------------ 8 files changed, 506 deletions(-) delete mode 100644 board/freescale/mx25pdk/Kconfig delete mode 100644 board/freescale/mx25pdk/MAINTAINERS delete mode 100644 board/freescale/mx25pdk/Makefile delete mode 100644 board/freescale/mx25pdk/imximage.cfg delete mode 100644 board/freescale/mx25pdk/mx25pdk.c delete mode 100644 configs/mx25pdk_defconfig delete mode 100644 include/configs/mx25pdk.h
diff --git a/arch/arm/mach-imx/mx2/Kconfig b/arch/arm/mach-imx/mx2/Kconfig index 30a331ae43b7..fad5dcc940aa 100644 --- a/arch/arm/mach-imx/mx2/Kconfig +++ b/arch/arm/mach-imx/mx2/Kconfig @@ -8,12 +8,6 @@ choice prompt "MX25 board select" optional
-config TARGET_MX25PDK - bool "Support mx25pdk" - select BOARD_LATE_INIT - select CPU_ARM926EJS - select BOARD_EARLY_INIT_F - config TARGET_ZMX25 bool "Support zmx25" select BOARD_LATE_INIT @@ -24,7 +18,6 @@ endchoice config SYS_SOC default "mx25"
-source "board/freescale/mx25pdk/Kconfig" source "board/syteco/zmx25/Kconfig"
endif diff --git a/board/freescale/mx25pdk/Kconfig b/board/freescale/mx25pdk/Kconfig deleted file mode 100644 index af06b4c827e1..000000000000 --- a/board/freescale/mx25pdk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX25PDK - -config SYS_BOARD - default "mx25pdk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx25" - -config SYS_CONFIG_NAME - default "mx25pdk" - -endif diff --git a/board/freescale/mx25pdk/MAINTAINERS b/board/freescale/mx25pdk/MAINTAINERS deleted file mode 100644 index fa4651e2dfbc..000000000000 --- a/board/freescale/mx25pdk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX25PDK BOARD -M: Fabio Estevam fabio.estevam@nxp.com -S: Maintained -F: board/freescale/mx25pdk/ -F: include/configs/mx25pdk.h -F: configs/mx25pdk_defconfig diff --git a/board/freescale/mx25pdk/Makefile b/board/freescale/mx25pdk/Makefile deleted file mode 100644 index d3697d3f5f09..000000000000 --- a/board/freescale/mx25pdk/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. - -obj-y := mx25pdk.o diff --git a/board/freescale/mx25pdk/imximage.cfg b/board/freescale/mx25pdk/imximage.cfg deleted file mode 100644 index 762ccd0ab3fb..000000000000 --- a/board/freescale/mx25pdk/imximage.cfg +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Stefano Babic DENX Software Engineering sbabic@denx.de. - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -/* EIM config-CS5 init -- CPLD */ -DATA 4 0xB8002050 0x0000D843 -DATA 4 0xB8002054 0x22252521 -DATA 4 0xB8002058 0x22220A00 - -/* DDR2 init */ -DATA 4 0xB8001004 0x0076E83A -DATA 4 0xB8001010 0x00000204 -DATA 4 0xB8001000 0x92210000 -DATA 4 0x80000f00 0x12344321 -DATA 4 0xB8001000 0xB2210000 -DATA 1 0x82000000 0xda -DATA 1 0x83000000 0xda -DATA 1 0x81000400 0xda -DATA 1 0x80000333 0xda - -DATA 4 0xB8001000 0x92210000 -DATA 1 0x80000400 0x12345678 - -DATA 4 0xB8001000 0xA2210000 -DATA 4 0x80000000 0x87654321 -DATA 4 0x80000000 0x87654321 - -DATA 4 0xB8001000 0xB2210000 -DATA 1 0x80000233 0xda -DATA 1 0x81000780 0xda -DATA 1 0x81000400 0xda -DATA 4 0xB8001000 0x82216080 -DATA 4 0x43FAC454 0x00001000 - -DATA 4 0x53F80008 0x20034000 - -/* Enable the clocks */ -DATA 4 0x53f8000c 0x1fffffff -DATA 4 0x53f80010 0xffffffff -DATA 4 0x53f80014 0xfdfff diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c deleted file mode 100644 index 1cffdd933172..000000000000 --- a/board/freescale/mx25pdk/mx25pdk.c +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam fabio.estevam@freescale.com - */ - -#include <common.h> -#include <init.h> -#include <asm/io.h> -#include <asm/gpio.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx25.h> -#include <asm/arch/clock.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <i2c.h> -#include <linux/delay.h> -#include <power/pmic.h> -#include <fsl_pmic.h> -#include <mc34704.h> - -#define FEC_RESET_B IMX_GPIO_NR(4, 8) -#define FEC_ENABLE_B IMX_GPIO_NR(2, 3) -#define CARD_DETECT IMX_GPIO_NR(2, 1) - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {IMX_MMC_SDHC1_BASE}, -}; -#endif - -/* - * FIXME: need to revisit this - * The original code enabled PUE and 100-k pull-down without PKE, so the right - * value here is likely: - * 0 for no pull - * or: - * PAD_CTL_PUS_100K_DOWN for 100-k pull-down - */ -#define FEC_OUT_PAD_CTRL 0 - -#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_ODE) - -static void mx25pdk_fec_init(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX25_PAD_FEC_RX_DV__FEC_RX_DV, - MX25_PAD_FEC_RDATA0__FEC_RDATA0, - NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL), - MX25_PAD_FEC_MDIO__FEC_MDIO, - MX25_PAD_FEC_RDATA1__FEC_RDATA1, - NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL), - - NEW_PAD_CTRL(MX25_PAD_D12__GPIO_4_8, 0), /* FEC_RESET_B */ - NEW_PAD_CTRL(MX25_PAD_A17__GPIO_2_3, 0), /* FEC_ENABLE_B */ - }; - - static const iomux_v3_cfg_t i2c_pads[] = { - NEW_PAD_CTRL(MX25_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); - - /* Assert RESET and ENABLE low */ - gpio_direction_output(FEC_RESET_B, 0); - gpio_direction_output(FEC_ENABLE_B, 0); - - udelay(10); - - /* Deassert RESET and ENABLE */ - gpio_set_value(FEC_RESET_B, 1); - gpio_set_value(FEC_ENABLE_B, 1); - - /* Setup I2C pins so that PMIC can turn on PHY supply */ - imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); -} - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -/* - * Set up input pins with hysteresis and 100-k pull-ups - */ -#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP) -/* - * FIXME: need to revisit this - * The original code enabled PUE and 100-k pull-down without PKE, so the right - * value here is likely: - * 0 for no pull - * or: - * PAD_CTL_PUS_100K_DOWN for 100-k pull-down - */ -#define UART1_OUT_PAD_CTRL 0 - -static void mx25pdk_uart1_init(void) -{ - static const iomux_v3_cfg_t uart1_pads[] = { - NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -int board_early_init_f(void) -{ - mx25pdk_uart1_init(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int board_late_init(void) -{ - struct pmic *p; - int ret; - - mx25pdk_fec_init(); - - ret = pmic_init(I2C_0); - if (ret) - return ret; - - p = pmic_get("FSL_PMIC"); - if (!p) - return -ENODEV; - - /* Turn on Ethernet PHY and LCD supplies */ - pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE | ONOFFA); - - return 0; -} - -#ifdef CONFIG_FSL_ESDHC_IMX -int board_mmc_getcd(struct mmc *mmc) -{ - /* Set up the Card Detect pin. */ - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_A15__GPIO_2_1, 0)); - - gpio_direction_input(CARD_DETECT); - return !gpio_get_value(CARD_DETECT); -} - -int board_mmc_init(struct bd_info *bis) -{ - static const iomux_v3_cfg_t sdhc1_pads[] = { - NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); - - /* - * Set the eSDHC1 PER clock to the maximum frequency lower than or equal - * to 50 MHz that can be obtained, which requires to use UPLL as the - * clock source. This actually gives 48 MHz. - */ - imx_set_perclk(MXC_ESDHC1_CLK, true, 50000000); - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} -#endif - -int checkboard(void) -{ - puts("Board: MX25PDK\n"); - - return 0; -} - -/* Lowlevel init isn't used on mx25pdk, so just provide a dummy one here */ -void lowlevel_init(void) {} diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig deleted file mode 100644 index 58d42444b37f..000000000000 --- a/configs/mx25pdk_defconfig +++ /dev/null @@ -1,31 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX25=y -CONFIG_SYS_TEXT_BASE=0x81200000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 -CONFIG_TARGET_MX25PDK=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg" -CONFIG_DEFAULT_FDT_FILE="imx25-pdk.dtb" -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_FUSE=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC_IMX=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_FS_EXT4=y -CONFIG_FS_FAT=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h deleted file mode 100644 index 27d0c25ac733..000000000000 --- a/include/configs/mx25pdk.h +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - -/* High Level Configuration Options */ - -#define CONFIG_SYS_TEXT_BASE 0x81200000 -#define CONFIG_SYS_FSL_CLK - -#define CONFIG_SYS_TIMER_RATE 32768 -#define CONFIG_SYS_TIMER_COUNTER \ - (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_MACH_TYPE MACH_TYPE_MX25_3DS - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -/* Physical Memory Map */ - -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IMX_RAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE IMX_RAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Memory Test */ - -/* Serial Info */ -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* No NOR flash present */ - -/* U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x1f - -/* ESDHC driver */ -#define CONFIG_SYS_FSL_ESDHC_ADDR IMX_MMC_SDHC1_BASE -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -/* PMIC Configs */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_FSL -#define CONFIG_POWER_FSL_MC34704 -#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54 - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ - -/* RTC */ -#define CONFIG_RTC_IMXDI - -/* Fuse API support */ -#define CONFIG_FSL_IIM - -/* Ethernet Configs */ - - -#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "splashpos=m,m\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x82000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "update_sd_firmware_filename=u-boot.imx\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Miscellaneous configurable options */ - -#endif /* __CONFIG_H */
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Stefan Roese sr@denx.de Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/dts/Makefile | 3 - arch/arm/dts/kirkwood-openrd-base.dts | 39 ------ arch/arm/dts/kirkwood-openrd-client.dts | 73 ---------- arch/arm/dts/kirkwood-openrd-ultimate.dts | 55 -------- arch/arm/dts/kirkwood-openrd.dtsi | 122 ---------------- arch/arm/mach-kirkwood/Kconfig | 4 - board/Marvell/openrd/Kconfig | 12 -- board/Marvell/openrd/MAINTAINERS | 8 -- board/Marvell/openrd/Makefile | 12 -- board/Marvell/openrd/kwbimage.cfg | 150 -------------------- board/Marvell/openrd/openrd.c | 162 ---------------------- board/Marvell/openrd/openrd.h | 29 ---- configs/openrd_base_defconfig | 49 ------- configs/openrd_client_defconfig | 49 ------- configs/openrd_ultimate_defconfig | 49 ------- include/configs/openrd.h | 82 ----------- 16 files changed, 898 deletions(-) delete mode 100644 arch/arm/dts/kirkwood-openrd-base.dts delete mode 100644 arch/arm/dts/kirkwood-openrd-client.dts delete mode 100644 arch/arm/dts/kirkwood-openrd-ultimate.dts delete mode 100644 arch/arm/dts/kirkwood-openrd.dtsi delete mode 100644 board/Marvell/openrd/Kconfig delete mode 100644 board/Marvell/openrd/MAINTAINERS delete mode 100644 board/Marvell/openrd/Makefile delete mode 100644 board/Marvell/openrd/kwbimage.cfg delete mode 100644 board/Marvell/openrd/openrd.c delete mode 100644 board/Marvell/openrd/openrd.h delete mode 100644 configs/openrd_base_defconfig delete mode 100644 configs/openrd_client_defconfig delete mode 100644 configs/openrd_ultimate_defconfig delete mode 100644 include/configs/openrd.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index af2842a0f8bf..b8f88bca0af9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -58,9 +58,6 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += \ kirkwood-ns2lite.dtb \ kirkwood-ns2max.dtb \ kirkwood-ns2mini.dtb \ - kirkwood-openrd-base.dtb \ - kirkwood-openrd-client.dtb \ - kirkwood-openrd-ultimate.dtb \ kirkwood-pogo_e02.dtb \ kirkwood-sheevaplug.dtb
diff --git a/arch/arm/dts/kirkwood-openrd-base.dts b/arch/arm/dts/kirkwood-openrd-base.dts deleted file mode 100644 index 094191ece3d7..000000000000 --- a/arch/arm/dts/kirkwood-openrd-base.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Base Board Description - * - * Andrew Lunn andrew@lunn.ch - * - * This file contains the definitions that are specific to OpenRD - * base variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Base"; - compatible = "marvell,openrd-base", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - serial@12100 { - status = "okay"; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-openrd-client.dts b/arch/arm/dts/kirkwood-openrd-client.dts deleted file mode 100644 index 74dc23daf646..000000000000 --- a/arch/arm/dts/kirkwood-openrd-client.dts +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Client Board Description - * - * Andrew Lunn andrew@lunn.ch - * - * This file contains the definitions that are specific to OpenRD - * client variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Client"; - compatible = "marvell,openrd-client", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - audio-controller@a0000 { - status = "okay"; - }; - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - #sound-dai-cells = <0>; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&audio0 0>; - }; - - simple-audio-card,codec { - sound-dai = <&cs42l51>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; - ethphy1: ethernet-phy@24 { - reg = <24>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/dts/kirkwood-openrd-ultimate.dts b/arch/arm/dts/kirkwood-openrd-ultimate.dts deleted file mode 100644 index 888e13320c19..000000000000 --- a/arch/arm/dts/kirkwood-openrd-ultimate.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Ultimate Board Description - * - * Andrew Lunn andrew@lunn.ch - * - * This file contains the definitions that are specific to OpenRD - * ultimate variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Ultimate"; - compatible = "marvell,openrd-ultimate", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/dts/kirkwood-openrd.dtsi b/arch/arm/dts/kirkwood-openrd.dtsi deleted file mode 100644 index 47f03c69c55a..000000000000 --- a/arch/arm/dts/kirkwood-openrd.dtsi +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD (Base|Client|Ultimate) Board Description - * - * Andrew Lunn andrew@lunn.ch - * - * This file contains the definitions that are common between the three - * variants of the Marvell Kirkwood Development Board. - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>; - pinctrl-names = "default"; - - pmx_select28: pmx-select-rs232-rs485 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_select34: pmx-select-uart-sd { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - - }; - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - mvsdio@90000 { - status = "okay"; - cd-gpios = <&gpio0 29 9>; - }; - gpio@10100 { - p28 { - gpio-hog; - gpios = <28 GPIO_ACTIVE_HIGH>; - /* - * SelRS232or485 selects between RS-232 or RS-485 - * mode for the second UART. - * - * Low: RS-232 - * High: RS-485 - * - * To use the second UART, you need to change also - * the SelUARTorSD. - */ - output-low; - line-name = "SelRS232or485"; - }; - }; - gpio@10140 { - p2 { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - /* - * SelUARTorSD selects between the second UART - * (serial@12100) and SD (mvsdio@90000). - * - * Low: UART - * High: SD - * - * When changing this line make sure the newly - * selected device node is enabled and the - * previously selected device node is disabled. - */ - output-high; /* Select SD by default */ - line-name = "SelUARTorSD"; - }; - }; - }; -}; - -&nand { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@600000 { - label = "root"; - reg = <0x0600000 0x1FA00000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index ae44cb665e0b..6082bdb35b6c 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -4,9 +4,6 @@ choice prompt "Marvell Kirkwood board select" optional
-config TARGET_OPENRD - bool "Marvell OpenRD Board" - config TARGET_DREAMPLUG bool "DreamPlug Board"
@@ -70,7 +67,6 @@ endchoice config SYS_SOC default "kirkwood"
-source "board/Marvell/openrd/Kconfig" source "board/Marvell/dreamplug/Kconfig" source "board/Synology/ds109/Kconfig" source "board/Marvell/guruplug/Kconfig" diff --git a/board/Marvell/openrd/Kconfig b/board/Marvell/openrd/Kconfig deleted file mode 100644 index 124b66da0f13..000000000000 --- a/board/Marvell/openrd/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_OPENRD - -config SYS_BOARD - default "openrd" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "openrd" - -endif diff --git a/board/Marvell/openrd/MAINTAINERS b/board/Marvell/openrd/MAINTAINERS deleted file mode 100644 index 8170452b44aa..000000000000 --- a/board/Marvell/openrd/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -OPENRD / OPENRD_CLIENT BOARD -M: Stefan Roese sr@denx.de -S: Maintained -F: board/Marvell/openrd/ -F: include/configs/openrd.h -F: configs/openrd_base_defconfig -F: configs/openrd_client_defconfig -F: configs/openrd_ultimate_defconfig diff --git a/board/Marvell/openrd/Makefile b/board/Marvell/openrd/Makefile deleted file mode 100644 index ecebb421f703..000000000000 --- a/board/Marvell/openrd/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2009 -# Net Insight <www.netinsight.net> -# Written-by: Simon Kagstrom simon.kagstrom@netinsight.net -# -# Based on sheevaplug: -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com - -obj-y := openrd.o diff --git a/board/Marvell/openrd/kwbimage.cfg b/board/Marvell/openrd/kwbimage.cfg deleted file mode 100644 index 356fd46f933d..000000000000 --- a/board/Marvell/openrd/kwbimage.cfg +++ /dev/null @@ -1,150 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM nand -NAND_ECC_MODE default -NAND_PAGE_SIZE 0x0800 - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b1b9b - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register -# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x37543000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x000000cc # DDR Address Control -# bit1-0: 00, Cs0width=x8 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs1width=x8 -# bit7-6: 11, Cs1size=1Gb -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000C52 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000042 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 1, DDR drive strength reduced -# bit2: 0, DDR ODT control lsd (disabled) -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, (disabled) -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB) - -DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb -DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 - -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) -# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 -# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 -# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. -# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) - -DATA 0xFFD0149C 0x0000E40f # CPU ODT Control -# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 -# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm -# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm -# bit14: 1, M_STARTBURST_IN ODT: Enabled -# bit15: 1, DDR IO ODT Unit: Use ODT block -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c deleted file mode 100644 index d9b5b213feab..000000000000 --- a/board/Marvell/openrd/openrd.c +++ /dev/null @@ -1,162 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 - * Net Insight <www.netinsight.net> - * Written-by: Simon Kagstrom simon.kagstrom@netinsight.net - * - * Based on sheevaplug.c: - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#include <common.h> -#include <init.h> -#include <miiphy.h> -#include <net.h> -#include <asm/mach-types.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> -#include <asm/arch/mpp.h> -#include "openrd.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* - * default gpio configuration - * There are maximum 64 gpios controlled through 2 sets of registers - * the below configuration configures mainly initial LED status - */ - mvebu_config_gpio(OPENRD_OE_VAL_LOW, - OPENRD_OE_VAL_HIGH, - OPENRD_OE_LOW, OPENRD_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, - MPP13_SD_CMD, /* Alt UART1_TXD */ - MPP14_SD_D0, /* Alt UART1_RXD */ - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_GE1_0, - MPP21_GE1_1, - MPP22_GE1_2, - MPP23_GE1_3, - MPP24_GE1_4, - MPP25_GE1_5, - MPP26_GE1_6, - MPP27_GE1_7, - MPP28_GPIO, - MPP29_TSMP9, - MPP30_GE1_10, - MPP31_GE1_11, - MPP32_GE1_12, - MPP33_GE1_13, - MPP34_GPIO, /* UART1 / SD sel */ - MPP35_TDM_CH0_TX_QL, - MPP36_TDM_SPI_CS1, - MPP37_TDM_CH2_TX_QL, - MPP38_TDM_CH2_RX_QL, - MPP39_AUDIO_I2SBCLK, - MPP40_AUDIO_I2SDO, - MPP41_AUDIO_I2SLRC, - MPP42_AUDIO_I2SMCLK, - MPP43_AUDIO_I2SDI, - MPP44_AUDIO_EXTCLK, - MPP45_TDM_PCLK, - MPP46_TDM_FS, - MPP47_TDM_DRX, - MPP48_TDM_DTX, - MPP49_TDM_CH0_RX_QL, - 0 - }; - - kirkwood_mpp_conf(kwmpp_config, NULL); - return 0; -} - -int board_init(void) -{ - /* - * arch number of board - */ -#if defined(CONFIG_BOARD_IS_OPENRD_BASE) - gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; -#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT) - gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT; -#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) - gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE; -#endif - - /* adress of boot parameters */ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -/* Configure and enable MV88E1116/88E1121 PHY */ -void mv_phy_init(char *name) -{ - u16 reg; - u16 devadr; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { - printf("Err..%s could not read PHY dev address\n", __func__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); - - printf(PHY_NO" Initialized on %s\n", name); -} - -void reset_phy(void) -{ - mv_phy_init("egiga0"); - -#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT - /* Kirkwood ethernet driver is written with the assumption that in case - * of multiple PHYs, their addresses are consecutive. But unfortunately - * in case of OpenRD-Client, PHY addresses are not consecutive.*/ - miiphy_write("egiga1", 0xEE, 0xEE, 24); -#endif - -#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \ - defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) - /* configure and initialize both PHY's */ - mv_phy_init("egiga1"); -#endif -} -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/openrd/openrd.h b/board/Marvell/openrd/openrd.h deleted file mode 100644 index ade8d2739263..000000000000 --- a/board/Marvell/openrd/openrd.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Net Insight <www.netinsight.net> - * Written-by: Simon Kagstrom simon.kagstrom@netinsight.net - * - * Based on sheevaplug.h: - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#ifndef __OPENRD_BASE_H -#define __OPENRD_BASE_H - -#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */ -#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */ -#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */ -#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ - -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -#endif /* __OPENRD_BASE_H */ diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig deleted file mode 100644 index ebe22ab877d9..000000000000 --- a/configs/openrd_base_defconfig +++ /dev/null @@ -1,49 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_TARGET_OPENRD=y -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_IDENT_STRING="\nOpenRD-Base" -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-base" -CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -CONFIG_LOGLEVEL=2 -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_MVSATA_IDE=y -# CONFIG_MMC_HW_PARTITIONING is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig deleted file mode 100644 index 04fcea2d0d4f..000000000000 --- a/configs/openrd_client_defconfig +++ /dev/null @@ -1,49 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_TARGET_OPENRD=y -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_IDENT_STRING="\nOpenRD-Client" -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-client" -CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -CONFIG_LOGLEVEL=2 -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_MVSATA_IDE=y -# CONFIG_MMC_HW_PARTITIONING is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig deleted file mode 100644 index de7526dd7086..000000000000 --- a/configs/openrd_ultimate_defconfig +++ /dev/null @@ -1,49 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_TARGET_OPENRD=y -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_IDENT_STRING="\nOpenRD-Ultimate" -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-ultimate" -CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -CONFIG_LOGLEVEL=2 -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_MVSATA_IDE=y -# CONFIG_MMC_HW_PARTITIONING is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/include/configs/openrd.h b/include/configs/openrd.h deleted file mode 100644 index e9fd0fc749ba..000000000000 --- a/include/configs/openrd.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Net Insight <www.netinsight.net> - * Written-by: Simon Kagstrom simon.kagstrom@netinsight.net - * - * Based on sheevaplug.h: - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#ifndef _CONFIG_OPENRD_H -#define _CONFIG_OPENRD_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -#include "mv-common.h" - -/* - * Environment variables configurations - */ -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -/* - * Environment is right behind U-Boot in flash. Make sure U-Boot - * doesn't grow into the environment area. - */ -#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "${x_bootcmd_usb}; bootm 0x6400000;" - -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console=ttyS0,115200 " \ - CONFIG_MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -# ifdef CONFIG_BOARD_IS_OPENRD_BASE -# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -# else -# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -# endif -# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE -# define CONFIG_PHY_BASE_ADR 0x0 -# define PHY_NO "88E1121" -# else -# define CONFIG_PHY_BASE_ADR 0x8 -# define PHY_NO "88E1116" -# endif -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#ifdef CONFIG_CMD_MMC -#define CONFIG_MVEBU_MMC -#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE -#endif /* CONFIG_CMD_MMC */ - -#endif /* _CONFIG_OPENRD_BASE_H */
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Prafulla Wadaskar prafulla@marvell.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/kirkwood-sheevaplug-common.dtsi | 104 -------------- arch/arm/dts/kirkwood-sheevaplug.dts | 42 ------ arch/arm/mach-kirkwood/Kconfig | 4 - board/Marvell/sheevaplug/Kconfig | 12 -- board/Marvell/sheevaplug/MAINTAINERS | 6 - board/Marvell/sheevaplug/Makefile | 7 - board/Marvell/sheevaplug/kwbimage.cfg | 144 ------------------- board/Marvell/sheevaplug/sheevaplug.c | 135 ----------------- board/Marvell/sheevaplug/sheevaplug.h | 24 ---- configs/sheevaplug_defconfig | 55 ------- include/configs/sheevaplug.h | 73 ---------- 12 files changed, 1 insertion(+), 608 deletions(-) delete mode 100644 arch/arm/dts/kirkwood-sheevaplug-common.dtsi delete mode 100644 arch/arm/dts/kirkwood-sheevaplug.dts delete mode 100644 board/Marvell/sheevaplug/Kconfig delete mode 100644 board/Marvell/sheevaplug/MAINTAINERS delete mode 100644 board/Marvell/sheevaplug/Makefile delete mode 100644 board/Marvell/sheevaplug/kwbimage.cfg delete mode 100644 board/Marvell/sheevaplug/sheevaplug.c delete mode 100644 board/Marvell/sheevaplug/sheevaplug.h delete mode 100644 configs/sheevaplug_defconfig delete mode 100644 include/configs/sheevaplug.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b8f88bca0af9..12a74ed0eb08 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -58,8 +58,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += \ kirkwood-ns2lite.dtb \ kirkwood-ns2max.dtb \ kirkwood-ns2mini.dtb \ - kirkwood-pogo_e02.dtb \ - kirkwood-sheevaplug.dtb + kirkwood-pogo_e02.dtb
dtb-$(CONFIG_MACH_S900) += \ bubblegum_96.dtb diff --git a/arch/arm/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/dts/kirkwood-sheevaplug-common.dtsi deleted file mode 100644 index 0a698d3b7393..000000000000 --- a/arch/arm/dts/kirkwood-sheevaplug-common.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs - * - * Copyright (C) 2013 Simon Baatz gmbnomis@gmail.com - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_red: pmx-led-red { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_blue: pmx-led-blue { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_sdio_wp: pmx-sdio-wp { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 0>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "root"; - reg = <0x0500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-sheevaplug.dts b/arch/arm/dts/kirkwood-sheevaplug.dts deleted file mode 100644 index c73cc904e5c4..000000000000 --- a/arch/arm/dts/kirkwood-sheevaplug.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug - * - * Copyright (C) 2013 Simon Baatz gmbnomis@gmail.com - */ - -/dts-v1/; - -#include "kirkwood-sheevaplug-common.dtsi" - -/ { - model = "Globalscale Technologies SheevaPlug"; - compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_blue &pmx_led_red>; - pinctrl-names = "default"; - - health { - label = "sheevaplug:blue:health"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - misc { - label = "sheevaplug:red:misc"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 6082bdb35b6c..1d2ba886dd1a 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -13,9 +13,6 @@ config TARGET_DS109 config TARGET_GURUPLUG bool "GuruPlug Board"
-config TARGET_SHEEVAPLUG - bool "SheevaPlug Board" - config TARGET_LSXL bool "lsxl Board"
@@ -70,7 +67,6 @@ config SYS_SOC source "board/Marvell/dreamplug/Kconfig" source "board/Synology/ds109/Kconfig" source "board/Marvell/guruplug/Kconfig" -source "board/Marvell/sheevaplug/Kconfig" source "board/buffalo/lsxl/Kconfig" source "board/cloudengines/pogo_e02/Kconfig" source "board/d-link/dns325/Kconfig" diff --git a/board/Marvell/sheevaplug/Kconfig b/board/Marvell/sheevaplug/Kconfig deleted file mode 100644 index e5f928472994..000000000000 --- a/board/Marvell/sheevaplug/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SHEEVAPLUG - -config SYS_BOARD - default "sheevaplug" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "sheevaplug" - -endif diff --git a/board/Marvell/sheevaplug/MAINTAINERS b/board/Marvell/sheevaplug/MAINTAINERS deleted file mode 100644 index 2b0103d07dc9..000000000000 --- a/board/Marvell/sheevaplug/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SHEEVAPLUG BOARD -M: Prafulla Wadaskar prafulla@marvell.com -S: Maintained -F: board/Marvell/sheevaplug/ -F: include/configs/sheevaplug.h -F: configs/sheevaplug_defconfig diff --git a/board/Marvell/sheevaplug/Makefile b/board/Marvell/sheevaplug/Makefile deleted file mode 100644 index c39dd03e2d30..000000000000 --- a/board/Marvell/sheevaplug/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com - -obj-y := sheevaplug.o diff --git a/board/Marvell/sheevaplug/kwbimage.cfg b/board/Marvell/sheevaplug/kwbimage.cfg deleted file mode 100644 index f5206451da44..000000000000 --- a/board/Marvell/sheevaplug/kwbimage.cfg +++ /dev/null @@ -1,144 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com -# Refer to doc/README.kwbimage for more details about how-to -# configure and create kirkwood boot images. -# - -# Boot Media configurations -BOOT_FROM nand -NAND_ECC_MODE default -NAND_PAGE_SIZE 0x0800 - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b1b9b - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register -# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x37543000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x000000cc # DDR Address Control -# bit1-0: 00, Cs0width=x8 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs1width=x8 -# bit7-6: 11, Cs1size=1Gb -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000C52 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000040 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 0, DDR drive strenght normal -# bit2: 0, DDR ODT control lsd (disabled) -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, (disabled) -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB) - -DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb -DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 - -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 01, ODT1 active NEVER! -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000E803 # CPU ODT Control -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c deleted file mode 100644 index 6311ed3b2e59..000000000000 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#include <common.h> -#include <init.h> -#include <miiphy.h> -#include <net.h> -#include <asm/mach-types.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> -#include <asm/arch/mpp.h> -#include "sheevaplug.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* - * default gpio configuration - * There are maximum 64 gpios controlled through 2 sets of registers - * the below configuration configures mainly initial LED status - */ - mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW, - SHEEVAPLUG_OE_VAL_HIGH, - SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, - MPP8_UART0_RTS, - MPP9_UART0_CTS, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, - MPP13_SD_CMD, - MPP14_SD_D0, - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_GPIO, - MPP21_GPIO, - MPP22_GPIO, - MPP23_GPIO, - MPP24_GPIO, - MPP25_GPIO, - MPP26_GPIO, - MPP27_GPIO, - MPP28_GPIO, - MPP29_TSMP9, - MPP30_GPIO, - MPP31_GPIO, - MPP32_GPIO, - MPP33_GPIO, - MPP34_GPIO, - MPP35_GPIO, - MPP36_GPIO, - MPP37_GPIO, - MPP38_GPIO, - MPP39_GPIO, - MPP40_GPIO, - MPP41_GPIO, - MPP42_GPIO, - MPP43_GPIO, - MPP44_GPIO, - MPP45_GPIO, - MPP46_GPIO, - MPP47_GPIO, - MPP48_GPIO, - MPP49_GPIO, - 0 - }; - kirkwood_mpp_conf(kwmpp_config, NULL); - return 0; -} - -int board_init(void) -{ - /* - * arch number of board - */ - gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) -{ - u16 reg; - u16 devadr; - char *name = "egiga0"; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..%s could not read PHY dev address\n", - __FUNCTION__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); - - printf("88E1116 Initialized on %s\n", name); -} -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/sheevaplug/sheevaplug.h b/board/Marvell/sheevaplug/sheevaplug.h deleted file mode 100644 index e026c1b53bd0..000000000000 --- a/board/Marvell/sheevaplug/sheevaplug.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#ifndef __SHEEVAPLUG_H -#define __SHEEVAPLUG_H - -#define SHEEVAPLUG_OE_LOW (~(0)) -#define SHEEVAPLUG_OE_HIGH (~(0)) -#define SHEEVAPLUG_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ -#define SHEEVAPLUG_OE_VAL_HIGH (1 << 17) /* LED pin high */ - -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -#endif /* __SHEEVAPLUG_H */ diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig deleted file mode 100644 index 34da356b8e2a..000000000000 --- a/configs/sheevaplug_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_TARGET_SHEEVAPLUG=y -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_IDENT_STRING="\nMarvell-Sheevaplug" -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-sheevaplug" -# CONFIG_SYS_MALLOC_F is not set -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_NETCONSOLE=y -CONFIG_DM=y -CONFIG_MVSATA_IDE=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_DM_RTC=y -CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_LZMA=y -CONFIG_BZIP2=y diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h deleted file mode 100644 index e1f8fb8ac84b..000000000000 --- a/include/configs/sheevaplug.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009-2014 - * Gerald Kerma dreagle@doukki.net - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#ifndef _CONFIG_SHEEVAPLUG_H -#define _CONFIG_SHEEVAPLUG_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ - -#include "mv-plug-common.h" - -/* - * Environment variables configurations - */ -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -/* - * Environment is right behind U-Boot in flash. Make sure U-Boot - * doesn't grow into the environment area. - */ -#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "bootm 0x6400000;" - -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS_DEFAULT \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */ - -/* - * SDIO/MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MVEBU_MMC -#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE -#endif /* CONFIG_CMD_MMC */ - -/* - * SATA driver configuration - */ -#ifdef CONFIG_IDE -#define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT0 -#define CONFIG_MVSATA_IDE_USE_PORT1 -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /* CONFIG_IDE */ - -#endif /* _CONFIG_SHEEVAPLUG_H */
On Wed, 10 Feb 2021, 2:07 AM Tom Rini, trini@konsulko.com wrote:
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
We did get the odd bug report from debian for sheevaplug. They were reasonably popular with enthusiasts at one point. Personally I wouldn't miss this board but it might be worth a heads up (hence adding Vagrant C. to the Cc).
Cc: Prafulla Wadaskar prafulla@marvell.com Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/dts/Makefile | 3 +- arch/arm/dts/kirkwood-sheevaplug-common.dtsi | 104 -------------- arch/arm/dts/kirkwood-sheevaplug.dts | 42 ------ arch/arm/mach-kirkwood/Kconfig | 4 - board/Marvell/sheevaplug/Kconfig | 12 -- board/Marvell/sheevaplug/MAINTAINERS | 6 - board/Marvell/sheevaplug/Makefile | 7 - board/Marvell/sheevaplug/kwbimage.cfg | 144 ------------------- board/Marvell/sheevaplug/sheevaplug.c | 135 ----------------- board/Marvell/sheevaplug/sheevaplug.h | 24 ---- configs/sheevaplug_defconfig | 55 ------- include/configs/sheevaplug.h | 73 ---------- 12 files changed, 1 insertion(+), 608 deletions(-) delete mode 100644 arch/arm/dts/kirkwood-sheevaplug-common.dtsi delete mode 100644 arch/arm/dts/kirkwood-sheevaplug.dts delete mode 100644 board/Marvell/sheevaplug/Kconfig delete mode 100644 board/Marvell/sheevaplug/MAINTAINERS delete mode 100644 board/Marvell/sheevaplug/Makefile delete mode 100644 board/Marvell/sheevaplug/kwbimage.cfg delete mode 100644 board/Marvell/sheevaplug/sheevaplug.c delete mode 100644 board/Marvell/sheevaplug/sheevaplug.h delete mode 100644 configs/sheevaplug_defconfig delete mode 100644 include/configs/sheevaplug.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b8f88bca0af9..12a74ed0eb08 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -58,8 +58,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += \ kirkwood-ns2lite.dtb \ kirkwood-ns2max.dtb \ kirkwood-ns2mini.dtb \
kirkwood-pogo_e02.dtb \kirkwood-sheevaplug.dtb
kirkwood-pogo_e02.dtbdtb-$(CONFIG_MACH_S900) += \ bubblegum_96.dtb diff --git a/arch/arm/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/dts/kirkwood-sheevaplug-common.dtsi deleted file mode 100644 index 0a698d3b7393..000000000000 --- a/arch/arm/dts/kirkwood-sheevaplug-common.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/*
- kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs
- Copyright (C) 2013 Simon Baatz gmbnomis@gmail.com
- */
-#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi"
-/ {
memory {device_type = "memory";reg = <0x00000000 0x20000000>;};chosen {bootargs = "console=ttyS0,115200n8 earlyprintk";stdout-path = &uart0;};ocp@f1000000 {pinctrl: pin-controller@10000 {pmx_usb_power_enable: pmx-usb-power-enable {marvell,pins = "mpp29";marvell,function = "gpio";};pmx_led_red: pmx-led-red {marvell,pins = "mpp46";marvell,function = "gpio";};pmx_led_blue: pmx-led-blue {marvell,pins = "mpp49";marvell,function = "gpio";};pmx_sdio_cd: pmx-sdio-cd {marvell,pins = "mpp44";marvell,function = "gpio";};pmx_sdio_wp: pmx-sdio-wp {marvell,pins = "mpp47";marvell,function = "gpio";};};serial@12000 {status = "okay";};};regulators {compatible = "simple-bus";#address-cells = <1>;#size-cells = <0>;pinctrl-0 = <&pmx_usb_power_enable>;pinctrl-names = "default";usb_power: regulator@1 {compatible = "regulator-fixed";reg = <1>;regulator-name = "USB Power";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;enable-active-high;regulator-always-on;regulator-boot-on;gpio = <&gpio0 29 0>;};};-};
-&nand {
status = "okay";partition@0 {label = "u-boot";reg = <0x0000000 0x100000>;};partition@100000 {label = "uImage";reg = <0x0100000 0x400000>;};partition@500000 {label = "root";reg = <0x0500000 0x1fb00000>;};-};
-&mdio {
status = "okay";ethphy0: ethernet-phy@0 {reg = <0>;};-};
-ð0 {
status = "okay";ethernet0-port@0 {phy-handle = <ðphy0>;};-}; diff --git a/arch/arm/dts/kirkwood-sheevaplug.dts b/arch/arm/dts/kirkwood-sheevaplug.dts deleted file mode 100644 index c73cc904e5c4..000000000000 --- a/arch/arm/dts/kirkwood-sheevaplug.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/*
- kirkwood-sheevaplug.dts - Device tree file for Sheevaplug
- Copyright (C) 2013 Simon Baatz gmbnomis@gmail.com
- */
-/dts-v1/;
-#include "kirkwood-sheevaplug-common.dtsi"
-/ {
model = "Globalscale Technologies SheevaPlug";compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281","marvell,kirkwood";
ocp@f1000000 {mvsdio@90000 {pinctrl-0 = <&pmx_sdio>;pinctrl-names = "default";status = "okay";/* No CD or WP GPIOs */broken-cd;};};gpio-leds {compatible = "gpio-leds";pinctrl-0 = <&pmx_led_blue &pmx_led_red>;pinctrl-names = "default";health {label = "sheevaplug:blue:health";gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;default-state = "keep";};misc {label = "sheevaplug:red:misc";gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;};};-}; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 6082bdb35b6c..1d2ba886dd1a 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -13,9 +13,6 @@ config TARGET_DS109 config TARGET_GURUPLUG bool "GuruPlug Board"
-config TARGET_SHEEVAPLUG
bool "SheevaPlug Board"config TARGET_LSXL bool "lsxl Board"
@@ -70,7 +67,6 @@ config SYS_SOC source "board/Marvell/dreamplug/Kconfig" source "board/Synology/ds109/Kconfig" source "board/Marvell/guruplug/Kconfig" -source "board/Marvell/sheevaplug/Kconfig" source "board/buffalo/lsxl/Kconfig" source "board/cloudengines/pogo_e02/Kconfig" source "board/d-link/dns325/Kconfig" diff --git a/board/Marvell/sheevaplug/Kconfig b/board/Marvell/sheevaplug/Kconfig deleted file mode 100644 index e5f928472994..000000000000 --- a/board/Marvell/sheevaplug/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SHEEVAPLUG
-config SYS_BOARD
default "sheevaplug"-config SYS_VENDOR
default "Marvell"-config SYS_CONFIG_NAME
default "sheevaplug"-endif diff --git a/board/Marvell/sheevaplug/MAINTAINERS b/board/Marvell/sheevaplug/MAINTAINERS deleted file mode 100644 index 2b0103d07dc9..000000000000 --- a/board/Marvell/sheevaplug/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SHEEVAPLUG BOARD -M: Prafulla Wadaskar prafulla@marvell.com -S: Maintained -F: board/Marvell/sheevaplug/ -F: include/configs/sheevaplug.h -F: configs/sheevaplug_defconfig diff --git a/board/Marvell/sheevaplug/Makefile b/board/Marvell/sheevaplug/Makefile deleted file mode 100644 index c39dd03e2d30..000000000000 --- a/board/Marvell/sheevaplug/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com
-obj-y := sheevaplug.o diff --git a/board/Marvell/sheevaplug/kwbimage.cfg b/board/Marvell/sheevaplug/kwbimage.cfg deleted file mode 100644 index f5206451da44..000000000000 --- a/board/Marvell/sheevaplug/kwbimage.cfg +++ /dev/null @@ -1,144 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com -# Refer to doc/README.kwbimage for more details about how-to -# configure and create kirkwood boot images. -#
-# Boot Media configurations -BOOT_FROM nand -NAND_ECC_MODE default -NAND_PAGE_SIZE 0x0800
-# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b1b9b
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register -# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01
-DATA 0xFFD01404 0x37543000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP
-DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required
-DATA 0xFFD01410 0x000000cc # DDR Address Control -# bit1-0: 00, Cs0width=x8 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs1width=x8 -# bit7-6: 11, Cs1size=1Gb -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required
-DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required
-DATA 0xFFD0141C 0x00000C52 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required
-DATA 0xFFD01420 0x00000040 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 0, DDR drive strenght normal -# bit2: 0, DDR ODT control lsd (disabled) -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, (disabled) -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB)
-DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb -DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 01, ODT1 active NEVER! -# bit31-4: zero, required
-DATA 0xFFD0149C 0x0000E803 # CPU ODT Control -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write
-# End of Header extension -DATA 0x0 0x0 diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c deleted file mode 100644 index 6311ed3b2e59..000000000000 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- */
-#include <common.h> -#include <init.h> -#include <miiphy.h> -#include <net.h> -#include <asm/mach-types.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> -#include <asm/arch/mpp.h> -#include "sheevaplug.h"
-DECLARE_GLOBAL_DATA_PTR;
-int board_early_init_f(void) -{
/** default gpio configuration* There are maximum 64 gpios controlled through 2 sets ofregisters
* the below configuration configures mainly initial LED status*/mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,SHEEVAPLUG_OE_VAL_HIGH,SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);/* Multi-Purpose Pins Functionality configuration */static const u32 kwmpp_config[] = {MPP0_NF_IO2,MPP1_NF_IO3,MPP2_NF_IO4,MPP3_NF_IO5,MPP4_NF_IO6,MPP5_NF_IO7,MPP6_SYSRST_OUTn,MPP7_GPO,MPP8_UART0_RTS,MPP9_UART0_CTS,MPP10_UART0_TXD,MPP11_UART0_RXD,MPP12_SD_CLK,MPP13_SD_CMD,MPP14_SD_D0,MPP15_SD_D1,MPP16_SD_D2,MPP17_SD_D3,MPP18_NF_IO0,MPP19_NF_IO1,MPP20_GPIO,MPP21_GPIO,MPP22_GPIO,MPP23_GPIO,MPP24_GPIO,MPP25_GPIO,MPP26_GPIO,MPP27_GPIO,MPP28_GPIO,MPP29_TSMP9,MPP30_GPIO,MPP31_GPIO,MPP32_GPIO,MPP33_GPIO,MPP34_GPIO,MPP35_GPIO,MPP36_GPIO,MPP37_GPIO,MPP38_GPIO,MPP39_GPIO,MPP40_GPIO,MPP41_GPIO,MPP42_GPIO,MPP43_GPIO,MPP44_GPIO,MPP45_GPIO,MPP46_GPIO,MPP47_GPIO,MPP48_GPIO,MPP49_GPIO,0};kirkwood_mpp_conf(kwmpp_config, NULL);return 0;-}
-int board_init(void) -{
/** arch number of board*/gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;/* adress of boot parameters */gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;return 0;-}
-#ifdef CONFIG_RESET_PHY_R -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) -{
u16 reg;u16 devadr;char *name = "egiga0";if (miiphy_set_current_dev(name))return;/* command to read PHY dev address */if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {printf("Err..%s could not read PHY dev address\n",__FUNCTION__);return;}/** Enable RGMII delay on Tx and Rx for CPU port* Ref: sec 4.7.2 of chip datasheet*/miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);/* reset the phy */miiphy_reset(name, devadr);printf("88E1116 Initialized on %s\n", name);-} -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/sheevaplug/sheevaplug.h b/board/Marvell/sheevaplug/sheevaplug.h deleted file mode 100644 index e026c1b53bd0..000000000000 --- a/board/Marvell/sheevaplug/sheevaplug.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- */
-#ifndef __SHEEVAPLUG_H -#define __SHEEVAPLUG_H
-#define SHEEVAPLUG_OE_LOW (~(0)) -#define SHEEVAPLUG_OE_HIGH (~(0)) -#define SHEEVAPLUG_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ -#define SHEEVAPLUG_OE_VAL_HIGH (1 << 17) /* LED pin high */
-/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-#endif /* __SHEEVAPLUG_H */ diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig deleted file mode 100644 index 34da356b8e2a..000000000000 --- a/configs/sheevaplug_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_TARGET_SHEEVAPLUG=y -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_IDENT_STRING="\nMarvell-Sheevaplug" -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-sheevaplug" -# CONFIG_SYS_MALLOC_F is not set -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_NETCONSOLE=y -CONFIG_DM=y -CONFIG_MVSATA_IDE=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_DM_RTC=y -CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_LZMA=y -CONFIG_BZIP2=y diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h deleted file mode 100644 index e1f8fb8ac84b..000000000000 --- a/include/configs/sheevaplug.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- (C) Copyright 2009-2014
- Gerald Kerma dreagle@doukki.net
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- */
-#ifndef _CONFIG_SHEEVAPLUG_H -#define _CONFIG_SHEEVAPLUG_H
-/*
- High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#include "mv-plug-common.h"
-/*
- Environment variables configurations
- */
-/*
- max 4k env size is enough, but in case of nand
- it has to be rounded to sector size
- */
-/*
- Environment is right behind U-Boot in flash. Make sure U-Boot
- doesn't grow into the environment area.
- */
-#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
-/*
- Default environment variables
- */
-#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \"bootm 0x6400000;"-#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS_DEFAULT \"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \"x_bootcmd_usb=usb start\0" \"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"-/*
- Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */
-/*
- SDIO/MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC -#define CONFIG_MVEBU_MMC -#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE -#endif /* CONFIG_CMD_MMC */
-/*
- SATA driver configuration
- */
-#ifdef CONFIG_IDE -#define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT0 -#define CONFIG_MVSATA_IDE_USE_PORT1 -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /* CONFIG_IDE */
-#endif /* _CONFIG_SHEEVAPLUG_H */
2.17.1
If you decide to do this, please make sure you advertise it more widely than just this list.
I have a sheevaplug that I'd be sad to have to decommission. For the last decade, with never a complaint, it's been happily serving DHCP, DNS, and NTP to about 20 machines in my home network. I like it because the slightly unusual architecture makes it slightly less attractive as a target to the bad-guys out there.
Maybe I'll replace it with a Raspberry Pi.
Oh well: To everything there is a season...
Rick
On Tue, Feb 9, 2021, at 11:07 PM, Chris Packham wrote:
On Wed, 10 Feb 2021, 2:07 AM Tom Rini, trini@konsulko.com wrote:
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
We did get the odd bug report from debian for sheevaplug. They were reasonably popular with enthusiasts at one point. Personally I wouldn't miss this board but it might be worth a heads up (hence adding Vagrant C. to the Cc).
Cc: Prafulla Wadaskar prafulla@marvell.com Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/dts/Makefile | 3 +- arch/arm/dts/kirkwood-sheevaplug-common.dtsi | 104 -------------- arch/arm/dts/kirkwood-sheevaplug.dts | 42 ------ arch/arm/mach-kirkwood/Kconfig | 4 - board/Marvell/sheevaplug/Kconfig | 12 -- board/Marvell/sheevaplug/MAINTAINERS | 6 - board/Marvell/sheevaplug/Makefile | 7 - board/Marvell/sheevaplug/kwbimage.cfg | 144 ------------------- board/Marvell/sheevaplug/sheevaplug.c | 135 ----------------- board/Marvell/sheevaplug/sheevaplug.h | 24 ---- configs/sheevaplug_defconfig | 55 ------- include/configs/sheevaplug.h | 73 ---------- 12 files changed, 1 insertion(+), 608 deletions(-) delete mode 100644 arch/arm/dts/kirkwood-sheevaplug-common.dtsi delete mode 100644 arch/arm/dts/kirkwood-sheevaplug.dts delete mode 100644 board/Marvell/sheevaplug/Kconfig delete mode 100644 board/Marvell/sheevaplug/MAINTAINERS delete mode 100644 board/Marvell/sheevaplug/Makefile delete mode 100644 board/Marvell/sheevaplug/kwbimage.cfg delete mode 100644 board/Marvell/sheevaplug/sheevaplug.c delete mode 100644 board/Marvell/sheevaplug/sheevaplug.h delete mode 100644 configs/sheevaplug_defconfig delete mode 100644 include/configs/sheevaplug.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b8f88bca0af9..12a74ed0eb08 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -58,8 +58,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += \ kirkwood-ns2lite.dtb \ kirkwood-ns2max.dtb \ kirkwood-ns2mini.dtb \
kirkwood-pogo_e02.dtb \kirkwood-sheevaplug.dtb
kirkwood-pogo_e02.dtbdtb-$(CONFIG_MACH_S900) += \ bubblegum_96.dtb diff --git a/arch/arm/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/dts/kirkwood-sheevaplug-common.dtsi deleted file mode 100644 index 0a698d3b7393..000000000000 --- a/arch/arm/dts/kirkwood-sheevaplug-common.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/*
- kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs
- Copyright (C) 2013 Simon Baatz gmbnomis@gmail.com
- */
-#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi"
-/ {
memory {device_type = "memory";reg = <0x00000000 0x20000000>;};chosen {bootargs = "console=ttyS0,115200n8 earlyprintk";stdout-path = &uart0;};ocp@f1000000 {pinctrl: pin-controller@10000 {pmx_usb_power_enable: pmx-usb-power-enable {marvell,pins = "mpp29";marvell,function = "gpio";};pmx_led_red: pmx-led-red {marvell,pins = "mpp46";marvell,function = "gpio";};pmx_led_blue: pmx-led-blue {marvell,pins = "mpp49";marvell,function = "gpio";};pmx_sdio_cd: pmx-sdio-cd {marvell,pins = "mpp44";marvell,function = "gpio";};pmx_sdio_wp: pmx-sdio-wp {marvell,pins = "mpp47";marvell,function = "gpio";};};serial@12000 {status = "okay";};};regulators {compatible = "simple-bus";#address-cells = <1>;#size-cells = <0>;pinctrl-0 = <&pmx_usb_power_enable>;pinctrl-names = "default";usb_power: regulator@1 {compatible = "regulator-fixed";reg = <1>;regulator-name = "USB Power";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;enable-active-high;regulator-always-on;regulator-boot-on;gpio = <&gpio0 29 0>;};};-};
-&nand {
status = "okay";partition@0 {label = "u-boot";reg = <0x0000000 0x100000>;};partition@100000 {label = "uImage";reg = <0x0100000 0x400000>;};partition@500000 {label = "root";reg = <0x0500000 0x1fb00000>;};-};
-&mdio {
status = "okay";ethphy0: ethernet-phy@0 {reg = <0>;};-};
-ð0 {
status = "okay";ethernet0-port@0 {phy-handle = <ðphy0>;};-}; diff --git a/arch/arm/dts/kirkwood-sheevaplug.dts b/arch/arm/dts/kirkwood-sheevaplug.dts deleted file mode 100644 index c73cc904e5c4..000000000000 --- a/arch/arm/dts/kirkwood-sheevaplug.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/*
- kirkwood-sheevaplug.dts - Device tree file for Sheevaplug
- Copyright (C) 2013 Simon Baatz gmbnomis@gmail.com
- */
-/dts-v1/;
-#include "kirkwood-sheevaplug-common.dtsi"
-/ {
model = "Globalscale Technologies SheevaPlug";compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281","marvell,kirkwood";
ocp@f1000000 {mvsdio@90000 {pinctrl-0 = <&pmx_sdio>;pinctrl-names = "default";status = "okay";/* No CD or WP GPIOs */broken-cd;};};gpio-leds {compatible = "gpio-leds";pinctrl-0 = <&pmx_led_blue &pmx_led_red>;pinctrl-names = "default";health {label = "sheevaplug:blue:health";gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;default-state = "keep";};misc {label = "sheevaplug:red:misc";gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;};};-}; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 6082bdb35b6c..1d2ba886dd1a 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -13,9 +13,6 @@ config TARGET_DS109 config TARGET_GURUPLUG bool "GuruPlug Board"
-config TARGET_SHEEVAPLUG
bool "SheevaPlug Board"config TARGET_LSXL bool "lsxl Board"
@@ -70,7 +67,6 @@ config SYS_SOC source "board/Marvell/dreamplug/Kconfig" source "board/Synology/ds109/Kconfig" source "board/Marvell/guruplug/Kconfig" -source "board/Marvell/sheevaplug/Kconfig" source "board/buffalo/lsxl/Kconfig" source "board/cloudengines/pogo_e02/Kconfig" source "board/d-link/dns325/Kconfig" diff --git a/board/Marvell/sheevaplug/Kconfig b/board/Marvell/sheevaplug/Kconfig deleted file mode 100644 index e5f928472994..000000000000 --- a/board/Marvell/sheevaplug/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SHEEVAPLUG
-config SYS_BOARD
default "sheevaplug"-config SYS_VENDOR
default "Marvell"-config SYS_CONFIG_NAME
default "sheevaplug"-endif diff --git a/board/Marvell/sheevaplug/MAINTAINERS b/board/Marvell/sheevaplug/MAINTAINERS deleted file mode 100644 index 2b0103d07dc9..000000000000 --- a/board/Marvell/sheevaplug/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SHEEVAPLUG BOARD -M: Prafulla Wadaskar prafulla@marvell.com -S: Maintained -F: board/Marvell/sheevaplug/ -F: include/configs/sheevaplug.h -F: configs/sheevaplug_defconfig diff --git a/board/Marvell/sheevaplug/Makefile b/board/Marvell/sheevaplug/Makefile deleted file mode 100644 index c39dd03e2d30..000000000000 --- a/board/Marvell/sheevaplug/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com
-obj-y := sheevaplug.o diff --git a/board/Marvell/sheevaplug/kwbimage.cfg b/board/Marvell/sheevaplug/kwbimage.cfg deleted file mode 100644 index f5206451da44..000000000000 --- a/board/Marvell/sheevaplug/kwbimage.cfg +++ /dev/null @@ -1,144 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com -# Refer to doc/README.kwbimage for more details about how-to -# configure and create kirkwood boot images. -#
-# Boot Media configurations -BOOT_FROM nand -NAND_ECC_MODE default -NAND_PAGE_SIZE 0x0800
-# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b1b9b
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register -# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01
-DATA 0xFFD01404 0x37543000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP
-DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required
-DATA 0xFFD01410 0x000000cc # DDR Address Control -# bit1-0: 00, Cs0width=x8 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs1width=x8 -# bit7-6: 11, Cs1size=1Gb -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required
-DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required
-DATA 0xFFD0141C 0x00000C52 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required
-DATA 0xFFD01420 0x00000040 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 0, DDR drive strenght normal -# bit2: 0, DDR ODT control lsd (disabled) -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, (disabled) -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB)
-DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb -DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 01, ODT1 active NEVER! -# bit31-4: zero, required
-DATA 0xFFD0149C 0x0000E803 # CPU ODT Control -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write
-# End of Header extension -DATA 0x0 0x0 diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c deleted file mode 100644 index 6311ed3b2e59..000000000000 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- */
-#include <common.h> -#include <init.h> -#include <miiphy.h> -#include <net.h> -#include <asm/mach-types.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> -#include <asm/arch/mpp.h> -#include "sheevaplug.h"
-DECLARE_GLOBAL_DATA_PTR;
-int board_early_init_f(void) -{
/** default gpio configuration* There are maximum 64 gpios controlled through 2 sets ofregisters
* the below configuration configures mainly initial LED status*/mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,SHEEVAPLUG_OE_VAL_HIGH,SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);/* Multi-Purpose Pins Functionality configuration */static const u32 kwmpp_config[] = {MPP0_NF_IO2,MPP1_NF_IO3,MPP2_NF_IO4,MPP3_NF_IO5,MPP4_NF_IO6,MPP5_NF_IO7,MPP6_SYSRST_OUTn,MPP7_GPO,MPP8_UART0_RTS,MPP9_UART0_CTS,MPP10_UART0_TXD,MPP11_UART0_RXD,MPP12_SD_CLK,MPP13_SD_CMD,MPP14_SD_D0,MPP15_SD_D1,MPP16_SD_D2,MPP17_SD_D3,MPP18_NF_IO0,MPP19_NF_IO1,MPP20_GPIO,MPP21_GPIO,MPP22_GPIO,MPP23_GPIO,MPP24_GPIO,MPP25_GPIO,MPP26_GPIO,MPP27_GPIO,MPP28_GPIO,MPP29_TSMP9,MPP30_GPIO,MPP31_GPIO,MPP32_GPIO,MPP33_GPIO,MPP34_GPIO,MPP35_GPIO,MPP36_GPIO,MPP37_GPIO,MPP38_GPIO,MPP39_GPIO,MPP40_GPIO,MPP41_GPIO,MPP42_GPIO,MPP43_GPIO,MPP44_GPIO,MPP45_GPIO,MPP46_GPIO,MPP47_GPIO,MPP48_GPIO,MPP49_GPIO,0};kirkwood_mpp_conf(kwmpp_config, NULL);return 0;-}
-int board_init(void) -{
/** arch number of board*/gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;/* adress of boot parameters */gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;return 0;-}
-#ifdef CONFIG_RESET_PHY_R -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) -{
u16 reg;u16 devadr;char *name = "egiga0";if (miiphy_set_current_dev(name))return;/* command to read PHY dev address */if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {printf("Err..%s could not read PHY dev address\n",__FUNCTION__);return;}/** Enable RGMII delay on Tx and Rx for CPU port* Ref: sec 4.7.2 of chip datasheet*/miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);/* reset the phy */miiphy_reset(name, devadr);printf("88E1116 Initialized on %s\n", name);-} -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/sheevaplug/sheevaplug.h b/board/Marvell/sheevaplug/sheevaplug.h deleted file mode 100644 index e026c1b53bd0..000000000000 --- a/board/Marvell/sheevaplug/sheevaplug.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- */
-#ifndef __SHEEVAPLUG_H -#define __SHEEVAPLUG_H
-#define SHEEVAPLUG_OE_LOW (~(0)) -#define SHEEVAPLUG_OE_HIGH (~(0)) -#define SHEEVAPLUG_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ -#define SHEEVAPLUG_OE_VAL_HIGH (1 << 17) /* LED pin high */
-/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-#endif /* __SHEEVAPLUG_H */ diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig deleted file mode 100644 index 34da356b8e2a..000000000000 --- a/configs/sheevaplug_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_TARGET_SHEEVAPLUG=y -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_IDENT_STRING="\nMarvell-Sheevaplug" -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-sheevaplug" -# CONFIG_SYS_MALLOC_F is not set -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_NETCONSOLE=y -CONFIG_DM=y -CONFIG_MVSATA_IDE=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_DM_RTC=y -CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_LZMA=y -CONFIG_BZIP2=y diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h deleted file mode 100644 index e1f8fb8ac84b..000000000000 --- a/include/configs/sheevaplug.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- (C) Copyright 2009-2014
- Gerald Kerma dreagle@doukki.net
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- */
-#ifndef _CONFIG_SHEEVAPLUG_H -#define _CONFIG_SHEEVAPLUG_H
-/*
- High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#include "mv-plug-common.h"
-/*
- Environment variables configurations
- */
-/*
- max 4k env size is enough, but in case of nand
- it has to be rounded to sector size
- */
-/*
- Environment is right behind U-Boot in flash. Make sure U-Boot
- doesn't grow into the environment area.
- */
-#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
-/*
- Default environment variables
- */
-#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \"bootm 0x6400000;"-#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS_DEFAULT \"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \"x_bootcmd_usb=usb start\0" \"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"-/*
- Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */
-/*
- SDIO/MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC -#define CONFIG_MVEBU_MMC -#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE -#endif /* CONFIG_CMD_MMC */
-/*
- SATA driver configuration
- */
-#ifdef CONFIG_IDE -#define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT0 -#define CONFIG_MVSATA_IDE_USE_PORT1 -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /* CONFIG_IDE */
-#endif /* _CONFIG_SHEEVAPLUG_H */
2.17.1
On Wed, Feb 10, 2021 at 12:09:06PM -0800, Rick Thomas wrote:
If you decide to do this, please make sure you advertise it more widely than just this list.
I have a sheevaplug that I'd be sad to have to decommission. For the last decade, with never a complaint, it's been happily serving DHCP, DNS, and NTP to about 20 machines in my home network. I like it because the slightly unusual architecture makes it slightly less attractive as a target to the bad-guys out there.
Maybe I'll replace it with a Raspberry Pi.
I'm quite happy to keep the board, if someone will step up and maintain it. It's had the initial conversion to DM done, but it needs a number of others still. Almost all of the drivers it uses have been converted already (the IDE driver being the exception).
I assume that however you're building U-Boot the warnings that get printed about conversion deadlines having come and gone are hidden in some way or another.
On Wed, Feb 10, 2021, at 12:15 PM, Tom Rini wrote:
On Wed, Feb 10, 2021 at 12:09:06PM -0800, Rick Thomas wrote:
If you decide to do this, please make sure you advertise it more widely than just this list.
I have a sheevaplug that I'd be sad to have to decommission. For the last decade, with never a complaint, it's been happily serving DHCP, DNS, and NTP to about 20 machines in my home network. I like it because the slightly unusual architecture makes it slightly less attractive as a target to the bad-guys out there.
Maybe I'll replace it with a Raspberry Pi.
I'm quite happy to keep the board, if someone will step up and maintain it. It's had the initial conversion to DM done, but it needs a number of others still. Almost all of the drivers it uses have been converted already (the IDE driver being the exception).
I assume that however you're building U-Boot the warnings that get printed about conversion deadlines having come and gone are hidden in some way or another.
Sad to say, I don't have the skills to step up and maintain it myself. Though I'll be happy to participate in the effort as a willing (nay, eager) tester of new versions. I've got a second sheevaplug sitting on a shelf that somehow bricked itself about 5-7 years ago. I'd love to try to resurrect it, if somebody can point me to instructions for re-flashing the firmware. If I can get it running, it will be perfect for use as a testing machine.
Thanks! Rick
On Wed, Feb 10, 2021, at 12:15 PM, Tom Rini wrote:
I assume that however you're building U-Boot the warnings that get printed about conversion deadlines having come and gone are hidden in some way or another.
I used to have my sheevaplug's serial console hooked up to a nearby PC. But the PC died a year or so ago, so I don't have any way to watch the messages at boot time. If I need to reboot it, I just ssh to it, type "sudo shutdown -r now" and pray. It hasn't failed me yet (knock wood!). If it starts to fail, I'll have to find another PC to hook up the serial console to, but I figure I'll cross that bridge when I come to it.
Now, if anybody wanted me to test a new bit of software on it, I'd have some incentive.
Enjoy! Rick
On Wed, Feb 10, 2021 at 05:01:47PM -0800, Rick Thomas wrote:
On Wed, Feb 10, 2021, at 12:15 PM, Tom Rini wrote:
I assume that however you're building U-Boot the warnings that get printed about conversion deadlines having come and gone are hidden in some way or another.
I used to have my sheevaplug's serial console hooked up to a nearby PC. But the PC died a year or so ago, so I don't have any way to watch the messages at boot time. If I need to reboot it, I just ssh to it, type "sudo shutdown -r now" and pray. It hasn't failed me yet (knock wood!). If it starts to fail, I'll have to find another PC to hook up the serial console to, but I figure I'll cross that bridge when I come to it.
Now, if anybody wanted me to test a new bit of software on it, I'd have some incentive.
To be clear, have you been updating U-Boot on the device?
On Wed, Feb 10, 2021, at 5:55 PM, Tom Rini wrote:
On Wed, Feb 10, 2021 at 05:01:47PM -0800, Rick Thomas wrote:
On Wed, Feb 10, 2021, at 12:15 PM, Tom Rini wrote:
I assume that however you're building U-Boot the warnings that get printed about conversion deadlines having come and gone are hidden in some way or another.
I used to have my sheevaplug's serial console hooked up to a nearby PC. But the PC died a year or so ago, so I don't have any way to watch the messages at boot time. If I need to reboot it, I just ssh to it, type "sudo shutdown -r now" and pray. It hasn't failed me yet (knock wood!). If it starts to fail, I'll have to find another PC to hook up the serial console to, but I figure I'll cross that bridge when I come to it.
Now, if anybody wanted me to test a new bit of software on it, I'd have some incentive.
To be clear, have you been updating U-Boot on the device?
I'm not sure. If it helps, here's what aptitude thinks is installed:
rbthomas@sheeva:~$ aptitude versions u-boot i 2019.01+dfsg-7 stable 500
I have not recently (since before 2019) done anything more than allow aptitude to upgrade packages as it thinks best. In particular, I have not made any attempt to burn new firmware on the device.
Does that help? Rick
On 2021-02-10, Rick Thomas wrote:
On Wed, Feb 10, 2021, at 5:55 PM, Tom Rini wrote:
On Wed, Feb 10, 2021 at 05:01:47PM -0800, Rick Thomas wrote:
On Wed, Feb 10, 2021, at 12:15 PM, Tom Rini wrote:
I assume that however you're building U-Boot the warnings that get printed about conversion deadlines having come and gone are hidden in some way or another.
I definitely see some warnings in the build logs, but try to get other people to help with testing and maintaining them in Debian and for most boards there is someone listed who has offered to test new versions:
https://salsa.debian.org/debian/u-boot/-/blob/master/debian/targets
Unfortunately, mostly I only have evidence of boards I and a few other people have tested:
https://wiki.debian.org/U-boot/Status
If you use Debian and want the u-boot package to work for your favorite platform working the next release, it would be a really good time to test the packaged u-boot in Debian bullseye Real Soon Now. :)
I used to have my sheevaplug's serial console hooked up to a nearby PC. But the PC died a year or so ago, so I don't have any way to watch the messages at boot time. If I need to reboot it, I just ssh to it, type "sudo shutdown -r now" and pray. It hasn't failed me yet (knock wood!). If it starts to fail, I'll have to find another PC to hook up the serial console to, but I figure I'll cross that bridge when I come to it.
Now, if anybody wanted me to test a new bit of software on it, I'd have some incentive.
To be clear, have you been updating U-Boot on the device?
I'm not sure. If it helps, here's what aptitude thinks is installed:
rbthomas@sheeva:~$ aptitude versions u-boot i 2019.01+dfsg-7 stable 500
I have not recently (since before 2019) done anything more than allow aptitude to upgrade packages as it thinks best. In particular, I have not made any attempt to burn new firmware on the device.
The debian u-boot packages do not automatically upgrade the u-boot installed to the device; it requires manual intervention on the part of the system administrator above and beyond just upgrading the debian packages through apt, aptitude, etc.
I think u-boot upstream is talking about dropping it for 2021.04, so my guess is you would still have another entire debian release cycle with the available 2021.01 version of u-boot *if* that version still works...
live well, vagrant
On Wed, Feb 10, 2021, at 8:57 PM, Vagrant Cascadian wrote:
On 2021-02-10, Rick Thomas wrote:
I have not recently (since before 2019) done anything more than allow aptitude to upgrade packages as it thinks best. In particular, I have not made any attempt to burn new firmware on the device.
The debian u-boot packages do not automatically upgrade the u-boot installed to the device; it requires manual intervention on the part of the system administrator above and beyond just upgrading the debian packages through apt, aptitude, etc.
I think u-boot upstream is talking about dropping it for 2021.04, so my guess is you would still have another entire debian release cycle with the available 2021.01 version of u-boot *if* that version still works...
If you can point me to instructions for doing that manual intervention, I'll be happy to test whatever version you recommend, I hope the instructions also include how to recover if it *doesn't* work!
Enjoy! Rick
On Wed, Feb 10, 2021 at 09:09:56PM -0800, Rick Thomas wrote:
On Wed, Feb 10, 2021, at 8:57 PM, Vagrant Cascadian wrote:
On 2021-02-10, Rick Thomas wrote:
I have not recently (since before 2019) done anything more than allow aptitude to upgrade packages as it thinks best. In particular, I have not made any attempt to burn new firmware on the device.
The debian u-boot packages do not automatically upgrade the u-boot installed to the device; it requires manual intervention on the part of the system administrator above and beyond just upgrading the debian packages through apt, aptitude, etc.
I think u-boot upstream is talking about dropping it for 2021.04, so my guess is you would still have another entire debian release cycle with the available 2021.01 version of u-boot *if* that version still works...
If you can point me to instructions for doing that manual intervention, I'll be happy to test whatever version you recommend, I hope the instructions also include how to recover if it *doesn't* work!
I think this unfortunately gets to the heart of the problem. We need someone that cares about the platform to step up and do the maintenance. Most of the work shouldn't be too hard and there's examples of many previous conversions. The mvsata_ide driver is probably the hardest part but I think it just means that the ide_preinit() call needs to be worked in to the new ide_probe() function rather than the old ide_init().
On Thu, 2021-02-11 at 15:06 -0500, Tom Rini wrote:
On Wed, Feb 10, 2021 at 09:09:56PM -0800, Rick Thomas wrote:
On Wed, Feb 10, 2021, at 8:57 PM, Vagrant Cascadian wrote:
On 2021-02-10, Rick Thomas wrote:
I have not recently (since before 2019) done anything more than allow aptitude to upgrade packages as it thinks best. In particular, I have not made any attempt to burn new firmware on the device.
The debian u-boot packages do not automatically upgrade the u-boot installed to the device; it requires manual intervention on the part of the system administrator above and beyond just upgrading the debian packages through apt, aptitude, etc.
I think u-boot upstream is talking about dropping it for 2021.04, so my guess is you would still have another entire debian release cycle with the available 2021.01 version of u-boot *if* that version still works...
If you can point me to instructions for doing that manual intervention, I'll be happy to test whatever version you recommend, I hope the instructions also include how to recover if it *doesn't* work!
I think this unfortunately gets to the heart of the problem. We need someone that cares about the platform to step up and do the maintenance. Most of the work shouldn't be too hard and there's examples of many previous conversions. The mvsata_ide driver is probably the hardest part but I think it just means that the ide_preinit() call needs to be worked in to the new ide_probe() function rather than the old ide_init().
I have just converted the MMC driver (mmc_mvebu) to the driver model and that works on my Kirkwood based board (not a sheevaplug though). I'll run it through my GitLab CI and submit it to the mailing list soon.
Would MMC support be enough to keep this board in U-Boot? If I understand Tom correctly the only non-DM driver is the IDE driver. Would it be an option to keep the Sheevaplug board without IDE support (unless someone submits a driver)? I do not own a Sheevaplug and thus I am not familiar with it. I suppose it could also boot from MMC.
On Wed, Mar 24, 2021 at 09:11:01PM +0000, Harm Berntsen wrote:
On Thu, 2021-02-11 at 15:06 -0500, Tom Rini wrote:
On Wed, Feb 10, 2021 at 09:09:56PM -0800, Rick Thomas wrote:
On Wed, Feb 10, 2021, at 8:57 PM, Vagrant Cascadian wrote:
On 2021-02-10, Rick Thomas wrote:
I have not recently (since before 2019) done anything more than allow aptitude to upgrade packages as it thinks best. In particular, I have not made any attempt to burn new firmware on the device.
The debian u-boot packages do not automatically upgrade the u-boot installed to the device; it requires manual intervention on the part of the system administrator above and beyond just upgrading the debian packages through apt, aptitude, etc.
I think u-boot upstream is talking about dropping it for 2021.04, so my guess is you would still have another entire debian release cycle with the available 2021.01 version of u-boot *if* that version still works...
If you can point me to instructions for doing that manual intervention, I'll be happy to test whatever version you recommend, I hope the instructions also include how to recover if it *doesn't* work!
I think this unfortunately gets to the heart of the problem. We need someone that cares about the platform to step up and do the maintenance. Most of the work shouldn't be too hard and there's examples of many previous conversions. The mvsata_ide driver is probably the hardest part but I think it just means that the ide_preinit() call needs to be worked in to the new ide_probe() function rather than the old ide_init().
I have just converted the MMC driver (mmc_mvebu) to the driver model and that works on my Kirkwood based board (not a sheevaplug though). I'll run it through my GitLab CI and submit it to the mailing list soon.
Would MMC support be enough to keep this board in U-Boot? If I understand Tom correctly the only non-DM driver is the IDE driver. Would it be an option to keep the Sheevaplug board without IDE support (unless someone submits a driver)? I do not own a Sheevaplug and thus I am not familiar with it. I suppose it could also boot from MMC.
I would really like to see someone be active in maintaining the sheevaplug, especially given how popular it was among enthusiasts. But yes, if MMC is converted that does mean there's a viable path to keep using a modern U-Boot on the system and I'll just rip out the IDE driver until someone wants to convert that and test it. USB will also need to be converted soon too as I will start pulling out v2019.07 deadline items for after v2021.07 release and that's both the IDE and USB drivers. But maybe both can be easily disabled.
On Wed, 2021-03-24 at 17:22 -0400, Tom Rini wrote:
On Wed, Mar 24, 2021 at 09:11:01PM +0000, Harm Berntsen wrote:
On Thu, 2021-02-11 at 15:06 -0500, Tom Rini wrote:
On Wed, Feb 10, 2021 at 09:09:56PM -0800, Rick Thomas wrote:
On Wed, Feb 10, 2021, at 8:57 PM, Vagrant Cascadian wrote:
On 2021-02-10, Rick Thomas wrote:
I have not recently (since before 2019) done anything more than allow aptitude to upgrade packages as it thinks best. In particular, I have not made any attempt to burn new firmware on the device.
The debian u-boot packages do not automatically upgrade the u-boot installed to the device; it requires manual intervention on the part of the system administrator above and beyond just upgrading the debian packages through apt, aptitude, etc.
I think u-boot upstream is talking about dropping it for 2021.04, so my guess is you would still have another entire debian release cycle with the available 2021.01 version of u-boot *if* that version still works...
If you can point me to instructions for doing that manual intervention, I'll be happy to test whatever version you recommend, I hope the instructions also include how to recover if it *doesn't* work!
I think this unfortunately gets to the heart of the problem. We need someone that cares about the platform to step up and do the maintenance. Most of the work shouldn't be too hard and there's examples of many previous conversions. The mvsata_ide driver is probably the hardest part but I think it just means that the ide_preinit() call needs to be worked in to the new ide_probe() function rather than the old ide_init().
I have just converted the MMC driver (mmc_mvebu) to the driver model and that works on my Kirkwood based board (not a sheevaplug though). I'll run it through my GitLab CI and submit it to the mailing list soon.
Would MMC support be enough to keep this board in U-Boot? If I understand Tom correctly the only non-DM driver is the IDE driver. Would it be an option to keep the Sheevaplug board without IDE support (unless someone submits a driver)? I do not own a Sheevaplug and thus I am not familiar with it. I suppose it could also boot from MMC.
I would really like to see someone be active in maintaining the sheevaplug, especially given how popular it was among enthusiasts. But yes, if MMC is converted that does mean there's a viable path to keep using a modern U-Boot on the system and I'll just rip out the IDE driver until someone wants to convert that and test it. USB will also need to be converted soon too as I will start pulling out v2019.07 deadline items for after v2021.07 release and that's both the IDE and USB drivers. But maybe both can be easily disabled.
Great :). The sheevaplug currently already has driver-model based USB drivers in its defconfig. I just checked and confirmed that that driver still works on my (non-sheevaplug) Kirkwood board.
On Wed, Mar 24, 2021 at 09:54:06PM +0000, Harm Berntsen wrote:
On Wed, 2021-03-24 at 17:22 -0400, Tom Rini wrote:
On Wed, Mar 24, 2021 at 09:11:01PM +0000, Harm Berntsen wrote:
On Thu, 2021-02-11 at 15:06 -0500, Tom Rini wrote:
On Wed, Feb 10, 2021 at 09:09:56PM -0800, Rick Thomas wrote:
On Wed, Feb 10, 2021, at 8:57 PM, Vagrant Cascadian wrote:
On 2021-02-10, Rick Thomas wrote: > I have not recently (since before 2019) done anything more > than > allow > aptitude to upgrade packages as it thinks best. In > particular, I > have > not made any attempt to burn new firmware on the device.
The debian u-boot packages do not automatically upgrade the u-boot installed to the device; it requires manual intervention on the part of the system administrator above and beyond just upgrading the debian packages through apt, aptitude, etc.
I think u-boot upstream is talking about dropping it for 2021.04, so my guess is you would still have another entire debian release cycle with the available 2021.01 version of u-boot *if* that version still works...
If you can point me to instructions for doing that manual intervention, I'll be happy to test whatever version you recommend, I hope the instructions also include how to recover if it *doesn't* work!
I think this unfortunately gets to the heart of the problem. We need someone that cares about the platform to step up and do the maintenance. Most of the work shouldn't be too hard and there's examples of many previous conversions. The mvsata_ide driver is probably the hardest part but I think it just means that the ide_preinit() call needs to be worked in to the new ide_probe() function rather than the old ide_init().
I have just converted the MMC driver (mmc_mvebu) to the driver model and that works on my Kirkwood based board (not a sheevaplug though). I'll run it through my GitLab CI and submit it to the mailing list soon.
Would MMC support be enough to keep this board in U-Boot? If I understand Tom correctly the only non-DM driver is the IDE driver. Would it be an option to keep the Sheevaplug board without IDE support (unless someone submits a driver)? I do not own a Sheevaplug and thus I am not familiar with it. I suppose it could also boot from MMC.
I would really like to see someone be active in maintaining the sheevaplug, especially given how popular it was among enthusiasts. But yes, if MMC is converted that does mean there's a viable path to keep using a modern U-Boot on the system and I'll just rip out the IDE driver until someone wants to convert that and test it. USB will also need to be converted soon too as I will start pulling out v2019.07 deadline items for after v2021.07 release and that's both the IDE and USB drivers. But maybe both can be easily disabled.
Great :). The sheevaplug currently already has driver-model based USB drivers in its defconfig. I just checked and confirmed that that driver still works on my (non-sheevaplug) Kirkwood board.
Ah, I bet that means the "hard" part is that you can't have both DM_MMC/DM_USB and non-DM IDE at the same time without some build failure. So turning off IDE (and deleting the driver after) and then with the MMC conversion USB should just be switched over.
These boards have not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove them.
Cc: Linus Walleij linus.walleij@linaro.org Signed-off-by: Tom Rini trini@konsulko.com --- .azure-pipelines.yml | 6 - .gitlab-ci.yml | 14 - arch/arm/Kconfig | 18 - arch/arm/dts/Makefile | 4 - arch/arm/dts/vexpress-v2m-rs1.dtsi | 437 --------------- arch/arm/dts/vexpress-v2m.dtsi | 451 ---------------- arch/arm/dts/vexpress-v2p-ca15_a7.dts | 682 ------------------------ arch/arm/dts/vexpress-v2p-ca5s.dts | 280 ---------- arch/arm/dts/vexpress-v2p-ca9.dts | 368 ------------- board/armltd/vexpress/Kconfig | 38 -- board/armltd/vexpress/MAINTAINERS | 10 - board/armltd/vexpress/Makefile | 7 - board/armltd/vexpress/vexpress_common.c | 203 ------- board/armltd/vexpress/vexpress_tc2.c | 84 --- configs/vexpress_ca15_tc2_defconfig | 40 -- configs/vexpress_ca5x2_defconfig | 38 -- configs/vexpress_ca9x4_defconfig | 39 -- drivers/i2c/Kconfig | 2 +- include/configs/vexpress_ca15_tc2.h | 19 - include/configs/vexpress_ca5x2.h | 16 - include/configs/vexpress_ca9x4.h | 16 - 21 files changed, 1 insertion(+), 2771 deletions(-) delete mode 100644 arch/arm/dts/vexpress-v2m-rs1.dtsi delete mode 100644 arch/arm/dts/vexpress-v2m.dtsi delete mode 100644 arch/arm/dts/vexpress-v2p-ca15_a7.dts delete mode 100644 arch/arm/dts/vexpress-v2p-ca5s.dts delete mode 100644 arch/arm/dts/vexpress-v2p-ca9.dts delete mode 100644 board/armltd/vexpress/Kconfig delete mode 100644 board/armltd/vexpress/MAINTAINERS delete mode 100644 board/armltd/vexpress/Makefile delete mode 100644 board/armltd/vexpress/vexpress_common.c delete mode 100644 board/armltd/vexpress/vexpress_tc2.c delete mode 100644 configs/vexpress_ca15_tc2_defconfig delete mode 100644 configs/vexpress_ca5x2_defconfig delete mode 100644 configs/vexpress_ca9x4_defconfig delete mode 100644 include/configs/vexpress_ca15_tc2.h delete mode 100644 include/configs/vexpress_ca5x2.h delete mode 100644 include/configs/vexpress_ca9x4.h
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index a6279427e138..8a89a7959ee9 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -192,12 +192,6 @@ jobs: evb_ast2500: TEST_PY_BD: "evb-ast2500" TEST_PY_ID: "--id qemu" - vexpress_ca15_tc2: - TEST_PY_BD: "vexpress_ca15_tc2" - TEST_PY_ID: "--id qemu" - vexpress_ca9x4: - TEST_PY_BD: "vexpress_ca9x4" - TEST_PY_ID: "--id qemu" integratorcp_cm926ejs: TEST_PY_BD: "integratorcp_cm926ejs" TEST_PY_ID: "--id qemu" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2cdcd864c86a..8e18c3d8fbdd 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -217,20 +217,6 @@ sandbox_flattree test.py: TEST_PY_BD: "sandbox_flattree" <<: *buildman_and_testpy_dfn
-vexpress_ca15_tc2 test.py: - tags: [ 'all' ] - variables: - TEST_PY_BD: "vexpress_ca15_tc2" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - -vexpress_ca9x4 test.py: - tags: [ 'all' ] - variables: - TEST_PY_BD: "vexpress_ca9x4" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - integratorcp_cm926ejs test.py: tags: [ 'all' ] variables: diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index acffdc6a1ed8..2e75efe2da8e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -645,13 +645,6 @@ config ARCH_BCM6858 select OF_CONTROL imply CMD_DM
-config TARGET_VEXPRESS_CA15_TC2 - bool "Support vexpress_ca15_tc2" - select CPU_V7A - select CPU_V7_HAS_NONSEC - select CPU_V7_HAS_VIRT - select PL011_SERIAL - config ARCH_BCMSTB bool "Broadcom BCM7XXX family" select CPU_V7A @@ -663,16 +656,6 @@ config ARCH_BCMSTB This enables support for Broadcom ARM-based set-top box chipsets, including the 7445 family of chips.
-config TARGET_VEXPRESS_CA5X2 - bool "Support vexpress_ca5x2" - select CPU_V7A - select PL011_SERIAL - -config TARGET_VEXPRESS_CA9X4 - bool "Support vexpress_ca9x4" - select CPU_V7A - select PL011_SERIAL - config TARGET_BCM23550_W1D bool "Support bcm23550_w1d" select CPU_V7A @@ -1964,7 +1947,6 @@ source "board/Marvell/aspenite/Kconfig" source "board/Marvell/gplugd/Kconfig" source "board/Marvell/octeontx/Kconfig" source "board/Marvell/octeontx2/Kconfig" -source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" source "board/cortina/presidio-asic/Kconfig" source "board/broadcom/bcm23550_w1d/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 12a74ed0eb08..f0944b7590cf 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1009,10 +1009,6 @@ dtb-$(CONFIG_TARGET_GE_BX50V3) += \ dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
-dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb -dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb -dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb - dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb diff --git a/arch/arm/dts/vexpress-v2m-rs1.dtsi b/arch/arm/dts/vexpress-v2m-rs1.dtsi deleted file mode 100644 index d3963e9eaf48..000000000000 --- a/arch/arm/dts/vexpress-v2m-rs1.dtsi +++ /dev/null @@ -1,437 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * RS1 memory map ("ARM Cortex-A Series memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * original variant (vexpress-v2m.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m.dtsi! - */ - -/ { - smb@8000000 { - motherboard { - model = "V2M-P1"; - arm,hbi = <0x190>; - arm,vexpress,site = <0>; - arm,v2m-memory-map = "rs1"; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - }; - - psram@1,00000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <1 0x00000000 0x02000000>; - bank-width = <4>; - }; - - ethernet@2,02000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&v2m_fixed_3v3>; - vddvario-supply = <&v2m_fixed_3v3>; - }; - - usb@2,03000000 { - compatible = "nxp,usb-isp1761"; - reg = <2 0x03000000 0x20000>; - interrupts = <16>; - port1-otg; - }; - - iofpga@3,00000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysreg: sysreg@10000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10000 0x1000>; - - v2m_led_gpios: gpio@8 { - compatible = "arm,vexpress-sysreg,sys_led"; - reg = <0x008 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_mmc_gpios: gpio@48 { - compatible = "arm,vexpress-sysreg,sys_mci"; - reg = <0x048 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_flash_gpios: gpio@4c { - compatible = "arm,vexpress-sysreg,sys_flash"; - reg = <0x04c 4>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@30000 { - compatible = "arm,versatile-i2c"; - reg = <0x030000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@40000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <11>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - mmci@50000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <9>, <10>; - cd-gpios = <&v2m_mmc_gpios 0 0>; - wp-gpios = <&v2m_mmc_gpios 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@60000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@70000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: uart@90000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: uart@a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: uart@b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: uart@c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdogclk", "apb_pclk"; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@160000 { - compatible = "arm,versatile-i2c"; - reg = <0x160000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dvi_bridge_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - }; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <4>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - compact-flash@1a0000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a0000 0x100 - 0x1a0100 0xf00>; - reg-shift = <2>; - }; - - clcd@1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&smbclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 800x600 16bpp @36MHz works fine */ - max-memory-bandwidth = <54000000>; - memory-region = <&vram>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&dvi_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; - - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; - - user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - - user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/vexpress-v2m.dtsi b/arch/arm/dts/vexpress-v2m.dtsi deleted file mode 100644 index 798c97aff7fa..000000000000 --- a/arch/arm/dts/vexpress-v2m.dtsi +++ /dev/null @@ -1,451 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * Original memory map ("Legacy memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m-rs1.dtsi! - */ - -/ { - smb@4000000 { - motherboard { - model = "V2M-P1"; - arm,hbi = <0x190>; - arm,vexpress,site = <0>; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <1 0x00000000 0x04000000>; - bank-width = <4>; - }; - - psram@2,00000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <2 0x00000000 0x02000000>; - bank-width = <4>; - }; - - ethernet@3,02000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <3 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&v2m_fixed_3v3>; - vddvario-supply = <&v2m_fixed_3v3>; - }; - - usb@3,03000000 { - compatible = "nxp,usb-isp1761"; - reg = <3 0x03000000 0x20000>; - interrupts = <16>; - port1-otg; - }; - - iofpga@7,00000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 7 0 0x20000>; - - v2m_sysreg: sysreg@0 { - compatible = "arm,vexpress-sysreg"; - reg = <0x00000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - - v2m_led_gpios: gpio@8 { - compatible = "arm,vexpress-sysreg,sys_led"; - reg = <0x008 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_mmc_gpios: gpio@48 { - compatible = "arm,vexpress-sysreg,sys_mci"; - reg = <0x048 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_flash_gpios: gpio@4c { - compatible = "arm,vexpress-sysreg,sys_flash"; - reg = <0x04c 4>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - v2m_sysctl: sysctl@1000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x01000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@2000 { - compatible = "arm,versatile-i2c"; - reg = <0x02000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@4000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x04000 0x1000>; - interrupts = <11>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - mmci@5000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x05000 0x1000>; - interrupts = <9>, <10>; - cd-gpios = <&v2m_mmc_gpios 0 0>; - wp-gpios = <&v2m_mmc_gpios 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@6000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x06000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@7000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x07000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: uart@9000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x09000 0x1000>; - interrupts = <5>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: uart@a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a000 0x1000>; - interrupts = <6>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: uart@b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b000 0x1000>; - interrupts = <7>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: uart@c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c000 0x1000>; - interrupts = <8>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@f000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdogclk", "apb_pclk"; - }; - - v2m_timer01: timer@11000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x11000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@12000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@16000 { - compatible = "arm,versatile-i2c"; - reg = <0x16000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Both the core tile and the motherboard routes their output - * pads to this transmitter. The motherboard system controller - * can select one of them as input using a mux register in - * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is - * the only platform with this specific set-up. - */ - port@0 { - reg = <0>; - dvi_bridge_in_ct: endpoint { - remote-endpoint = <&clcd_pads_ct>; - }; - }; - port@1 { - reg = <1>; - dvi_bridge_in_mb: endpoint { - remote-endpoint = <&clcd_pads_mb>; - }; - }; - }; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@17000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x17000 0x1000>; - interrupts = <4>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - compact-flash@1a000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a000 0x100 - 0x1a100 0xf00>; - reg-shift = <2>; - }; - - - clcd@1f000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&smbclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 800x600 16bpp @36MHz works fine */ - max-memory-bandwidth = <54000000>; - memory-region = <&vram>; - - port { - clcd_pads_mb: endpoint { - remote-endpoint = <&dvi_bridge_in_mb>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; - - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; - - user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - - user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - }; - }; -}; \ No newline at end of file diff --git a/arch/arm/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/dts/vexpress-v2p-ca15_a7.dts deleted file mode 100644 index 00cd9f5bef2e..000000000000 --- a/arch/arm/dts/vexpress-v2p-ca15_a7.dts +++ /dev/null @@ -1,682 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A15x2 A7x3 - * Cortex-A15_A7 MPCore (V2P-CA15_A7) - * - * HBI-0249A - */ - -/dts-v1/; -#include "vexpress-v2m-rs1.dtsi" - -/ { - model = "V2P-CA15_CA7"; - arm,hbi = <0x249>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - cci-control-port = <&cci_control1>; - cpu-idle-states = <&CLUSTER_SLEEP_BIG>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <990>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - cci-control-port = <&cci_control1>; - cpu-idle-states = <&CLUSTER_SLEEP_BIG>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <990>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - capacity-dmips-mhz = <516>; - dynamic-power-coefficient = <133>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - capacity-dmips-mhz = <516>; - dynamic-power-coefficient = <133>; - }; - - cpu4: cpu@4 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - capacity-dmips-mhz = <516>; - dynamic-power-coefficient = <133>; - }; - - idle-states { - CLUSTER_SLEEP_BIG: cluster-sleep-big { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2000>; - }; - - CLUSTER_SLEEP_LITTLE: cluster-sleep-little { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <500>; - min-residency-us = <2500>; - }; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Chipselect 2 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0 0x18000000 0 0x00800000>; - no-map; - }; - }; - - wdt@2a490000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0 0x2a490000 0 0x1000>; - interrupts = <0 98 4>; - clocks = <&oscclk6a>, <&oscclk6a>; - clock-names = "wdogclk", "apb_pclk"; - }; - - hdlcd@2b000000 { - compatible = "arm,hdlcd"; - reg = <0 0x2b000000 0 0x1000>; - interrupts = <0 85 4>; - clocks = <&hdlcd_clk>; - clock-names = "pxlclk"; - }; - - memory-controller@2b0a0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0 0x2b0a0000 0 0x1000>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x2000>, - <0 0x2c004000 0 0x2000>, - <0 0x2c006000 0 0x2000>; - interrupts = <1 9 0xf04>; - }; - - cci@2c090000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x2c090000 0 0x1000>; - ranges = <0x0 0x0 0x2c090000 0x10000>; - - cci_control1: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control2: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r0"; - reg = <0x9000 0x5000>; - interrupts = <0 105 4>, - <0 101 4>, - <0 102 4>, - <0 103 4>, - <0 104 4>; - }; - }; - - memory-controller@7ffd0000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0 0x7ffd0000 0 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - dma@7ff00000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0 0x7ff00000 0 0x1000>; - interrupts = <0 92 4>, - <0 88 4>, - <0 89 4>, - <0 90 4>, - <0 91 4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - scc@7fff0000 { - compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; - reg = <0 0x7fff0000 0 0x1000>; - interrupts = <0 95 4>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - pmu-a15 { - compatible = "arm,cortex-a15-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - interrupt-affinity = <&cpu0>, - <&cpu1>; - }; - - pmu-a7 { - compatible = "arm,cortex-a7-pmu"; - interrupts = <0 128 4>, - <0 129 4>, - <0 130 4>; - interrupt-affinity = <&cpu2>, - <&cpu3>, - <&cpu4>; - }; - - oscclk6a: oscclk6a { - /* Reference 24MHz clock */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "oscclk6a"; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* A15 PLL 0 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk0"; - }; - - oscclk1 { - /* A15 PLL 1 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk1"; - }; - - oscclk2 { - /* A7 PLL 0 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk2"; - }; - - oscclk3 { - /* A7 PLL 1 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 3>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk3"; - }; - - oscclk4 { - /* External AXI master clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <20000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk4"; - }; - - hdlcd_clk: oscclk5 { - /* HDLCD PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 5>; - freq-range = <23750000 165000000>; - #clock-cells = <0>; - clock-output-names = "oscclk5"; - }; - - smbclk: oscclk6 { - /* Static memory controller clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 6>; - freq-range = <20000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk6"; - }; - - oscclk7 { - /* SYS PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 7>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk7"; - }; - - oscclk8 { - /* DDR2 PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 8>; - freq-range = <20000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk8"; - }; - - volt-a15 { - /* A15 CPU core voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "A15 Vcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - label = "A15 Vcore"; - }; - - volt-a7 { - /* A7 CPU core voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 1>; - regulator-name = "A7 Vcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - label = "A7 Vcore"; - }; - - amp-a15 { - /* Total current for the two A15 cores */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 0>; - label = "A15 Icore"; - }; - - amp-a7 { - /* Total current for the three A7 cores */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 1>; - label = "A7 Icore"; - }; - - temp-dcc { - /* DCC internal temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "DCC"; - }; - - power-a15 { - /* Total power for the two A15 cores */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 0>; - label = "A15 Pcore"; - }; - - power-a7 { - /* Total power for the three A7 cores */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 1>; - label = "A7 Pcore"; - }; - - energy-a15 { - /* Total energy for the two A15 cores */ - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 0>, <13 1>; - label = "A15 Jcore"; - }; - - energy-a7 { - /* Total energy for the three A7 cores */ - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 2>, <13 3>; - label = "A7 Jcore"; - }; - }; - - etb@20010000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0x20010000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - etb_in_port: endpoint { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - tpiu@20030000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0x20030000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - tpiu_in_port: endpoint { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - replicator { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&etb_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - }; - - in-ports { - port { - replicator_in_port0: endpoint { - remote-endpoint = <&funnel_out_port0>; - }; - }; - }; - }; - - funnel@20040000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0 0x20040000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel_out_port0: endpoint { - remote-endpoint = - <&replicator_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_in_port0: endpoint { - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel_in_port1: endpoint { - remote-endpoint = <&ptm1_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel_in_port2: endpoint { - remote-endpoint = <&etm0_out_port>; - }; - }; - - /* Input port #3 is for ITM, not supported here */ - - port@4 { - reg = <4>; - funnel_in_port4: endpoint { - remote-endpoint = <&etm1_out_port>; - }; - }; - - port@5 { - reg = <5>; - funnel_in_port5: endpoint { - remote-endpoint = <&etm2_out_port>; - }; - }; - }; - }; - - ptm@2201c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201c000 0 0x1000>; - - cpu = <&cpu0>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - }; - - ptm@2201d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201d000 0 0x1000>; - - cpu = <&cpu1>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port1>; - }; - }; - }; - }; - - etm@2203c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203c000 0 0x1000>; - - cpu = <&cpu2>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - etm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port2>; - }; - }; - }; - }; - - etm@2203d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203d000 0 0x1000>; - - cpu = <&cpu3>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - etm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port4>; - }; - }; - }; - }; - - etm@2203e000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203e000 0 0x1000>; - - cpu = <&cpu4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - etm2_out_port: endpoint { - remote-endpoint = <&funnel_in_port5>; - }; - }; - }; - }; - - smb: smb@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; - - site2: hsb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x3fef0000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/arch/arm/dts/vexpress-v2p-ca5s.dts b/arch/arm/dts/vexpress-v2p-ca5s.dts deleted file mode 100644 index d5b47d526f9e..000000000000 --- a/arch/arm/dts/vexpress-v2p-ca5s.dts +++ /dev/null @@ -1,280 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A5x2 - * Cortex-A5 MPCore (V2P-CA5s) - * - * HBI-0225B - */ - -/dts-v1/; -#include "vexpress-v2m-rs1.dtsi" - -/ { - model = "V2P-CA5s"; - arm,hbi = <0x225>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Chipselect 2 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0x18000000 0x00800000>; - no-map; - }; - }; - - hdlcd@2a110000 { - compatible = "arm,hdlcd"; - reg = <0x2a110000 0x1000>; - interrupts = <0 85 4>; - clocks = <&hdlcd_clk>; - clock-names = "pxlclk"; - }; - - memory-controller@2a150000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x2a150000 0x1000>; - clocks = <&axi_clk>; - clock-names = "apb_pclk"; - }; - - memory-controller@2a190000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x2a190000 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - clocks = <&axi_clk>; - clock-names = "apb_pclk"; - }; - - scu@2c000000 { - compatible = "arm,cortex-a5-scu"; - reg = <0x2c000000 0x58>; - }; - - timer@2c000600 { - compatible = "arm,cortex-a5-twd-timer"; - reg = <0x2c000600 0x20>; - interrupts = <1 13 0x304>; - }; - - timer@2c000200 { - compatible = "arm,cortex-a5-global-timer", - "arm,cortex-a9-global-timer"; - reg = <0x2c000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&cpu_clk>; - }; - - watchdog@2c000620 { - compatible = "arm,cortex-a5-twd-wdt"; - reg = <0x2c000620 0x20>; - interrupts = <1 14 0x304>; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c000100 0x100>; - }; - - L2: cache-controller@2c0f0000 { - compatible = "arm,pl310-cache"; - reg = <0x2c0f0000 0x1000>; - interrupts = <0 84 4>; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - cpu_clk: oscclk0 { - /* CPU and internal AXI reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <50000000 100000000>; - #clock-cells = <0>; - clock-output-names = "oscclk0"; - }; - - axi_clk: oscclk1 { - /* Multiplexed AXI master clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <5000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk1"; - }; - - oscclk2 { - /* DDR2 */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <80000000 120000000>; - #clock-cells = <0>; - clock-output-names = "oscclk2"; - }; - - hdlcd_clk: oscclk3 { - /* HDLCD */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 3>; - freq-range = <23750000 165000000>; - #clock-cells = <0>; - clock-output-names = "oscclk3"; - }; - - oscclk4 { - /* Test chip gate configuration */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <80000000 80000000>; - #clock-cells = <0>; - clock-output-names = "oscclk4"; - }; - - smbclk: oscclk5 { - /* SMB clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 5>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "oscclk5"; - }; - - temp-dcc { - /* DCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "DCC"; - }; - }; - - smb: smb@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x04000000>, - <1 0 0x14000000 0x04000000>, - <2 0 0x18000000 0x04000000>, - <3 0 0x1c000000 0x04000000>, - <4 0 0x0c000000 0x04000000>, - <5 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; - - site2: hsb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000000 0x40000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/arch/arm/dts/vexpress-v2p-ca9.dts b/arch/arm/dts/vexpress-v2p-ca9.dts deleted file mode 100644 index d796efaadbe3..000000000000 --- a/arch/arm/dts/vexpress-v2p-ca9.dts +++ /dev/null @@ -1,368 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A9x4 - * Cortex-A9 MPCore (V2P-CA9) - * - * HBI-0191B - */ - -/dts-v1/; -#include "vexpress-v2m.dtsi" - -/ { - model = "V2P-CA9"; - arm,hbi = <0x191>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - A9_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - }; - - A9_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&L2>; - }; - - A9_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&L2>; - }; - - A9_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Chipselect 3 is physically at 0x4c000000 */ - vram: vram@4c000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0x4c000000 0x00800000>; - no-map; - }; - }; - - clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-names = "combined"; - interrupts = <0 44 4>; - clocks = <&oscclk1>, <&oscclk2>; - clock-names = "clcdclk", "apb_pclk"; - /* 1024x768 16bpp @65MHz */ - max-memory-bandwidth = <95000000>; - - port { - clcd_pads_ct: endpoint { - remote-endpoint = <&dvi_bridge_in_ct>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - - memory-controller@100e0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x100e0000 0x1000>; - clocks = <&oscclk2>; - clock-names = "apb_pclk"; - }; - - memory-controller@100e1000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x100e1000 0x1000>; - interrupts = <0 45 4>, - <0 46 4>; - clocks = <&oscclk2>; - clock-names = "apb_pclk"; - }; - - timer@100e4000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x100e4000 0x1000>; - interrupts = <0 48 4>, - <0 49 4>; - clocks = <&oscclk2>, <&oscclk2>; - clock-names = "timclk", "apb_pclk"; - status = "disabled"; - }; - - watchdog@100e5000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x100e5000 0x1000>; - interrupts = <0 51 4>; - clocks = <&oscclk2>, <&oscclk2>; - clock-names = "wdogclk", "apb_pclk"; - }; - - scu@1e000000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1e000000 0x58>; - }; - - timer@1e000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1e000600 0x20>; - interrupts = <1 13 0xf04>; - }; - - watchdog@1e000620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x1e000620 0x20>; - interrupts = <1 14 0xf04>; - }; - - gic: interrupt-controller@1e001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1e001000 0x1000>, - <0x1e000100 0x100>; - }; - - L2: cache-controller@1e00a000 { - compatible = "arm,pl310-cache"; - reg = <0x1e00a000 0x1000>; - interrupts = <0 43 4>; - cache-unified; - cache-level = <2>; - arm,data-latency = <1 1 1>; - arm,tag-latency = <1 1 1>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; - interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; - - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0: extsaxiclk { - /* ACLK clock to the AXI master port on the test chip */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <30000000 50000000>; - #clock-cells = <0>; - clock-output-names = "extsaxiclk"; - }; - - oscclk1: clcdclk { - /* Reference clock for the CLCD */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <10000000 80000000>; - #clock-cells = <0>; - clock-output-names = "clcdclk"; - }; - - smbclk: oscclk2: tcrefclk { - /* Reference clock for the test chip internal PLLs */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <33000000 100000000>; - #clock-cells = <0>; - clock-output-names = "tcrefclk"; - }; - - volt-vd10 { - /* Test Chip internal logic voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VD10"; - regulator-always-on; - label = "VD10"; - }; - - volt-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 1>; - regulator-name = "VD10_S2"; - regulator-always-on; - label = "VD10_S2"; - }; - - volt-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 2>; - regulator-name = "VD10_S3"; - regulator-always-on; - label = "VD10_S3"; - }; - - volt-vcc1v8 { - /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 3>; - regulator-name = "VCC1V8"; - regulator-always-on; - label = "VCC1V8"; - }; - - volt-ddr2vtt { - /* DDR2 SDRAM VTT termination voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 4>; - regulator-name = "DDR2VTT"; - regulator-always-on; - label = "DDR2VTT"; - }; - - volt-vcc3v3 { - /* Local board supply for miscellaneous logic external to the Test Chip */ - arm,vexpress-sysreg,func = <2 5>; - compatible = "arm,vexpress-volt"; - regulator-name = "VCC3V3"; - regulator-always-on; - label = "VCC3V3"; - }; - - amp-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 0>; - label = "VD10_S2"; - }; - - amp-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 1>; - label = "VD10_S3"; - }; - - power-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 0>; - label = "PVD10_S2"; - }; - - power-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 1>; - label = "PVD10_S3"; - }; - }; - - smb: smb@4000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x04000000>, - <1 0 0x44000000 0x04000000>, - <2 0 0x48000000 0x04000000>, - <3 0 0x4c000000 0x04000000>, - <7 0 0x10000000 0x00020000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; - - site2: hsb@e0000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe0000000 0x20000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/board/armltd/vexpress/Kconfig b/board/armltd/vexpress/Kconfig deleted file mode 100644 index 2e15e0d4975f..000000000000 --- a/board/armltd/vexpress/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -if TARGET_VEXPRESS_CA15_TC2 - -config SYS_BOARD - default "vexpress" - -config SYS_VENDOR - default "armltd" - -config SYS_CONFIG_NAME - default "vexpress_ca15_tc2" - -endif - -if TARGET_VEXPRESS_CA5X2 - -config SYS_BOARD - default "vexpress" - -config SYS_VENDOR - default "armltd" - -config SYS_CONFIG_NAME - default "vexpress_ca5x2" - -endif - -if TARGET_VEXPRESS_CA9X4 - -config SYS_BOARD - default "vexpress" - -config SYS_VENDOR - default "armltd" - -config SYS_CONFIG_NAME - default "vexpress_ca9x4" - -endif diff --git a/board/armltd/vexpress/MAINTAINERS b/board/armltd/vexpress/MAINTAINERS deleted file mode 100644 index 7b3fb42e5651..000000000000 --- a/board/armltd/vexpress/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -VERSATILE EXPRESS BOARDS -M: Linus Walleij linus.walleij@linaro.org -S: Maintained -F: board/armltd/vexpress/ -F: include/configs/vexpress_ca15_tc2.h -F: configs/vexpress_ca15_tc2_defconfig -F: include/configs/vexpress_ca5x2.h -F: configs/vexpress_ca5x2_defconfig -F: include/configs/vexpress_ca9x4.h -F: configs/vexpress_ca9x4_defconfig diff --git a/board/armltd/vexpress/Makefile b/board/armltd/vexpress/Makefile deleted file mode 100644 index 2a659de012ac..000000000000 --- a/board/armltd/vexpress/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y := vexpress_common.o -obj-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress_tc2.o diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c deleted file mode 100644 index 8fea8ff35294..000000000000 --- a/board/armltd/vexpress/vexpress_common.c +++ /dev/null @@ -1,203 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * (C) Copyright 2003 - * Texas Instruments, <www.ti.com> - * Kshitij Gupta Kshitij@ti.com - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, philippe.robin@arm.com - */ -#include <common.h> -#include <bootstage.h> -#include <cpu_func.h> -#include <init.h> -#include <malloc.h> -#include <errno.h> -#include <net.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/mach-types.h> -#include <asm/arch/systimer.h> -#include <asm/arch/sysctrl.h> -#include <asm/arch/wdt.h> -#include "../drivers/mmc/arm_pl180_mmci.h" - -static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01; -static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE; - -static void flash__init(void); -static void vexpress_timer_init(void); -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_SHOW_BOOT_PROGRESS) -void show_boot_progress(int progress) -{ - printf("Boot reached stage %d\n", progress); -} -#endif - -static inline void delay(ulong loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b" : "=r" (loops) : "0" (loops)); -} - -int board_init(void) -{ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS; - - icache_enable(); - flash__init(); - vexpress_timer_init(); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} - -int cpu_mmc_init(struct bd_info *bis) -{ - int rc = 0; - (void) bis; -#ifdef CONFIG_ARM_PL180_MMCI - struct pl180_mmc_host *host; - struct mmc *mmc; - - host = malloc(sizeof(struct pl180_mmc_host)); - if (!host) - return -ENOMEM; - memset(host, 0, sizeof(*host)); - - strcpy(host->name, "MMC"); - host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; - host->pwr_init = INIT_PWR; - host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN; - host->voltages = VOLTAGE_WINDOW_MMC; - host->caps = 0; - host->clock_in = ARM_MCLK; - host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1)); - host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ; - rc = arm_pl180_mmci_init(host, &mmc); -#endif - return rc; -} - -static void flash__init(void) -{ - /* Setup the sytem control register to allow writing to flash */ - writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN, - &sysctrl_base->scflashctrl); -} - -int dram_init(void) -{ - gd->ram_size = - get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = - get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - return 0; -} - -/* - * Start timer: - * Setup a 32 bit timer, running at 1KHz - * Versatile Express Motherboard provides 1 MHz timer - */ -static void vexpress_timer_init(void) -{ - /* - * Set clock frequency in system controller: - * VEXPRESS_REFCLK is 32KHz - * VEXPRESS_TIMCLK is 1MHz - */ - writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL | - SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL | - readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl); - - /* - * Set Timer0 to be: - * Enabled, free running, no interrupt, 32-bit, wrapping - */ - writel(SYSTIMER_RELOAD, &systimer_base->timer0load); - writel(SYSTIMER_RELOAD, &systimer_base->timer0value); - writel(SYSTIMER_EN | SYSTIMER_32BIT | - readl(&systimer_base->timer0control), - &systimer_base->timer0control); -} - -int v2m_cfg_write(u32 devfn, u32 data) -{ - /* Configuration interface broken? */ - u32 val; - - devfn |= SYS_CFG_START | SYS_CFG_WRITE; - - val = readl(V2M_SYS_CFGSTAT); - writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT); - - writel(data, V2M_SYS_CFGDATA); - writel(devfn, V2M_SYS_CFGCTRL); - - do { - val = readl(V2M_SYS_CFGSTAT); - } while (val == 0); - - return !!(val & SYS_CFG_ERR); -} - -/* Use the ARM Watchdog System to cause reset */ -void reset_cpu(ulong addr) -{ - if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0)) - printf("Unable to reboot\n"); -} - -void lowlevel_init(void) -{ -} - -ulong get_board_rev(void){ - return readl((u32 *)SYS_ID); -} - -#ifdef CONFIG_ARMV7_NONSEC -/* Setting the address at which secondary cores start from. - * Versatile Express uses one address for all cores, so ignore corenr - */ -void smp_set_core_boot_addr(unsigned long addr, int corenr) -{ - /* The SYSFLAGS register on VExpress needs to be cleared first - * by writing to the next address, since any writes to the address - * at offset 0 will only be ORed in - */ - writel(~0, CONFIG_SYSFLAGS_ADDR + 4); - writel(addr, CONFIG_SYSFLAGS_ADDR); -} -#endif diff --git a/board/armltd/vexpress/vexpress_tc2.c b/board/armltd/vexpress/vexpress_tc2.c deleted file mode 100644 index 8ee24bdde731..000000000000 --- a/board/armltd/vexpress/vexpress_tc2.c +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Linaro - * Jon Medhurst tixy@linaro.org - * - * TC2 specific code for Versatile Express. - */ - -#include <asm/armv7.h> -#include <asm/io.h> -#include <asm/u-boot.h> -#include <common.h> -#include <linux/libfdt.h> - -#define SCC_BASE 0x7fff0000 - -bool armv7_boot_nonsec_default(void) -{ -#ifdef CONFIG_ARMV7_BOOT_SEC_DEFAULT - return false; -#else - /* - * The Serial Configuration Controller (SCC) register at address 0x700 - * contains flags for configuring the behaviour of the Boot Monitor - * (which CPUs execute from reset). Two of these bits are of interest: - * - * bit 12 = Use per-cpu mailboxes for power management - * bit 13 = Power down the non-boot cluster - * - * It is only when both of these are false that U-Boot's current - * implementation of 'nonsec' mode can work as expected because we - * rely on getting all CPUs to execute _nonsec_init, so let's check that. - */ - return (readl((u32 *)(SCC_BASE + 0x700)) & ((1 << 12) | (1 << 13))) == 0; -#endif -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *fdt, struct bd_info *bd) -{ - int offset, tmp, len; - const struct fdt_property *prop; - const char *cci_compatible = "arm,cci-400-ctrl-if"; - -#ifdef CONFIG_ARMV7_NONSEC - if (!armv7_boot_nonsec()) - return 0; -#else - return 0; -#endif - /* Booting in nonsec mode, disable CCI access */ - offset = fdt_path_offset(fdt, "/cpus"); - if (offset < 0) { - printf("couldn't find /cpus\n"); - return offset; - } - - /* delete cci-control-port in each cpu node */ - for (tmp = fdt_first_subnode(fdt, offset); tmp >= 0; - tmp = fdt_next_subnode(fdt, tmp)) - fdt_delprop(fdt, tmp, "cci-control-port"); - - /* disable all ace cci slave ports */ - offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible", - cci_compatible, 20); - while (offset > 0) { - prop = fdt_get_property(fdt, offset, "interface-type", - &len); - if (!prop) - continue; - if (len < 4) - continue; - if (strcmp(prop->data, "ace")) - continue; - - fdt_setprop_string(fdt, offset, "status", "disabled"); - - offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible", - cci_compatible, 20); - } - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig deleted file mode 100644 index e8e401b17903..000000000000 --- a/configs/vexpress_ca15_tc2_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_VEXPRESS_CA15_TC2=y -CONFIG_SYS_TEXT_BASE=0x80800000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash" -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -# CONFIG_CMD_SLEEP is not set -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xFF80000 -CONFIG_ARM_PL180_MMCI=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x1a000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_BAUDRATE=38400 -CONFIG_CONS_INDEX=0 -CONFIG_OF_LIBFDT=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig deleted file mode 100644 index 88027b940bae..000000000000 --- a/configs/vexpress_ca5x2_defconfig +++ /dev/null @@ -1,38 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_VEXPRESS_CA5X2=y -CONFIG_SYS_TEXT_BASE=0x80800000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash" -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -# CONFIG_CMD_SLEEP is not set -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xFF80000 -CONFIG_ARM_PL180_MMCI=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x1a000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_BAUDRATE=38400 -CONFIG_CONS_INDEX=0 -CONFIG_OF_LIBFDT=y diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig deleted file mode 100644 index 7b148450e567..000000000000 --- a/configs/vexpress_ca9x4_defconfig +++ /dev/null @@ -1,39 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_VEXPRESS_CA9X4=y -CONFIG_SYS_TEXT_BASE=0x60800000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash" -CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb" -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -# CONFIG_CMD_SLEEP is not set -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0x47F80000 -CONFIG_ARM_PL180_MMCI=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x4e000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_BAUDRATE=38400 -CONFIG_CONS_INDEX=0 -CONFIG_OF_LIBFDT=y diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 403602fddff2..367004b15bc7 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -458,7 +458,7 @@ config SYS_I2C_UNIPHIER_F
config SYS_I2C_VERSATILE bool "Arm Ltd Versatile I2C bus driver" - depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || TARGET_VEXPRESS64_JUNO) + depends on DM_I2C && TARGET_VEXPRESS64_JUNO help Add support for the Arm Ltd Versatile Express I2C driver. The I2C host controller is present in the development boards manufactured by Arm Ltd. diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h deleted file mode 100644 index 4f8e63574dfb..000000000000 --- a/include/configs/vexpress_ca15_tc2.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Linaro - * Andre Przywara, andre.przywara@linaro.org - * - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_CA15X2_TC2_h -#define __VEXPRESS_CA15X2_TC2_h - -#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP -#include "vexpress_common.h" - -#define CONFIG_SYSFLAGS_ADDR 0x1c010030 -#define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR - -#endif diff --git a/include/configs/vexpress_ca5x2.h b/include/configs/vexpress_ca5x2.h deleted file mode 100644 index b8079e63d666..000000000000 --- a/include/configs/vexpress_ca5x2.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Linaro - * Ryan Harkin, ryan.harkin@linaro.org - * - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_CA5X2_h -#define __VEXPRESS_CA5X2_h - -#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP -#include "vexpress_common.h" - -#endif /* __VEXPRESS_CA5X2_h */ diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h deleted file mode 100644 index 8157a5868d65..000000000000 --- a/include/configs/vexpress_ca9x4.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Linaro - * Ryan Harkin, ryan.harkin@linaro.org - * - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_CA9X4_H -#define __VEXPRESS_CA9X4_H - -#define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP -#include "vexpress_common.h" - -#endif /* VEXPRESS_CA9X4_H */
These boards have not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove them.
Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-imx/mx6/Kconfig | 1 - board/gateworks/gw_ventana/Kconfig | 28 - board/gateworks/gw_ventana/MAINTAINERS | 8 - board/gateworks/gw_ventana/Makefile | 11 - board/gateworks/gw_ventana/README | 320 ---- board/gateworks/gw_ventana/common.c | 1760 ------------------- board/gateworks/gw_ventana/common.h | 99 -- board/gateworks/gw_ventana/eeprom.c | 266 --- board/gateworks/gw_ventana/gsc.c | 283 --- board/gateworks/gw_ventana/gsc.h | 71 - board/gateworks/gw_ventana/gw_ventana.c | 1381 --------------- board/gateworks/gw_ventana/gw_ventana_spl.c | 779 -------- board/gateworks/gw_ventana/ventana_eeprom.h | 140 -- configs/gwventana_emmc_defconfig | 111 -- configs/gwventana_gw5904_defconfig | 115 -- configs/gwventana_nand_defconfig | 115 -- include/configs/gw_ventana.h | 298 ---- 17 files changed, 5786 deletions(-) delete mode 100644 board/gateworks/gw_ventana/Kconfig delete mode 100644 board/gateworks/gw_ventana/MAINTAINERS delete mode 100644 board/gateworks/gw_ventana/Makefile delete mode 100644 board/gateworks/gw_ventana/README delete mode 100644 board/gateworks/gw_ventana/common.c delete mode 100644 board/gateworks/gw_ventana/common.h delete mode 100644 board/gateworks/gw_ventana/eeprom.c delete mode 100644 board/gateworks/gw_ventana/gsc.c delete mode 100644 board/gateworks/gw_ventana/gsc.h delete mode 100644 board/gateworks/gw_ventana/gw_ventana.c delete mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c delete mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h delete mode 100644 configs/gwventana_emmc_defconfig delete mode 100644 configs/gwventana_gw5904_defconfig delete mode 100644 configs/gwventana_nand_defconfig delete mode 100644 include/configs/gw_ventana.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 513d007ce75a..dacfe623903c 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -730,7 +730,6 @@ source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/phytec/pfla02/Kconfig" source "board/phytec/pcl063/Kconfig" -source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" source "board/softing/vining_2000/Kconfig" source "board/liebherr/display5/Kconfig" diff --git a/board/gateworks/gw_ventana/Kconfig b/board/gateworks/gw_ventana/Kconfig deleted file mode 100644 index fee910ca837d..000000000000 --- a/board/gateworks/gw_ventana/Kconfig +++ /dev/null @@ -1,28 +0,0 @@ -if TARGET_GW_VENTANA - -config DM_GPIO - default y - -config SYS_BOARD - default "gw_ventana" - -config SYS_VENDOR - default "gateworks" - -config SYS_CONFIG_NAME - default "gw_ventana" - -config CMD_EECONFIG - bool "Enable the 'econfig' command" - help - Provides access to EEPROM configuration on Gateworks Ventana - -config CMD_GSC - bool "Enable the 'gsc' command" - help - Provides access to the GSC configuration: - - gsc sleep - sleeps for a period of seconds - gsc wd - enables / disables the watchdog - -endif diff --git a/board/gateworks/gw_ventana/MAINTAINERS b/board/gateworks/gw_ventana/MAINTAINERS deleted file mode 100644 index 265ddac1c054..000000000000 --- a/board/gateworks/gw_ventana/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -GW_VENTANA BOARD -M: Tim Harvey tharvey@gateworks.com -S: Maintained -F: board/gateworks/gw_ventana/ -F: include/configs/gw_ventana.h -F: configs/gwventana_nand_defconfig -F: configs/gwventana_emmc_defconfig -F: configs/gwventana_gw5904_defconfig diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile deleted file mode 100644 index 8fa691aefc4f..000000000000 --- a/board/gateworks/gw_ventana/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (C) 2012-2013, Guennadi Liakhovetski lg@denx.de -# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. -# Copyright (C) 2013, Gateworks Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := gw_ventana.o gsc.o eeprom.o common.o -obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o - diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README deleted file mode 100644 index 57c64a1b2ad5..000000000000 --- a/board/gateworks/gw_ventana/README +++ /dev/null @@ -1,320 +0,0 @@ -U-Boot for the Gateworks Ventana Product Family boards - -This file contains information for the port of U-Boot to the Gateworks -Ventana Product family boards. - -The entire Ventana product family (http://www.gateworks.com/product#ventana) -is supported by a single bootloader build by using a common SPL and U-Boot -that dynamically determines the characterstics of the board at runtime via -information from an EEPROM on the board programmed at the factory and supports -all of the various boot mediums available. - -1. Secondary Program Loader (SPL) ---------------------------------- - -The i.MX6 has a BOOT ROM PPL (Primary Program Loader) which supports loading -an executable image from various boot devices. - -The Gateworks Ventana board config uses an SPL build configuration. This -will build the following artifacts from U-Boot source: - - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program - Loader) boots. This detects CPU/DRAM configuration, configures - The DRAM controller, loads u-boot.img from the detected boot device, - and jumps to it. As this is booted from the PPL, it has an IVT/DCD - table. - - u-boot.img - The main U-Boot core which is u-boot.bin with a image header. - - -2. Build --------- - -To build U-Boot for the Gateworks Ventana product family: - -For NAND FLASH based boards: - make gwventana_nand_config - make - -For EMMC FLASH based boards: - make gwventana_emmc_config - make - - -3. Boot source: ---------------- - -The Gateworks Ventana boards support booting from NAND or micro-SD depending -on the board model. The IMX6 BOOT ROM will choose a boot media based on eFUSE -settings programmed at the factory. - -Boards with NAND flash will always boot from NAND, and NAND-less boards will -always boot from micro-SD. However, it is possible to use the U-Boot bmode -command (or the technique it uses) to essentially bootstrap to another boot -media at runtime. - -3.1. boot from NAND -------------------- - -The i.MX6 BOOT ROM expects some structures that provide details of NAND layout -and bad block information (referred to as 'bootstreams') which are replicated -multiple times in NAND. The number of replications and their spacing (referred -to as search stride) is configurable through board strapping options and/or -eFUSE settings (BOOT_SEARCH_COUNT / Pages in block from BOOT_CFG2). In -addition, the i.MX6 BOOT ROM Flash Configuration Block (FCB) supports two -copies of a bootloader in flash in the case that a bad block has corrupted one. -The Freescale 'kobs-ng' application from the Freescale LTIB BSP, which runs -under Linux and operates on an MTD partition, must be used to program the -bootstream in order to setup this flash structure correctly. - -The Gateworks Ventana boards with NAND flash have been factory programmed -such that their eFUSE settings expect 2 copies of the boostream (this is -specified by providing kobs-ng with the --search_exponent=1 argument). Once in -Linux with MTD support for the NAND on /dev/mtd0 you can program the SPL -with: - -kobs-ng init -v -x --search_exponent=1 SPL - -The kobs-ng application uses an imximage which contains the Image Vector Table -(IVT) and Device Configuration Data (DCD) structures that the i.MX6 BOOT ROM -requires to boot. The kobs-ng adds the Firmware Configuration Block (FCB) and -Discovered Bad Block Table (DBBT). The SPL build artifact from U-Boot is -an imximage. - -The u-boot.img, which is the non SPL U-Boot binary appended to a U-Boot image -header must be programmed in the NAND flash boot device at an offset hard -coded in the SPL. For the Ventana boards, this has been chosen to be 14MB. -The image can be programmed from either U-Boot or Linux: - -U-Boot: -Ventana > setenv mtdparts mtdparts=nand:14m(spl),2m(uboot),1m(env),-(rootfs) -Ventana > tftp ${loadaddr} u-boot.img && nand erase.part uboot && \ - nand write ${loadaddr} uboot ${filesize} - -Linux: -nandwrite /dev/mtd1 u-boot.img - -The above assumes the default Ventana partitioning scheme which is configured -via the mtdparts env var: - - spl: 14MB - - uboot: 2M - - env: 1M - - rootfs: the rest - -This information is taken from: - http://trac.gateworks.com/wiki/ventana/bootloader#nand - -More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual. - -3.1. boot from MMC (eMMC/microSD) ---------------------------------- - -When the IMX6 eFUSE settings have been factory programmed to boot from -MMC the SPL will be loaded from offset 0x400 (1KB). Once the SPL is -booted, it will load and execute U-Boot (u-boot.img) from offset 69KB -on the micro-SD (defined by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR). - -While it is technically possible to enable the SPL to be able to load -U-Boot from a file on a FAT/EXT filesystem on the micro-SD, we chose to -use raw micro-SD access to keep the code-size and boot time of the SPL down. - -For these reasons an MMC device that will be used as an IMX6 primary boot -device must be carefully partitioned and prepared. - -The following shell commands are executed on a Linux host (adjust DEV to the -block storage device of your MMC, ie /dev/mmcblk0): - - DEV=/dev/sdc - # zero out 1MB of device - sudo dd if=/dev/zero of=$DEV count=1 bs=1M oflag=sync status=none && sync - # copy SPL to 1KB offset - sudo dd if=SPL of=$DEV bs=1K seek=1 oflag=sync status=none && sync - # copy U-Boot to 69KB offset - sudo dd if=u-boot.img of=$DEV bs=1K seek=69 oflag=sync status=none && sync - # create a partition table with a single rootfs partition starting at 1MB - printf "1,,L\n" | sudo sfdisk --in-order --no-reread -L -uM $DEV && sync - # format partition - sudo mkfs.ext4 -L root ${DEV}1 - # mount the partition - sudo udisks --mount ${DEV}1 - # extract filesystem - sudo tar xvf rootfs.tar.gz -C /media/root - # flush and unmount - sync && sudo umount /media/root - -The above assumes the default Ventana micro-SD partitioning scheme - - spl : 1KB-69KB (68KB) required by IMX6 BOOT ROM - - uboot : 69KB-709KB (640KB) defined by - CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - - env : 709KB-965KB (256KB) defined by - CONFIG_ENV_MMC_SIZE - CONFIG_ENV_MMC_OFFSET_REDUND - - rootfs : 1MB- - -This information is taken from: - http://trac.gateworks.com/wiki/ventana/bootloader#microsd - -More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual. - -4. Falcon Mode ------------------------------- - -The Gateworks Ventana board config enables Falcon mode (CONFIG_SPL_OS_BOOT) -which allows the SPL to boot directly to an OS instead of to U-Boot -(u-boot.img) thus acheiving a faster overall boot time. The time savings -depends on your boot medium (ie NAND Flash vs micro-SD) and size/storage -of the OS. The time savings can be anywhere from 2 seconds (256MB NAND Flash -with ~1MB kernel) to 6 seconds or more (2GB NAND Flash with ~6 kernel) - -The Gateworks Ventana board supports Falcon mode for the following boot -medium: - - NAND flash - - micro-SD - -For all boot mediums, raw mode is used. While support of more complex storage -such as files on top of FAT/EXT filesystem is possible but not practical -as the size of the SPL is fairly limitted (to 64KB based on the smallest -size of available IMX6 iRAM) as well as the fact that this would increase -OS load time which defeats the purpose of Falcon mode in the first place. - -The SPL decides to boot either U-Boot (u-boot.img) or the OS (args + kernel) -based on the return value of the spl_start_uboot() function. While often -this can simply be the state of a GPIO based pushbutton or DIP switch, for -Gateworks Ventana, we use an EEPROM register on i2c-0 at 0x50:0x00: -set to '0' will choose to boot to U-Boot and otherwise it will boot to OS. - -To use Falcon mode it is required that you first 'prepare' the 'args' data -that is stored on your boot medium along with the kernel (which can be any -OS or bare-metal application). In the case of the Linux kernel the 'args' -is the flatenned device-tree which normally gets altered prior to booting linux -by U-Boot's 'bootm' command. To achieve this for SPL we use the -'spl export fdt' command in U-Boot after loading the kernel and dtb which -will go through the same process of modifying the device-tree for the board -being executed on but not jump to the kernel. This allows you to save the -args data to the location the SPL expects it and then enable Falcon mode. - -It is important to realize that there are certain values in the dtb that -are board model specific (IMX6Q vs IMX6DL for example) and board specific -(board serial number, MAC addrs) so you do not want to use the 'args' -data prepared from one board on another board. - -4.1. Falcon Mode on NAND flash ------------------------------- -To prepare a Gateworks Ventana board that boots from NAND flash for Falcon -mode you must program your flash such that the 'args' and 'kernel' are -located where defined at compile time by the following: - CONFIG_CMD_SPL_NAND_OFS 17MB - offset of 'args' - CONFIG_SYS_NAND_SPL_KERNEL_OFFS 18MB - offset of 'kernel' - -The location offsets defined above are defaults chosen by Gateworks and are -flexible if you want to re-define them. - -The following steps executed in U-Boot will configure Falcon mode for NAND -using rootfs (ubi), kernel (uImage), and dtb from the network: - - # change mtd partitions to the above mapping - Ventana > setenv mtdparts 'mtdparts=nand:14m(spl),2m(uboot),1m(env),1m(args),10m(kernel),-(rootfs)' - - # flash rootfs (at 28MB) - Ventana > tftp ${loadaddr} rootfs_${flash_layout}.ubi && \ - nand erase.part rootfs && nand write ${loadaddr} rootfs ${filesize} - - # load the device-tree - Ventana > tftp ${fdt_addr} ventana/${fdt_file2} - - # load the kernel - Ventana > tftp ${loadaddr} ventana/uImage - - # flash kernel (at 18MB) - Ventana > nand erase.part kernel && nand write ${loadaddr} kernel ${filesize} - - # set kernel args for the console and rootfs (used by spl export) - Ventana > setenv bootargs 'console=ttymxc1,115200 root=ubi0:rootfs ubi.mtd=5 rootfstype=ubifs quiet' - - # create args based on env, board, EEPROM, and dtb - Ventana > spl export fdt ${loadaddr} - ${fdt_addr} - - # flash args (at 17MB) - Ventana > nand erase.part args && nand write 18000000 args 100000 - - # set i2c register 0x50:0x00=0 to boot to Linux - Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1 - -Be sure to adjust 'bootargs' above to your OS needs (this will be different -for various distros such as OpenWrt, Yocto, Android, etc). You can use the -value obtained from 'cat /proc/cmdline' when booted to Linux. - -This information is taken from: - http://trac.gateworks.com/wiki/ventana/bootloader/falcon-mode#nand - - -4.2. Falcon Mode on micro-SD card ---------------------------------- - -To prepare a Gateworks Ventana board with a primary boot device of micro-SD -you first need to make sure you build U-Boot with CONFIG_ENV_IS_IN_MMC -instead of CONFIG_ENV_IS_IN_NAND. - -For micro-SD based Falcon mode you must program your micro-SD such that -the 'args' and 'kernel' are located where defined at compile time -by the following: - CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 (1MB) - offset of 'args' - CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 (2MB) - offset of 'kernel' - -The location offsets defined above are defaults chosen by Gateworks and are -flexible if you want to re-define them. - -First you must prepare a micro-SD such that the SPL can be loaded by the -IMX6 BOOT ROM (fixed offset of 1KB), and U-Boot can be loaded by the SPL -(fixed offset of 69KB defined by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR). - -The following shell commands are executed on a Linux host (adjust DEV to the -block storage device of your micro-SD): - - DEV=/dev/sdc - # zero out 1MB of device - sudo dd if=/dev/zero of=$DEV count=1 bs=1M oflag=sync status=none && sync - # copy SPL to 1KB offset - sudo dd if=SPL of=$DEV bs=1K seek=1 oflag=sync status=none && sync - # copy U-Boot to 69KB offset - sudo dd if=u-boot.img of=$DEV bs=1K seek=69 oflag=sync status=none && sync - # create a partition table with a single rootfs partition starting at 10MB - printf "10,,L\n" | sudo sfdisk --in-order --no-reread -L -uM $DEV && sync - # format partition - sudo mkfs.ext4 -L root ${DEV}1 - # mount the partition - sudo udisks --mount ${DEV}1 - # extract filesystem - sudo tar xvf rootfs.tar.gz -C /media/root - # flush and unmount - sync && sudo umount /media/root - -Now that your micro-SD partitioning has been adjusted to leave room for the -raw 'args' and 'kernel' data boot the board with the prepared micro-SD, break -out in U-Boot and use the following to enable Falcon mode: - - # load device-tree from rootfs - Ventana > ext2load mmc 0:1 ${fdt_addr} boot/${fdt_file2} - - # load kernel from rootfs - Ventana > ext2load mmc 0:1 ${loadaddr} boot/uImage - - # write kernel at 2MB offset - Ventana > mmc write ${loadaddr} 0x1000 0x4000 - - # setup kernel bootargs - Ventana > setenv bootargs 'console=ttymxc1,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw' - - # prepare args - Ventana > spl export fdt ${loadaddr} - ${fdt_addr} - - # write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors) - Ventana > mmc write 18000000 0x800 0x800 - - # set i2c register 0x50:0x00=0 to boot to Linux - Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1 - -Be sure to adjust 'bootargs' above to your OS needs (this will be different -for various distros such as OpenWrt, Yocto, Android, etc). You can use the -value obtained from 'cat /proc/cmdline' when booted to Linux. - -This information is taken from: - http://trac.gateworks.com/wiki/ventana/bootloader/falcon-mode#microsd diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c deleted file mode 100644 index 14f45bf07da8..000000000000 --- a/board/gateworks/gw_ventana/common.c +++ /dev/null @@ -1,1760 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Gateworks Corporation - * - * Author: Tim Harvey tharvey@gateworks.com - */ - -#include <common.h> -#include <log.h> -#include <asm/arch/clock.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <env.h> -#include <fsl_esdhc_imx.h> -#include <hwconfig.h> -#include <linux/delay.h> -#include <power/pmic.h> -#include <power/ltc3676_pmic.h> -#include <power/pfuze100_pmic.h> - -#include "common.h" - -/* UART2: Serial Console */ -static iomux_v3_cfg_t const uart2_pads[] = { - IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - -void setup_iomux_uart(void) -{ - SETUP_IOMUX_PADS(uart2_pads); -} - -/* MMC */ -static iomux_v3_cfg_t const gw5904_emmc_pads[] = { - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; -/* 4-bit microSD on SD2 */ -static iomux_v3_cfg_t const gw5904_mmc_pads[] = { - IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - /* CD */ - IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; -/* 8-bit eMMC on SD2/NAND */ -static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = { - IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; - -/* - * I2C pad configs: - * I2C1: GSC - * I2C2: PMIC,PCIe Switch,Clock,Mezz - * I2C3: Multimedia/Expansion - */ -static struct i2c_pads_info mx6q_i2c_pad_info[] = { - { - .scl = { - .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, - .gp = IMX_GPIO_NR(3, 28) - } - }, { - .scl = { - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } - }, { - .scl = { - .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } - } -}; - -static struct i2c_pads_info mx6dl_i2c_pad_info[] = { - { - .scl = { - .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, - .gp = IMX_GPIO_NR(3, 28) - } - }, { - .scl = { - .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } - }, { - .scl = { - .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } - } -}; - -void setup_ventana_i2c(int i2c) -{ - struct i2c_pads_info *p; - - if (is_cpu_type(MXC_CPU_MX6Q)) - p = &mx6q_i2c_pad_info[i2c]; - else - p = &mx6dl_i2c_pad_info[i2c]; - - setup_i2c(i2c, CONFIG_SYS_I2C_SPEED, 0x7f, p); -} - -/* - * Baseboard specific GPIO - */ -static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - - /* GPS_SHDN */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* VID_PWR */ - IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { - /* SD3_VSELECT */ - IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), - /* RS232_EN# */ - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), - /* MSATA_EN */ - IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - /* CAN_STBY */ - IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* GPS_SHDN */ - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), - /* USBOTG_SEL */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* VID_PWR */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* PCI_RST# (GW522x) */ - IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), - /* RS485_EN */ - IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { - /* SD3_VSELECT */ - IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), - /* RS232_EN# */ - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), - /* MSATA_EN */ - IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), - /* CAN_STBY */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* USB_HUBRST# */ - IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - /* DIOI2C_DIS# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* GPS_SHDN */ - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), - /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* RS485_EN */ - IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { - /* SD3_VSELECT */ - IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), - /* RS232_EN# */ - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), - /* MSATA_EN */ - IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), - /* CAN_STBY */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* USB_HUBRST# */ - IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG), - /* MIPI_DIO */ - IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), - /* RS485_EN */ - IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - /* DIOI2C_DIS# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* RS485_EN */ - IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw551x_gpio_pads[] = { - /* CAN_STBY */ - IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), - /* PANLED# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw552x_gpio_pads[] = { - /* MSATA_EN */ - IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), - /* USBOTG_SEL */ - IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), - /* USB_HUBRST# */ - IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* MX6_DIO[4:9] */ - IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG), - /* PCIEGBE1_OFF# */ - IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), - /* PCIEGBE2_OFF# */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw553x_gpio_pads[] = { - /* SD3_VSELECT */ - IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG), - /* VID_PWR */ - IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw560x_gpio_pads[] = { - /* RS232_EN# */ - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), - /* CAN_STBY */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* USB_HUBRST# */ - IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - /* DIOI2C_DIS# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG), - /* RS485_EN */ - IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), - /* USBH2_PEN (OTG) */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* 12V0_PWR_EN */ - IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw5901_gpio_pads[] = { - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* ETH1_EN */ - IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), - /* CAN_STBY */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* PMIC reset */ - IOMUX_PADS(PAD_DISP0_DAT8__WDOG1_B | DIO_PAD_CFG), - /* COM_CFGA/B/C/D */ - IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG), - IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15 | DIO_PAD_CFG), - IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16 | DIO_PAD_CFG), - IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), - /* ETI_IRQ# */ - IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG), - /* DIO_IRQ# */ - IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), - /* FIBER_SIGDET */ - IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw5902_gpio_pads[] = { - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* CAN1_STBY */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* CAN2_STBY */ - IOMUX_PADS(PAD_SD3_CLK__GPIO7_IO03 | DIO_PAD_CFG), - /* UART1_EN# */ - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), - /* 5V_UVLO */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), - /* ETI_IRQ# */ - IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG), - /* DIO_IRQ# */ - IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), - /* USBOTG_PEN */ - IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw5903_gpio_pads[] = { - /* BKLT_12VEN */ - IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), - /* EMMY_PDN# */ - IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG), - /* EMMY_CFG1# */ - IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG), - /* EMMY_CFG1# */ - IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG), - /* USBH1_PEN (EHCI) */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* USBH2_PEN (OTG) */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* USBDPC_PEN */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* TOUCH_RST */ - IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG), - /* AUDIO_RST# */ - IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), - /* UART1_TEN# */ - IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), - /* LVDS_BKLEN # */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), - /* RGMII_PDWN# */ - IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG), - /* TOUCH_IRQ# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* TOUCH_RST# */ - IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw5904_gpio_pads[] = { - /* USB_HUBRST# */ - IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - /* DIOI2C_DIS# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* UART_RS485 */ - IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG), - /* UART_HALF */ - IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG), - /* SKT1_WDIS# */ - IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG), - /* SKT1_RST# */ - IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG), - /* SKT2_WDIS# */ - IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG), - /* SKT2_RST# */ - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), - /* M2_OFF# */ - IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG), - /* M2_WDIS# */ - IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG), - /* M2_RST# */ - IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG), - /* RS232_EN# */ - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw5905_gpio_pads[] = { - /* EMMY_PDN# */ - IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), - /* MIPI_RST */ - IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG), - /* MIPI_PWDN */ - IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG), - /* USBEHCI_SEL */ - IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_16__GPIO7_IO11 | DIO_PAD_CFG), - /* LVDS_BKLEN # */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | DIO_PAD_CFG), - /* SPK_SHDN# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* LOCLED# */ - IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), - /* FLASH LED1 */ - IOMUX_PADS(PAD_DISP0_DAT11__GPIO5_IO05 | DIO_PAD_CFG), - /* FLASH LED2 */ - IOMUX_PADS(PAD_DISP0_DAT12__GPIO5_IO06 | DIO_PAD_CFG), - /* DECT_RST# */ - IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG), - /* USBH1_PEN (EHCI) */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* LVDS_PWM */ - IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), - /* CODEC_RST */ - IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), - /* GYRO_CONTROL/DATA_EN */ - IOMUX_PADS(PAD_CSI0_DAT8__GPIO5_IO26 | DIO_PAD_CFG), - /* TOUCH_RST */ - IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG), - /* TOUCH_IRQ */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), -}; - -/* Digital I/O */ -struct dio_cfg gw51xx_dio[] = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, - IMX_GPIO_NR(1, 18), - { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, - 4 - }, -}; - -struct dio_cfg gw52xx_dio[] = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(1, 20), - { 0, 0 }, - 0 - }, -}; - -struct dio_cfg gw53xx_dio[] = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(1, 20), - { 0, 0 }, - 0 - }, -}; - -struct dio_cfg gw54xx_dio[] = { - { - { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, - IMX_GPIO_NR(1, 9), - { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, - 1 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, - IMX_GPIO_NR(2, 9), - { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, - IMX_GPIO_NR(2, 10), - { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, - 4 - }, -}; - -struct dio_cfg gw551x_dio[] = { - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, -}; - -struct dio_cfg gw552x_dio[] = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(1, 20), - { 0, 0 }, - 0 - }, - { - {IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18) }, - IMX_GPIO_NR(5, 18), - { 0, 0 }, - 0 - }, - { - {IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20) }, - IMX_GPIO_NR(5, 20), - { 0, 0 }, - 0 - }, - { - {IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21) }, - IMX_GPIO_NR(5, 21), - { 0, 0 }, - 0 - }, - { - {IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22) }, - IMX_GPIO_NR(5, 22), - { 0, 0 }, - 0 - }, - { - {IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23) }, - IMX_GPIO_NR(5, 23), - { 0, 0 }, - 0 - }, - { - {IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25) }, - IMX_GPIO_NR(5, 25), - { 0, 0 }, - 0 - }, -}; - -struct dio_cfg gw553x_dio[] = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, - IMX_GPIO_NR(1, 18), - { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, - 4 - }, -}; - -struct dio_cfg gw560x_dio[] = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(1, 20), - { 0, 0 }, - 0 - }, -}; - -struct dio_cfg gw5901_dio[] = { - { - { IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) }, - IMX_GPIO_NR(5, 14), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) }, - IMX_GPIO_NR(5, 15), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) }, - IMX_GPIO_NR(5, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) }, - IMX_GPIO_NR(5, 17), - { 0, 0 }, - 0 - }, -}; - -struct dio_cfg gw5902_dio[] = { - { - { IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) }, - IMX_GPIO_NR(5, 14), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) }, - IMX_GPIO_NR(5, 15), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) }, - IMX_GPIO_NR(5, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) }, - IMX_GPIO_NR(5, 17), - { 0, 0 }, - 0 - }, -}; - -struct dio_cfg gw5903_dio[] = { -}; - -struct dio_cfg gw5904_dio[] = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(1, 20), - { 0, 0 }, - 0 - }, - { - {IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) }, - IMX_GPIO_NR(2, 0), - { 0, 0 }, - 0 - }, - { - {IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) }, - IMX_GPIO_NR(2, 1), - { 0, 0 }, - 0 - }, - { - {IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) }, - IMX_GPIO_NR(2, 2), - { 0, 0 }, - 0 - }, - { - {IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) }, - IMX_GPIO_NR(2, 3), - { 0, 0 }, - 0 - }, - { - {IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04) }, - IMX_GPIO_NR(2, 4), - { 0, 0 }, - 0 - }, - { - {IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05) }, - IMX_GPIO_NR(2, 5), - { 0, 0 }, - 0 - }, - { - {IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06) }, - IMX_GPIO_NR(2, 6), - { 0, 0 }, - 0 - }, - { - {IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07) }, - IMX_GPIO_NR(2, 7), - { 0, 0 }, - 0 - }, -}; - -struct dio_cfg gw5906_dio[] = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(1, 20), - { 0, 0 }, - 0 - }, -}; - -/* - * Board Specific GPIO - */ -struct ventana gpio_cfg[GW_UNKNOWN] = { - /* GW5400proto */ - { - .gpio_pads = gw54xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, - .dio_cfg = gw54xx_dio, - .dio_num = ARRAY_SIZE(gw54xx_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 10), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .mezz_pwren = IMX_GPIO_NR(4, 7), - .mezz_irq = IMX_GPIO_NR(4, 9), - .rs485en = IMX_GPIO_NR(3, 24), - .dioi2c_en = IMX_GPIO_NR(4, 5), - .pcie_sson = IMX_GPIO_NR(1, 20), - .otgpwr_en = IMX_GPIO_NR(3, 22), - .mmc_cd = IMX_GPIO_NR(7, 0), - }, - - /* GW51xx */ - { - .gpio_pads = gw51xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, - .dio_cfg = gw51xx_dio, - .dio_num = ARRAY_SIZE(gw51xx_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 10), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .gps_shdn = IMX_GPIO_NR(1, 2), - .vidin_en = IMX_GPIO_NR(5, 20), - .wdis = IMX_GPIO_NR(7, 12), - .otgpwr_en = IMX_GPIO_NR(3, 22), - .nand = true, - }, - - /* GW52xx */ - { - .gpio_pads = gw52xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, - .dio_cfg = gw52xx_dio, - .dio_num = ARRAY_SIZE(gw52xx_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .gps_shdn = IMX_GPIO_NR(1, 27), - .vidin_en = IMX_GPIO_NR(3, 31), - .usb_sel = IMX_GPIO_NR(1, 2), - .wdis = IMX_GPIO_NR(7, 12), - .msata_en = GP_MSATA_SEL, - .rs232_en = GP_RS232_EN, - .otgpwr_en = IMX_GPIO_NR(3, 22), - .vsel_pin = IMX_GPIO_NR(6, 14), - .mmc_cd = IMX_GPIO_NR(7, 0), - .nand = true, - }, - - /* GW53xx */ - { - .gpio_pads = gw53xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, - .dio_cfg = gw53xx_dio, - .dio_num = ARRAY_SIZE(gw53xx_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .gps_shdn = IMX_GPIO_NR(1, 27), - .vidin_en = IMX_GPIO_NR(3, 31), - .wdis = IMX_GPIO_NR(7, 12), - .msata_en = GP_MSATA_SEL, - .rs232_en = GP_RS232_EN, - .otgpwr_en = IMX_GPIO_NR(3, 22), - .vsel_pin = IMX_GPIO_NR(6, 14), - .mmc_cd = IMX_GPIO_NR(7, 0), - .nand = true, - }, - - /* GW54xx */ - { - .gpio_pads = gw54xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, - .dio_cfg = gw54xx_dio, - .dio_num = ARRAY_SIZE(gw54xx_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .rs485en = IMX_GPIO_NR(7, 1), - .vidin_en = IMX_GPIO_NR(3, 31), - .dioi2c_en = IMX_GPIO_NR(4, 5), - .pcie_sson = IMX_GPIO_NR(1, 20), - .wdis = IMX_GPIO_NR(5, 17), - .msata_en = GP_MSATA_SEL, - .rs232_en = GP_RS232_EN, - .otgpwr_en = IMX_GPIO_NR(3, 22), - .vsel_pin = IMX_GPIO_NR(6, 14), - .mmc_cd = IMX_GPIO_NR(7, 0), - .nand = true, - }, - - /* GW551x */ - { - .gpio_pads = gw551x_gpio_pads, - .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, - .dio_cfg = gw551x_dio, - .dio_num = ARRAY_SIZE(gw551x_dio), - .leds = { - IMX_GPIO_NR(4, 7), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), - .wdis = IMX_GPIO_NR(7, 12), - .nand = true, - }, - - /* GW552x */ - { - .gpio_pads = gw552x_gpio_pads, - .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, - .dio_cfg = gw552x_dio, - .dio_num = ARRAY_SIZE(gw552x_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .usb_sel = IMX_GPIO_NR(1, 7), - .wdis = IMX_GPIO_NR(7, 12), - .msata_en = GP_MSATA_SEL, - .nand = true, - }, - - /* GW553x */ - { - .gpio_pads = gw553x_gpio_pads, - .num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2, - .dio_cfg = gw553x_dio, - .dio_num = ARRAY_SIZE(gw553x_dio), - .leds = { - IMX_GPIO_NR(4, 10), - IMX_GPIO_NR(4, 11), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), - .vidin_en = IMX_GPIO_NR(5, 20), - .wdis = IMX_GPIO_NR(7, 12), - .otgpwr_en = IMX_GPIO_NR(3, 22), - .vsel_pin = IMX_GPIO_NR(6, 14), - .mmc_cd = IMX_GPIO_NR(7, 0), - .nand = true, - }, - - /* GW560x */ - { - .gpio_pads = gw560x_gpio_pads, - .num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2, - .dio_cfg = gw560x_dio, - .dio_num = ARRAY_SIZE(gw560x_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(4, 31), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .rs232_en = GP_RS232_EN, - .vidin_en = IMX_GPIO_NR(3, 31), - .wdis = IMX_GPIO_NR(7, 12), - .otgpwr_en = IMX_GPIO_NR(4, 15), - .mmc_cd = IMX_GPIO_NR(7, 0), - }, - - /* GW5901 */ - { - .gpio_pads = gw5901_gpio_pads, - .num_pads = ARRAY_SIZE(gw5901_gpio_pads)/2, - .dio_cfg = gw5901_dio, - .leds = { - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .nand = true, - }, - - /* GW5902 */ - { - .gpio_pads = gw5902_gpio_pads, - .num_pads = ARRAY_SIZE(gw5902_gpio_pads)/2, - .dio_cfg = gw5902_dio, - .leds = { - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), - .rs232_en = GP_RS232_EN, - .otgpwr_en = IMX_GPIO_NR(3, 23), - .nand = true, - }, - - /* GW5903 */ - { - .gpio_pads = gw5903_gpio_pads, - .num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2, - .dio_cfg = gw5903_dio, - .dio_num = ARRAY_SIZE(gw5903_dio), - .leds = { - IMX_GPIO_NR(6, 14), - }, - .otgpwr_en = IMX_GPIO_NR(4, 15), - .mmc_cd = IMX_GPIO_NR(6, 11), - }, - - /* GW5904 */ - { - .gpio_pads = gw5904_gpio_pads, - .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2, - .dio_cfg = gw5904_dio, - .dio_num = ARRAY_SIZE(gw5904_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .otgpwr_en = IMX_GPIO_NR(3, 22), - }, - - /* GW5905 */ - { - .gpio_pads = gw5905_gpio_pads, - .num_pads = ARRAY_SIZE(gw5905_gpio_pads)/2, - .leds = { - IMX_GPIO_NR(6, 14), - }, - .pcie_rst = IMX_GPIO_NR(7, 11), - .wdis = IMX_GPIO_NR(7, 13), - }, - - /* GW5906 */ - { - .gpio_pads = gw552x_gpio_pads, - .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, - .dio_cfg = gw5906_dio, - .dio_num = ARRAY_SIZE(gw5906_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .usb_sel = IMX_GPIO_NR(1, 7), - .wdis = IMX_GPIO_NR(7, 12), - .msata_en = GP_MSATA_SEL, - .nand = true, - }, - - /* GW5907 */ - { - .gpio_pads = gw51xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, - .dio_cfg = gw51xx_dio, - .dio_num = ARRAY_SIZE(gw51xx_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 10), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), - .wdis = IMX_GPIO_NR(7, 12), - .nand = true, - }, - - /* GW5908 */ - { - .gpio_pads = gw53xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, - .dio_cfg = gw53xx_dio, - .dio_num = ARRAY_SIZE(gw53xx_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .gps_shdn = IMX_GPIO_NR(1, 27), - .vidin_en = IMX_GPIO_NR(3, 31), - .wdis = IMX_GPIO_NR(7, 12), - .msata_en = GP_MSATA_SEL, - .rs232_en = GP_RS232_EN, - }, - - /* GW5909 */ - { - .gpio_pads = gw5904_gpio_pads, - .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2, - .dio_cfg = gw5904_dio, - .dio_num = ARRAY_SIZE(gw5904_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .otgpwr_en = IMX_GPIO_NR(3, 22), - }, -}; - -#define SETUP_GPIO_OUTPUT(gpio, name, level) \ - gpio_request(gpio, name); \ - gpio_direction_output(gpio, level); -#define SETUP_GPIO_INPUT(gpio, name) \ - gpio_request(gpio, name); \ - gpio_direction_input(gpio); -void setup_iomux_gpio(int board, struct ventana_board_info *info) -{ - int i; - - if (board >= GW_UNKNOWN) - return; - - /* board specific iomux */ - imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads, - gpio_cfg[board].num_pads); - - /* RS232_EN# */ - if (gpio_cfg[board].rs232_en) { - gpio_request(gpio_cfg[board].rs232_en, "rs232_en#"); - gpio_direction_output(gpio_cfg[board].rs232_en, 0); - } - - /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ - if (board == GW52xx && info->model[4] == '2') - gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23); - - /* assert PCI_RST# */ - gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#"); - gpio_direction_output(gpio_cfg[board].pcie_rst, 0); - - /* turn off (active-high) user LED's */ - for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { - char name[16]; - if (gpio_cfg[board].leds[i]) { - sprintf(name, "led_user%d", i); - gpio_request(gpio_cfg[board].leds[i], name); - gpio_direction_output(gpio_cfg[board].leds[i], 1); - } - } - - /* MSATA Enable - default to PCI */ - if (gpio_cfg[board].msata_en) { - gpio_request(gpio_cfg[board].msata_en, "msata_en"); - gpio_direction_output(gpio_cfg[board].msata_en, 0); - } - - /* Expansion Mezzanine IO */ - if (gpio_cfg[board].mezz_pwren) { - gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr"); - gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); - } - if (gpio_cfg[board].mezz_irq) { - gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#"); - gpio_direction_input(gpio_cfg[board].mezz_irq); - } - - /* RS485 Transmit Enable */ - if (gpio_cfg[board].rs485en) { - gpio_request(gpio_cfg[board].rs485en, "rs485_en"); - gpio_direction_output(gpio_cfg[board].rs485en, 0); - } - - /* GPS_SHDN */ - if (gpio_cfg[board].gps_shdn) { - gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn"); - gpio_direction_output(gpio_cfg[board].gps_shdn, 1); - } - - /* Analog video codec power enable */ - if (gpio_cfg[board].vidin_en) { - gpio_request(gpio_cfg[board].vidin_en, "anavidin_en"); - gpio_direction_output(gpio_cfg[board].vidin_en, 1); - } - - /* DIOI2C_DIS# */ - if (gpio_cfg[board].dioi2c_en) { - gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#"); - gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); - } - - /* PCICK_SSON: disable spread-spectrum clock */ - if (gpio_cfg[board].pcie_sson) { - gpio_request(gpio_cfg[board].pcie_sson, "pci_sson"); - gpio_direction_output(gpio_cfg[board].pcie_sson, 0); - } - - /* USBOTG mux routing */ - if (gpio_cfg[board].usb_sel) { - gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel"); - gpio_direction_output(gpio_cfg[board].usb_sel, 0); - } - - /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ - if (gpio_cfg[board].wdis) { - gpio_request(gpio_cfg[board].wdis, "wlan_dis"); - gpio_direction_output(gpio_cfg[board].wdis, 1); - } - - /* OTG power off */ - if (gpio_cfg[board].otgpwr_en) { - gpio_request(gpio_cfg[board].otgpwr_en, "usbotg_pwr"); - gpio_direction_output(gpio_cfg[board].otgpwr_en, 0); - } - - /* sense vselect pin to see if we support uhs-i */ - if (gpio_cfg[board].vsel_pin) { - gpio_request(gpio_cfg[board].vsel_pin, "sd3_vselect"); - gpio_direction_input(gpio_cfg[board].vsel_pin); - gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin); - } - - /* microSD CD */ - if (gpio_cfg[board].mmc_cd) { - gpio_request(gpio_cfg[board].mmc_cd, "sd_cd"); - gpio_direction_input(gpio_cfg[board].mmc_cd); - } - - /* Anything else board specific */ - switch(board) { - case GW560x: - gpio_request(IMX_GPIO_NR(4, 26), "12p0_en"); - gpio_direction_output(IMX_GPIO_NR(4, 26), 1); - break; - case GW5901: - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 2), "can_stby", 0); - break; - case GW5902: - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 2), "can1_stby", 0); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 3), "can2_stby", 0); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "5P0V_EN", 1); - break; - case GW5903: - gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr"); - gpio_direction_output(IMX_GPIO_NR(3, 31), 1); - gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr"); - gpio_direction_output(IMX_GPIO_NR(4, 15), 1); - gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr"); - gpio_direction_output(IMX_GPIO_NR(4, 15), 1); - gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en"); - gpio_direction_output(IMX_GPIO_NR(1, 25), 1); - gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#"); - gpio_direction_input(IMX_GPIO_NR(4, 6)); - gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst"); - gpio_direction_output(IMX_GPIO_NR(4, 8), 1); - gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven"); - gpio_direction_output(IMX_GPIO_NR(1, 7), 1); - break; - case GW5909: - case GW5904: - gpio_request(IMX_GPIO_NR(4, 23), "rs485_en"); - gpio_direction_output(IMX_GPIO_NR(4, 23), 0); - gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#"); - gpio_direction_output(IMX_GPIO_NR(5, 11), 1); - gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#"); - gpio_direction_output(IMX_GPIO_NR(5, 12), 1); - gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#"); - gpio_direction_output(IMX_GPIO_NR(5, 13), 1); - gpio_request(IMX_GPIO_NR(1, 15), "m2_off#"); - gpio_direction_output(IMX_GPIO_NR(1, 15), 1); - gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#"); - gpio_direction_output(IMX_GPIO_NR(1, 14), 1); - gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#"); - gpio_direction_output(IMX_GPIO_NR(1, 13), 1); - break; - case GW5905: - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 7), "usb_pcisel", 0); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 9), "lvds_cabc", 1); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 14), "mipi_pdwn", 1); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 15), "mipi_rst#", 0); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(2, 3), "emmy_pdwn#", 1); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 5), "spk_shdn#", 0); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 0); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 6), "touch_irq", 0); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 5), "flash_en1", 0); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 6), "flash_en2", 0); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 14), "dect_rst#", 1); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 17), "codec_rst#", 0); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 26), "imu_den", 1); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "lvds_cabc", 0); - mdelay(100); - /* - * gauruntee touch controller comes out of reset with INT - * low for address - */ - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 1); - break; - } -} - -/* setup GPIO pinmux and default configuration per baseboard and env */ -void setup_board_gpio(int board, struct ventana_board_info *info) -{ - const char *s; - char arg[10]; - size_t len; - int i; - int quiet = simple_strtol(env_get("quiet"), NULL, 10); - - if (board >= GW_UNKNOWN) - return; - - /* RS232_EN# */ - if (gpio_cfg[board].rs232_en) { - gpio_direction_output(gpio_cfg[board].rs232_en, - (hwconfig("rs232")) ? 0 : 1); - } - - /* MSATA Enable */ - if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) { - gpio_direction_output(GP_MSATA_SEL, - (hwconfig("msata")) ? 1 : 0); - } - - /* USBOTG Select (PCISKT or FrontPanel) */ - if (gpio_cfg[board].usb_sel) { - gpio_direction_output(gpio_cfg[board].usb_sel, - (hwconfig("usb_pcisel")) ? 1 : 0); - } - - /* - * Configure DIO pinmux/padctl registers - * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions - */ - for (i = 0; i < gpio_cfg[board].dio_num; i++) { - struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; - iomux_v3_cfg_t ctrl = DIO_PAD_CFG; - unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; - - if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1]) - continue; - sprintf(arg, "dio%d", i); - if (!hwconfig(arg)) - continue; - s = hwconfig_subarg(arg, "padctrl", &len); - if (s) { - ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16) - & 0x1ffff) | MUX_MODE_SION; - } - if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { - if (!quiet) { - printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, - (cfg->gpio_param/32)+1, - cfg->gpio_param%32, - cfg->gpio_param); - } - imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | - ctrl); - gpio_requestf(cfg->gpio_param, "dio%d", i); - gpio_direction_input(cfg->gpio_param); - } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") && - cfg->pwm_padmux) { - if (!cfg->pwm_param) { - printf("DIO%d: Error: pwm config invalid\n", - i); - continue; - } - if (!quiet) - printf("DIO%d: pwm%d\n", i, cfg->pwm_param); - imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] | - MUX_PAD_CTRL(ctrl)); - } - } - - if (!quiet) { - if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) { - printf("MSATA: %s\n", (hwconfig("msata") ? - "enabled" : "disabled")); - } - if (gpio_cfg[board].rs232_en) { - printf("RS232: %s\n", (hwconfig("rs232")) ? - "enabled" : "disabled"); - } - } -} - -/* setup board specific PMIC */ -void setup_pmic(void) -{ - struct pmic *p; - struct ventana_board_info ventana_info; - int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info); - const int i2c_pmic = 1; - u32 reg; - - i2c_set_bus_num(i2c_pmic); - - /* configure PFUZE100 PMIC */ - if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) { - debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR); - power_pfuze100_init(i2c_pmic); - p = pmic_get("PFUZE100"); - if (p && !pmic_probe(p)) { - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - - /* Set VGEN1 to 1.5V and enable */ - pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); - reg &= ~(LDO_VOL_MASK); - reg |= (LDOA_1_50V | LDO_EN); - pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); - - /* Set SWBST to 5.0V and enable */ - pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); - reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); - reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT)); - pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); - } - } - - /* configure LTC3676 PMIC */ - else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) { - debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR); - power_ltc3676_init(i2c_pmic); - p = pmic_get("LTC3676_PMIC"); - if (!p || pmic_probe(p)) - return; - puts("PMIC: LTC3676\n"); - /* - * set board-specific scalar for max CPU frequency - * per CPU based on the LDO enabled Operating Ranges - * defined in the respective IMX6DQ and IMX6SDL - * datasheets. The voltage resulting from the R1/R2 - * feedback inputs on Ventana is 1308mV. Note that this - * is a bit shy of the Vmin of 1350mV in the datasheet - * for LDO enabled mode but is as high as we can go. - */ - switch (board) { - case GW560x: - /* mask PGOOD during SW3 transition */ - pmic_reg_write(p, LTC3676_DVB3B, - 0x1f | LTC3676_PGOOD_MASK); - /* set SW3 (VDD_ARM) */ - pmic_reg_write(p, LTC3676_DVB3A, 0x1f); - break; - case GW5903: - /* mask PGOOD during SW3 transition */ - pmic_reg_write(p, LTC3676_DVB3B, - 0x1f | LTC3676_PGOOD_MASK); - /* set SW3 (VDD_ARM) */ - pmic_reg_write(p, LTC3676_DVB3A, 0x1f); - - /* mask PGOOD during SW4 transition */ - pmic_reg_write(p, LTC3676_DVB4B, - 0x1f | LTC3676_PGOOD_MASK); - /* set SW4 (VDD_SOC) */ - pmic_reg_write(p, LTC3676_DVB4A, 0x1f); - break; - case GW5905: - /* mask PGOOD during SW1 transition */ - pmic_reg_write(p, LTC3676_DVB1B, - 0x1f | LTC3676_PGOOD_MASK); - /* set SW1 (VDD_ARM) */ - pmic_reg_write(p, LTC3676_DVB1A, 0x1f); - - /* mask PGOOD during SW3 transition */ - pmic_reg_write(p, LTC3676_DVB3B, - 0x1f | LTC3676_PGOOD_MASK); - /* set SW3 (VDD_SOC) */ - pmic_reg_write(p, LTC3676_DVB3A, 0x1f); - break; - default: - /* mask PGOOD during SW1 transition */ - pmic_reg_write(p, LTC3676_DVB1B, - 0x1f | LTC3676_PGOOD_MASK); - /* set SW1 (VDD_SOC) */ - pmic_reg_write(p, LTC3676_DVB1A, 0x1f); - - /* mask PGOOD during SW3 transition */ - pmic_reg_write(p, LTC3676_DVB3B, - 0x1f | LTC3676_PGOOD_MASK); - /* set SW3 (VDD_ARM) */ - pmic_reg_write(p, LTC3676_DVB3A, 0x1f); - } - } -} - -#ifdef CONFIG_FSL_ESDHC_IMX -static struct fsl_esdhc_cfg usdhc_cfg[2]; - -int board_mmc_init(struct bd_info *bis) -{ - struct ventana_board_info ventana_info; - int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); - int ret; - - switch (board_type) { - case GW52xx: - case GW53xx: - case GW54xx: - case GW553x: - /* usdhc3: 4bit microSD */ - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[0].max_bus_width = 4; - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); - case GW560x: - /* usdhc2: 8-bit eMMC */ - SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads); - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - usdhc_cfg[0].max_bus_width = 8; - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); - if (ret) - return ret; - /* usdhc3: 4-bit microSD */ - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].max_bus_width = 4; - return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); - case GW5903: - /* usdhc3: 8-bit eMMC */ - SETUP_IOMUX_PADS(gw5904_emmc_pads); - usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[0].max_bus_width = 8; - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); - if (ret) - return ret; - /* usdhc2: 4-bit microSD */ - SETUP_IOMUX_PADS(gw5904_mmc_pads); - usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR; - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - usdhc_cfg[1].max_bus_width = 4; - return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); - case GW5904: - case GW5905: - case GW5909: - /* usdhc3: 8bit eMMC */ - SETUP_IOMUX_PADS(gw5904_emmc_pads); - usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[0].max_bus_width = 8; - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); - default: - /* doesn't have MMC */ - return -1; - } -} - -int board_mmc_getcd(struct mmc *mmc) -{ - struct ventana_board_info ventana_info; - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info); - int gpio = gpio_cfg[board].mmc_cd; - - /* Card Detect */ - switch (board) { - case GW560x: - /* emmc is always present */ - if (cfg->esdhc_base == USDHC2_BASE_ADDR) - return 1; - break; - case GW5903: - case GW5904: - case GW5905: - case GW5909: - /* emmc is always present */ - if (cfg->esdhc_base == USDHC3_BASE_ADDR) - return 1; - break; - } - - if (gpio) { - debug("%s: gpio%d=%d\n", __func__, gpio, gpio_get_value(gpio)); - return !gpio_get_value(gpio); - } - - return -1; -} - -#endif /* CONFIG_FSL_ESDHC_IMX */ diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h deleted file mode 100644 index 5cec01c83827..000000000000 --- a/board/gateworks/gw_ventana/common.h +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Gateworks Corporation - * - * Author: Tim Harvey tharvey@gateworks.com - */ - -#ifndef _GWVENTANA_COMMON_H_ -#define _GWVENTANA_COMMON_H_ - -#include "ventana_eeprom.h" - -/* GPIO's common to all baseboards */ -#define GP_PHY_RST IMX_GPIO_NR(1, 30) -#define GP_RS232_EN IMX_GPIO_NR(2, 11) -#define GP_MSATA_SEL IMX_GPIO_NR(2, 8) - -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | \ - PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) - -#define DIO_PAD_CFG (MUX_PAD_CTRL(IRQ_PAD_CTRL) | MUX_MODE_SION) - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -/* - * each baseboard has an optional set user configurable Digital IO lines which - * can be pinmuxed as a GPIO or in some cases a PWM - */ -struct dio_cfg { - iomux_v3_cfg_t gpio_padmux[2]; - unsigned gpio_param; - iomux_v3_cfg_t pwm_padmux[2]; - unsigned pwm_param; -}; - -struct ventana { - /* pinmux */ - iomux_v3_cfg_t const *gpio_pads; - int num_pads; - /* DIO pinmux/val */ - struct dio_cfg *dio_cfg; - int dio_num; - /* various gpios (0 if non-existent) */ - int leds[3]; - int pcie_rst; - int mezz_pwren; - int mezz_irq; - int rs485en; - int gps_shdn; - int vidin_en; - int dioi2c_en; - int pcie_sson; - int usb_sel; - int wdis; - int msata_en; - int rs232_en; - int otgpwr_en; - int vsel_pin; - int mmc_cd; - /* various features */ - bool usd_vsel; - bool nand; -}; - -extern struct ventana gpio_cfg[GW_UNKNOWN]; - -/* configure i2c iomux */ -void setup_ventana_i2c(int); -/* configure uart iomux */ -void setup_iomux_uart(void); -/* conifgure PMIC */ -void setup_pmic(void); -/* configure gpio iomux/defaults */ -void setup_iomux_gpio(int board, struct ventana_board_info *); -/* late setup of GPIO (configuration per baseboard and env) */ -void setup_board_gpio(int board, struct ventana_board_info *); - -#endif /* #ifndef _GWVENTANA_COMMON_H_ */ diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c deleted file mode 100644 index a5a151d85b43..000000000000 --- a/board/gateworks/gw_ventana/eeprom.c +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014 Gateworks Corporation - * Author: Tim Harvey tharvey@gateworks.com - */ - -#include <common.h> -#include <command.h> -#include <errno.h> -#include <hexdump.h> -#include <i2c.h> -#include <log.h> -#include <malloc.h> -#include <asm/bitops.h> -#include <linux/delay.h> - -#include "gsc.h" -#include "ventana_eeprom.h" - -/* read ventana EEPROM, check for validity, and return baseboard type */ -int -read_eeprom(int bus, struct ventana_board_info *info) -{ - int i; - int chksum; - char baseboard; - int type; - unsigned char *buf = (unsigned char *)info; - - memset(info, 0, sizeof(*info)); - - /* - * On a board with a missing/depleted backup battery for GSC, the - * board may be ready to probe the GSC before its firmware is - * running. We will wait here indefinately for the GSC/EEPROM. - */ - while (1) { - if (0 == i2c_set_bus_num(bus) && - 0 == i2c_probe(GSC_EEPROM_ADDR)) - break; - mdelay(1); - } - - /* read eeprom config section */ - if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) { - puts("EEPROM: Failed to read EEPROM\n"); - return GW_UNKNOWN; - } - - /* sanity checks */ - if (info->model[0] != 'G' || info->model[1] != 'W') { - puts("EEPROM: Invalid Model in EEPROM\n"); - print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, - sizeof(*info)); - return GW_UNKNOWN; - } - - /* validate checksum */ - for (chksum = 0, i = 0; i < sizeof(*info)-2; i++) - chksum += buf[i]; - if ((info->chksum[0] != chksum>>8) || - (info->chksum[1] != (chksum&0xff))) { - puts("EEPROM: Failed EEPROM checksum\n"); - print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, - sizeof(*info)); - return GW_UNKNOWN; - } - - /* original GW5400-A prototype */ - baseboard = info->model[3]; - if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0) - baseboard = '0'; - - type = GW_UNKNOWN; - switch (baseboard) { - case '0': /* original GW5400-A prototype */ - type = GW54proto; - break; - case '1': - type = GW51xx; - break; - case '2': - type = GW52xx; - break; - case '3': - type = GW53xx; - break; - case '4': - type = GW54xx; - break; - case '5': - if (info->model[4] == '1') { - type = GW551x; - break; - } else if (info->model[4] == '2') { - type = GW552x; - break; - } else if (info->model[4] == '3') { - type = GW553x; - break; - } - break; - case '6': - if (info->model[4] == '0') - type = GW560x; - break; - case '9': - if (info->model[4] == '0' && info->model[5] == '1') - type = GW5901; - else if (info->model[4] == '0' && info->model[5] == '2') - type = GW5902; - else if (info->model[4] == '0' && info->model[5] == '3') - type = GW5903; - else if (info->model[4] == '0' && info->model[5] == '4') - type = GW5904; - else if (info->model[4] == '0' && info->model[5] == '5') - type = GW5905; - else if (info->model[4] == '0' && info->model[5] == '6') - type = GW5906; - else if (info->model[4] == '0' && info->model[5] == '7') - type = GW5907; - else if (info->model[4] == '0' && info->model[5] == '8') - type = GW5908; - else if (info->model[4] == '0' && info->model[5] == '9') - type = GW5909; - break; - default: - printf("EEPROM: Unknown model in EEPROM: %s\n", info->model); - print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, - sizeof(*info)); - break; - } - return type; -} - -/* list of config bits that the bootloader will remove from dtb if not set */ -struct ventana_eeprom_config econfig[] = { - { "eth0", "ethernet0", EECONFIG_ETH0 }, - { "usb0", NULL, EECONFIG_USB0 }, - { "usb1", NULL, EECONFIG_USB1 }, - { "mmc0", NULL, EECONFIG_SD0 }, - { "mmc1", NULL, EECONFIG_SD1 }, - { "mmc2", NULL, EECONFIG_SD2 }, - { "mmc3", NULL, EECONFIG_SD3 }, - { /* Sentinel */ } -}; - -#if defined(CONFIG_CMD_EECONFIG) && !defined(CONFIG_SPL_BUILD) -static struct ventana_eeprom_config *get_config(const char *name) -{ - struct ventana_eeprom_config *cfg = econfig; - - while (cfg->name) { - if (0 == strcmp(name, cfg->name)) - return cfg; - cfg++; - } - return NULL; -} - -static u8 econfig_bytes[sizeof(ventana_info.config)]; -static int econfig_init = -1; - -static int do_econfig(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - struct ventana_eeprom_config *cfg; - struct ventana_board_info *info = &ventana_info; - int i; - - if (argc < 2) - return CMD_RET_USAGE; - - /* initialize */ - if (econfig_init != 1) { - memcpy(econfig_bytes, info->config, sizeof(econfig_bytes)); - econfig_init = 1; - } - - /* list configs */ - if ((strncmp(argv[1], "list", 4) == 0)) { - cfg = econfig; - while (cfg->name) { - printf("%s: %d\n", cfg->name, - test_bit(cfg->bit, econfig_bytes) ? 1 : 0); - cfg++; - } - } - - /* save */ - else if ((strncmp(argv[1], "save", 4) == 0)) { - unsigned char *buf = (unsigned char *)info; - int chksum; - - /* calculate new checksum */ - memcpy(info->config, econfig_bytes, sizeof(econfig_bytes)); - for (chksum = 0, i = 0; i < sizeof(*info)-2; i++) - chksum += buf[i]; - debug("old chksum:0x%04x\n", - (info->chksum[0] << 8) | info->chksum[1]); - debug("new chksum:0x%04x\n", chksum); - info->chksum[0] = chksum >> 8; - info->chksum[1] = chksum & 0xff; - - /* write new config data */ - if (gsc_i2c_write(GSC_EEPROM_ADDR, info->config - (u8 *)info, - 1, econfig_bytes, sizeof(econfig_bytes))) { - printf("EEPROM: Failed updating config\n"); - return CMD_RET_FAILURE; - } - - /* write new config data */ - if (gsc_i2c_write(GSC_EEPROM_ADDR, info->chksum - (u8 *)info, - 1, info->chksum, 2)) { - printf("EEPROM: Failed updating checksum\n"); - return CMD_RET_FAILURE; - } - - printf("Config saved to EEPROM\n"); - } - - /* get config */ - else if (argc == 2) { - cfg = get_config(argv[1]); - if (cfg) { - printf("%s: %d\n", cfg->name, - test_bit(cfg->bit, econfig_bytes) ? 1 : 0); - } else { - printf("invalid config: %s\n", argv[1]); - return CMD_RET_FAILURE; - } - } - - /* set config */ - else if (argc == 3) { - cfg = get_config(argv[1]); - if (cfg) { - if (simple_strtol(argv[2], NULL, 10)) { - test_and_set_bit(cfg->bit, econfig_bytes); - printf("Enabled %s\n", cfg->name); - } else { - test_and_clear_bit(cfg->bit, econfig_bytes); - printf("Disabled %s\n", cfg->name); - } - } else { - printf("invalid config: %s\n", argv[1]); - return CMD_RET_FAILURE; - } - } - - else - return CMD_RET_USAGE; - - return CMD_RET_SUCCESS; -} - -U_BOOT_CMD( - econfig, 3, 0, do_econfig, - "EEPROM configuration", - "list - list config\n" - "save - save config to EEPROM\n" - "<name> - get config 'name'\n" - "<name> [0|1] - set config 'name' to value\n" -); - -#endif /* CONFIG_CMD_EECONFIG */ diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c deleted file mode 100644 index bcb6bca3462d..000000000000 --- a/board/gateworks/gw_ventana/gsc.c +++ /dev/null @@ -1,283 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Gateworks Corporation - * - * Author: Tim Harvey tharvey@gateworks.com - */ - -#include <common.h> -#include <command.h> -#include <log.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <common.h> -#include <i2c.h> -#include <linux/ctype.h> - -#include "ventana_eeprom.h" -#include "gsc.h" - -/* - * The Gateworks System Controller will fail to ACK a master transaction if - * it is busy, which can occur during its 1HZ timer tick while reading ADC's. - * When this does occur, it will never be busy long enough to fail more than - * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with - * 3 retries. - */ -int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) -{ - int retry = 3; - int n = 0; - int ret; - - while (n++ < retry) { - ret = i2c_read(chip, addr, alen, buf, len); - if (!ret) - break; - debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, - n, ret); - if (ret != -ENODEV) - break; - mdelay(10); - } - return ret; -} - -int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) -{ - int retry = 3; - int n = 0; - int ret; - - while (n++ < retry) { - ret = i2c_write(chip, addr, alen, buf, len); - if (!ret) - break; - debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, - n, ret); - if (ret != -ENODEV) - break; - mdelay(10); - } - mdelay(100); - return ret; -} - -static void read_hwmon(const char *name, uint reg, uint size) -{ - unsigned char buf[3]; - uint ui; - - printf("%-8s:", name); - memset(buf, 0, sizeof(buf)); - if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) { - puts("fRD\n"); - } else { - ui = buf[0] | (buf[1]<<8) | (buf[2]<<16); - if (size == 2 && ui > 0x8000) - ui -= 0xffff; - if (ui == 0xffffff) - puts("invalid\n"); - else - printf("%d\n", ui); - } -} - -int gsc_info(int verbose) -{ - unsigned char buf[16]; - - i2c_set_bus_num(0); - if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16)) - return CMD_RET_FAILURE; - - printf("GSC: v%d", buf[GSC_SC_FWVER]); - printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8); - printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN)) - ? "en" : "dis"); - if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) { - buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG); - puts(" WDT_RESET"); - gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, - &buf[GSC_SC_STATUS], 1); - } - if (!gsc_i2c_read(GSC_HWMON_ADDR, GSC_HWMON_TEMP, 1, buf, 2)) { - int ui = buf[0] | buf[1]<<8; - if (ui > 0x8000) - ui -= 0xffff; - printf(" board temp at %dC", ui / 10); - } - puts("\n"); - if (!verbose) - return CMD_RET_SUCCESS; - - read_hwmon("Temp", GSC_HWMON_TEMP, 2); - read_hwmon("VIN", GSC_HWMON_VIN, 3); - read_hwmon("VBATT", GSC_HWMON_VBATT, 3); - read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3); - read_hwmon("VDD_ARM", GSC_HWMON_VDD_CORE, 3); - read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); - read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3); - read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3); - read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3); - if (strncasecmp((const char*) ventana_info.model, "GW553", 5)) - read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3); - read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3); - read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3); - switch (ventana_info.model[3]) { - case '1': /* GW51xx */ - read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ - break; - case '2': /* GW52xx */ - break; - case '3': /* GW53xx */ - read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); /* -C rev */ - read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); - break; - case '4': /* GW54xx */ - read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ - read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); - break; - case '5': /* GW55xx */ - break; - case '6': /* GW560x */ - read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); - read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); - break; - case '9': /* GW590x */ - read_hwmon("AMONBMON", GSC_HWMON_VDD_IO3, 3); - read_hwmon("BAT_VOLT", GSC_HWMON_VDD_EXT, 3); - read_hwmon("BAT_TEMP", GSC_HWMON_VDD_IO4, 2); - } - return 0; -} - -/* - * The Gateworks System Controller implements a boot - * watchdog (always enabled) as a workaround for IMX6 boot related - * errata such as: - * ERR005768 - no fix scheduled - * ERR006282 - fixed in silicon r1.2 - * ERR007117 - fixed in silicon r1.3 - * ERR007220 - fixed in silicon r1.3 - * ERR007926 - no fix scheduled - * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf - * - * Disable the boot watchdog - */ -int gsc_boot_wd_disable(void) -{ - u8 reg; - - i2c_set_bus_num(CONFIG_I2C_GSC); - if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) { - reg |= (1 << GSC_SC_CTRL1_WDDIS); - if (!gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) - return 0; - } - puts("Error: could not disable GSC Watchdog\n"); - return 1; -} - -#if defined(CONFIG_CMD_GSC) && !defined(CONFIG_SPL_BUILD) -static int do_gsc_sleep(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - unsigned char reg; - unsigned long secs = 0; - - if (argc < 2) - return CMD_RET_USAGE; - - secs = simple_strtoul(argv[1], NULL, 10); - printf("GSC Sleeping for %ld seconds\n", secs); - - i2c_set_bus_num(0); - reg = (secs >> 24) & 0xff; - if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, ®, 1)) - goto error; - reg = (secs >> 16) & 0xff; - if (gsc_i2c_write(GSC_SC_ADDR, 8, 1, ®, 1)) - goto error; - reg = (secs >> 8) & 0xff; - if (gsc_i2c_write(GSC_SC_ADDR, 7, 1, ®, 1)) - goto error; - reg = secs & 0xff; - if (gsc_i2c_write(GSC_SC_ADDR, 6, 1, ®, 1)) - goto error; - if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) - goto error; - reg |= (1 << 2); - if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) - goto error; - reg &= ~(1 << 2); - reg |= 0x3; - if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) - goto error; - - return CMD_RET_SUCCESS; - -error: - printf("i2c error\n"); - return CMD_RET_FAILURE; -} - -static int do_gsc_wd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - unsigned char reg; - - if (argc < 2) - return CMD_RET_USAGE; - - if (strcasecmp(argv[1], "enable") == 0) { - int timeout = 0; - - if (argc > 2) - timeout = simple_strtoul(argv[2], NULL, 10); - i2c_set_bus_num(0); - if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) - return CMD_RET_FAILURE; - reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME)); - if (timeout == 60) - reg |= (1 << GSC_SC_CTRL1_WDTIME); - else - timeout = 30; - reg |= (1 << GSC_SC_CTRL1_WDEN); - if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) - return CMD_RET_FAILURE; - printf("GSC Watchdog enabled with timeout=%d seconds\n", - timeout); - } else if (strcasecmp(argv[1], "disable") == 0) { - i2c_set_bus_num(0); - if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) - return CMD_RET_FAILURE; - reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME)); - if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) - return CMD_RET_FAILURE; - printf("GSC Watchdog disabled\n"); - } else { - return CMD_RET_USAGE; - } - return CMD_RET_SUCCESS; -} - -static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - if (argc < 2) - return gsc_info(1); - - if (strcasecmp(argv[1], "wd") == 0) - return do_gsc_wd(cmdtp, flag, --argc, ++argv); - else if (strcasecmp(argv[1], "sleep") == 0) - return do_gsc_sleep(cmdtp, flag, --argc, ++argv); - - return CMD_RET_USAGE; -} - -U_BOOT_CMD( - gsc, 4, 1, do_gsc, "GSC configuration", - "[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n" - ); - -#endif /* CONFIG_CMD_GSC */ diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h deleted file mode 100644 index 6dcaafadf376..000000000000 --- a/board/gateworks/gw_ventana/gsc.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Gateworks Corporation - * - * Author: Tim Harvey tharvey@gateworks.com - */ - -#ifndef __ASSEMBLY__ - -/* i2c slave addresses */ -#define GSC_SC_ADDR 0x20 -#define GSC_RTC_ADDR 0x68 -#define GSC_HWMON_ADDR 0x29 -#define GSC_EEPROM_ADDR 0x51 - -/* System Controller registers */ -enum { - GSC_SC_CTRL0 = 0x00, - GSC_SC_CTRL1 = 0x01, - GSC_SC_STATUS = 0x0a, - GSC_SC_FWCRC = 0x0c, - GSC_SC_FWVER = 0x0e, -}; - -/* System Controller Control1 bits */ -enum { - GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */ - GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */ - GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */ -}; - -/* System Controller Interrupt bits */ -enum { - GSC_SC_IRQ_PB = 0, /* Pushbutton switch */ - GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */ - GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */ - GSC_SC_IRQ_GPIO = 4, /* GPIO change */ - GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */ - GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */ - GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */ -}; - -/* Hardware Monitor registers */ -enum { - GSC_HWMON_TEMP = 0x00, - GSC_HWMON_VIN = 0x02, - GSC_HWMON_VDD_3P3 = 0x05, - GSC_HWMON_VBATT = 0x08, - GSC_HWMON_VDD_5P0 = 0x0b, - GSC_HWMON_VDD_CORE = 0x0e, - GSC_HWMON_VDD_SOC = 0x11, - GSC_HWMON_VDD_HIGH = 0x14, - GSC_HWMON_VDD_DDR = 0x17, - GSC_HWMON_VDD_EXT = 0x1a, - GSC_HWMON_VDD_1P8 = 0x1d, - GSC_HWMON_VDD_IO2 = 0x20, - GSC_HWMON_VDD_2P5 = 0x23, - GSC_HWMON_VDD_IO3 = 0x26, - GSC_HWMON_VDD_IO4 = 0x29, -}; - -/* - * I2C transactions to the GSC are done via these functions which - * perform retries in the case of a busy GSC NAK'ing the transaction - */ -int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len); -int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len); -int gsc_info(int verbose); -int gsc_boot_wd_disable(void); -#endif - diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c deleted file mode 100644 index 048f624c3529..000000000000 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ /dev/null @@ -1,1381 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Gateworks Corporation - * - * Author: Tim Harvey tharvey@gateworks.com - */ - -#include <common.h> -#include <init.h> -#include <log.h> -#include <net.h> -#include <asm/arch/clock.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/sata.h> -#include <asm/mach-imx/spi.h> -#include <asm/mach-imx/video.h> -#include <asm/io.h> -#include <asm/setup.h> -#include <dm.h> -#include <dm/platform_data/serial_mxc.h> -#include <env.h> -#include <hwconfig.h> -#include <i2c.h> -#include <fdt_support.h> -#include <fsl_esdhc_imx.h> -#include <jffs2/load_kernel.h> -#include <linux/ctype.h> -#include <miiphy.h> -#include <mtd_node.h> -#include <netdev.h> -#include <pci.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <power/pmic.h> -#include <power/ltc3676_pmic.h> -#include <power/pfuze100_pmic.h> -#include <fdt_support.h> -#include <jffs2/load_kernel.h> -#include <spi_flash.h> - -#include "gsc.h" -#include "common.h" - -DECLARE_GLOBAL_DATA_PTR; - - -/* - * EEPROM board info struct populated by read_eeprom so that we only have to - * read it once. - */ -struct ventana_board_info ventana_info; - -static int board_type; - -/* ENET */ -static iomux_v3_cfg_t const enet_pads[] = { - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - /* PHY nRST */ - IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG), -}; - -#ifdef CONFIG_CMD_NAND -static iomux_v3_cfg_t const nfc_pads[] = { - IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - SETUP_IOMUX_PADS(nfc_pads); - - /* config gpmi and bch clock to 100 MHz */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); - - /* enable gpmi and bch clock gating */ - setbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} -#endif - -static void setup_iomux_enet(int gpio) -{ - SETUP_IOMUX_PADS(enet_pads); - - /* toggle PHY_RST# */ - gpio_request(gpio, "phy_rst#"); - gpio_direction_output(gpio, 0); - mdelay(10); - gpio_set_value(gpio, 1); - mdelay(100); -} - -#ifdef CONFIG_USB_EHCI_MX6 -static iomux_v3_cfg_t const usb_pads[] = { - IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG), - IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG), - /* OTG PWR */ - IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG), -}; - -int board_ehci_hcd_init(int port) -{ - int gpio; - - SETUP_IOMUX_PADS(usb_pads); - - /* Reset USB HUB */ - switch (board_type) { - case GW53xx: - case GW552x: - case GW5906: - gpio = (IMX_GPIO_NR(1, 9)); - break; - case GW54proto: - case GW54xx: - gpio = (IMX_GPIO_NR(1, 16)); - break; - default: - return 0; - } - - /* request and toggle hub rst */ - gpio_request(gpio, "usb_hub_rst#"); - gpio_direction_output(gpio, 0); - mdelay(2); - gpio_set_value(gpio, 1); - - return 0; -} - -int board_ehci_power(int port, int on) -{ - /* enable OTG VBUS */ - if (!port && board_type < GW_UNKNOWN) { - if (gpio_cfg[board_type].otgpwr_en) - gpio_set_value(gpio_cfg[board_type].otgpwr_en, on); - } - return 0; -} -#endif /* CONFIG_USB_EHCI_MX6 */ - -#ifdef CONFIG_MXC_SPI -iomux_v3_cfg_t const ecspi1_pads[] = { - /* SS1 */ - IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), -}; - -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1; -} - -static void setup_spi(void) -{ - gpio_request(IMX_GPIO_NR(3, 19), "spi_cs"); - gpio_direction_output(IMX_GPIO_NR(3, 19), 1); - SETUP_IOMUX_PADS(ecspi1_pads); -} -#endif - -/* configure eth0 PHY board-specific LED behavior */ -int board_phy_config(struct phy_device *phydev) -{ - unsigned short val; - - /* Marvel 88E1510 */ - if (phydev->phy_id == 0x1410dd1) { - /* - * Page 3, Register 16: LED[2:0] Function Control Register - * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link - * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity - */ - phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); - val = phy_read(phydev, MDIO_DEVAD_NONE, 16); - val &= 0xff00; - val |= 0x0017; - phy_write(phydev, MDIO_DEVAD_NONE, 16, val); - phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); - } - - /* TI DP83867 */ - else if (phydev->phy_id == 0x2000a231) { - /* configure register 0x170 for ref CLKOUT */ - phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f); - phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170); - phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f); - val = phy_read(phydev, MDIO_DEVAD_NONE, 14); - val &= ~0x1f00; - val |= 0x0b00; /* chD tx clock*/ - phy_write(phydev, MDIO_DEVAD_NONE, 14, val); - } - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -#ifdef CONFIG_MV88E61XX_SWITCH -int mv88e61xx_hw_reset(struct phy_device *phydev) -{ - struct mii_dev *bus = phydev->bus; - - /* GPIO[0] output, CLK125 */ - debug("enabling RGMII_REFCLK\n"); - bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0, - 0x1a /*MV_SCRATCH_MISC*/, - (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe); - bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0, - 0x1a /*MV_SCRATCH_MISC*/, - (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7); - - /* RGMII delay - Physical Control register bit[15:14] */ - debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT); - /* forced 1000mbps full-duplex link */ - bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe); - phydev->autoneg = AUTONEG_DISABLE; - phydev->speed = SPEED_1000; - phydev->duplex = DUPLEX_FULL; - - /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */ - bus->write(bus, 0x10, 0, 0x16, 0x8088); - bus->write(bus, 0x11, 0, 0x16, 0x8088); - bus->write(bus, 0x12, 0, 0x16, 0x8088); - bus->write(bus, 0x13, 0, 0x16, 0x8088); - - return 0; -} -#endif // CONFIG_MV88E61XX_SWITCH - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FEC_MXC - struct ventana_board_info *info = &ventana_info; - - if (test_bit(EECONFIG_ETH0, info->config)) { - setup_iomux_enet(GP_PHY_RST); - cpu_eth_init(bis); - } -#endif - -#ifdef CONFIG_E1000 - e1000_initialize(bis); -#endif - -#ifdef CONFIG_CI_UDC - /* For otg ethernet*/ - usb_eth_initialize(bis); -#endif - - /* default to the first detected enet dev */ - if (!env_get("ethprime")) { - struct eth_device *dev = eth_get_dev_by_index(0); - if (dev) { - env_set("ethprime", dev->name); - printf("set ethprime to %s\n", env_get("ethprime")); - } - } - - return 0; -} - -#if defined(CONFIG_VIDEO_IPUV3) - -static void enable_hdmi(struct display_info_t const *dev) -{ - imx_enable_hdmi_phy(); -} - -static int detect_i2c(struct display_info_t const *dev) -{ - return i2c_set_bus_num(dev->bus) == 0 && - i2c_probe(dev->addr) == 0; -} - -static void enable_lvds(struct display_info_t const *dev) -{ - struct iomuxc *iomux = (struct iomuxc *) - IOMUXC_BASE_ADDR; - - /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */ - u32 reg = readl(&iomux->gpr[2]); - reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; - writel(reg, &iomux->gpr[2]); - - /* Enable Backlight */ - gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio"); - gpio_direction_output(IMX_GPIO_NR(1, 10), 0); - gpio_request(IMX_GPIO_NR(1, 18), "bklt_en"); - SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG); - gpio_direction_output(IMX_GPIO_NR(1, 18), 1); -} - -struct display_info_t const displays[] = {{ - /* HDMI Output */ - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = enable_hdmi, - .mode = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} }, { - /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */ - .bus = 2, - .addr = 0x4, - .pixfmt = IPU_PIX_FMT_LVDS666, - .detect = detect_i2c, - .enable = enable_lvds, - .mode = { - .name = "Hannstar-XGA", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} }, { - /* DLC700JMG-T-4 */ - .bus = 2, - .addr = 0x38, - .detect = NULL, - .enable = enable_lvds, - .pixfmt = IPU_PIX_FMT_LVDS666, - .mode = { - .name = "DLC700JMGT4", - .refresh = 60, - .xres = 1024, /* 1024x600active pixels */ - .yres = 600, - .pixclock = 15385, /* 64MHz */ - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} }, { - /* DLC800FIG-T-3 */ - .bus = 2, - .addr = 0x14, - .detect = NULL, - .enable = enable_lvds, - .pixfmt = IPU_PIX_FMT_LVDS666, - .mode = { - .name = "DLC800FIGT3", - .refresh = 60, - .xres = 1024, /* 1024x768 active pixels */ - .yres = 768, - .pixclock = 15385, /* 64MHz */ - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} }, { - .bus = 2, - .addr = 0x5d, - .detect = detect_i2c, - .enable = enable_lvds, - .pixfmt = IPU_PIX_FMT_LVDS666, - .mode = { - .name = "Z101WX01", - .refresh = 60, - .xres = 1280, - .yres = 800, - .pixclock = 15385, /* 64MHz */ - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED - } -}, -}; -size_t display_count = ARRAY_SIZE(displays); - -static void setup_display(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - int reg; - - enable_ipu_clock(); - imx_setup_hdmi(); - /* Turn on LDB0,IPU,IPU DI0 clocks */ - reg = __raw_readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; - writel(reg, &mxc_ccm->CCGR3); - - /* set LDB0, LDB1 clk select to 011/011 */ - reg = readl(&mxc_ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK - |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) - |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); - writel(reg, &mxc_ccm->cs2cdr); - - reg = readl(&mxc_ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; - writel(reg, &mxc_ccm->cscmr2); - - reg = readl(&mxc_ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - writel(reg, &mxc_ccm->chsccdr); - - reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES - |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH - |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW - |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG - |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT - |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG - |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT - |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED - |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; - writel(reg, &iomux->gpr[2]); - - reg = readl(&iomux->gpr[3]); - reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 - <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); - writel(reg, &iomux->gpr[3]); - - /* LVDS Backlight GPIO on LVDS connector - output low */ - SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG); - gpio_direction_output(IMX_GPIO_NR(1, 10), 0); -} -#endif /* CONFIG_VIDEO_IPUV3 */ - -/* setup board specific PMIC */ -int power_init_board(void) -{ - setup_pmic(); - return 0; -} - -#if defined(CONFIG_CMD_PCI) -int imx6_pcie_toggle_reset(void) -{ - if (board_type < GW_UNKNOWN) { - uint pin = gpio_cfg[board_type].pcie_rst; - gpio_request(pin, "pci_rst#"); - gpio_direction_output(pin, 0); - mdelay(50); - gpio_direction_output(pin, 1); - } - return 0; -} - -/* - * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its - * GPIO's as PERST# signals for its downstream ports - configure the GPIO's - * properly and assert reset for 100ms. - */ -#define MAX_PCI_DEVS 32 -struct pci_dev { - pci_dev_t devfn; - unsigned short vendor; - unsigned short device; - unsigned short class; - unsigned short busno; /* subbordinate busno */ - struct pci_dev *ppar; -}; -struct pci_dev pci_devs[MAX_PCI_DEVS]; -int pci_devno; -int pci_bridgeno; - -void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, - unsigned short vendor, unsigned short device, - unsigned short class) -{ - int i; - u32 dw; - struct pci_dev *pdev = &pci_devs[pci_devno++]; - - debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__, - PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device); - - /* store array of devs for later use in device-tree fixup */ - pdev->devfn = dev; - pdev->vendor = vendor; - pdev->device = device; - pdev->class = class; - pdev->ppar = NULL; - if (class == PCI_CLASS_BRIDGE_PCI) - pdev->busno = ++pci_bridgeno; - else - pdev->busno = 0; - - /* fixup RC - it should be 00:00.0 not 00:01.0 */ - if (PCI_BUS(dev) == 0) - pdev->devfn = 0; - - /* find dev's parent */ - for (i = 0; i < pci_devno; i++) { - if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) { - pdev->ppar = &pci_devs[i]; - break; - } - } - - /* assert downstream PERST# */ - if (vendor == PCI_VENDOR_ID_PLX && - (device & 0xfff0) == 0x8600 && - PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) { - debug("configuring PLX 860X downstream PERST#\n"); - pci_hose_read_config_dword(hose, dev, 0x62c, &dw); - dw |= 0xaaa8; /* GPIO1-7 outputs */ - pci_hose_write_config_dword(hose, dev, 0x62c, dw); - - pci_hose_read_config_dword(hose, dev, 0x644, &dw); - dw |= 0xfe; /* GPIO1-7 output high */ - pci_hose_write_config_dword(hose, dev, 0x644, dw); - - mdelay(100); - } -} -#endif /* CONFIG_CMD_PCI */ - -#ifdef CONFIG_SERIAL_TAG -/* - * called when setting up ATAGS before booting kernel - * populate serialnum from the following (in order of priority): - * serial# env var - * eeprom - */ -void get_board_serial(struct tag_serialnr *serialnr) -{ - char *serial = env_get("serial#"); - - if (serial) { - serialnr->high = 0; - serialnr->low = simple_strtoul(serial, NULL, 10); - } else if (ventana_info.model[0]) { - serialnr->high = 0; - serialnr->low = ventana_info.serial; - } else { - serialnr->high = 0; - serialnr->low = 0; - } -} -#endif - -/* - * Board Support - */ - -int board_early_init_f(void) -{ - setup_iomux_uart(); - -#if defined(CONFIG_VIDEO_IPUV3) - setup_display(); -#endif - return 0; -} - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - return 0; -} - -int board_init(void) -{ - struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - - clrsetbits_le32(&iomuxc_regs->gpr[1], - IOMUXC_GPR1_OTG_ID_MASK, - IOMUXC_GPR1_OTG_ID_GPIO1); - - /* address of linux boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - /* read Gateworks EEPROM into global struct (used later) */ - setup_ventana_i2c(0); - board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); - -#ifdef CONFIG_CMD_NAND - if (gpio_cfg[board_type].nand) - setup_gpmi_nand(); -#endif -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif - setup_ventana_i2c(1); - setup_ventana_i2c(2); - -#ifdef CONFIG_SATA - setup_sata(); -#endif - - setup_iomux_gpio(board_type, &ventana_info); - - return 0; -} - -#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) -/* - * called during late init (after relocation and after board_init()) - * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and - * EEPROM read. - */ -int checkboard(void) -{ - struct ventana_board_info *info = &ventana_info; - unsigned char buf[4]; - const char *p; - int quiet; /* Quiet or minimal output mode */ - - quiet = 0; - p = env_get("quiet"); - if (p) - quiet = simple_strtol(p, NULL, 10); - else - env_set("quiet", "0"); - - puts("\nGateworks Corporation Copyright 2014\n"); - if (info->model[0]) { - printf("Model: %s\n", info->model); - printf("MFGDate: %02x-%02x-%02x%02x\n", - info->mfgdate[0], info->mfgdate[1], - info->mfgdate[2], info->mfgdate[3]); - printf("Serial:%d\n", info->serial); - } else { - puts("Invalid EEPROM - board will not function fully\n"); - } - if (quiet) - return 0; - - /* Display GSC firmware revision/CRC/status */ - gsc_info(0); - - /* Display RTC */ - if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) { - printf("RTC: %d\n", - buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24); - } - - return 0; -} -#endif - -#ifdef CONFIG_CMD_BMODE -/* - * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 - * see Table 8-11 and Table 5-9 - * BOOT_CFG1[7] = 1 (boot from NAND) - * BOOT_CFG1[5] = 0 - raw NAND - * BOOT_CFG1[4] = 0 - default pad settings - * BOOT_CFG1[3:2] = 00 - devices = 1 - * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 - * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 - * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 - * BOOT_CFG2[0] = 0 - Reset time 12ms - */ -static const struct boot_mode board_boot_modes[] = { - /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ - { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, - { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */ - { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */ - { NULL, 0 }, -}; -#endif - -/* late init */ -int misc_init_r(void) -{ - struct ventana_board_info *info = &ventana_info; - char buf[256]; - int i; - - /* set env vars based on EEPROM data */ - if (ventana_info.model[0]) { - char str[16], fdt[36]; - char *p; - const char *cputype = ""; - - /* - * FDT name will be prefixed with CPU type. Three versions - * will be created each increasingly generic and bootloader - * env scripts will try loading each from most specific to - * least. - */ - if (is_cpu_type(MXC_CPU_MX6Q) || - is_cpu_type(MXC_CPU_MX6D)) - cputype = "imx6q"; - else if (is_cpu_type(MXC_CPU_MX6DL) || - is_cpu_type(MXC_CPU_MX6SOLO)) - cputype = "imx6dl"; - env_set("soctype", cputype); - if (8 << (ventana_info.nand_flash_size-1) >= 2048) - env_set("flash_layout", "large"); - else - env_set("flash_layout", "normal"); - memset(str, 0, sizeof(str)); - for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++) - str[i] = tolower(info->model[i]); - env_set("model", str); - if (!env_get("fdt_file")) { - sprintf(fdt, "%s-%s.dtb", cputype, str); - env_set("fdt_file", fdt); - } - p = strchr(str, '-'); - if (p) { - *p++ = 0; - - env_set("model_base", str); - sprintf(fdt, "%s-%s.dtb", cputype, str); - env_set("fdt_file1", fdt); - if (board_type != GW551x && - board_type != GW552x && - board_type != GW553x && - board_type != GW560x) - str[4] = 'x'; - str[5] = 'x'; - str[6] = 0; - sprintf(fdt, "%s-%s.dtb", cputype, str); - env_set("fdt_file2", fdt); - } - - /* initialize env from EEPROM */ - if (test_bit(EECONFIG_ETH0, info->config) && - !env_get("ethaddr")) { - eth_env_set_enetaddr("ethaddr", info->mac0); - } - if (test_bit(EECONFIG_ETH1, info->config) && - !env_get("eth1addr")) { - eth_env_set_enetaddr("eth1addr", info->mac1); - } - - /* board serial-number */ - sprintf(str, "%6d", info->serial); - env_set("serial#", str); - - /* memory MB */ - sprintf(str, "%d", (int) (gd->ram_size >> 20)); - env_set("mem_mb", str); - } - - /* Set a non-initialized hwconfig based on board configuration */ - if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) { - buf[0] = 0; - if (gpio_cfg[board_type].rs232_en) - strcat(buf, "rs232;"); - for (i = 0; i < gpio_cfg[board_type].dio_num; i++) { - char buf1[32]; - sprintf(buf1, "dio%d:mode=gpio;", i); - if (strlen(buf) + strlen(buf1) < sizeof(buf)) - strcat(buf, buf1); - } - env_set("hwconfig", buf); - } - - /* setup baseboard specific GPIO based on board and env */ - setup_board_gpio(board_type, info); - -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - - /* disable boot watchdog */ - gsc_boot_wd_disable(); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP - -static int ft_sethdmiinfmt(void *blob, char *mode) -{ - int off; - - if (!mode) - return -EINVAL; - - off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x"); - if (off < 0) - return off; - - if (0 == strcasecmp(mode, "yuv422bt656")) { - u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00, - 0x00, 0x00, 0x00 }; - mode = "422_ccir"; - fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1); - fdt_setprop_u32(blob, off, "vidout_trc", 1); - fdt_setprop_u32(blob, off, "vidout_blc", 1); - fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg)); - printf(" set HDMI input mode to %s\n", mode); - } else if (0 == strcasecmp(mode, "yuv422smp")) { - u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00, - 0x82, 0x81, 0x00 }; - mode = "422_smp"; - fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1); - fdt_setprop_u32(blob, off, "vidout_trc", 0); - fdt_setprop_u32(blob, off, "vidout_blc", 0); - fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg)); - printf(" set HDMI input mode to %s\n", mode); - } else { - return -EINVAL; - } - - return 0; -} - -#if defined(CONFIG_CMD_PCI) -#define PCI_ID(x) ( \ - (PCI_BUS(x->devfn)<<16)| \ - (PCI_DEV(x->devfn)<<11)| \ - (PCI_FUNC(x->devfn)<<8) \ - ) -int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev) -{ - uint32_t reg[5]; - char node[32]; - int np; - - sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn), - PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn)); - - np = fdt_subnode_offset(blob, par, node); - if (np >= 0) - return np; - np = fdt_add_subnode(blob, par, node); - if (np < 0) { - printf(" %s failed: no space\n", __func__); - return np; - } - - memset(reg, 0, sizeof(reg)); - reg[0] = cpu_to_fdt32(PCI_ID(dev)); - fdt_setprop(blob, np, "reg", reg, sizeof(reg)); - - return np; -} - -/* build a path of nested PCI devs for all bridges passed through */ -int fdt_add_pci_path(void *blob, struct pci_dev *dev) -{ - struct pci_dev *bridges[MAX_PCI_DEVS]; - int k, np; - - /* build list of parents */ - np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie"); - if (np < 0) - return np; - - k = 0; - while (dev) { - bridges[k++] = dev; - dev = dev->ppar; - }; - - /* now add them the to DT in reverse order */ - while (k--) { - np = fdt_add_pci_node(blob, np, bridges[k]); - if (np < 0) - break; - } - - return np; -} - -/* - * The GW16082 has a hardware errata errata such that it's - * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because - * of this normal PCI interrupt swizzling will not work so we will - * provide an irq-map via device-tree. - */ -int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev) -{ - int len; - int host; - uint32_t imap_new[8*4*4]; - const uint32_t *imap; - uint32_t irq[4]; - uint32_t reg[4]; - int i; - - /* build irq-map based on host controllers map */ - host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie"); - if (host < 0) { - printf(" %s failed: missing host\n", __func__); - return host; - } - - /* use interrupt data from root complex's node */ - imap = fdt_getprop(blob, host, "interrupt-map", &len); - if (!imap || len != 128) { - printf(" %s failed: invalid interrupt-map\n", - __func__); - return -FDT_ERR_NOTFOUND; - } - - /* obtain irq's of host controller in pin order */ - for (i = 0; i < 4; i++) - irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6]; - - /* - * determine number of swizzles necessary: - * For each bridge we pass through we need to swizzle - * the number of the slot we are on. - */ - struct pci_dev *d; - int b; - b = 0; - d = dev->ppar; - while(d && d->ppar) { - b += PCI_DEV(d->devfn); - d = d->ppar; - } - - /* create new irq mappings for slots12-15 - * <skt> <idsel> <slot> <skt-inta> <skt-intb> - * J3 AD28 12 INTD INTA - * J4 AD29 13 INTC INTD - * J5 AD30 14 INTB INTC - * J2 AD31 15 INTA INTB - */ - for (i = 0; i < 4; i++) { - /* addr matches bus:dev:func */ - u32 addr = dev->busno << 16 | (12+i) << 11; - - /* default cells from root complex */ - memcpy(&imap_new[i*32], imap, 128); - /* first cell is PCI device address (BDF) */ - imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr); - imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr); - imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr); - imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr); - /* third cell is pin */ - imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1); - imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2); - imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3); - imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4); - /* sixth cell is relative interrupt */ - imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4]; - imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4]; - imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4]; - imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4]; - } - fdt_setprop(blob, np, "interrupt-map", imap_new, - sizeof(imap_new)); - reg[0] = cpu_to_fdt32(0xfff00); - reg[1] = 0; - reg[2] = 0; - reg[3] = cpu_to_fdt32(0x7); - fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg)); - fdt_setprop_cell(blob, np, "#interrupt-cells", 1); - fdt_setprop_string(blob, np, "device_type", "pci"); - fdt_setprop_cell(blob, np, "#address-cells", 3); - fdt_setprop_cell(blob, np, "#size-cells", 2); - printf(" Added custom interrupt-map for GW16082\n"); - - return 0; -} - -/* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */ -int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev) -{ - char *tmp, *end; - char mac[16]; - unsigned char mac_addr[6]; - int j; - - sprintf(mac, "eth1addr"); - tmp = env_get(mac); - if (tmp) { - for (j = 0; j < 6; j++) { - mac_addr[j] = tmp ? - simple_strtoul(tmp, &end,16) : 0; - if (tmp) - tmp = (*end) ? end+1 : end; - } - fdt_setprop(blob, np, "local-mac-address", mac_addr, - sizeof(mac_addr)); - printf(" Added mac addr for eth1\n"); - return 0; - } - - return -1; -} - -/* - * PCI DT nodes must be nested therefore if we need to apply a DT fixup - * we will walk the PCI bus and add bridge nodes up to the device receiving - * the fixup. - */ -void ft_board_pci_fixup(void *blob, struct bd_info *bd) -{ - int i, np; - struct pci_dev *dev; - - for (i = 0; i < pci_devno; i++) { - dev = &pci_devs[i]; - - /* - * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and - * an EEPROM at i2c1-0x50. - */ - if ((dev->vendor == PCI_VENDOR_ID_TI) && - (dev->device == 0x8240) && - (i2c_set_bus_num(1) == 0) && - (i2c_probe(0x50) == 0)) - { - np = fdt_add_pci_path(blob, dev); - if (np > 0) - fdt_fixup_gw16082(blob, np, dev); - } - - /* ethernet1 mac address */ - else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) && - (dev->device == 0x4380)) - { - np = fdt_add_pci_path(blob, dev); - if (np > 0) - fdt_fixup_sky2(blob, np, dev); - } - } -} -#endif /* if defined(CONFIG_CMD_PCI) */ - -void ft_board_wdog_fixup(void *blob, phys_addr_t addr) -{ - int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr); - - if (off) { - fdt_delprop(blob, off, "ext-reset-output"); - fdt_delprop(blob, off, "fsl,ext-reset-output"); - } -} - -/* - * called prior to booting kernel or by 'fdt boardsetup' command - * - * unless 'fdt_noauto' env var is set we will update the following in the DTB: - * - mtd partitions based on mtdparts/mtdids env - * - system-serial (board serial num from EEPROM) - * - board (full model from EEPROM) - * - peripherals removed from DTB if not loaded on board (per EEPROM config) - */ -#define WDOG1_ADDR 0x20bc000 -#define WDOG2_ADDR 0x20c0000 -#define GPIO3_ADDR 0x20a4000 -#define USDHC3_ADDR 0x2198000 -#define PWM0_ADDR 0x2080000 -int ft_board_setup(void *blob, struct bd_info *bd) -{ - struct ventana_board_info *info = &ventana_info; - struct ventana_eeprom_config *cfg; - static const struct node_info nodes[] = { - { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */ - { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ - }; - const char *model = env_get("model"); - const char *display = env_get("display"); - int i; - char rev = 0; - - /* determine board revision */ - for (i = sizeof(ventana_info.model) - 1; i > 0; i--) { - if (ventana_info.model[i] >= 'A') { - rev = ventana_info.model[i]; - break; - } - } - - if (env_get("fdt_noauto")) { - puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); - return 0; - } - - if (test_bit(EECONFIG_NAND, info->config)) { - /* Update partition nodes using info from mtdparts env var */ - puts(" Updating MTD partitions...\n"); - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); - } - - /* Update display timings from display env var */ - if (display) { - if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"), - display) >= 0) - printf(" Set display timings for %s...\n", display); - } - - printf(" Adjusting FDT per EEPROM for %s...\n", model); - - /* board serial number */ - fdt_setprop(blob, 0, "system-serial", env_get("serial#"), - strlen(env_get("serial#")) + 1); - - /* board (model contains model from device-tree) */ - fdt_setprop(blob, 0, "board", info->model, - strlen((const char *)info->model) + 1); - - /* set desired digital video capture format */ - ft_sethdmiinfmt(blob, env_get("hdmiinfmt")); - - /* - * Board model specific fixups - */ - switch (board_type) { - case GW51xx: - /* - * disable wdog node for GW51xx-A/B to work around - * errata causing wdog timer to be unreliable. - */ - if (rev >= 'A' && rev < 'C') { - i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", - WDOG1_ADDR); - if (i) - fdt_status_disabled(blob, i); - } - - /* GW51xx-E adds WDOG1_B external reset */ - if (rev < 'E') - ft_board_wdog_fixup(blob, WDOG1_ADDR); - break; - - case GW52xx: - /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */ - if (info->model[4] == '2') { - u32 handle = 0; - u32 *range = NULL; - - i = fdt_node_offset_by_compatible(blob, -1, - "fsl,imx6q-pcie"); - if (i) - range = (u32 *)fdt_getprop(blob, i, - "reset-gpio", NULL); - - if (range) { - i = fdt_node_offset_by_compat_reg(blob, - "fsl,imx6q-gpio", GPIO3_ADDR); - if (i) - handle = fdt_get_phandle(blob, i); - if (handle) { - range[0] = cpu_to_fdt32(handle); - range[1] = cpu_to_fdt32(23); - } - } - - /* these have broken usd_vsel */ - if (strstr((const char *)info->model, "SP318-B") || - strstr((const char *)info->model, "SP331-B")) - gpio_cfg[board_type].usd_vsel = 0; - - /* GW522x-B adds WDOG1_B external reset */ - if (rev < 'B') - ft_board_wdog_fixup(blob, WDOG1_ADDR); - } - - /* GW520x-E adds WDOG1_B external reset */ - else if (info->model[4] == '0' && rev < 'E') - ft_board_wdog_fixup(blob, WDOG1_ADDR); - break; - - case GW53xx: - /* GW53xx-E adds WDOG1_B external reset */ - if (rev < 'E') - ft_board_wdog_fixup(blob, WDOG1_ADDR); - break; - - case GW54xx: - /* - * disable serial2 node for GW54xx for compatibility with older - * 3.10.x kernel that improperly had this node enabled in the DT - */ - fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED, - 0); - - /* GW54xx-E adds WDOG2_B external reset */ - if (rev < 'E') - ft_board_wdog_fixup(blob, WDOG2_ADDR); - break; - - case GW551x: - /* - * isolate CSI0_DATA_EN for GW551x-A to work around errata - * causing non functional digital video in (it is not hooked up) - */ - if (rev == 'A') { - u32 *range = NULL; - int len; - const u32 *handle = NULL; - - i = fdt_node_offset_by_compatible(blob, -1, - "fsl,imx-tda1997x-video"); - if (i) - handle = fdt_getprop(blob, i, "pinctrl-0", - NULL); - if (handle) - i = fdt_node_offset_by_phandle(blob, - fdt32_to_cpu(*handle)); - if (i) - range = (u32 *)fdt_getprop(blob, i, "fsl,pins", - &len); - if (range) { - len /= sizeof(u32); - for (i = 0; i < len; i += 6) { - u32 mux_reg = fdt32_to_cpu(range[i+0]); - u32 conf_reg = fdt32_to_cpu(range[i+1]); - /* mux PAD_CSI0_DATA_EN to GPIO */ - if (is_cpu_type(MXC_CPU_MX6Q) && - mux_reg == 0x260 && - conf_reg == 0x630) - range[i+3] = cpu_to_fdt32(0x5); - else if (!is_cpu_type(MXC_CPU_MX6Q) && - mux_reg == 0x08c && - conf_reg == 0x3a0) - range[i+3] = cpu_to_fdt32(0x5); - } - fdt_setprop_inplace(blob, i, "fsl,pins", range, - len); - } - - /* set BT656 video format */ - ft_sethdmiinfmt(blob, "yuv422bt656"); - } - - /* GW551x-C adds WDOG1_B external reset */ - if (rev < 'C') - ft_board_wdog_fixup(blob, WDOG1_ADDR); - break; - case GW5901: - case GW5902: - /* GW5901/GW5901 revB adds WDOG1_B as an external reset */ - if (rev < 'B') - ft_board_wdog_fixup(blob, WDOG1_ADDR); - break; - } - - /* Configure DIO */ - for (i = 0; i < gpio_cfg[board_type].dio_num; i++) { - struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i]; - char arg[10]; - - sprintf(arg, "dio%d", i); - if (!hwconfig(arg)) - continue; - if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param) - { - phys_addr_t addr; - int off; - - printf(" Enabling pwm%d for DIO%d\n", - cfg->pwm_param, i); - addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1)); - off = fdt_node_offset_by_compat_reg(blob, - "fsl,imx6q-pwm", - addr); - if (off) - fdt_status_okay(blob, off); - } - } - - /* remove no-1-8-v if UHS-I support is present */ - if (gpio_cfg[board_type].usd_vsel) { - debug("Enabling UHS-I support\n"); - i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc", - USDHC3_ADDR); - if (i) - fdt_delprop(blob, i, "no-1-8-v"); - } - -#if defined(CONFIG_CMD_PCI) - if (!env_get("nopcifixup")) - ft_board_pci_fixup(blob, bd); -#endif - - /* - * Peripheral Config: - * remove nodes by alias path if EEPROM config tells us the - * peripheral is not loaded on the board. - */ - if (env_get("fdt_noconfig")) { - puts(" Skiping periperhal config (fdt_noconfig defined)\n"); - return 0; - } - cfg = econfig; - while (cfg->name) { - if (!test_bit(cfg->bit, info->config)) { - fdt_del_node_and_alias(blob, cfg->dtalias ? - cfg->dtalias : cfg->name); - } - cfg++; - } - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -static struct mxc_serial_plat ventana_mxc_serial_plat = { - .reg = (struct mxc_uart *)UART2_BASE, -}; - -U_BOOT_DRVINFO(ventana_serial) = { - .name = "serial_mxc", - .plat = &ventana_mxc_serial_plat, -}; diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c deleted file mode 100644 index e0e4bac16126..000000000000 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ /dev/null @@ -1,779 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014 Gateworks Corporation - * Author: Tim Harvey tharvey@gateworks.com - */ - -#include <common.h> -#include <env.h> -#include <hang.h> -#include <init.h> -#include <log.h> -#include <asm/io.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/mx6-ddr.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <env.h> -#include <i2c.h> -#include <spl.h> - -#include "gsc.h" -#include "common.h" - -#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ -#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */ -#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */ - -/* configure MX6Q/DUAL mmdc DDR io registers */ -struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { - /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ - .dram_sdclk_0 = 0x00020030, - .dram_sdclk_1 = 0x00020030, - .dram_cas = 0x00020030, - .dram_ras = 0x00020030, - .dram_reset = 0x00020030, - /* SDCKE[0:1]: 100k pull-up */ - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - /* SDBA2: pull-up disabled */ - .dram_sdba2 = 0x00000000, - /* SDODT[0:1]: 100k pull-up, 40 ohm */ - .dram_sdodt0 = 0x00003030, - .dram_sdodt1 = 0x00003030, - /* SDQS[0:7]: Differential input, 40 ohm */ - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_sdqs2 = 0x00000030, - .dram_sdqs3 = 0x00000030, - .dram_sdqs4 = 0x00000030, - .dram_sdqs5 = 0x00000030, - .dram_sdqs6 = 0x00000030, - .dram_sdqs7 = 0x00000030, - - /* DQM[0:7]: Differential input, 40 ohm */ - .dram_dqm0 = 0x00020030, - .dram_dqm1 = 0x00020030, - .dram_dqm2 = 0x00020030, - .dram_dqm3 = 0x00020030, - .dram_dqm4 = 0x00020030, - .dram_dqm5 = 0x00020030, - .dram_dqm6 = 0x00020030, - .dram_dqm7 = 0x00020030, -}; - -/* configure MX6Q/DUAL mmdc GRP io registers */ -struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { - /* DDR3 */ - .grp_ddr_type = 0x000c0000, - .grp_ddrmode_ctl = 0x00020000, - /* disable DDR pullups */ - .grp_ddrpke = 0x00000000, - /* ADDR[00:16], SDBA[0:1]: 40 ohm */ - .grp_addds = 0x00000030, - /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ - .grp_ctlds = 0x00000030, - /* DATA[00:63]: Differential input, 40 ohm */ - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_b2ds = 0x00000030, - .grp_b3ds = 0x00000030, - .grp_b4ds = 0x00000030, - .grp_b5ds = 0x00000030, - .grp_b6ds = 0x00000030, - .grp_b7ds = 0x00000030, -}; - -/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ -struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { - /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ - .dram_sdclk_0 = 0x00020030, - .dram_sdclk_1 = 0x00020030, - .dram_cas = 0x00020030, - .dram_ras = 0x00020030, - .dram_reset = 0x00020030, - /* SDCKE[0:1]: 100k pull-up */ - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - /* SDBA2: pull-up disabled */ - .dram_sdba2 = 0x00000000, - /* SDODT[0:1]: 100k pull-up, 40 ohm */ - .dram_sdodt0 = 0x00003030, - .dram_sdodt1 = 0x00003030, - /* SDQS[0:7]: Differential input, 40 ohm */ - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_sdqs2 = 0x00000030, - .dram_sdqs3 = 0x00000030, - .dram_sdqs4 = 0x00000030, - .dram_sdqs5 = 0x00000030, - .dram_sdqs6 = 0x00000030, - .dram_sdqs7 = 0x00000030, - - /* DQM[0:7]: Differential input, 40 ohm */ - .dram_dqm0 = 0x00020030, - .dram_dqm1 = 0x00020030, - .dram_dqm2 = 0x00020030, - .dram_dqm3 = 0x00020030, - .dram_dqm4 = 0x00020030, - .dram_dqm5 = 0x00020030, - .dram_dqm6 = 0x00020030, - .dram_dqm7 = 0x00020030, -}; - -/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ -struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { - /* DDR3 */ - .grp_ddr_type = 0x000c0000, - /* SDQS[0:7]: Differential input, 40 ohm */ - .grp_ddrmode_ctl = 0x00020000, - /* disable DDR pullups */ - .grp_ddrpke = 0x00000000, - /* ADDR[00:16], SDBA[0:1]: 40 ohm */ - .grp_addds = 0x00000030, - /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ - .grp_ctlds = 0x00000030, - /* DATA[00:63]: Differential input, 40 ohm */ - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_b2ds = 0x00000030, - .grp_b3ds = 0x00000030, - .grp_b4ds = 0x00000030, - .grp_b5ds = 0x00000030, - .grp_b6ds = 0x00000030, - .grp_b7ds = 0x00000030, -}; - -/* MT41K64M16JT-125 (1Gb density) */ -static struct mx6_ddr3_cfg mt41k64m16jt_125 = { - .mem_speed = 1600, - .density = 1, - .width = 16, - .banks = 8, - .rowaddr = 13, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -/* MT41K128M16JT-125 (2Gb density) */ -static struct mx6_ddr3_cfg mt41k128m16jt_125 = { - .mem_speed = 1600, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -/* MT41K256M16HA-125 (4Gb density) */ -static struct mx6_ddr3_cfg mt41k256m16ha_125 = { - .mem_speed = 1600, - .density = 4, - .width = 16, - .banks = 8, - .rowaddr = 15, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -/* MT41K512M16HA-125 (8Gb density) */ -static struct mx6_ddr3_cfg mt41k512m16ha_125 = { - .mem_speed = 1600, - .density = 8, - .width = 16, - .banks = 8, - .rowaddr = 16, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -/* - * calibration - these are the various CPU/DDR3 combinations we support - */ -static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x004C004E, - .p0_mpwldectrl1 = 0x00440044, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x42440247, - .p0_mpdgctrl1 = 0x02310232, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x45424746, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x33382C31, -}; - -/* TODO: update with calibrated values */ -static struct mx6_mmdc_calibration mx6dq_64x64_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00190017, - .p0_mpwldectrl1 = 0x00140026, - .p1_mpwldectrl0 = 0x0021001C, - .p1_mpwldectrl1 = 0x0011001D, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43380347, - .p0_mpdgctrl1 = 0x433C034D, - .p1_mpdgctrl0 = 0x032C0324, - .p1_mpdgctrl1 = 0x03310232, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3C313539, - .p1_mprddlctl = 0x37343141, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36393C39, - .p1_mpwrdlctl = 0x42344438, -}; - -/* TODO: update with calibrated values */ -static struct mx6_mmdc_calibration mx6sdl_64x64_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x003C003C, - .p0_mpwldectrl1 = 0x001F002A, - .p1_mpwldectrl0 = 0x00330038, - .p1_mpwldectrl1 = 0x0022003F, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x42410244, - .p0_mpdgctrl1 = 0x4234023A, - .p1_mpdgctrl0 = 0x022D022D, - .p1_mpdgctrl1 = 0x021C0228, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x484A4C4B, - .p1_mprddlctl = 0x4B4D4E4B, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x33342B32, - .p1_mpwrdlctl = 0x3933332B, -}; - -static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x001B0016, - .p0_mpwldectrl1 = 0x000C000E, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x4324033A, - .p0_mpdgctrl1 = 0x00000000, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x40403438, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x40403D36, -}; - -static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00420043, - .p0_mpwldectrl1 = 0x0016001A, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x4238023B, - .p0_mpdgctrl1 = 0x00000000, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x40404849, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x40402E2F, -}; - -static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00190017, - .p0_mpwldectrl1 = 0x00140026, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43380347, - .p0_mpdgctrl1 = 0x433C034D, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3C313539, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36393C39, -}; - -static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x003C003C, - .p0_mpwldectrl1 = 0x001F002A, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x42410244, - .p0_mpdgctrl1 = 0x4234023A, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x484A4C4B, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x33342B32, -}; - -static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00190017, - .p0_mpwldectrl1 = 0x00140026, - .p1_mpwldectrl0 = 0x0021001C, - .p1_mpwldectrl1 = 0x0011001D, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43380347, - .p0_mpdgctrl1 = 0x433C034D, - .p1_mpdgctrl0 = 0x032C0324, - .p1_mpdgctrl1 = 0x03310232, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3C313539, - .p1_mprddlctl = 0x37343141, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36393C39, - .p1_mpwrdlctl = 0x42344438, -}; - -static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x003C003C, - .p0_mpwldectrl1 = 0x001F002A, - .p1_mpwldectrl0 = 0x00330038, - .p1_mpwldectrl1 = 0x0022003F, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x42410244, - .p0_mpdgctrl1 = 0x4234023A, - .p1_mpdgctrl0 = 0x022D022D, - .p1_mpdgctrl1 = 0x021C0228, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x484A4C4B, - .p1_mprddlctl = 0x4B4D4E4B, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x33342B32, - .p1_mpwrdlctl = 0x3933332B, -}; - -static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x001E001A, - .p0_mpwldectrl1 = 0x0026001F, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43370349, - .p0_mpdgctrl1 = 0x032D0327, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3D303639, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x32363934, -}; - -static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0X00480047, - .p0_mpwldectrl1 = 0X003D003F, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0X423E0241, - .p0_mpdgctrl1 = 0X022B022C, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0X49454A4A, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0X2E372C32, -}; - -static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0X00220021, - .p0_mpwldectrl1 = 0X00200030, - .p1_mpwldectrl0 = 0X002D0027, - .p1_mpwldectrl1 = 0X00150026, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43330342, - .p0_mpdgctrl1 = 0x0339034A, - .p1_mpdgctrl0 = 0x032F0325, - .p1_mpdgctrl1 = 0x032F022E, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0X3A2E3437, - .p1_mprddlctl = 0X35312F3F, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0X33363B37, - .p1_mpwrdlctl = 0X40304239, -}; - -static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x0048004A, - .p0_mpwldectrl1 = 0x003F004A, - .p1_mpwldectrl0 = 0x001E0028, - .p1_mpwldectrl1 = 0x002C0043, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x02250219, - .p0_mpdgctrl1 = 0x01790202, - .p1_mpdgctrl0 = 0x02080208, - .p1_mpdgctrl1 = 0x016C0175, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x4A4C4D4C, - .p1_mprddlctl = 0x494C4A48, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x403F3437, - .p1_mpwrdlctl = 0x383A3930, -}; - -static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x001F003F, - .p0_mpwldectrl1 = 0x001F001F, - .p1_mpwldectrl0 = 0x001F004E, - .p1_mpwldectrl1 = 0x0059001F, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x42220225, - .p0_mpdgctrl1 = 0x0213021F, - .p1_mpdgctrl0 = 0x022C0242, - .p1_mpdgctrl1 = 0x022C0244, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x474A4C4A, - .p1_mprddlctl = 0x48494C45, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x3F3F3F36, - .p1_mpwrdlctl = 0x3F36363F, -}; - -static struct mx6_mmdc_calibration mx6sdl_128x64x2_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x001F003F, - .p0_mpwldectrl1 = 0x001F001F, - .p1_mpwldectrl0 = 0x001F004E, - .p1_mpwldectrl1 = 0x0059001F, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x42220225, - .p0_mpdgctrl1 = 0x0213021F, - .p1_mpdgctrl0 = 0x022C0242, - .p1_mpdgctrl1 = 0x022C0244, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x474A4C4A, - .p1_mprddlctl = 0x48494C45, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x3F3F3F36, - .p1_mpwrdlctl = 0x3F36363F, -}; - -static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x002A0025, - .p0_mpwldectrl1 = 0x003A002A, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43430356, - .p0_mpdgctrl1 = 0x033C0335, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x4B373F42, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x303E3C36, -}; - -static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00230020, - .p0_mpwldectrl1 = 0x002F002A, - .p1_mpwldectrl0 = 0x001D0027, - .p1_mpwldectrl1 = 0x00100023, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x03250339, - .p0_mpdgctrl1 = 0x031C0316, - .p1_mpdgctrl0 = 0x03210331, - .p1_mpdgctrl1 = 0x031C025A, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x40373C40, - .p1_mprddlctl = 0x3A373646, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x2E353933, - .p1_mpwrdlctl = 0x3C2F3F35, -}; - -static void spl_dram_init(int width, int size_mb, int board_model) -{ - struct mx6_ddr3_cfg *mem = NULL; - struct mx6_mmdc_calibration *calib = NULL; - struct mx6_ddr_sysinfo sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ - .dsize = width/32, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 32Gb per CS */ - /* single chip select */ - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ -#ifdef RTT_NOM_120OHM - .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ -#else - .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ -#endif - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .pd_fast_exit = 1, /* enable precharge power-down fast exit */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; - - /* - * MMDC Calibration requires the following data: - * mx6_mmdc_calibration - board-specific calibration (routing delays) - * these calibration values depend on board routing, SoC, and DDR - * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) - * mx6_ddr_cfg - chip specific timing/layout details - */ - if (width == 16 && size_mb == 128) { - mem = &mt41k64m16jt_125; - if (is_cpu_type(MXC_CPU_MX6Q)) - ; - else - calib = &mx6sdl_64x16_mmdc_calib; - debug("1gB density\n"); - } else if (width == 16 && size_mb == 256) { - /* 1x 2Gb density chip - same calib as 2x 2Gb */ - mem = &mt41k128m16jt_125; - if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_128x32_mmdc_calib; - else - calib = &mx6sdl_128x32_mmdc_calib; - debug("2gB density\n"); - } else if (width == 16 && size_mb == 512) { - mem = &mt41k256m16ha_125; - if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_256x16_mmdc_calib; - else - calib = &mx6sdl_256x16_mmdc_calib; - debug("4gB density\n"); - } else if (width == 16 && size_mb == 1024) { - mem = &mt41k512m16ha_125; - if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_512x32_mmdc_calib; - debug("8gB density\n"); - } else if (width == 32 && size_mb == 256) { - /* Same calib as width==16, size==128 */ - mem = &mt41k64m16jt_125; - if (is_cpu_type(MXC_CPU_MX6Q)) - ; - else - calib = &mx6sdl_64x16_mmdc_calib; - debug("1gB density\n"); - } else if (width == 32 && size_mb == 512) { - mem = &mt41k128m16jt_125; - if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_128x32_mmdc_calib; - else - calib = &mx6sdl_128x32_mmdc_calib; - debug("2gB density\n"); - } else if (width == 32 && size_mb == 1024) { - mem = &mt41k256m16ha_125; - if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_256x32_mmdc_calib; - else - calib = &mx6sdl_256x32_mmdc_calib; - debug("4gB density\n"); - } else if (width == 32 && size_mb == 2048) { - mem = &mt41k512m16ha_125; - if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_512x32_mmdc_calib; - debug("8gB density\n"); - } else if (width == 64 && size_mb == 512) { - mem = &mt41k64m16jt_125; - debug("1gB density\n"); - if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_64x64_mmdc_calib; - else - calib = &mx6sdl_64x64_mmdc_calib; - } else if (width == 64 && size_mb == 1024) { - mem = &mt41k128m16jt_125; - if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_128x64_mmdc_calib; - else - calib = &mx6sdl_128x64_mmdc_calib; - debug("2gB density\n"); - } else if (width == 64 && size_mb == 2048) { - switch(board_model) { - case GW5905: - /* 8xMT41K128M16 (2GiB) fly-by mirrored 2-chipsels */ - mem = &mt41k128m16jt_125; - debug("2gB density - 2 chipsel\n"); - if (!is_cpu_type(MXC_CPU_MX6Q)) { - calib = &mx6sdl_128x64x2_mmdc_calib; - sysinfo.ncs = 2; - sysinfo.cs_density = 10; /* CS0_END=39 */ - sysinfo.cs1_mirror = 1; /* mirror enabled */ - } - break; - default: - mem = &mt41k256m16ha_125; - if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_256x64_mmdc_calib; - else - calib = &mx6sdl_256x64_mmdc_calib; - debug("4gB density\n"); - break; - } - } else if (width == 64 && size_mb == 4096) { - switch(board_model) { - case GW5903: - /* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */ - mem = &mt41k256m16ha_125; - debug("4gB density - 2 chipsel\n"); - if (!is_cpu_type(MXC_CPU_MX6Q)) { - calib = &mx6sdl_256x64x2_mmdc_calib; - sysinfo.ncs = 2; - sysinfo.cs_density = 18; /* CS0_END=71 */ - sysinfo.cs1_mirror = 1; /* mirror enabled */ - } - break; - default: - mem = &mt41k512m16ha_125; - if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_512x64_mmdc_calib; - debug("8gB density\n"); - break; - } - } - - if (!(mem && calib)) { - puts("Error: Invalid Calibration/Board Configuration\n"); - printf("MEM : %s\n", mem ? "OKAY" : "NULL"); - printf("CALIB : %s\n", calib ? "OKAY" : "NULL"); - printf("CPUTYPE: %s\n", - is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL"); - printf("SIZE_MB: %d\n", size_mb); - printf("WIDTH : %d\n", width); - hang(); - } - - if (is_cpu_type(MXC_CPU_MX6Q)) - mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, - &mx6dq_grp_ioregs); - else - mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, - &mx6sdl_grp_ioregs); - mx6_dram_cfg(&sysinfo, calib, mem); -} - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC03, &ccm->CCGR1); - writel(0x0FFFC000, &ccm->CCGR2); - writel(0x3FF00000, &ccm->CCGR3); - writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003FF, &ccm->CCGR6); -} - -/* - * called from C runtime startup code (arch/arm/lib/crt0.S:_main) - * - we have a stack and a place to store GD, both in SRAM - * - no variable global data is available - */ -void board_init_f(ulong dummy) -{ - struct ventana_board_info ventana_info; - int board_model; - - /* setup clock gating */ - ccgr_init(); - - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - /* setup AXI */ - gpr_init(); - - /* iomux and setup of uart/i2c */ - setup_iomux_uart(); - setup_ventana_i2c(0); - setup_ventana_i2c(1); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* read/validate EEPROM info to determine board model and SDRAM cfg */ - board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info); - - /* configure model-specific gpio */ - setup_iomux_gpio(board_model, &ventana_info); - - /* provide some some default: 32bit 128MB */ - if (GW_UNKNOWN == board_model) - hang(); - - /* configure MMDC for SDRAM width/size and per-model calibration */ - spl_dram_init(8 << ventana_info.sdram_width, - 16 << ventana_info.sdram_size, - board_model); -} - -void board_boot_order(u32 *spl_boot_list) -{ - spl_boot_list[0] = spl_boot_device(); - switch (spl_boot_list[0]) { - case BOOT_DEVICE_NAND: - spl_boot_list[1] = BOOT_DEVICE_MMC1; - spl_boot_list[2] = BOOT_DEVICE_UART; - break; - case BOOT_DEVICE_MMC1: - spl_boot_list[1] = BOOT_DEVICE_UART; - break; - } -} - -/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */ -/* its our chance to print info about boot device */ -void spl_board_init(void) -{ - /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */ - u32 boot_device = spl_boot_device(); - - switch (boot_device) { - case BOOT_DEVICE_MMC1: - puts("Booting from MMC\n"); - break; - case BOOT_DEVICE_NAND: - puts("Booting from NAND\n"); - break; - case BOOT_DEVICE_SATA: - puts("Booting from SATA\n"); - break; - default: - puts("Unknown boot device\n"); - } - - /* PMIC init */ - setup_pmic(); -} - -#ifdef CONFIG_SPL_OS_BOOT -/* return 1 if we wish to boot to uboot vs os (falcon mode) */ -int spl_start_uboot(void) -{ - unsigned char ret = 1; - - debug("%s\n", __func__); -#ifdef CONFIG_SPL_ENV_SUPPORT - env_init(); - env_load(); - debug("boot_os=%s\n", env_get("boot_os")); - if (env_get_yesno("boot_os") == 1) - ret = 0; -#else - /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */ - i2c_set_bus_num(0); - gsc_i2c_read(0x50, 0x0, 1, &ret, 1); -#endif - if (!ret) - gsc_boot_wd_disable(); - - debug("%s booting %s\n", __func__, ret ? "uboot" : "linux"); - return ret; -} -#endif diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h deleted file mode 100644 index 4fa085b320cc..000000000000 --- a/board/gateworks/gw_ventana/ventana_eeprom.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Gateworks Corporation - */ - -#ifndef _VENTANA_EEPROM_ -#define _VENTANA_EEPROM_ - -struct ventana_board_info { - u8 mac0[6]; /* 0x00: MAC1 */ - u8 mac1[6]; /* 0x06: MAC2 */ - u8 res0[12]; /* 0x0C: reserved */ - u32 serial; /* 0x18: Serial Number (read only) */ - u8 res1[4]; /* 0x1C: reserved */ - u8 mfgdate[4]; /* 0x20: MFG date (read only) */ - u8 res2[7]; /* 0x24 */ - /* sdram config */ - u8 sdram_size; /* 0x2B: (16 << n) MB */ - u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */ - u8 sdram_width; /* 0x2D: (8 << n) bit */ - /* cpu config */ - u8 cpu_speed; /* 0x2E: (33.333 * n) MHz */ - u8 cpu_type; /* 0x2F: 7=imx6q, 8=imx6dl */ - u8 model[16]; /* 0x30: model string */ - /* FLASH config */ - u8 nand_flash_size; /* 0x40: (8 << (n-1)) MB */ - u8 spi_flash_size; /* 0x41: (4 << (n-1)) MB */ - - /* Config1: SoC Peripherals */ - u8 config[8]; /* 0x42: loading options */ - - u8 res3[4]; /* 0x4A */ - - u8 chksum[2]; /* 0x4E */ -}; - -/* config bits */ -enum { - EECONFIG_ETH0, - EECONFIG_ETH1, - EECONFIG_HDMI_OUT, - EECONFIG_SATA, - EECONFIG_PCIE, - EECONFIG_SSI0, - EECONFIG_SSI1, - EECONFIG_LCD, - EECONFIG_LVDS0, - EECONFIG_LVDS1, - EECONFIG_USB0, - EECONFIG_USB1, - EECONFIG_SD0, - EECONFIG_SD1, - EECONFIG_SD2, - EECONFIG_SD3, - EECONFIG_UART0, - EECONFIG_UART1, - EECONFIG_UART2, - EECONFIG_UART3, - EECONFIG_UART4, - EECONFIG_IPU0, - EECONFIG_IPU1, - EECONFIG_FLEXCAN, - EECONFIG_MIPI_DSI, - EECONFIG_MIPI_CSI, - EECONFIG_TZASC0, - EECONFIG_TZASC1, - EECONFIG_I2C0, - EECONFIG_I2C1, - EECONFIG_I2C2, - EECONFIG_VPU, - EECONFIG_CSI0, - EECONFIG_CSI1, - EECONFIG_CAAM, - EECONFIG_MEZZ, - EECONFIG_RES1, - EECONFIG_RES2, - EECONFIG_RES3, - EECONFIG_RES4, - EECONFIG_ESPCI0, - EECONFIG_ESPCI1, - EECONFIG_ESPCI2, - EECONFIG_ESPCI3, - EECONFIG_ESPCI4, - EECONFIG_ESPCI5, - EECONFIG_RES5, - EECONFIG_RES6, - EECONFIG_GPS, - EECONFIG_SPIFL0, - EECONFIG_SPIFL1, - EECONFIG_GSPBATT, - EECONFIG_HDMI_IN, - EECONFIG_VID_OUT, - EECONFIG_VID_IN, - EECONFIG_NAND, - EECONFIG_RES8, - EECONFIG_RES9, - EECONFIG_RES10, - EECONFIG_RES11, - EECONFIG_RES12, - EECONFIG_RES13, - EECONFIG_RES14, - EECONFIG_RES15, -}; - -enum { - GW54proto, /* original GW5400-A prototype */ - GW51xx, - GW52xx, - GW53xx, - GW54xx, - GW551x, - GW552x, - GW553x, - GW560x, - GW5901, - GW5902, - GW5903, - GW5904, - GW5905, - GW5906, - GW5907, - GW5908, - GW5909, - GW_UNKNOWN, - GW_BADCRC, -}; - -/* config items */ -struct ventana_eeprom_config { - const char *name; /* name of item */ - const char *dtalias; /* name of dt node to remove if not set */ - int bit; /* bit within config */ -}; - -extern struct ventana_eeprom_config econfig[]; -extern struct ventana_board_info ventana_info; - -int read_eeprom(int bus, struct ventana_board_info *); - -#endif diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig deleted file mode 100644 index 41e190bf1e80..000000000000 --- a/configs/gwventana_emmc_defconfig +++ /dev/null @@ -1,111 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xB1400 -CONFIG_MX6QDL=y -CONFIG_TARGET_GW_VENTANA=y -CONFIG_CMD_EECONFIG=y -CONFIG_CMD_GSC=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x18000000 -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0xD1400 -CONFIG_CMD_HDMIDETECT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_MISC_INIT_R=y -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_DMA=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Ventana > " -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_SPL_WRITE_SIZE=0x20000 -CONFIG_CMD_UNZIP=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 -CONFIG_NETCONSOLE=y -CONFIG_DM=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_DWC_AHSATA=y -CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_PHYLIB=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_PCI=y -CONFIG_DM_SERIAL=y -CONFIG_MXC_UART=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_THERMAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Gateworks" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_ETHER=y -CONFIG_USB_ETH_CDC=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_DM_VIDEO=y -# CONFIG_BACKLIGHT is not set -# CONFIG_CMD_VIDCONSOLE is not set -# CONFIG_VIDEO_BPP8 is not set -# CONFIG_VIDEO_BPP32 is not set -# CONFIG_VIDEO_ANSI is not set -CONFIG_SYS_WHITE_ON_BLACK=y -# CONFIG_PANEL is not set -CONFIG_VIDEO_IPUV3=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig deleted file mode 100644 index 66b044197828..000000000000 --- a/configs/gwventana_gw5904_defconfig +++ /dev/null @@ -1,115 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xB1400 -CONFIG_MX6QDL=y -CONFIG_TARGET_GW_VENTANA=y -CONFIG_CMD_EECONFIG=y -CONFIG_CMD_GSC=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x18000000 -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0xD1400 -CONFIG_CMD_HDMIDETECT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_MISC_INIT_R=y -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_DMA=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Ventana > " -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_SPL_WRITE_SIZE=0x20000 -CONFIG_CMD_UNZIP=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 -CONFIG_NETCONSOLE=y -CONFIG_DM=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_DWC_AHSATA=y -CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_PHYLIB=y -CONFIG_MV88E61XX_SWITCH=y -CONFIG_MV88E61XX_CPU_PORT=5 -CONFIG_MV88E61XX_PHY_PORTS=0xf -CONFIG_MV88E61XX_FIXED_PORTS=0x0 -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_PCI=y -CONFIG_DM_SERIAL=y -CONFIG_MXC_UART=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_THERMAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Gateworks" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_ETHER=y -CONFIG_USB_ETH_CDC=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_DM_VIDEO=y -# CONFIG_BACKLIGHT is not set -# CONFIG_CMD_VIDCONSOLE is not set -# CONFIG_VIDEO_BPP8 is not set -# CONFIG_VIDEO_BPP32 is not set -# CONFIG_VIDEO_ANSI is not set -CONFIG_SYS_WHITE_ON_BLACK=y -# CONFIG_PANEL is not set -CONFIG_VIDEO_IPUV3=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig deleted file mode 100644 index 9022f350d13f..000000000000 --- a/configs/gwventana_nand_defconfig +++ /dev/null @@ -1,115 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x1000000 -CONFIG_MX6QDL=y -CONFIG_TARGET_GW_VENTANA=y -CONFIG_CMD_EECONFIG=y -CONFIG_CMD_GSC=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x18000000 -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x1080000 -CONFIG_CMD_HDMIDETECT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_USE_PREBOOT=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_MISC_INIT_R=y -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_DMA=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Ventana > " -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_SPL_NAND_OFS=0x1100000 -CONFIG_CMD_SPL_WRITE_SIZE=0x20000 -CONFIG_CMD_UNZIP=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_PCI=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_DM=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_DWC_AHSATA=y -CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_PHYLIB=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_PCI=y -CONFIG_DM_SERIAL=y -CONFIG_MXC_UART=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_THERMAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Gateworks" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_ETHER=y -CONFIG_USB_ETH_CDC=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_DM_VIDEO=y -# CONFIG_BACKLIGHT is not set -# CONFIG_CMD_VIDCONSOLE is not set -# CONFIG_VIDEO_BPP8 is not set -# CONFIG_VIDEO_BPP32 is not set -# CONFIG_VIDEO_ANSI is not set -CONFIG_SYS_WHITE_ON_BLACK=y -# CONFIG_PANEL is not set -CONFIG_VIDEO_IPUV3=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h deleted file mode 100644 index 7c8abda1d26e..000000000000 --- a/include/configs/gw_ventana.h +++ /dev/null @@ -1,298 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Gateworks Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* SPL */ -/* Location in NAND to read U-Boot from */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * SZ_1M) - -/* Falcon Mode */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - -/* Falcon Mode - NAND support: args@17MB kernel@18MB */ -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS (18 * SZ_1M) - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ - -#include "imx6_spl.h" /* common IMX6 SPL configuration */ -#include "mx6_common.h" - -#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ - -/* Serial ATAG */ -#define CONFIG_SERIAL_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -/* Serial */ -#define CONFIG_MXC_UART_BASE UART2_BASE - -#if !defined(CONFIG_SPI_FLASH) && defined(CONFIG_SPL_NAND_SUPPORT) -/* Enable NAND support */ -#ifdef CONFIG_CMD_NAND - #define CONFIG_SYS_MAX_NAND_DEVICE 1 - #define CONFIG_SYS_NAND_BASE 0x40000000 - #define CONFIG_SYS_NAND_5_ADDR_CYCLE - #define CONFIG_SYS_NAND_ONFI_DETECTION - - /* DMA stuff, needed for GPMI/MXS NAND support */ -#endif - -#endif /* CONFIG_SPI_FLASH */ - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_I2C_GSC 0 -#define CONFIG_I2C_EDID - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 1 - #define CONFIG_DWC_AHSATA_PORT_ID 0 - #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR - #define CONFIG_LBA48 -#endif - -/* - * PCI express - */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCI_FIXUP_DEV -#define CONFIG_PCIE_IMX -#endif - -/* - * PMIC - */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 -#define CONFIG_POWER_LTC3676 -#define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c - -/* Various command support */ - -/* Ethernet support */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_ARP_TIMEOUT 200UL - -/* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USBD_HS - -/* Framebuffer and LCD */ -#define CONFIG_VIDEO_LOGO -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_HIDE_LOGO_VERSION /* Custom config to hide U-boot version */ - -/* Miscellaneous configurable options */ -#define CONFIG_HWCONFIG - -/* Memory configuration */ - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* - * MTD Command for mtdparts - */ - -/* Persistent Environment Config */ - -/* Environment */ -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.146 - -#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "pcidisable=1\0" \ - "splashpos=m,m\0" \ - "usb_pgood_delay=2000\0" \ - "console=ttymxc1\0" \ - "bootdevs=usb mmc sata flash\0" \ - "hwconfig=_UNKNOWN_\0" \ - "video=\0" \ - \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "disk=0\0" \ - "part=1\0" \ - \ - "fdt_high=0xffffffff\0" \ - "fdt_addr=0x18000000\0" \ - "initrd_high=0xffffffff\0" \ - "fixfdt=" \ - "fdt addr ${fdt_addr}\0" \ - "bootdir=boot\0" \ - "loadfdt=" \ - "if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file}; " \ - "run fixfdt; " \ - "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file1}; " \ - "run fixfdt; " \ - "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file2}; " \ - "run fixfdt; " \ - "fi\0" \ - \ - "fs=ext4\0" \ - "script=6x_bootscript-ventana\0" \ - "loadscript=" \ - "if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \ - "source ${loadaddr}; " \ - "fi\0" \ - \ - "uimage=uImage\0" \ - "mmc_root=mmcblk0p1\0" \ - "mmc_boot=" \ - "setenv fsload "${fs}load mmc ${disk}:${part}"; " \ - "mmc dev ${disk} && mmc rescan && " \ - "setenv dtype mmc; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/${mmc_root} rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" \ - \ - "sata_boot=" \ - "setenv fsload "${fs}load sata ${disk}:${part}"; " \ - "sata init && " \ - "setenv dtype sata; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/sda1 rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" \ - "usb_boot=" \ - "setenv fsload "${fs}load usb ${disk}:${part}"; " \ - "usb start && usb dev ${disk} && " \ - "setenv dtype usb; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/sda1 rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" - -#ifdef CONFIG_SPI_FLASH - #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \ - "image_uboot=ventana/u-boot_spi.imx\0" \ - \ - "spi_koffset=0x90000\0" \ - "spi_klen=0x200000\0" \ - \ - "spi_updateuboot=echo Updating uboot from " \ - "${serverip}:${image_uboot}...; " \ - "tftpboot ${loadaddr} ${image_uboot} && " \ - "sf probe && sf erase 0 80000 && " \ - "sf write ${loadaddr} 400 ${filesize}\0" \ - "spi_update=echo Updating OS from ${serverip}:${image_os} " \ - "to ${spi_koffset} ...; " \ - "tftp ${loadaddr} ${image_os} && " \ - "sf probe && " \ - "sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \ - \ - "flash_boot=" \ - "if sf probe && " \ - "sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/mtdblock3 " \ - "rootfstype=squashfs,jffs2 " \ - "${video} ${extra}; " \ - "bootm; " \ - "fi\0" -#else - #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - \ - "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ - "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \ - "tftp ${loadaddr} ${image_rootfs} && " \ - "nand erase.part rootfs && " \ - "nand write ${loadaddr} rootfs ${filesize}\0" \ - \ - "flash_boot=" \ - "setenv fsload 'ubifsload'; " \ - "ubi part rootfs; " \ - "if ubi check boot; then " \ - "ubifsmount ubi0:boot; " \ - "setenv root ubi0:rootfs ubi.mtd=2 " \ - "rootfstype=squashfs,ubifs; " \ - "setenv bootdir; " \ - "elif ubi check rootfs; then " \ - "ubifsmount ubi0:rootfs; " \ - "setenv root ubi0:rootfs ubi.mtd=2 " \ - "rootfstype=ubifs; " \ - "fi; " \ - "setenv dtype nand; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=${root} ${video} ${extra}; " \ - "if run loadfdt; then " \ - "ubifsumount; " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "ubifsumount; bootm; " \ - "fi; " \ - "fi\0" -#endif - -#define CONFIG_BOOTCOMMAND \ - "for btype in ${bootdevs}; do " \ - "echo; echo Attempting ${btype} boot...; " \ - "if run ${btype}_boot; then; fi; " \ - "done" - -#endif /* __CONFIG_H */
On Tue, Feb 9, 2021 at 5:03 AM Tom Rini trini@konsulko.com wrote:
These boards have not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove them.
Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/mach-imx/mx6/Kconfig | 1 - board/gateworks/gw_ventana/Kconfig | 28 - board/gateworks/gw_ventana/MAINTAINERS | 8 - board/gateworks/gw_ventana/Makefile | 11 - board/gateworks/gw_ventana/README | 320 ---- board/gateworks/gw_ventana/common.c | 1760 ------------------- board/gateworks/gw_ventana/common.h | 99 -- board/gateworks/gw_ventana/eeprom.c | 266 --- board/gateworks/gw_ventana/gsc.c | 283 --- board/gateworks/gw_ventana/gsc.h | 71 - board/gateworks/gw_ventana/gw_ventana.c | 1381 --------------- board/gateworks/gw_ventana/gw_ventana_spl.c | 779 -------- board/gateworks/gw_ventana/ventana_eeprom.h | 140 -- configs/gwventana_emmc_defconfig | 111 -- configs/gwventana_gw5904_defconfig | 115 -- configs/gwventana_nand_defconfig | 115 -- include/configs/gw_ventana.h | 298 ---- 17 files changed, 5786 deletions(-) delete mode 100644 board/gateworks/gw_ventana/Kconfig delete mode 100644 board/gateworks/gw_ventana/MAINTAINERS delete mode 100644 board/gateworks/gw_ventana/Makefile delete mode 100644 board/gateworks/gw_ventana/README delete mode 100644 board/gateworks/gw_ventana/common.c delete mode 100644 board/gateworks/gw_ventana/common.h delete mode 100644 board/gateworks/gw_ventana/eeprom.c delete mode 100644 board/gateworks/gw_ventana/gsc.c delete mode 100644 board/gateworks/gw_ventana/gsc.h delete mode 100644 board/gateworks/gw_ventana/gw_ventana.c delete mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c delete mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h delete mode 100644 configs/gwventana_emmc_defconfig delete mode 100644 configs/gwventana_gw5904_defconfig delete mode 100644 configs/gwventana_nand_defconfig delete mode 100644 include/configs/gw_ventana.h
Tom,
I will submit a patchset to convert the gw_ventana IMX6 based boards to DM. I started this effort over a year ago and got stuck at some point but I think I know how to get through that now.
I hope to be able to submit something by the end of next week.
Best regards,
Tim
On Wed, Feb 10, 2021 at 09:29:44AM -0800, Tim Harvey wrote:
On Tue, Feb 9, 2021 at 5:03 AM Tom Rini trini@konsulko.com wrote:
These boards have not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove them.
Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/mach-imx/mx6/Kconfig | 1 - board/gateworks/gw_ventana/Kconfig | 28 - board/gateworks/gw_ventana/MAINTAINERS | 8 - board/gateworks/gw_ventana/Makefile | 11 - board/gateworks/gw_ventana/README | 320 ---- board/gateworks/gw_ventana/common.c | 1760 ------------------- board/gateworks/gw_ventana/common.h | 99 -- board/gateworks/gw_ventana/eeprom.c | 266 --- board/gateworks/gw_ventana/gsc.c | 283 --- board/gateworks/gw_ventana/gsc.h | 71 - board/gateworks/gw_ventana/gw_ventana.c | 1381 --------------- board/gateworks/gw_ventana/gw_ventana_spl.c | 779 -------- board/gateworks/gw_ventana/ventana_eeprom.h | 140 -- configs/gwventana_emmc_defconfig | 111 -- configs/gwventana_gw5904_defconfig | 115 -- configs/gwventana_nand_defconfig | 115 -- include/configs/gw_ventana.h | 298 ---- 17 files changed, 5786 deletions(-) delete mode 100644 board/gateworks/gw_ventana/Kconfig delete mode 100644 board/gateworks/gw_ventana/MAINTAINERS delete mode 100644 board/gateworks/gw_ventana/Makefile delete mode 100644 board/gateworks/gw_ventana/README delete mode 100644 board/gateworks/gw_ventana/common.c delete mode 100644 board/gateworks/gw_ventana/common.h delete mode 100644 board/gateworks/gw_ventana/eeprom.c delete mode 100644 board/gateworks/gw_ventana/gsc.c delete mode 100644 board/gateworks/gw_ventana/gsc.h delete mode 100644 board/gateworks/gw_ventana/gw_ventana.c delete mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c delete mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h delete mode 100644 configs/gwventana_emmc_defconfig delete mode 100644 configs/gwventana_gw5904_defconfig delete mode 100644 configs/gwventana_nand_defconfig delete mode 100644 include/configs/gw_ventana.h
Tom,
I will submit a patchset to convert the gw_ventana IMX6 based boards to DM. I started this effort over a year ago and got stuck at some point but I think I know how to get through that now.
I hope to be able to submit something by the end of next week.
Thanks! Their conversion will help unblock a few of the older migrations.
On Wed, Feb 10, 2021 at 9:31 AM Tom Rini trini@konsulko.com wrote:
On Wed, Feb 10, 2021 at 09:29:44AM -0800, Tim Harvey wrote:
On Tue, Feb 9, 2021 at 5:03 AM Tom Rini trini@konsulko.com wrote:
These boards have not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove them.
Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/mach-imx/mx6/Kconfig | 1 - board/gateworks/gw_ventana/Kconfig | 28 - board/gateworks/gw_ventana/MAINTAINERS | 8 - board/gateworks/gw_ventana/Makefile | 11 - board/gateworks/gw_ventana/README | 320 ---- board/gateworks/gw_ventana/common.c | 1760 ------------------- board/gateworks/gw_ventana/common.h | 99 -- board/gateworks/gw_ventana/eeprom.c | 266 --- board/gateworks/gw_ventana/gsc.c | 283 --- board/gateworks/gw_ventana/gsc.h | 71 - board/gateworks/gw_ventana/gw_ventana.c | 1381 --------------- board/gateworks/gw_ventana/gw_ventana_spl.c | 779 -------- board/gateworks/gw_ventana/ventana_eeprom.h | 140 -- configs/gwventana_emmc_defconfig | 111 -- configs/gwventana_gw5904_defconfig | 115 -- configs/gwventana_nand_defconfig | 115 -- include/configs/gw_ventana.h | 298 ---- 17 files changed, 5786 deletions(-) delete mode 100644 board/gateworks/gw_ventana/Kconfig delete mode 100644 board/gateworks/gw_ventana/MAINTAINERS delete mode 100644 board/gateworks/gw_ventana/Makefile delete mode 100644 board/gateworks/gw_ventana/README delete mode 100644 board/gateworks/gw_ventana/common.c delete mode 100644 board/gateworks/gw_ventana/common.h delete mode 100644 board/gateworks/gw_ventana/eeprom.c delete mode 100644 board/gateworks/gw_ventana/gsc.c delete mode 100644 board/gateworks/gw_ventana/gsc.h delete mode 100644 board/gateworks/gw_ventana/gw_ventana.c delete mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c delete mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h delete mode 100644 configs/gwventana_emmc_defconfig delete mode 100644 configs/gwventana_gw5904_defconfig delete mode 100644 configs/gwventana_nand_defconfig delete mode 100644 include/configs/gw_ventana.h
Tom,
I will submit a patchset to convert the gw_ventana IMX6 based boards to DM. I started this effort over a year ago and got stuck at some point but I think I know how to get through that now.
I hope to be able to submit something by the end of next week.
Thanks! Their conversion will help unblock a few of the older migrations.
Tom / Stefano,
Looking at this again I realize where I got stuck previously trying to migrate the Gateworks Ventana support to driver-model.
1. I need MULTI_DTB_FIT for raw NAND and the following issues are blocking me: a. spl_nand_fit_read() requires the reads to be page-aligned to the writesize of the NAND device. I have to work through trying to give the common nand spl code knowledge of the mtd device to get around this. b. spl_nand_fit_read() since 9f6a14c47ff9 ("spl: fit: nand: fix fit loading in case of bad blocks") which introduces bad block handling now requires a lot of static defines describing the NAND chip such as CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_SYS_NAND_BAD_BLOCK_POS and a few more that I need to get from mtd as well as we support multiple flash devices that have different geometries. I can wrap that code around an 'ifdef CONFIG_SYS_NAND_BLOCK_SIZE' to opt out of that feature. 2. I have a board with an MV88E61XX switch and drivers/net/phy/mv88e61xx.c and I don't see any driver-model support for eth switches connected to a phy. This blocks me from using DM_ETH. I have an unsubmitted patch queued up depending on my imx8mm-venice series that I think may provide a dm solution for network switches via DM_ETH_PHY. 3. I can't use driver model for SPL because of memory constraints: I need to read the board model from an I2C EEPROM in the SPL and then if I wanted to use SPL dm I would have to use dm_uninit() followed by dm_init_and_scan() which doesn't work because dm_uninit() does not free memory. It seems to me the DM_SPL code needs to implement memory free.
The biggest hurdle I see is (3) above and as far as I can tell most if not all other IMX boards are not using driver model for SPL. If this is true, then there are a lot of boards out there that haven't been able to fully swtich to driver model and are getting missed in the checks because DM_USB, DM_MMC, DM_* are defined for U-boot proper. That does not help remove legacy code from what I can tell.
What are your thoughts on the fact that many (majority?) boards are still using non-dm code for SPL?
Tim
-- Tom
On Wed, Feb 17, 2021 at 10:26:20AM -0800, Tim Harvey wrote:
On Wed, Feb 10, 2021 at 9:31 AM Tom Rini trini@konsulko.com wrote:
On Wed, Feb 10, 2021 at 09:29:44AM -0800, Tim Harvey wrote:
On Tue, Feb 9, 2021 at 5:03 AM Tom Rini trini@konsulko.com wrote:
These boards have not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove them.
Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/mach-imx/mx6/Kconfig | 1 - board/gateworks/gw_ventana/Kconfig | 28 - board/gateworks/gw_ventana/MAINTAINERS | 8 - board/gateworks/gw_ventana/Makefile | 11 - board/gateworks/gw_ventana/README | 320 ---- board/gateworks/gw_ventana/common.c | 1760 ------------------- board/gateworks/gw_ventana/common.h | 99 -- board/gateworks/gw_ventana/eeprom.c | 266 --- board/gateworks/gw_ventana/gsc.c | 283 --- board/gateworks/gw_ventana/gsc.h | 71 - board/gateworks/gw_ventana/gw_ventana.c | 1381 --------------- board/gateworks/gw_ventana/gw_ventana_spl.c | 779 -------- board/gateworks/gw_ventana/ventana_eeprom.h | 140 -- configs/gwventana_emmc_defconfig | 111 -- configs/gwventana_gw5904_defconfig | 115 -- configs/gwventana_nand_defconfig | 115 -- include/configs/gw_ventana.h | 298 ---- 17 files changed, 5786 deletions(-) delete mode 100644 board/gateworks/gw_ventana/Kconfig delete mode 100644 board/gateworks/gw_ventana/MAINTAINERS delete mode 100644 board/gateworks/gw_ventana/Makefile delete mode 100644 board/gateworks/gw_ventana/README delete mode 100644 board/gateworks/gw_ventana/common.c delete mode 100644 board/gateworks/gw_ventana/common.h delete mode 100644 board/gateworks/gw_ventana/eeprom.c delete mode 100644 board/gateworks/gw_ventana/gsc.c delete mode 100644 board/gateworks/gw_ventana/gsc.h delete mode 100644 board/gateworks/gw_ventana/gw_ventana.c delete mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c delete mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h delete mode 100644 configs/gwventana_emmc_defconfig delete mode 100644 configs/gwventana_gw5904_defconfig delete mode 100644 configs/gwventana_nand_defconfig delete mode 100644 include/configs/gw_ventana.h
Tom,
I will submit a patchset to convert the gw_ventana IMX6 based boards to DM. I started this effort over a year ago and got stuck at some point but I think I know how to get through that now.
I hope to be able to submit something by the end of next week.
Thanks! Their conversion will help unblock a few of the older migrations.
Tom / Stefano,
Looking at this again I realize where I got stuck previously trying to migrate the Gateworks Ventana support to driver-model.
Thanks for digging in and summarizing.
- I need MULTI_DTB_FIT for raw NAND and the following issues are blocking me:
a. spl_nand_fit_read() requires the reads to be page-aligned to the writesize of the NAND device. I have to work through trying to give the common nand spl code knowledge of the mtd device to get around this. b. spl_nand_fit_read() since 9f6a14c47ff9 ("spl: fit: nand: fix fit loading in case of bad blocks") which introduces bad block handling now requires a lot of static defines describing the NAND chip such as CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_SYS_NAND_BAD_BLOCK_POS and a few more that I need to get from mtd as well as we support multiple flash devices that have different geometries. I can wrap that code around an 'ifdef CONFIG_SYS_NAND_BLOCK_SIZE' to opt out of that feature.
Which is all SPL related, right? It seems so, but to be clear...
- I have a board with an MV88E61XX switch and
drivers/net/phy/mv88e61xx.c and I don't see any driver-model support for eth switches connected to a phy. This blocks me from using DM_ETH. I have an unsubmitted patch queued up depending on my imx8mm-venice series that I think may provide a dm solution for network switches via DM_ETH_PHY. 3. I can't use driver model for SPL because of memory constraints: I need to read the board model from an I2C EEPROM in the SPL and then if I wanted to use SPL dm I would have to use dm_uninit() followed by dm_init_and_scan() which doesn't work because dm_uninit() does not free memory. It seems to me the DM_SPL code needs to implement memory free.
The biggest hurdle I see is (3) above and as far as I can tell most if not all other IMX boards are not using driver model for SPL. If this is true, then there are a lot of boards out there that haven't been able to fully swtich to driver model and are getting missed in the checks because DM_USB, DM_MMC, DM_* are defined for U-boot proper. That does not help remove legacy code from what I can tell.
What are your thoughts on the fact that many (majority?) boards are still using non-dm code for SPL?
So, SPL in DM is not a general requirement. There's some new features in SPL that aren't available without it, but if you aren't using them today, that's not a big problem.
That leaves DM_ETH, which has a deadline of v2020.07 (so just barely past) and since you're on the way to hopefully addressing the general problem, that's great. My big concern right now is all of the v2019.04/07 deadlines. If you can address those right now, that's great.
On Wed, Feb 17, 2021 at 10:35 AM Tom Rini trini@konsulko.com wrote:
On Wed, Feb 17, 2021 at 10:26:20AM -0800, Tim Harvey wrote:
On Wed, Feb 10, 2021 at 9:31 AM Tom Rini trini@konsulko.com wrote:
On Wed, Feb 10, 2021 at 09:29:44AM -0800, Tim Harvey wrote:
On Tue, Feb 9, 2021 at 5:03 AM Tom Rini trini@konsulko.com wrote:
These boards have not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove them.
Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/mach-imx/mx6/Kconfig | 1 - board/gateworks/gw_ventana/Kconfig | 28 - board/gateworks/gw_ventana/MAINTAINERS | 8 - board/gateworks/gw_ventana/Makefile | 11 - board/gateworks/gw_ventana/README | 320 ---- board/gateworks/gw_ventana/common.c | 1760 ------------------- board/gateworks/gw_ventana/common.h | 99 -- board/gateworks/gw_ventana/eeprom.c | 266 --- board/gateworks/gw_ventana/gsc.c | 283 --- board/gateworks/gw_ventana/gsc.h | 71 - board/gateworks/gw_ventana/gw_ventana.c | 1381 --------------- board/gateworks/gw_ventana/gw_ventana_spl.c | 779 -------- board/gateworks/gw_ventana/ventana_eeprom.h | 140 -- configs/gwventana_emmc_defconfig | 111 -- configs/gwventana_gw5904_defconfig | 115 -- configs/gwventana_nand_defconfig | 115 -- include/configs/gw_ventana.h | 298 ---- 17 files changed, 5786 deletions(-) delete mode 100644 board/gateworks/gw_ventana/Kconfig delete mode 100644 board/gateworks/gw_ventana/MAINTAINERS delete mode 100644 board/gateworks/gw_ventana/Makefile delete mode 100644 board/gateworks/gw_ventana/README delete mode 100644 board/gateworks/gw_ventana/common.c delete mode 100644 board/gateworks/gw_ventana/common.h delete mode 100644 board/gateworks/gw_ventana/eeprom.c delete mode 100644 board/gateworks/gw_ventana/gsc.c delete mode 100644 board/gateworks/gw_ventana/gsc.h delete mode 100644 board/gateworks/gw_ventana/gw_ventana.c delete mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c delete mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h delete mode 100644 configs/gwventana_emmc_defconfig delete mode 100644 configs/gwventana_gw5904_defconfig delete mode 100644 configs/gwventana_nand_defconfig delete mode 100644 include/configs/gw_ventana.h
Tom,
I will submit a patchset to convert the gw_ventana IMX6 based boards to DM. I started this effort over a year ago and got stuck at some point but I think I know how to get through that now.
I hope to be able to submit something by the end of next week.
Thanks! Their conversion will help unblock a few of the older migrations.
Tom / Stefano,
Looking at this again I realize where I got stuck previously trying to migrate the Gateworks Ventana support to driver-model.
Thanks for digging in and summarizing.
- I need MULTI_DTB_FIT for raw NAND and the following issues are blocking me:
a. spl_nand_fit_read() requires the reads to be page-aligned to the writesize of the NAND device. I have to work through trying to give the common nand spl code knowledge of the mtd device to get around this. b. spl_nand_fit_read() since 9f6a14c47ff9 ("spl: fit: nand: fix fit loading in case of bad blocks") which introduces bad block handling now requires a lot of static defines describing the NAND chip such as CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_SYS_NAND_BAD_BLOCK_POS and a few more that I need to get from mtd as well as we support multiple flash devices that have different geometries. I can wrap that code around an 'ifdef CONFIG_SYS_NAND_BLOCK_SIZE' to opt out of that feature.
Which is all SPL related, right? It seems so, but to be clear...
Yes, both issues above are with regards to imx SPL+FIT+NAND. Ironically if I could use driver-model for SPL it would make things much easier working around what I ran into.
- I have a board with an MV88E61XX switch and
drivers/net/phy/mv88e61xx.c and I don't see any driver-model support for eth switches connected to a phy. This blocks me from using DM_ETH. I have an unsubmitted patch queued up depending on my imx8mm-venice series that I think may provide a dm solution for network switches via DM_ETH_PHY. 3. I can't use driver model for SPL because of memory constraints: I need to read the board model from an I2C EEPROM in the SPL and then if I wanted to use SPL dm I would have to use dm_uninit() followed by dm_init_and_scan() which doesn't work because dm_uninit() does not free memory. It seems to me the DM_SPL code needs to implement memory free.
The biggest hurdle I see is (3) above and as far as I can tell most if not all other IMX boards are not using driver model for SPL. If this is true, then there are a lot of boards out there that haven't been able to fully swtich to driver model and are getting missed in the checks because DM_USB, DM_MMC, DM_* are defined for U-boot proper. That does not help remove legacy code from what I can tell.
What are your thoughts on the fact that many (majority?) boards are still using non-dm code for SPL?
So, SPL in DM is not a general requirement. There's some new features in SPL that aren't available without it, but if you aren't using them today, that's not a big problem.
Ok... I just thought it was strange that there was this big push to get all MMC to DM_MMC yet the non-dm mmc code still seems to be needed for all the boards using non-dm SPL.
That leaves DM_ETH, which has a deadline of v2020.07 (so just barely past) and since you're on the way to hopefully addressing the general problem, that's great. My big concern right now is all of the v2019.04/07 deadlines. If you can address those right now, that's great.
I should be able to address that. Hopefully I'll have a patch series submitted soon.
Thanks,
Tim
On Mon, Feb 22, 2021 at 09:24:22AM -0800, Tim Harvey wrote:
On Wed, Feb 17, 2021 at 10:35 AM Tom Rini trini@konsulko.com wrote:
On Wed, Feb 17, 2021 at 10:26:20AM -0800, Tim Harvey wrote:
On Wed, Feb 10, 2021 at 9:31 AM Tom Rini trini@konsulko.com wrote:
On Wed, Feb 10, 2021 at 09:29:44AM -0800, Tim Harvey wrote:
On Tue, Feb 9, 2021 at 5:03 AM Tom Rini trini@konsulko.com wrote:
These boards have not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove them.
Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/mach-imx/mx6/Kconfig | 1 - board/gateworks/gw_ventana/Kconfig | 28 - board/gateworks/gw_ventana/MAINTAINERS | 8 - board/gateworks/gw_ventana/Makefile | 11 - board/gateworks/gw_ventana/README | 320 ---- board/gateworks/gw_ventana/common.c | 1760 ------------------- board/gateworks/gw_ventana/common.h | 99 -- board/gateworks/gw_ventana/eeprom.c | 266 --- board/gateworks/gw_ventana/gsc.c | 283 --- board/gateworks/gw_ventana/gsc.h | 71 - board/gateworks/gw_ventana/gw_ventana.c | 1381 --------------- board/gateworks/gw_ventana/gw_ventana_spl.c | 779 -------- board/gateworks/gw_ventana/ventana_eeprom.h | 140 -- configs/gwventana_emmc_defconfig | 111 -- configs/gwventana_gw5904_defconfig | 115 -- configs/gwventana_nand_defconfig | 115 -- include/configs/gw_ventana.h | 298 ---- 17 files changed, 5786 deletions(-) delete mode 100644 board/gateworks/gw_ventana/Kconfig delete mode 100644 board/gateworks/gw_ventana/MAINTAINERS delete mode 100644 board/gateworks/gw_ventana/Makefile delete mode 100644 board/gateworks/gw_ventana/README delete mode 100644 board/gateworks/gw_ventana/common.c delete mode 100644 board/gateworks/gw_ventana/common.h delete mode 100644 board/gateworks/gw_ventana/eeprom.c delete mode 100644 board/gateworks/gw_ventana/gsc.c delete mode 100644 board/gateworks/gw_ventana/gsc.h delete mode 100644 board/gateworks/gw_ventana/gw_ventana.c delete mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c delete mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h delete mode 100644 configs/gwventana_emmc_defconfig delete mode 100644 configs/gwventana_gw5904_defconfig delete mode 100644 configs/gwventana_nand_defconfig delete mode 100644 include/configs/gw_ventana.h
Tom,
I will submit a patchset to convert the gw_ventana IMX6 based boards to DM. I started this effort over a year ago and got stuck at some point but I think I know how to get through that now.
I hope to be able to submit something by the end of next week.
Thanks! Their conversion will help unblock a few of the older migrations.
Tom / Stefano,
Looking at this again I realize where I got stuck previously trying to migrate the Gateworks Ventana support to driver-model.
Thanks for digging in and summarizing.
- I need MULTI_DTB_FIT for raw NAND and the following issues are blocking me:
a. spl_nand_fit_read() requires the reads to be page-aligned to the writesize of the NAND device. I have to work through trying to give the common nand spl code knowledge of the mtd device to get around this. b. spl_nand_fit_read() since 9f6a14c47ff9 ("spl: fit: nand: fix fit loading in case of bad blocks") which introduces bad block handling now requires a lot of static defines describing the NAND chip such as CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_SYS_NAND_BAD_BLOCK_POS and a few more that I need to get from mtd as well as we support multiple flash devices that have different geometries. I can wrap that code around an 'ifdef CONFIG_SYS_NAND_BLOCK_SIZE' to opt out of that feature.
Which is all SPL related, right? It seems so, but to be clear...
Yes, both issues above are with regards to imx SPL+FIT+NAND. Ironically if I could use driver-model for SPL it would make things much easier working around what I ran into.
- I have a board with an MV88E61XX switch and
drivers/net/phy/mv88e61xx.c and I don't see any driver-model support for eth switches connected to a phy. This blocks me from using DM_ETH. I have an unsubmitted patch queued up depending on my imx8mm-venice series that I think may provide a dm solution for network switches via DM_ETH_PHY. 3. I can't use driver model for SPL because of memory constraints: I need to read the board model from an I2C EEPROM in the SPL and then if I wanted to use SPL dm I would have to use dm_uninit() followed by dm_init_and_scan() which doesn't work because dm_uninit() does not free memory. It seems to me the DM_SPL code needs to implement memory free.
The biggest hurdle I see is (3) above and as far as I can tell most if not all other IMX boards are not using driver model for SPL. If this is true, then there are a lot of boards out there that haven't been able to fully swtich to driver model and are getting missed in the checks because DM_USB, DM_MMC, DM_* are defined for U-boot proper. That does not help remove legacy code from what I can tell.
What are your thoughts on the fact that many (majority?) boards are still using non-dm code for SPL?
So, SPL in DM is not a general requirement. There's some new features in SPL that aren't available without it, but if you aren't using them today, that's not a big problem.
Ok... I just thought it was strange that there was this big push to get all MMC to DM_MMC yet the non-dm mmc code still seems to be needed for all the boards using non-dm SPL.
It's this hard problem we're still working to solve. I'm going to assume you hit a hard size limit when trying to use DM+SPL. I'd really like to see those WIP patches, so that we can see what else needs to happen to make everything be small enough, but I'd like to see the rest of the migration happen first, so we can otherwise unblock things.
That leaves DM_ETH, which has a deadline of v2020.07 (so just barely past) and since you're on the way to hopefully addressing the general problem, that's great. My big concern right now is all of the v2019.04/07 deadlines. If you can address those right now, that's great.
I should be able to address that. Hopefully I'll have a patch series submitted soon.
Thanks!
On Mon, Feb 22, 2021 at 9:40 AM Tom Rini trini@konsulko.com wrote:
On Mon, Feb 22, 2021 at 09:24:22AM -0800, Tim Harvey wrote:
On Wed, Feb 17, 2021 at 10:35 AM Tom Rini trini@konsulko.com wrote:
On Wed, Feb 17, 2021 at 10:26:20AM -0800, Tim Harvey wrote:
On Wed, Feb 10, 2021 at 9:31 AM Tom Rini trini@konsulko.com wrote:
On Wed, Feb 10, 2021 at 09:29:44AM -0800, Tim Harvey wrote:
On Tue, Feb 9, 2021 at 5:03 AM Tom Rini trini@konsulko.com wrote: > > These boards have not been converted to CONFIG_DM_MMC by the deadline of > v2019.04, which is almost two years ago. In addition there are other DM > migrations it is also missing. Remove them. > > Cc: Tim Harvey tharvey@gateworks.com > Signed-off-by: Tom Rini trini@konsulko.com > --- > arch/arm/mach-imx/mx6/Kconfig | 1 - > board/gateworks/gw_ventana/Kconfig | 28 - > board/gateworks/gw_ventana/MAINTAINERS | 8 - > board/gateworks/gw_ventana/Makefile | 11 - > board/gateworks/gw_ventana/README | 320 ---- > board/gateworks/gw_ventana/common.c | 1760 ------------------- > board/gateworks/gw_ventana/common.h | 99 -- > board/gateworks/gw_ventana/eeprom.c | 266 --- > board/gateworks/gw_ventana/gsc.c | 283 --- > board/gateworks/gw_ventana/gsc.h | 71 - > board/gateworks/gw_ventana/gw_ventana.c | 1381 --------------- > board/gateworks/gw_ventana/gw_ventana_spl.c | 779 -------- > board/gateworks/gw_ventana/ventana_eeprom.h | 140 -- > configs/gwventana_emmc_defconfig | 111 -- > configs/gwventana_gw5904_defconfig | 115 -- > configs/gwventana_nand_defconfig | 115 -- > include/configs/gw_ventana.h | 298 ---- > 17 files changed, 5786 deletions(-) > delete mode 100644 board/gateworks/gw_ventana/Kconfig > delete mode 100644 board/gateworks/gw_ventana/MAINTAINERS > delete mode 100644 board/gateworks/gw_ventana/Makefile > delete mode 100644 board/gateworks/gw_ventana/README > delete mode 100644 board/gateworks/gw_ventana/common.c > delete mode 100644 board/gateworks/gw_ventana/common.h > delete mode 100644 board/gateworks/gw_ventana/eeprom.c > delete mode 100644 board/gateworks/gw_ventana/gsc.c > delete mode 100644 board/gateworks/gw_ventana/gsc.h > delete mode 100644 board/gateworks/gw_ventana/gw_ventana.c > delete mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c > delete mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h > delete mode 100644 configs/gwventana_emmc_defconfig > delete mode 100644 configs/gwventana_gw5904_defconfig > delete mode 100644 configs/gwventana_nand_defconfig > delete mode 100644 include/configs/gw_ventana.h >
Tom,
I will submit a patchset to convert the gw_ventana IMX6 based boards to DM. I started this effort over a year ago and got stuck at some point but I think I know how to get through that now.
I hope to be able to submit something by the end of next week.
Thanks! Their conversion will help unblock a few of the older migrations.
Tom / Stefano,
Looking at this again I realize where I got stuck previously trying to migrate the Gateworks Ventana support to driver-model.
Thanks for digging in and summarizing.
- I need MULTI_DTB_FIT for raw NAND and the following issues are blocking me:
a. spl_nand_fit_read() requires the reads to be page-aligned to the writesize of the NAND device. I have to work through trying to give the common nand spl code knowledge of the mtd device to get around this. b. spl_nand_fit_read() since 9f6a14c47ff9 ("spl: fit: nand: fix fit loading in case of bad blocks") which introduces bad block handling now requires a lot of static defines describing the NAND chip such as CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_SYS_NAND_BAD_BLOCK_POS and a few more that I need to get from mtd as well as we support multiple flash devices that have different geometries. I can wrap that code around an 'ifdef CONFIG_SYS_NAND_BLOCK_SIZE' to opt out of that feature.
Which is all SPL related, right? It seems so, but to be clear...
Yes, both issues above are with regards to imx SPL+FIT+NAND. Ironically if I could use driver-model for SPL it would make things much easier working around what I ran into.
- I have a board with an MV88E61XX switch and
drivers/net/phy/mv88e61xx.c and I don't see any driver-model support for eth switches connected to a phy. This blocks me from using DM_ETH. I have an unsubmitted patch queued up depending on my imx8mm-venice series that I think may provide a dm solution for network switches via DM_ETH_PHY. 3. I can't use driver model for SPL because of memory constraints: I need to read the board model from an I2C EEPROM in the SPL and then if I wanted to use SPL dm I would have to use dm_uninit() followed by dm_init_and_scan() which doesn't work because dm_uninit() does not free memory. It seems to me the DM_SPL code needs to implement memory free.
The biggest hurdle I see is (3) above and as far as I can tell most if not all other IMX boards are not using driver model for SPL. If this is true, then there are a lot of boards out there that haven't been able to fully swtich to driver model and are getting missed in the checks because DM_USB, DM_MMC, DM_* are defined for U-boot proper. That does not help remove legacy code from what I can tell.
What are your thoughts on the fact that many (majority?) boards are still using non-dm code for SPL?
So, SPL in DM is not a general requirement. There's some new features in SPL that aren't available without it, but if you aren't using them today, that's not a big problem.
Ok... I just thought it was strange that there was this big push to get all MMC to DM_MMC yet the non-dm mmc code still seems to be needed for all the boards using non-dm SPL.
It's this hard problem we're still working to solve. I'm going to assume you hit a hard size limit when trying to use DM+SPL. I'd really like to see those WIP patches, so that we can see what else needs to happen to make everything be small enough, but I'd like to see the rest of the migration happen first, so we can otherwise unblock things.
Tom,
Actually, on the imx8mm-venice board I was working on (patches submitted but not yet applied) I tried to use dm-SPL and I didn't run into a code size limit, I ran into a memory limit. On that board just like the ventana boards we have an i2c based eeprom that contains the specific board model which dictates the dtb to use. The documentation I found in U-Boot mentioned that if you need to switch dt's at runtime you use dm_uninit() followed by dm_init_and_scan() on the new dt and what happens there is that for SPL dm_uninit() ends up not freeing any memory thus during the binding in dm_init_and_scan() you will run out of memory available for your devices. I tried to work around this by resetting the malloc pointer but then ran into something else and it was at that time I realized that I just needed to let go of using dm in the SPL.
I can look at it again after getting the rest of the patches applied.
Tim
That leaves DM_ETH, which has a deadline of v2020.07 (so just barely past) and since you're on the way to hopefully addressing the general problem, that's great. My big concern right now is all of the v2019.04/07 deadlines. If you can address those right now, that's great.
I should be able to address that. Hopefully I'll have a patch series submitted soon.
Thanks!
-- Tom
Hi Tom,
On Tue, 23 Feb 2021 at 10:39, Tim Harvey tharvey@gateworks.com wrote:
On Mon, Feb 22, 2021 at 9:40 AM Tom Rini trini@konsulko.com wrote:
On Mon, Feb 22, 2021 at 09:24:22AM -0800, Tim Harvey wrote:
On Wed, Feb 17, 2021 at 10:35 AM Tom Rini trini@konsulko.com wrote:
On Wed, Feb 17, 2021 at 10:26:20AM -0800, Tim Harvey wrote:
On Wed, Feb 10, 2021 at 9:31 AM Tom Rini trini@konsulko.com wrote:
On Wed, Feb 10, 2021 at 09:29:44AM -0800, Tim Harvey wrote: > On Tue, Feb 9, 2021 at 5:03 AM Tom Rini trini@konsulko.com wrote: > > > > These boards have not been converted to CONFIG_DM_MMC by the deadline of > > v2019.04, which is almost two years ago. In addition there are other DM > > migrations it is also missing. Remove them. > > > > Cc: Tim Harvey tharvey@gateworks.com > > Signed-off-by: Tom Rini trini@konsulko.com > > --- > > arch/arm/mach-imx/mx6/Kconfig | 1 - > > board/gateworks/gw_ventana/Kconfig | 28 - > > board/gateworks/gw_ventana/MAINTAINERS | 8 - > > board/gateworks/gw_ventana/Makefile | 11 - > > board/gateworks/gw_ventana/README | 320 ---- > > board/gateworks/gw_ventana/common.c | 1760 ------------------- > > board/gateworks/gw_ventana/common.h | 99 -- > > board/gateworks/gw_ventana/eeprom.c | 266 --- > > board/gateworks/gw_ventana/gsc.c | 283 --- > > board/gateworks/gw_ventana/gsc.h | 71 - > > board/gateworks/gw_ventana/gw_ventana.c | 1381 --------------- > > board/gateworks/gw_ventana/gw_ventana_spl.c | 779 -------- > > board/gateworks/gw_ventana/ventana_eeprom.h | 140 -- > > configs/gwventana_emmc_defconfig | 111 -- > > configs/gwventana_gw5904_defconfig | 115 -- > > configs/gwventana_nand_defconfig | 115 -- > > include/configs/gw_ventana.h | 298 ---- > > 17 files changed, 5786 deletions(-) > > delete mode 100644 board/gateworks/gw_ventana/Kconfig > > delete mode 100644 board/gateworks/gw_ventana/MAINTAINERS > > delete mode 100644 board/gateworks/gw_ventana/Makefile > > delete mode 100644 board/gateworks/gw_ventana/README > > delete mode 100644 board/gateworks/gw_ventana/common.c > > delete mode 100644 board/gateworks/gw_ventana/common.h > > delete mode 100644 board/gateworks/gw_ventana/eeprom.c > > delete mode 100644 board/gateworks/gw_ventana/gsc.c > > delete mode 100644 board/gateworks/gw_ventana/gsc.h > > delete mode 100644 board/gateworks/gw_ventana/gw_ventana.c > > delete mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c > > delete mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h > > delete mode 100644 configs/gwventana_emmc_defconfig > > delete mode 100644 configs/gwventana_gw5904_defconfig > > delete mode 100644 configs/gwventana_nand_defconfig > > delete mode 100644 include/configs/gw_ventana.h > > > > Tom, > > I will submit a patchset to convert the gw_ventana IMX6 based boards > to DM. I started this effort over a year ago and got stuck at some > point but I think I know how to get through that now. > > I hope to be able to submit something by the end of next week.
Thanks! Their conversion will help unblock a few of the older migrations.
Tom / Stefano,
Looking at this again I realize where I got stuck previously trying to migrate the Gateworks Ventana support to driver-model.
Thanks for digging in and summarizing.
- I need MULTI_DTB_FIT for raw NAND and the following issues are blocking me:
a. spl_nand_fit_read() requires the reads to be page-aligned to the writesize of the NAND device. I have to work through trying to give the common nand spl code knowledge of the mtd device to get around this. b. spl_nand_fit_read() since 9f6a14c47ff9 ("spl: fit: nand: fix fit loading in case of bad blocks") which introduces bad block handling now requires a lot of static defines describing the NAND chip such as CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_SYS_NAND_BAD_BLOCK_POS and a few more that I need to get from mtd as well as we support multiple flash devices that have different geometries. I can wrap that code around an 'ifdef CONFIG_SYS_NAND_BLOCK_SIZE' to opt out of that feature.
Which is all SPL related, right? It seems so, but to be clear...
Yes, both issues above are with regards to imx SPL+FIT+NAND. Ironically if I could use driver-model for SPL it would make things much easier working around what I ran into.
- I have a board with an MV88E61XX switch and
drivers/net/phy/mv88e61xx.c and I don't see any driver-model support for eth switches connected to a phy. This blocks me from using DM_ETH. I have an unsubmitted patch queued up depending on my imx8mm-venice series that I think may provide a dm solution for network switches via DM_ETH_PHY. 3. I can't use driver model for SPL because of memory constraints: I need to read the board model from an I2C EEPROM in the SPL and then if I wanted to use SPL dm I would have to use dm_uninit() followed by dm_init_and_scan() which doesn't work because dm_uninit() does not free memory. It seems to me the DM_SPL code needs to implement memory free.
The biggest hurdle I see is (3) above and as far as I can tell most if not all other IMX boards are not using driver model for SPL. If this is true, then there are a lot of boards out there that haven't been able to fully swtich to driver model and are getting missed in the checks because DM_USB, DM_MMC, DM_* are defined for U-boot proper. That does not help remove legacy code from what I can tell.
What are your thoughts on the fact that many (majority?) boards are still using non-dm code for SPL?
So, SPL in DM is not a general requirement. There's some new features in SPL that aren't available without it, but if you aren't using them today, that's not a big problem.
Ok... I just thought it was strange that there was this big push to get all MMC to DM_MMC yet the non-dm mmc code still seems to be needed for all the boards using non-dm SPL.
It's this hard problem we're still working to solve. I'm going to assume you hit a hard size limit when trying to use DM+SPL. I'd really like to see those WIP patches, so that we can see what else needs to happen to make everything be small enough, but I'd like to see the rest of the migration happen first, so we can otherwise unblock things.
Tom,
Actually, on the imx8mm-venice board I was working on (patches submitted but not yet applied) I tried to use dm-SPL and I didn't run into a code size limit, I ran into a memory limit. On that board just like the ventana boards we have an i2c based eeprom that contains the specific board model which dictates the dtb to use. The documentation I found in U-Boot mentioned that if you need to switch dt's at runtime you use dm_uninit() followed by dm_init_and_scan() on the new dt and what happens there is that for SPL dm_uninit() ends up not freeing any memory thus during the binding in dm_init_and_scan() you will run out of memory available for your devices. I tried to work around this by resetting the malloc pointer but then ran into something else and it was at that time I realized that I just needed to let go of using dm in the SPL.
In SPL at least, you need to use the correct devicetree when initing driver model. The free() function is a nop in SPL.
So do you have multiple DTs in the SPL image, and select from one using the EEPROM? Can you not use TPL to handle this, so that it can load SPL with the correct devicetree? That might be easier. Also doing this all in SPL is not compatible with of-platdata-inst, which (at present at least) binds all devices at build time using a single DT.
The problem with resetting the malloc pointer is that there may be other allocations before or driver model. If you must avoid TPL, one option might be to implement a way to record the malloc pointer when dm_init() is called and after it finishes. Then add a dm_reinit() function which makes sure the malloc() pointer has not since moved, resets to the original and sets up DM again. This could only be used immediately after DM init, though.
But honestly I am not a fan of reiniting DM twice. At minimum you should make sure that the base devicetree has only the EEPROM device, i.e. just enough to get that up and running. So I think TPL is better.
Another option is to read from the EEPROM in pre-DM code. Not very nice or easy though. I think that might be a rabbit hole.
I can look at it again after getting the rest of the patches applied.
Tim
That leaves DM_ETH, which has a deadline of v2020.07 (so just barely past) and since you're on the way to hopefully addressing the general problem, that's great. My big concern right now is all of the v2019.04/07 deadlines. If you can address those right now, that's great.
I should be able to address that. Hopefully I'll have a patch series submitted soon.
Thanks!
-- Tom
Regards, Simon
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Boris Brezillon boris.brezillon@free-electrons.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-imx/mx6/Kconfig | 4 - board/seco/Kconfig | 65 ----------- board/seco/common/Makefile | 3 - board/seco/common/mx6.c | 137 ----------------------- board/seco/common/mx6.h | 9 -- board/seco/mx6quq7/MAINTAINERS | 6 - board/seco/mx6quq7/Makefile | 5 - board/seco/mx6quq7/mx6quq7-2g.cfg | 172 ---------------------------- board/seco/mx6quq7/mx6quq7.c | 180 ------------------------------ configs/secomx6quq7_defconfig | 39 ------- include/configs/secomx6quq7.h | 81 -------------- 11 files changed, 701 deletions(-) delete mode 100644 board/seco/Kconfig delete mode 100644 board/seco/common/Makefile delete mode 100644 board/seco/common/mx6.c delete mode 100644 board/seco/common/mx6.h delete mode 100644 board/seco/mx6quq7/MAINTAINERS delete mode 100644 board/seco/mx6quq7/Makefile delete mode 100644 board/seco/mx6quq7/mx6quq7-2g.cfg delete mode 100644 board/seco/mx6quq7/mx6quq7.c delete mode 100644 configs/secomx6quq7_defconfig delete mode 100644 include/configs/secomx6quq7.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index dacfe623903c..737e305f29f1 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -551,9 +551,6 @@ config TARGET_PCL063_ULL select DM_THERMAL select SUPPORT_SPL
-config TARGET_SECOMX6 - bool "secomx6 boards" - config TARGET_SKSIMX6 bool "sks-imx6" depends on MX6QDL @@ -735,7 +732,6 @@ source "board/softing/vining_2000/Kconfig" source "board/liebherr/display5/Kconfig" source "board/liebherr/mccmon6/Kconfig" source "board/logicpd/imx6/Kconfig" -source "board/seco/Kconfig" source "board/sks-kinkel/sksimx6/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" source "board/somlabs/visionsom-6ull/Kconfig" diff --git a/board/seco/Kconfig b/board/seco/Kconfig deleted file mode 100644 index 12dd965ad52a..000000000000 --- a/board/seco/Kconfig +++ /dev/null @@ -1,65 +0,0 @@ -if TARGET_SECOMX6 - -choice - prompt "SECO i.MX6 Board variant" - optional - -config SECOMX6_Q7 - bool "Q7" - -config SECOMX6_UQ7 - bool "uQ7" - -config SECOMX6_USBC - bool "uSBC" - -endchoice - -choice - prompt "SECO i.MX6 SoC variant" - optional - -config SECOMX6Q - bool "i.MX6Q" - depends on MX6Q - -config SECOMX6DL - bool "i.MX6DL" - depends on MX6DL - -config SECOMX6S - bool "i.MX6S" - depends on MX6S - -endchoice - -choice - prompt "DDR size" - -config SECOMX6_512MB - bool "512MB" - -config SECOMX6_1GB - bool "1GB" - -config SECOMX6_2GB - bool "2GB" - -config SECOMX6_4GB - bool "4GB" - -endchoice - -config IMX_CONFIG - default "board/seco/mx6quq7/mx6quq7-2g.cfg" if SECOMX6_UQ7 && SECOMX6Q && SECOMX6_2GB - -config SYS_BOARD - default "mx6quq7" if SECOMX6_UQ7 && SECOMX6Q - -config SYS_VENDOR - default "seco" - -config SYS_CONFIG_NAME - default "secomx6quq7" if SECOMX6_UQ7 && SECOMX6Q - -endif diff --git a/board/seco/common/Makefile b/board/seco/common/Makefile deleted file mode 100644 index 4220e89bc5c0..000000000000 --- a/board/seco/common/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -obj-$(CONFIG_TARGET_SECOMX6) += mx6.o diff --git a/board/seco/common/mx6.c b/board/seco/common/mx6.c deleted file mode 100644 index 51832b9d082f..000000000000 --- a/board/seco/common/mx6.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * Copyright (C) 2015 ECA Sinters - * - * Author: Fabio Estevam fabio.estevam@freescale.com - * Modified by: Boris Brezillon boris.brezillon@free-electrons.com - */ - -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/boot_mode.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/arch/crm_regs.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <micrel.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <i2c.h> - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -void seco_mx6_setup_uart_iomux(void) -{ - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); -} - -#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | \ - PAD_CTL_HYS) - -static iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -void seco_mx6_setup_enet_iomux(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); -} - -int seco_mx6_rgmii_rework(struct phy_device *phydev) -{ - /* control data pad skew - devaddr = 0x02, register = 0x04 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); - /* rx data pad skew - devaddr = 0x02, register = 0x05 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); - /* tx data pad skew - devaddr = 0x02, register = 0x05 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); - - /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); - return 0; -} - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | \ - PAD_CTL_HYS) - -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -void seco_mx6_setup_usdhc_iomux(int id) -{ - switch (id) { - case 3: - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, - ARRAY_SIZE(usdhc3_pads)); - break; - - case 4: - imx_iomux_v3_setup_multiple_pads(usdhc4_pads, - ARRAY_SIZE(usdhc4_pads)); - break; - - default: - printf("Warning: invalid usdhc id (%d)\n", id); - break; - } -} diff --git a/board/seco/common/mx6.h b/board/seco/common/mx6.h deleted file mode 100644 index a05db673e284..000000000000 --- a/board/seco/common/mx6.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __SECO_COMMON_MX6_H -#define __SECO_COMMON_MX6_H - -void seco_mx6_setup_uart_iomux(void); -void seco_mx6_setup_enet_iomux(void); -int seco_mx6_rgmii_rework(struct phy_device *phydev); -void seco_mx6_setup_usdhc_iomux(int id); - -#endif /* __SECO_COMMON_MX6_H */ diff --git a/board/seco/mx6quq7/MAINTAINERS b/board/seco/mx6quq7/MAINTAINERS deleted file mode 100644 index 60fd4caab8f5..000000000000 --- a/board/seco/mx6quq7/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX6QUQ7 BOARD -M: Boris Brezillon boris.brezillon@free-electrons.com -S: Maintained -F: board/seco/mx6quq7/ -F: include/configs/secomx6quq7.h -F: configs/secomx6quq7_defconfig diff --git a/board/seco/mx6quq7/Makefile b/board/seco/mx6quq7/Makefile deleted file mode 100644 index c7aea8c851a5..000000000000 --- a/board/seco/mx6quq7/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2015 ECA Sinters - -obj-y := mx6quq7.o diff --git a/board/seco/mx6quq7/mx6quq7-2g.cfg b/board/seco/mx6quq7/mx6quq7-2g.cfg deleted file mode 100644 index 68d13cc92bc8..000000000000 --- a/board/seco/mx6quq7/mx6quq7-2g.cfg +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2013 Seco USA Inc - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -/* DDR IO TYPE */ -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 - -/* DATA STROBE */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028 - -/* DATA */ -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -DATA 4, MX6_IOM_GRP_B0DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028 -/* ADDRESS */ -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000028 -DATA 4, MX6_IOM_DRAM_CAS, 0x00000028 -DATA 4, MX6_IOM_DRAM_RAS, 0x00000028 - -/* CONTROL */ -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RESET, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000028 - -/* CLOCK */ -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028 - -/* - * DDR3 SETTINGS - * Read Data Bit Delay - */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 - - -/* Write Leveling */ -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F0001 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F - -/* DQS gating, read delay, write delay calibration values */ -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x431A0326 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0323031B -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x433F0340 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0345031C - -/* Read calibration */ -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40343137 -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x40372F45 - -/* write calibration */ -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x32414741 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4731473C - -/* Complete calibration by forced measurement: */ -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 - -/* - * MMDC init: - * in DDR3, 64-bit mode, only MMDC0 is init - */ -DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 - -DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7955 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB - -DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 - -/* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */ -DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 - -/* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */ -DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 - -/* Initialize DDR3 on CS_0 and CS_1 */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x02088032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 - -/* P0 01c */ -/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 - -/*ZQ - Calibrationi */ -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 - -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 - -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 - -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0x00FFF300 -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF - -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F - diff --git a/board/seco/mx6quq7/mx6quq7.c b/board/seco/mx6quq7/mx6quq7.c deleted file mode 100644 index c7e3d425eacd..000000000000 --- a/board/seco/mx6quq7/mx6quq7.c +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * Copyright (C) 2015 ECA Sinters - * - * Author: Fabio Estevam fabio.estevam@freescale.com - * Modified by: Boris Brezillon boris.brezillon@free-electrons.com - */ - -#include <init.h> -#include <net.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/boot_mode.h> -#include <malloc.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/arch/crm_regs.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <i2c.h> - -#include "../common/mx6.h" - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - - return 0; -} - -int board_early_init_f(void) -{ - seco_mx6_setup_uart_iomux(); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - seco_mx6_rgmii_rework(phydev); - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - uint32_t base = IMX_FEC_BASE; - struct mii_dev *bus = NULL; - struct phy_device *phydev = NULL; - int ret = 0; - - seco_mx6_setup_enet_iomux(); - -#ifdef CONFIG_FEC_MXC - bus = fec_get_miibus(base, -1); - if (!bus) - return -ENOMEM; - - /* scan phy 4,5,6,7 */ - phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); - if (!phydev) { - free(bus); - return -ENOMEM; - } - - printf("using phy at %d\n", phydev->addr); - ret = fec_probe(bis, -1, base, bus, phydev); - if (ret) { - free(phydev); - free(bus); - printf("FEC MXC: %s:failed\n", __func__); - } -#endif - - return ret; -} - -#define USDHC4_CD_GPIO IMX_GPIO_NR(2, 6) - -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR, 0, 4}, - {USDHC4_BASE_ADDR, 0, 4}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC3_BASE_ADDR: - ret = 1; /* Assume eMMC is always present */ - break; - case USDHC4_BASE_ADDR: - ret = !gpio_get_value(USDHC4_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ - u32 index = 0; - int ret; - - /* - * Following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 eMMC on Board - * mmc1 Ext SD - */ - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - seco_mx6_setup_usdhc_iomux(3); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - case 1: - seco_mx6_setup_usdhc_iomux(4); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - break; - - default: - printf("Warning: %d exceed maximum number of SD ports %d\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D4__GPIO2_IO04 | - MUX_PAD_CTRL(NO_PAD_CTRL)); - - gpio_direction_output(IMX_GPIO_NR(2, 4), 0); - - /* Set Low */ - gpio_set_value(IMX_GPIO_NR(2, 4), 0); - udelay(1000); - - /* Set High */ - gpio_set_value(IMX_GPIO_NR(2, 4), 1); - - return 0; -} - -int checkboard(void) -{ - puts("Board: SECO uQ7\n"); - - return 0; -} diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig deleted file mode 100644 index cc56b2e2b6c4..000000000000 --- a/configs/secomx6quq7_defconfig +++ /dev/null @@ -1,39 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_MX6Q=y -CONFIG_TARGET_SECOMX6=y -CONFIG_SECOMX6_UQ7=y -CONFIG_SECOMX6Q=y -CONFIG_SECOMX6_2GB=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="SECO MX6Q uQ7 U-Boot > " -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_FSL_USDHC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/secomx6quq7.h b/include/configs/secomx6quq7.h deleted file mode 100644 index bd3c3402c485..000000000000 --- a/include/configs/secomx6quq7.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Seco S.r.l - * - * Configuration settings for the Seco Boards. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#define CONFIG_BOARD_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -#define CONFIG_MXC_UART_BASE UART2_BASE - -/* MMC Configuration */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* Ethernet Configuration */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 6 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "ethprime=FEC0\0" \ - "netdev=eth0\0" \ - "ethprime=FEC0\0" \ - "uboot=u-boot.bin\0" \ - "kernel=uImage\0" \ - "nfsroot=/opt/eldk/arm\0" \ - "ip_local=10.0.0.5::10.0.0.1:255.255.255.0::eth0:off\0" \ - "ip_server=10.0.0.1\0" \ - "nfs_path=/targetfs \0" \ - "memory=mem=1024M\0" \ - "bootdev=mmc dev 0; ext2load mmc 0:1\0" \ - "root=root=/dev/mmcblk0p1\0" \ - "option=rootwait rw fixrtc rootflags=barrier=1\0" \ - "cpu_freq=arm_freq=996\0" \ - "setbootargs=setenv bootargs console=ttymxc1,115200 ${root}" \ - " ${option} ${memory} ${cpu_freq}\0" \ - "setbootargs_nfs=setenv bootargs console=ttymxc1,115200" \ - " root=/dev/nfs nfsroot=${ip_server}:${nfs_path}" \ - " nolock,wsize=4096,rsize=4096 ip=:::::eth0:dhcp" \ - " ${memory} ${cpu_freq}\0" \ - "setbootdev=setenv boot_dev ${bootdev} 10800000 /boot/uImage\0" \ - "bootcmd=run setbootargs; run setbootdev; run boot_dev;" \ - " bootm 0x10800000\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ - -#if defined(CONFIG_ENV_IS_IN_MMC) - #define CONFIG_DYNAMIC_MMC_DEVNO -#endif - -#endif /* __CONFIG_H */
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Cc: Priyanka Jain priyanka.jain@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/Kconfig | 13 --- arch/arm/cpu/armv8/Kconfig | 2 +- board/freescale/ls2080a/Kconfig | 35 ------ board/freescale/ls2080a/MAINTAINERS | 9 -- board/freescale/ls2080a/Makefile | 6 - board/freescale/ls2080a/README | 27 ----- board/freescale/ls2080a/ddr.c | 171 ---------------------------- board/freescale/ls2080a/ddr.h | 85 -------------- board/freescale/ls2080a/ls2080a.c | 147 ------------------------ configs/ls2080a_emu_defconfig | 38 ------- configs/ls2080a_simu_defconfig | 46 -------- drivers/i2c/Kconfig | 4 +- include/configs/ls2080a_emu.h | 80 ------------- include/configs/ls2080a_simu.h | 147 ------------------------ 14 files changed, 3 insertions(+), 807 deletions(-) delete mode 100644 board/freescale/ls2080a/Kconfig delete mode 100644 board/freescale/ls2080a/MAINTAINERS delete mode 100644 board/freescale/ls2080a/Makefile delete mode 100644 board/freescale/ls2080a/README delete mode 100644 board/freescale/ls2080a/ddr.c delete mode 100644 board/freescale/ls2080a/ddr.h delete mode 100644 board/freescale/ls2080a/ls2080a.c delete mode 100644 configs/ls2080a_emu_defconfig delete mode 100644 configs/ls2080a_simu_defconfig delete mode 100644 include/configs/ls2080a_emu.h delete mode 100644 include/configs/ls2080a_simu.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2e75efe2da8e..6263781e6f60 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1193,18 +1193,6 @@ config TARGET_LS2080A_EMU development platform that supports the QorIQ LS2080A Layerscape Architecture processor.
-config TARGET_LS2080A_SIMU - bool "Support ls2080a_simu" - select ARCH_LS2080A - select ARM64 - select ARMV8_MULTIENTRY - select BOARD_LATE_INIT - help - Support for Freescale LS2080A_SIMU platform. - The LS2080A Development System (QDS) is a pre silicon - development platform that supports the QorIQ LS2080A - Layerscape Architecture processor. - config TARGET_LS1088AQDS bool "Support ls1088aqds" select ARCH_LS1088A @@ -1962,7 +1950,6 @@ source "board/cavium/thunderx/Kconfig" source "board/cirrus/edb93xx/Kconfig" source "board/eets/pdu001/Kconfig" source "board/emulation/qemu-arm/Kconfig" -source "board/freescale/ls2080a/Kconfig" source "board/freescale/ls2080aqds/Kconfig" source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1088a/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index f2474413ccab..9cd6a8d642b5 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -104,7 +104,7 @@ config PSCI_RESET default y select ARM_SMCCC if OF_CONTROL depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \ - !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \ + !TARGET_LS2080AQDS && \ !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \ !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \ !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ diff --git a/board/freescale/ls2080a/Kconfig b/board/freescale/ls2080a/Kconfig deleted file mode 100644 index b5033511b55b..000000000000 --- a/board/freescale/ls2080a/Kconfig +++ /dev/null @@ -1,35 +0,0 @@ -if TARGET_LS2080A_EMU - -config SYS_BOARD - default "ls2080a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls2080a_emu" - -source "board/freescale/common/Kconfig" - -endif - -if TARGET_LS2080A_SIMU - -config SYS_BOARD - default "ls2080a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls2080a_simu" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS deleted file mode 100644 index e0e4e3f83e89..000000000000 --- a/board/freescale/ls2080a/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -LS2080A BOARD -M: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com -M: Priyanka Jain priyanka.jain@nxp.com -S: Maintained -F: board/freescale/ls2080a/ -F: include/configs/ls2080a_emu.h -F: configs/ls2080a_emu_defconfig -F: include/configs/ls2080a_simu.h -F: configs/ls2080a_simu_defconfig diff --git a/board/freescale/ls2080a/Makefile b/board/freescale/ls2080a/Makefile deleted file mode 100644 index 87e26d977094..000000000000 --- a/board/freescale/ls2080a/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2014-15 Freescale Semiconductor - -obj-y += ls2080a.o -obj-y += ddr.o diff --git a/board/freescale/ls2080a/README b/board/freescale/ls2080a/README deleted file mode 100644 index 646cc02693bc..000000000000 --- a/board/freescale/ls2080a/README +++ /dev/null @@ -1,27 +0,0 @@ -Freescale ls2080a_emu - -This is a emulator target with limited peripherals. - -Memory map from core's view - -0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom -0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR -0x00_1800_0000 .. 0x00_181F_FFFF OCRAM -0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 -0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 -0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 -0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 - -Other addresses are either reserved, or not used directly by U-Boot. -This list should be updated when more addresses are used. - -Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) -------------------------------------------------------------------- -One needs to use appropriate bootargs to boot Linux flavors which do -not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown -below: - -=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram - earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m - hugepages=16 mem=2048M' - diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c deleted file mode 100644 index 229fc9cc30ea..000000000000 --- a/board/freescale/ls2080a/ddr.c +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include <log.h> -#include <asm/arch/soc.h> -#include <asm/arch/clock.h> -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 3) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for data rate %lu MT/s\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (ctrl_num == CONFIG_DP_DDR_CTRL) { - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - popts->bstopre = 0; /* enable auto precharge */ - } -#endif - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 1; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - -#ifdef CONFIG_SYS_FSL_DDR4 - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ -#else - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); -#endif -} - -#ifdef CONFIG_SYS_DDR_RAW_TIMING -dimm_params_t ddr_raw_timing = { - .n_ranks = 2, - .rank_density = 1073741824u, - .capacity = 2147483648, - .primary_sdram_width = 64, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 14, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 937, - .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */ - .taa_ps = 13090, - .twr_ps = 15000, - .trcd_ps = 13090, - .trrd_ps = 5000, - .trp_ps = 13090, - .tras_ps = 33000, - .trc_ps = 46090, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 25000, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if (((controller_number == 0) && (dimm_number == 0)) || - ((controller_number == 1) && (dimm_number == 0))) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} -#endif - -int fsl_initdram(void) -{ - puts("Initializing DDR...."); - - puts("using SPD\n"); - gd->ram_size = fsl_ddr_sdram(); - - return 0; -} diff --git a/board/freescale/ls2080a/ddr.h b/board/freescale/ls2080a/ddr.h deleted file mode 100644 index d21b9265586d..000000000000 --- a/board/freescale/ls2080a/ddr.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 2140, 0, 4, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters udimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 2140, 0, 4, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {4, 2140, 0, 5, 4, 0x0, 0x0}, - {2, 2140, 0, 5, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters rdimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {4, 2140, 0, 5, 4, 0x0, 0x0}, - {2, 2140, 0, 5, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm0, - udimm2, -}; - -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm0, - rdimm2, -}; - - -#endif diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c deleted file mode 100644 index 62da2a7af11a..000000000000 --- a/board/freescale/ls2080a/ls2080a.c +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor - */ -#include <common.h> -#include <init.h> -#include <malloc.h> -#include <errno.h> -#include <net.h> -#include <netdev.h> -#include <fsl_ifc.h> -#include <fsl_ddr.h> -#include <asm/io.h> -#include <fdt_support.h> -#include <linux/libfdt.h> -#include <fsl-mc/fsl_mc.h> -#include <env_internal.h> -#include <asm/arch/soc.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - init_final_memctl_regs(); - -#ifdef CONFIG_ENV_IS_NOWHERE - gd->env_addr = (ulong)&default_environment[0]; -#endif - - return 0; -} - -int board_early_init_f(void) -{ - fsl_lsch3_early_init_f(); - return 0; -} - -void detail_board_ddr_info(void) -{ - puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); - print_ddr_info(0); -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { - puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); - print_ddr_info(CONFIG_DP_DDR_CTRL); - } -#endif -} - -int board_eth_init(struct bd_info *bis) -{ - int error = 0; - -#ifdef CONFIG_SMC91111 - error = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) - error = cpu_eth_init(bis); -#endif - return error; -} - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) -void fdt_fixup_board_enet(void *fdt) -{ - int offset; - - offset = fdt_path_offset(fdt, "/soc/fsl-mc"); - - /* - * TODO: Remove this when backward compatibility - * with old DT node (/fsl-mc) is no longer needed. - */ - if (offset < 0) - offset = fdt_path_offset(fdt, "/fsl-mc"); - - if (offset < 0) { - printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", - __func__, offset); - return; - } - - if (get_mc_boot_status() == 0 && - (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) - fdt_status_okay(fdt, offset); - else - fdt_status_fail(fdt, offset); -} - -void board_quiesce_devices(void) -{ - fsl_mc_ldpaa_exit(gd->bd); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - - ft_cpu_setup(blob, bd); - - /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - -#ifdef CONFIG_RESV_RAM - /* reduce size if reserved memory is within this bank */ - if (gd->arch.resv_ram >= base[0] && - gd->arch.resv_ram < base[0] + size[0]) - size[0] = gd->arch.resv_ram - base[0]; - else if (gd->arch.resv_ram >= base[1] && - gd->arch.resv_ram < base[1] + size[1]) - size[1] = gd->arch.resv_ram - base[1]; -#endif - - fdt_fixup_memory_banks(blob, base, size, 2); - - fdt_fsl_mc_fixup_iommu_map_entry(blob); - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) - fdt_fixup_board_enet(blob); -#endif - - return 0; -} -#endif - -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ -} -#endif - -#ifdef CONFIG_TFABOOT -void *env_sf_get_env_addr(void) -{ - return (void *)(CONFIG_SYS_FSL_QSPI_BASE1 + CONFIG_ENV_OFFSET); -} -#endif diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig deleted file mode 100644 index c42f012a6a29..000000000000 --- a/configs/ls2080a_emu_defconfig +++ /dev/null @@ -1,38 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS2080A_EMU=y -CONFIG_SYS_TEXT_BASE=0x30100000 -CONFIG_NR_DRAM_BANKS=3 -CONFIG_ENV_SIZE=0x1000 -CONFIG_IDENT_STRING=" LS2080A-EMU" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="EMU" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" -# CONFIG_USE_BOOTCOMMAND is not set -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -CONFIG_CMD_CACHE=y -# CONFIG_CMD_SLEEP is not set -CONFIG_MP=y -# CONFIG_DOS_PARTITION is not set -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig deleted file mode 100644 index 2aabb772079d..000000000000 --- a/configs/ls2080a_simu_defconfig +++ /dev/null @@ -1,46 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS2080A_SIMU=y -CONFIG_SYS_TEXT_BASE=0x30100000 -CONFIG_NR_DRAM_BANKS=3 -CONFIG_ENV_SIZE=0x1000 -CONFIG_IDENT_STRING=" LS2080A-SIMU" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SIMU" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" -# CONFIG_USE_BOOTCOMMAND is not set -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -CONFIG_CMD_CACHE=y -# CONFIG_CMD_SLEEP is not set -CONFIG_MP=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 367004b15bc7..ec3d6779dfbb 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -222,7 +222,7 @@ endif if SYS_I2C_MXC_I2C1 config SYS_MXC_I2C1_SPEED int "I2C Channel 1 speed" - default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU + default 40000000 if TARGET_LS2080A_EMU default 100000 help MXC I2C Channel 1 speed @@ -237,7 +237,7 @@ endif if SYS_I2C_MXC_I2C2 config SYS_MXC_I2C2_SPEED int "I2C Channel 2 speed" - default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU + default 40000000 if TARGET_LS2080A_EMU default 100000 help MXC I2C Channel 2 speed diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h deleted file mode 100644 index 3e0ad48ddacc..000000000000 --- a/include/configs/ls2080a_emu.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor - */ - -#ifndef __LS2_EMU_H -#define __LS2_EMU_H - -#include "ls2080a_common.h" - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 133333333 - -#define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS3 0x53 -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* - * NOR Flash Timing Params - */ -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ - FTIM0_NOR_TEADC(0x1) | \ - FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ - FTIM1_NOR_TRAD_NOR(0x1)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ - FTIM2_NOR_TCH(0x0) | \ - FTIM2_NOR_TWP(0x1)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 - -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 - -/* Debug Server firmware */ -#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR -#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL - -/* - * This trick allows users to load MC images into DDR directly without - * copying from NOR flash. It dramatically improves speed. - */ -#define CONFIG_SYS_LS_MC_FW_IN_DDR -#define CONFIG_SYS_LS_MC_DPL_IN_DDR -#define CONFIG_SYS_LS_MC_DPC_IN_DDR - -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 - -/* Store environment at top of flash */ - -#endif /* __LS2_EMU_H */ diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h deleted file mode 100644 index ab46df76007f..000000000000 --- a/include/configs/ls2080a_simu.h +++ /dev/null @@ -1,147 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Freescale Semiconductor - */ - -#ifndef __LS2_SIMU_H -#define __LS2_SIMU_H - -#include "ls2080a_common.h" - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 133333333 - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -/* SMSC 91C111 ethernet configuration */ -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE (0x2210000) - -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_QUIET_TEST -#endif - -/* - * NOR Flash Timing Params - */ -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ - FTIM0_NOR_TEADC(0x1) | \ - FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ - FTIM1_NOR_TRAD_NOR(0x1)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ - FTIM2_NOR_TCH(0x0) | \ - FTIM2_NOR_TWP(0x1)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#endif - -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 - -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - -/* Debug Server firmware */ -#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR -#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL - -/* MC firmware */ -#define CONFIG_SYS_LS_MC_DPL_IN_NOR -#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL - -#define CONFIG_SYS_LS_MC_DPC_IN_NOR -#define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL - -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 - -/* Store environment at top of flash */ - -#endif /* __LS2_SIMU_H */
-----Original Message----- From: Tom Rini trini@konsulko.com Sent: Tuesday, February 9, 2021 6:33 PM To: u-boot@lists.denx.de Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Priyanka Jain priyanka.jain@nxp.com Subject: [PATCH 18/25] arm: Remove ls2080a_simu board
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Cc: Priyanka Jain priyanka.jain@nxp.com Signed-off-by: Tom Rini trini@konsulko.com
Reviewed-by: Priyanka Jain priyanka.jain@nxp.com
On Tue, Feb 09, 2021 at 08:03:10AM -0500, Tom Rini wrote:
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Cc: Priyanka Jain priyanka.jain@nxp.com Signed-off-by: Tom Rini trini@konsulko.com Reviewed-by: Priyanka Jain priyanka.jain@nxp.com
Applied to u-boot/master, thanks!
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Eddy Petrișor eddy.petrisor@gmail.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/Kconfig | 6 - arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/cpu/armv8/s32v234/Makefile | 6 - arch/arm/cpu/armv8/s32v234/cpu.c | 102 ----- arch/arm/cpu/armv8/s32v234/cpu.h | 7 - arch/arm/cpu/armv8/s32v234/generic.c | 353 ------------------ arch/arm/include/asm/arch-s32v234/clock.h | 31 -- arch/arm/include/asm/arch-s32v234/ddr.h | 156 -------- arch/arm/include/asm/arch-s32v234/imx-regs.h | 328 ---------------- arch/arm/include/asm/arch-s32v234/lpddr2.h | 74 ---- .../include/asm/arch-s32v234/mc_cgm_regs.h | 253 ------------- .../arm/include/asm/arch-s32v234/mc_me_regs.h | 198 ---------- .../include/asm/arch-s32v234/mc_rgm_regs.h | 30 -- arch/arm/include/asm/arch-s32v234/mmdc.h | 88 ----- arch/arm/include/asm/arch-s32v234/siul.h | 149 -------- board/freescale/s32v234evb/Kconfig | 23 -- board/freescale/s32v234evb/MAINTAINERS | 8 - board/freescale/s32v234evb/Makefile | 9 - board/freescale/s32v234evb/clock.c | 343 ----------------- board/freescale/s32v234evb/lpddr2.c | 136 ------- board/freescale/s32v234evb/s32v234evb.c | 183 --------- board/freescale/s32v234evb/s32v234evb.cfg | 28 -- configs/s32v234evb_defconfig | 25 -- drivers/mmc/Kconfig | 2 +- include/configs/s32v234evb.h | 167 --------- 25 files changed, 2 insertions(+), 2705 deletions(-) delete mode 100644 arch/arm/cpu/armv8/s32v234/Makefile delete mode 100644 arch/arm/cpu/armv8/s32v234/cpu.c delete mode 100644 arch/arm/cpu/armv8/s32v234/cpu.h delete mode 100644 arch/arm/cpu/armv8/s32v234/generic.c delete mode 100644 arch/arm/include/asm/arch-s32v234/clock.h delete mode 100644 arch/arm/include/asm/arch-s32v234/ddr.h delete mode 100644 arch/arm/include/asm/arch-s32v234/imx-regs.h delete mode 100644 arch/arm/include/asm/arch-s32v234/lpddr2.h delete mode 100644 arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h delete mode 100644 arch/arm/include/asm/arch-s32v234/mc_me_regs.h delete mode 100644 arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h delete mode 100644 arch/arm/include/asm/arch-s32v234/mmdc.h delete mode 100644 arch/arm/include/asm/arch-s32v234/siul.h delete mode 100644 board/freescale/s32v234evb/Kconfig delete mode 100644 board/freescale/s32v234evb/MAINTAINERS delete mode 100644 board/freescale/s32v234evb/Makefile delete mode 100644 board/freescale/s32v234evb/clock.c delete mode 100644 board/freescale/s32v234evb/lpddr2.c delete mode 100644 board/freescale/s32v234evb/s32v234evb.c delete mode 100644 board/freescale/s32v234evb/s32v234evb.cfg delete mode 100644 configs/s32v234evb_defconfig delete mode 100644 include/configs/s32v234evb.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6263781e6f60..535b71d4df51 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -920,11 +920,6 @@ config ARCH_RMOBILE imply SYS_THUMB_BUILD imply ARCH_MISC_INIT if DISPLAY_CPUINFO
-config TARGET_S32V234EVB - bool "Support s32v234evb" - select ARM64 - select SYS_FSL_ERRATUM_ESDHC111 - config ARCH_SNAPDRAGON bool "Qualcomm Snapdragon SoCs" select ARM64 @@ -1967,7 +1962,6 @@ source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" source "board/freescale/lx2160a/Kconfig" -source "board/freescale/s32v234evb/Kconfig" source "board/grinn/chiliboard/Kconfig" source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/hikey960/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 9cd6a8d642b5..b7a10a8e34e6 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -116,7 +116,7 @@ config PSCI_RESET !TARGET_LS1046AFRWY && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \ - !ARCH_UNIPHIER && !TARGET_S32V234EVB + !ARCH_UNIPHIER help Most armv8 systems have PSCI support enabled in EL3, either through ARM Trusted Firmware or other firmware. diff --git a/arch/arm/cpu/armv8/s32v234/Makefile b/arch/arm/cpu/armv8/s32v234/Makefile deleted file mode 100644 index 3bdb98d995e1..000000000000 --- a/arch/arm/cpu/armv8/s32v234/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2013-2016, Freescale Semiconductor, Inc. - -obj-y += generic.o -obj-y += cpu.o diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c deleted file mode 100644 index 8ee3adc80584..000000000000 --- a/arch/arm/cpu/armv8/s32v234/cpu.c +++ /dev/null @@ -1,102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014-2016, Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <asm/cache.h> -#include <asm/io.h> -#include <asm/system.h> -#include <asm/armv8/mmu.h> -#include <asm/io.h> -#include <asm/arch/mc_me_regs.h> -#include <linux/bitops.h> -#include "cpu.h" - -u32 cpu_mask(void) -{ - return readl(MC_ME_CS); -} - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) - -#define S32V234_IRAM_BASE 0x3e800000UL -#define S32V234_IRAM_SIZE 0x800000UL -#define S32V234_DRAM_BASE1 0x80000000UL -#define S32V234_DRAM_SIZE1 0x40000000UL -#define S32V234_DRAM_BASE2 0xC0000000UL -#define S32V234_DRAM_SIZE2 0x20000000UL -#define S32V234_PERIPH_BASE 0x40000000UL -#define S32V234_PERIPH_SIZE 0x40000000UL - -static struct mm_region s32v234_mem_map[] = { - { - .virt = S32V234_IRAM_BASE, - .phys = S32V234_IRAM_BASE, - .size = S32V234_IRAM_SIZE, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE - }, { - .virt = S32V234_DRAM_BASE1, - .phys = S32V234_DRAM_BASE1, - .size = S32V234_DRAM_SIZE1, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE - }, { - .virt = S32V234_PERIPH_BASE, - .phys = S32V234_PERIPH_BASE, - .size = S32V234_PERIPH_SIZE, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE - /* TODO: Do we need these? */ - /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */ - }, { - .virt = S32V234_DRAM_BASE2, - .phys = S32V234_DRAM_BASE2, - .size = S32V234_DRAM_SIZE2, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_OUTER_SHARE - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = s32v234_mem_map; - -#endif - -/* - * Return the number of cores on this SOC. - */ -int cpu_numcores(void) -{ - int numcores; - u32 mask; - - mask = cpu_mask(); - numcores = hweight32(cpu_mask()); - - /* Verify if M4 is deactivated */ - if (mask & 0x1) - numcores--; - - return numcores; -} - -#if defined(CONFIG_ARCH_EARLY_INIT_R) -int arch_early_init_r(void) -{ - int rv; - asm volatile ("dsb sy"); - rv = fsl_s32v234_wake_seconday_cores(); - - if (rv) - printf("Did not wake secondary cores\n"); - - asm volatile ("sev"); - return 0; -} -#endif /* CONFIG_ARCH_EARLY_INIT_R */ diff --git a/arch/arm/cpu/armv8/s32v234/cpu.h b/arch/arm/cpu/armv8/s32v234/cpu.h deleted file mode 100644 index 11c3a6b435e9..000000000000 --- a/arch/arm/cpu/armv8/s32v234/cpu.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014-2016, Freescale Semiconductor, Inc. - */ - -u32 cpu_mask(void); -int cpu_numcores(void); diff --git a/arch/arm/cpu/armv8/s32v234/generic.c b/arch/arm/cpu/armv8/s32v234/generic.c deleted file mode 100644 index de5a098adb8f..000000000000 --- a/arch/arm/cpu/armv8/s32v234/generic.c +++ /dev/null @@ -1,353 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013-2016, Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <clock_legacy.h> -#include <cpu_func.h> -#include <init.h> -#include <net.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/mc_cgm_regs.h> -#include <asm/arch/mc_me_regs.h> -#include <asm/arch/mc_rgm_regs.h> -#include <netdev.h> -#include <div64.h> -#include <errno.h> - -u32 get_cpu_rev(void) -{ - struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR; - u32 cpu = readl(&mscmir->cpxtype); - - return cpu; -} - -DECLARE_GLOBAL_DATA_PTR; - -static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv, - u32 pllfd, u32 selected_output) -{ - u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0; - u32 plldv_rfdphi_div = 0, fout = 0; - u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0; - - if (selected_output > DFS_MAXNUMBER) { - return -1; - } - - plldv_prediv = - (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET; - plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK); - - pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK); - - plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv; - - /* The formula for VCO is from TR manual, rev. D */ - vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481); - - if (selected_output != 0) { - /* Determine the RFDPHI for PHI1 */ - plldv_rfdphi_div = - (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >> - PLLDIG_PLLDV_RFDPHI1_OFFSET; - plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div; - if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) { - dfs_portn = - readl(DFS_DVPORTn(pll, selected_output - 1)); - dfs_mfi = - (dfs_portn & DFS_DVPORTn_MFI_MASK) >> - DFS_DVPORTn_MFI_OFFSET; - dfs_mfn = - (dfs_portn & DFS_DVPORTn_MFI_MASK) >> - DFS_DVPORTn_MFI_OFFSET; - fout = vco / (dfs_mfi + (dfs_mfn / 256)); - } else { - fout = vco / plldv_rfdphi_div; - } - - } else { - /* Determine the RFDPHI for PHI0 */ - plldv_rfdphi_div = - (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >> - PLLDIG_PLLDV_RFDPHI_OFFSET; - fout = vco / plldv_rfdphi_div; - } - - return fout; - -} - -/* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */ -static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq, - u32 selected_output) -{ - u32 plldv, pllfd; - - plldv = readl(PLLDIG_PLLDV(pll)); - pllfd = readl(PLLDIG_PLLFD(pll)); - - return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output); -} - -static u32 get_mcu_main_clk(void) -{ - u32 coreclk_div; - u32 sysclk_sel; - u32 freq = 0; - - sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK; - sysclk_sel >>= MC_CGM_SC_SEL_OFFSET; - - coreclk_div = - readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK; - coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET; - coreclk_div += 1; - - switch (sysclk_sel) { - case MC_CGM_SC_SEL_FIRC: - freq = FIRC_CLK_FREQ; - break; - case MC_CGM_SC_SEL_XOSC: - freq = XOSC_CLK_FREQ; - break; - case MC_CGM_SC_SEL_ARMPLL: - /* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */ - freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0); - break; - case MC_CGM_SC_SEL_CLKDISABLE: - printf("Sysclk is disabled\n"); - break; - default: - printf("unsupported system clock select\n"); - } - - return freq / coreclk_div; -} - -static u32 get_sys_clk(u32 number) -{ - u32 sysclk_div, sysclk_div_number; - u32 sysclk_sel; - u32 freq = 0; - - switch (number) { - case 3: - sysclk_div_number = 0; - break; - case 6: - sysclk_div_number = 1; - break; - default: - printf("unsupported system clock \n"); - return -1; - } - sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK; - sysclk_sel >>= MC_CGM_SC_SEL_OFFSET; - - sysclk_div = - readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) & - MC_CGM_SC_DCn_PREDIV_MASK; - sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET; - sysclk_div += 1; - - switch (sysclk_sel) { - case MC_CGM_SC_SEL_FIRC: - freq = FIRC_CLK_FREQ; - break; - case MC_CGM_SC_SEL_XOSC: - freq = XOSC_CLK_FREQ; - break; - case MC_CGM_SC_SEL_ARMPLL: - /* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */ - freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1); - break; - case MC_CGM_SC_SEL_CLKDISABLE: - printf("Sysclk is disabled\n"); - break; - default: - printf("unsupported system clock select\n"); - } - - return freq / sysclk_div; -} - -static u32 get_peripherals_clk(void) -{ - u32 aux5clk_div; - u32 freq = 0; - - aux5clk_div = - readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) & - MC_CGM_ACn_DCm_PREDIV_MASK; - aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET; - aux5clk_div += 1; - - freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0); - - return freq / aux5clk_div; - -} - -static u32 get_uart_clk(void) -{ - u32 auxclk3_div, auxclk3_sel, freq = 0; - - auxclk3_sel = - readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK; - auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET; - - auxclk3_div = - readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) & - MC_CGM_ACn_DCm_PREDIV_MASK; - auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET; - auxclk3_div += 1; - - switch (auxclk3_sel) { - case MC_CGM_ACn_SEL_FIRC: - freq = FIRC_CLK_FREQ; - break; - case MC_CGM_ACn_SEL_XOSC: - freq = XOSC_CLK_FREQ; - break; - case MC_CGM_ACn_SEL_PERPLLDIVX: - freq = get_peripherals_clk() / 3; - break; - case MC_CGM_ACn_SEL_SYSCLK: - freq = get_sys_clk(6); - break; - default: - printf("unsupported system clock select\n"); - } - - return freq / auxclk3_div; -} - -static u32 get_fec_clk(void) -{ - u32 aux2clk_div; - u32 freq = 0; - - aux2clk_div = - readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) & - MC_CGM_ACn_DCm_PREDIV_MASK; - aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET; - aux2clk_div += 1; - - freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0); - - return freq / aux2clk_div; -} - -static u32 get_usdhc_clk(void) -{ - u32 aux15clk_div; - u32 freq = 0; - - aux15clk_div = - readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) & - MC_CGM_ACn_DCm_PREDIV_MASK; - aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET; - aux15clk_div += 1; - - freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4); - - return freq / aux15clk_div; -} - -static u32 get_i2c_clk(void) -{ - return get_peripherals_clk(); -} - -/* return clocks in Hz */ -unsigned int mxc_get_clock(enum mxc_clock clk) -{ - switch (clk) { - case MXC_ARM_CLK: - return get_mcu_main_clk(); - case MXC_PERIPHERALS_CLK: - return get_peripherals_clk(); - case MXC_UART_CLK: - return get_uart_clk(); - case MXC_FEC_CLK: - return get_fec_clk(); - case MXC_I2C_CLK: - return get_i2c_clk(); - case MXC_USDHC_CLK: - return get_usdhc_clk(); - default: - break; - } - printf("Error: Unsupported function to read the frequency! \ - Please define it correctly!"); - return -1; -} - -/* Not yet implemented - int soc_clk_dump(); */ - -#if defined(CONFIG_DISPLAY_CPUINFO) -static char *get_reset_cause(void) -{ - u32 cause = readl(MC_RGM_BASE_ADDR + 0x300); - - switch (cause) { - case F_SWT4: - return "WDOG"; - case F_JTAG: - return "JTAG"; - case F_FCCU_SOFT: - return "FCCU soft reaction"; - case F_FCCU_HARD: - return "FCCU hard reaction"; - case F_SOFT_FUNC: - return "Software Functional reset"; - case F_ST_DONE: - return "Self Test done reset"; - case F_EXT_RST: - return "External reset"; - default: - return "unknown reset"; - } - -} - -#define SRC_SCR_SW_RST (1<<12) - -void reset_cpu(ulong addr) -{ - printf("Feature not supported.\n"); -}; - -int print_cpuinfo(void) -{ - printf("CPU: Freescale Treerunner S32V234 at %d MHz\n", - mxc_get_clock(MXC_ARM_CLK) / 1000000); - printf("Reset cause: %s\n", get_reset_cause()); - - return 0; -} -#endif - -int cpu_eth_init(struct bd_info * bis) -{ - int rc = -ENODEV; - -#if defined(CONFIG_FEC_MXC) - rc = fecmxc_initialize(bis); -#endif - - return rc; -} - -int get_clocks(void) -{ -#ifdef CONFIG_FSL_ESDHC_IMX - gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK); -#endif - return 0; -} diff --git a/arch/arm/include/asm/arch-s32v234/clock.h b/arch/arm/include/asm/arch-s32v234/clock.h deleted file mode 100644 index 70846094e898..000000000000 --- a/arch/arm/include/asm/arch-s32v234/clock.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015-2016, Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_BUS_CLK, - MXC_PERIPHERALS_CLK, - MXC_UART_CLK, - MXC_USDHC_CLK, - MXC_FEC_CLK, - MXC_I2C_CLK, -}; -enum pll_type { - ARM_PLL = 0, - PERIPH_PLL, - ENET_PLL, - DDR_PLL, - VIDEO_PLL, -}; - -unsigned int mxc_get_clock(enum mxc_clock clk); -void clock_init(void); - -#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-s32v234/ddr.h b/arch/arm/include/asm/arch-s32v234/ddr.h deleted file mode 100644 index 8c709af80d40..000000000000 --- a/arch/arm/include/asm/arch-s32v234/ddr.h +++ /dev/null @@ -1,156 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015-2016, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_DDR_H__ -#define __ARCH_ARM_MACH_S32V234_DDR_H__ - -#define DDR0 0 -#define DDR1 1 - -/* DDR offset in MSCR register */ -#define _DDR0_RESET 168 -#define _DDR0_CLK0 169 -#define _DDR0_CAS 170 -#define _DDR0_RAS 171 -#define _DDR0_WE_B 172 -#define _DDR0_CKE0 173 -#define _DDR0_CKE1 174 -#define _DDR0_CS_B0 175 -#define _DDR0_CS_B1 176 -#define _DDR0_BA0 177 -#define _DDR0_BA1 178 -#define _DDR0_BA2 179 -#define _DDR0_A0 180 -#define _DDR0_A1 181 -#define _DDR0_A2 182 -#define _DDR0_A3 183 -#define _DDR0_A4 184 -#define _DDR0_A5 185 -#define _DDR0_A6 186 -#define _DDR0_A7 187 -#define _DDR0_A8 188 -#define _DDR0_A9 189 -#define _DDR0_A10 190 -#define _DDR0_A11 191 -#define _DDR0_A12 192 -#define _DDR0_A13 193 -#define _DDR0_A14 194 -#define _DDR0_A15 195 -#define _DDR0_DM0 196 -#define _DDR0_DM1 197 -#define _DDR0_DM2 198 -#define _DDR0_DM3 199 -#define _DDR0_DQS0 200 -#define _DDR0_DQS1 201 -#define _DDR0_DQS2 202 -#define _DDR0_DQS3 203 -#define _DDR0_D0 204 -#define _DDR0_D1 205 -#define _DDR0_D2 206 -#define _DDR0_D3 207 -#define _DDR0_D4 208 -#define _DDR0_D5 209 -#define _DDR0_D6 210 -#define _DDR0_D7 211 -#define _DDR0_D8 212 -#define _DDR0_D9 213 -#define _DDR0_D10 214 -#define _DDR0_D11 215 -#define _DDR0_D12 216 -#define _DDR0_D13 217 -#define _DDR0_D14 218 -#define _DDR0_D15 219 -#define _DDR0_D16 220 -#define _DDR0_D17 221 -#define _DDR0_D18 222 -#define _DDR0_D19 223 -#define _DDR0_D20 224 -#define _DDR0_D21 225 -#define _DDR0_D22 226 -#define _DDR0_D23 227 -#define _DDR0_D24 228 -#define _DDR0_D25 229 -#define _DDR0_D26 230 -#define _DDR0_D27 231 -#define _DDR0_D28 232 -#define _DDR0_D29 233 -#define _DDR0_D30 234 -#define _DDR0_D31 235 -#define _DDR0_ODT0 236 -#define _DDR0_ODT1 237 -#define _DDR0_ZQ 238 -#define _DDR1_RESET 239 -#define _DDR1_CLK0 240 -#define _DDR1_CAS 241 -#define _DDR1_RAS 242 -#define _DDR1_WE_B 243 -#define _DDR1_CKE0 244 -#define _DDR1_CKE1 245 -#define _DDR1_CS_B0 246 -#define _DDR1_CS_B1 247 -#define _DDR1_BA0 248 -#define _DDR1_BA1 249 -#define _DDR1_BA2 250 -#define _DDR1_A0 251 -#define _DDR1_A1 252 -#define _DDR1_A2 253 -#define _DDR1_A3 254 -#define _DDR1_A4 255 -#define _DDR1_A5 256 -#define _DDR1_A6 257 -#define _DDR1_A7 258 -#define _DDR1_A8 259 -#define _DDR1_A9 260 -#define _DDR1_A10 261 -#define _DDR1_A11 262 -#define _DDR1_A12 263 -#define _DDR1_A13 264 -#define _DDR1_A14 265 -#define _DDR1_A15 266 -#define _DDR1_DM0 267 -#define _DDR1_DM1 268 -#define _DDR1_DM2 269 -#define _DDR1_DM3 270 -#define _DDR1_DQS0 271 -#define _DDR1_DQS1 272 -#define _DDR1_DQS2 273 -#define _DDR1_DQS3 274 -#define _DDR1_D0 275 -#define _DDR1_D1 276 -#define _DDR1_D2 277 -#define _DDR1_D3 278 -#define _DDR1_D4 279 -#define _DDR1_D5 280 -#define _DDR1_D6 281 -#define _DDR1_D7 282 -#define _DDR1_D8 283 -#define _DDR1_D9 284 -#define _DDR1_D10 285 -#define _DDR1_D11 286 -#define _DDR1_D12 287 -#define _DDR1_D13 288 -#define _DDR1_D14 289 -#define _DDR1_D15 290 -#define _DDR1_D16 291 -#define _DDR1_D17 292 -#define _DDR1_D18 293 -#define _DDR1_D19 294 -#define _DDR1_D20 295 -#define _DDR1_D21 296 -#define _DDR1_D22 297 -#define _DDR1_D23 298 -#define _DDR1_D24 299 -#define _DDR1_D25 300 -#define _DDR1_D26 301 -#define _DDR1_D27 302 -#define _DDR1_D28 303 -#define _DDR1_D29 304 -#define _DDR1_D30 305 -#define _DDR1_D31 306 -#define _DDR1_ODT0 307 -#define _DDR1_ODT1 308 -#define _DDR1_ZQ 309 - -#endif diff --git a/arch/arm/include/asm/arch-s32v234/imx-regs.h b/arch/arm/include/asm/arch-s32v234/imx-regs.h deleted file mode 100644 index 1472a43f1bc2..000000000000 --- a/arch/arm/include/asm/arch-s32v234/imx-regs.h +++ /dev/null @@ -1,328 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2016, Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_IMX_REGS_H__ -#define __ASM_ARCH_IMX_REGS_H__ - -#define ARCH_MXC - -#define IRAM_BASE_ADDR 0x3E800000 /* internal ram */ -#define IRAM_SIZE 0x00400000 /* 4MB */ - -#define AIPS0_BASE_ADDR (0x40000000UL) -#define AIPS1_BASE_ADDR (0x40080000UL) - -/* AIPS 0 */ -#define AXBS_BASE_ADDR (AIPS0_BASE_ADDR + 0x00000000) -#define CSE3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000) -#define EDMA_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000) -#define XRDC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00004000) -#define SWT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000) -#define SWT1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000) -#define STM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000) -#define NIC301_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000) -#define GC3000_BASE_ADDR (AIPS0_BASE_ADDR + 0x00020000) -#define DEC200_DECODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00026000) -#define DEC200_ENCODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00027000) -#define TWOD_ACE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00028000) -#define MIPI_CSI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000) -#define DMAMUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000) -#define ENET_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000) -#define FLEXRAY_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000) -#define MMDC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000) -#define MEW0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000) -#define MONITOR_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000) -#define MONITOR_CCI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000) -#define PIT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003A000) -#define MC_CGM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003C000) -#define MC_CGM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003F000) -#define MC_CGM2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000) -#define MC_CGM3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00045000) -#define MC_RGM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) -#define MC_ME_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004A000) -#define MC_PCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004B000) -#define ADC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004D000) -#define FLEXTIMER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004F000) -#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00051000) -#define LINFLEXD0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00053000) -#define FLEXCAN0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00055000) -#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00057000) -#define SPI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00059000) -#define CRC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005B000) -#define USDHC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005D000) -#define OCOTP_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005F000) -#define WKPU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000) -#define VIU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00064000) -#define HPSMI_SRAM_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00068000) -#define SIUL2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000) -#define SIPI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00074000) -#define LFAST_BASE_ADDR (AIPS0_BASE_ADDR + 0x00078000) -#define SSE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00079000) -#define SRC_SOC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0007C000) - -/* AIPS 1 */ -#define ERM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000000000) -#define MSCM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000001000) -#define SEMA42_BASE_ADDR (AIPS1_BASE_ADDR + 0X000002000) -#define INTC_MON_BASE_ADDR (AIPS1_BASE_ADDR + 0X000003000) -#define SWT2_BASE_ADDR (AIPS1_BASE_ADDR + 0X000004000) -#define SWT3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000005000) -#define SWT4_BASE_ADDR (AIPS1_BASE_ADDR + 0X000006000) -#define STM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000007000) -#define EIM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000008000) -#define APB_BASE_ADDR (AIPS1_BASE_ADDR + 0X000009000) -#define XBIC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000012000) -#define MIPI_BASE_ADDR (AIPS1_BASE_ADDR + 0X000020000) -#define DMAMUX1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000021000) -#define MMDC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000022000) -#define MEW1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000023000) -#define DDR1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000024000) -#define CCI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000025000) -#define QUADSPI0_BASE_ADDR (AIPS1_BASE_ADDR + 0X000026000) -#define PIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00002A000) -#define FCCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000030000) -#define FLEXTIMER_FTM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000036000) -#define I2C1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000038000) -#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003A000) -#define LINFLEXD1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003C000) -#define FLEXCAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003E000) -#define SPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000040000) -#define SPI3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000042000) -#define IPL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000043000) -#define CGM_CMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000044000) -#define PMC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000048000) -#define CRC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004C000) -#define TMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004E000) -#define VIU1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000050000) -#define JPEG_BASE_ADDR (AIPS1_BASE_ADDR + 0X000054000) -#define H264_DEC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000058000) -#define H264_ENC_BASE_ADDR (AIPS1_BASE_ADDR + 0X00005C000) -#define MEMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000060000) -#define STCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000064000) -#define SLFTST_CTRL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000066000) -#define MCT_BASE_ADDR (AIPS1_BASE_ADDR + 0X000068000) -#define REP_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006A000) -#define MBIST_CONTROLLER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006C000) -#define BOOT_LOADER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006F000) - -/* TODO Remove this after the IOMUX framework is implemented */ -#define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR - -/* MUX mode and PAD ctrl are in one register */ -#define CONFIG_IOMUX_SHARE_CONF_REG - -#define FEC_QUIRK_ENET_MAC -#define I2C_QUIRK_REG - -/* MSCM interrupt router */ -#define MSCM_IRSPRC_CPn_EN 3 -#define MSCM_IRSPRC_NUM 176 -#define MSCM_CPXTYPE_RYPZ_MASK 0xFF -#define MSCM_CPXTYPE_RYPZ_OFFSET 0 -#define MSCM_CPXTYPE_PERS_MASK 0xFFFFFF00 -#define MSCM_CPXTYPE_PERS_OFFSET 8 -#define MSCM_CPXTYPE_PERS_A53 0x413533 -#define MSCM_CPXTYPE_PERS_CM4 0x434d34 - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* System Reset Controller (SRC) */ -struct src { - u32 bmr1; - u32 bmr2; - u32 gpr1_boot; - u32 reserved_0x00C[61]; - u32 gpr1; - u32 gpr2; - u32 gpr3; - u32 gpr4; - u32 gpr5; - u32 gpr6; - u32 gpr7; - u32 reserved_0x11C[1]; - u32 gpr9; - u32 gpr10; - u32 gpr11; - u32 gpr12; - u32 gpr13; - u32 gpr14; - u32 gpr15; - u32 gpr16; - u32 reserved_0x140[1]; - u32 gpr17; - u32 gpr18; - u32 gpr19; - u32 gpr20; - u32 gpr21; - u32 gpr22; - u32 gpr23; - u32 gpr24; - u32 gpr25; - u32 gpr26; - u32 gpr27; - u32 reserved_0x16C[5]; - u32 pcie_config1; - u32 ddr_self_ref_ctrl; - u32 pcie_config0; - u32 reserved_0x18C[4]; - u32 soc_misc_config2; -}; - -/* SRC registers definitions */ - -/* SRC_GPR1 */ -#define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \ - (SRC_GPR1_PLL_OFFSET + (pll)) ) -#define SRC_GPR1_PLL_SOURCE_MASK (0x1) - -#define SRC_GPR1_PLL_OFFSET (27) -#define SRC_GPR1_FIRC_CLK_SOURCE (0x0) -#define SRC_GPR1_XOSC_CLK_SOURCE (0x1) - -/* Periodic Interrupt Timer (PIT) */ -struct pit_reg { - u32 mcr; - u32 recv0[55]; - u32 ltmr64h; - u32 ltmr64l; - u32 recv1[6]; - u32 ldval0; - u32 cval0; - u32 tctrl0; - u32 tflg0; - u32 ldval1; - u32 cval1; - u32 tctrl1; - u32 tflg1; - u32 ldval2; - u32 cval2; - u32 tctrl2; - u32 tflg2; - u32 ldval3; - u32 cval3; - u32 tctrl3; - u32 tflg3; - u32 ldval4; - u32 cval4; - u32 tctrl4; - u32 tflg4; - u32 ldval5; - u32 cval5; - u32 tctrl5; - u32 tflg5; -}; - -/* Watchdog Timer (WDOG) */ -struct wdog_regs { - u32 cr; - u32 ir; - u32 to; - u32 wn; - u32 sr; - u32 co; - u32 sk; -}; - -/* UART */ -struct linflex_fsl { - u32 lincr1; - u32 linier; - u32 linsr; - u32 linesr; - u32 uartcr; - u32 uartsr; - u32 lintcsr; - u32 linocr; - u32 lintocr; - u32 linfbrr; - u32 linibrr; - u32 lincfr; - u32 lincr2; - u32 bidr; - u32 bdrl; - u32 bdrm; - u32 ifer; - u32 ifmi; - u32 ifmr; - u32 ifcr0; - u32 ifcr1; - u32 ifcr2; - u32 ifcr3; - u32 ifcr4; - u32 ifcr5; - u32 ifcr6; - u32 ifcr7; - u32 ifcr8; - u32 ifcr9; - u32 ifcr10; - u32 ifcr11; - u32 ifcr12; - u32 ifcr13; - u32 ifcr14; - u32 ifcr15; - u32 gcr; - u32 uartpto; - u32 uartcto; - u32 dmatxe; - u32 dmarxe; -}; - -/* MSCM Interrupt Router */ -struct mscm_ir { - u32 cpxtype; /* Processor x Type Register */ - u32 cpxnum; /* Processor x Number Register */ - u32 cpxmaster; /* Processor x Master Number Register */ - u32 cpxcount; /* Processor x Count Register */ - u32 cpxcfg0; /* Processor x Configuration 0 Register */ - u32 cpxcfg1; /* Processor x Configuration 1 Register */ - u32 cpxcfg2; /* Processor x Configuration 2 Register */ - u32 cpxcfg3; /* Processor x Configuration 3 Register */ - u32 cp0type; /* Processor 0 Type Register */ - u32 cp0num; /* Processor 0 Number Register */ - u32 cp0master; /* Processor 0 Master Number Register */ - u32 cp0count; /* Processor 0 Count Register */ - u32 cp0cfg0; /* Processor 0 Configuration 0 Register */ - u32 cp0cfg1; /* Processor 0 Configuration 1 Register */ - u32 cp0cfg2; /* Processor 0 Configuration 2 Register */ - u32 cp0cfg3; /* Processor 0 Configuration 3 Register */ - u32 cp1type; /* Processor 1 Type Register */ - u32 cp1num; /* Processor 1 Number Register */ - u32 cp1master; /* Processor 1 Master Number Register */ - u32 cp1count; /* Processor 1 Count Register */ - u32 cp1cfg0; /* Processor 1 Configuration 0 Register */ - u32 cp1cfg1; /* Processor 1 Configuration 1 Register */ - u32 cp1cfg2; /* Processor 1 Configuration 2 Register */ - u32 cp1cfg3; /* Processor 1 Configuration 3 Register */ - u32 reserved_0x060[232]; - u32 ocmdr0; /* On-Chip Memory Descriptor Register */ - u32 reserved_0x404[2]; - u32 ocmdr3; /* On-Chip Memory Descriptor Register */ - u32 reserved_0x410[28]; - u32 tcmdr[4]; /* Generic Tightly Coupled Memory Descriptor Register */ - u32 reserved_0x490[28]; - u32 cpce0; /* Core Parity Checking Enable Register 0 */ - u32 reserved_0x504[191]; - u32 ircp0ir; /* Interrupt Router CP0 Interrupt Register */ - u32 ircp1ir; /* Interrupt Router CP1 Interrupt Register */ - u32 reserved_0x808[6]; - u32 ircpgir; /* Interrupt Router CPU Generate Interrupt Register */ - u32 reserved_0x824[23]; - u16 irsprc[176]; /* Interrupt Router Shared Peripheral Routing Control Register */ - u32 reserved_0x9e0[136]; - u32 iahbbe0; /* Gasket Burst Enable Register */ - u32 reserved_0xc04[63]; - u32 ipcge; /* Interconnect Parity Checking Global Enable Register */ - u32 reserved_0xd04[3]; - u32 ipce[4]; /* Interconnect Parity Checking Enable Register */ - u32 reserved_0xd20[8]; - u32 ipcgie; /* Interconnect Parity Checking Global Injection Enable Register */ - u32 reserved_0xd44[3]; - u32 ipcie[4]; /* Interconnect Parity Checking Injection Enable Register */ -}; - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-s32v234/lpddr2.h b/arch/arm/include/asm/arch-s32v234/lpddr2.h deleted file mode 100644 index c5efee5b75d0..000000000000 --- a/arch/arm/include/asm/arch-s32v234/lpddr2.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015-2016, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_LPDDR2_H__ -#define __ARCH_ARM_MACH_S32V234_LPDDR2_H__ - -/* definitions for LPDDR2 PAD values */ -#define LPDDR2_CLK0_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ - SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_CRPOINT_TRIM_1 | \ - SIUL2_MSCR_DCYCLE_TRIM_NONE) -#define LPDDR2_CKEn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ - SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm) -#define LPDDR2_CS_Bn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ - SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm) -#define LPDDR2_DMn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ - SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm) -#define LPDDR2_DQSn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \ - SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUE_EN | SIUL2_MSCR_PUS_100K_DOWN | \ - SIUL2_MSCR_PKE_EN | SIUL2_MSCR_CRPOINT_TRIM_1 | SIUL2_MSCR_DCYCLE_TRIM_NONE) -#define LPDDR2_An_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \ - SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \ - SIUL2_MSCR_PUS_100K_UP) -#define LPDDR2_Dn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \ - SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \ - SIUL2_MSCR_PUS_100K_UP) - -#define _MDCTL 0x03010000 - -#define MMDC_MDSCR_CFG_VALUE 0x00008000 /* Set MDSCR[CON_REQ] (configuration request) */ -#define MMDC_MDCFG0_VALUE 0x464F61A5 /* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns),tXPDLL=n/a,tFAW=27 (50 ns),tCL(RL)=8 */ -#define MMDC_MDCFG1_VALUE 0x00180E63 /* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR=8 (=15.0ns),tMRD=3,tWL=4 */ -#define MMDC_MDCFG2_VALUE 0x000000DD /* tDLLK=n/a,tRTP=4 (=7.5ns),tWTR=4 (=7.5ns),tRRD=6 (=10ns) */ -#define MMDC_MDCFG3LP_VALUE 0x001F099B /* RC_LP=tRAS+tRPab=32 (>60ns), tRCD_LP=10 (18ns) , tRPpb_LP=10 (18ns), tRPab_LP=12 (21ns) */ -#define MMDC_MDOTC_VALUE 0x00000000 /* tAOFPD=n/a,tAONPD=n/a,tANPD=n/a,tAXPD=n/a,tODTLon=n/a,tODT_idle_off=n/a */ -#define MMDC_MDMISC_VALUE 0x00001688 /* WALAT=0, BI bank interleave on, LPDDR2_S2=0, MIF3=3, RALAT=2, 8 banks, LPDDR2 */ -#define MMDC_MDOR_VALUE 0x00000010 /* tXPR=n/a , SDE_to_RST=n/a, RST_to_CKE=14 */ -#define MMDC_MPMUR0_VALUE 0x00000800 /* Force delay line initialisation */ -#define MMDC_MDSCR_RST_VALUE 0x003F8030 /* Reset command CS0 */ -#define MMDC_MPZQLP2CTL_VALUE 0x1B5F0109 /* ZQ_LP2_HW_ZQCS=0x1B (90ns spec), ZQ_LP2_HW_ZQCL=0x5F (160ns spec), ZQ_LP2_HW_ZQINIT=0x109 (1us spec) */ -#define MMDC_MPZQHWCTRL_VALUE 0xA0010003 /* ZQ_EARLY_COMPARATOR_EN_TIMER=0x14, TZQ_CS=n/a, TZQ_OPER=n/a, TZQ_INIT=n/a, ZQ_HW_FOR=1, ZQ_HW_PER=0, ZQ_MODE=3 */ -#define MMDC_MDSCR_MR1_VALUE 0xC2018030 /* Configure MR1: BL 4, burst type interleaved, wrap control no wrap, tWR cycles 8 */ -#define MMDC_MDSCR_MR2_VALUE 0x06028030 /* Configure MR2: RL=8, WL=4 */ -#define MMDC_MDSCR_MR3_VALUE 0x01038030 /* Configure MR3: DS=34R */ -#define MMDC_MDSCR_MR10_VALUE 0xFF0A8030 /* Configure MR10: Calibration at init */ -#define MMDC_MDASP_MODULE0_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0x90000000) */ -#define MMDC_MPRDDLCTL_MODULE0_VALUE 0x4D4B4F4B /* Read delay line offsets */ -#define MMDC_MPWRDLCTL_MODULE0_VALUE 0x38383737 /* Write delay line offsets */ -#define MMDC_MPDGCTRL0_MODULE0_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */ -#define MMDC_MPDGCTRL1_MODULE0_VALUE 0x00000000 /* Read DQS gating control 1 */ -#define MMDC_MDASP_MODULE1_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0xD0000000) */ -#define MMDC_MPRDDLCTL_MODULE1_VALUE 0x4D4B4F4B /* Read delay line offsets */ -#define MMDC_MPWRDLCTL_MODULE1_VALUE 0x38383737 /* Write delay line offsets */ -#define MMDC_MPDGCTRL0_MODULE1_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */ -#define MMDC_MPDGCTRL1_MODULE1_VALUE 0x00000000 /* Read DQS gating control 1 */ -#define MMDC_MDRWD_VALUE 0x0F9F26D2 /* Read/write command delay - default used */ -#define MMDC_MDPDC_VALUE 0x00020024 /* Power down control */ -#define MMDC_MDREF_VALUE 0x30B01800 /* Refresh control */ -#define MMDC_MPODTCTRL_VALUE 0x00000000 /* No ODT */ -#define MMDC_MDSCR_DEASSERT_VALUE 0x00000000 /* Deassert the configuration request */ - -/* set I/O pads for DDR */ -void lpddr2_config_iomux(uint8_t module); -void config_mmdc(uint8_t module); - -#endif diff --git a/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h deleted file mode 100644 index 957d48f9c03a..000000000000 --- a/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h +++ /dev/null @@ -1,253 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ -#define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ - -#ifndef __ASSEMBLY__ - -/* MC_CGM registers definitions */ -/* MC_CGM_SC_SS */ -#define CGM_SC_SS(cgm_addr) ( ((cgm_addr) + 0x000007E4) ) -#define MC_CGM_SC_SEL_FIRC (0x0) -#define MC_CGM_SC_SEL_XOSC (0x1) -#define MC_CGM_SC_SEL_ARMPLL (0x2) -#define MC_CGM_SC_SEL_CLKDISABLE (0xF) - -/* MC_CGM_SC_DCn */ -#define CGM_SC_DCn(cgm_addr,dc) ( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) ) -#define MC_CGM_SC_DCn_PREDIV(val) (MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET)) -#define MC_CGM_SC_DCn_PREDIV_MASK (0x00070000) -#define MC_CGM_SC_DCn_PREDIV_OFFSET (16) -#define MC_CGM_SC_DCn_DE (1 << 31) -#define MC_CGM_SC_SEL_MASK (0x0F000000) -#define MC_CGM_SC_SEL_OFFSET (24) - -/* MC_CGM_ACn_DCm */ -#define CGM_ACn_DCm(cgm_addr,ac,dc) ( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) ) -#define MC_CGM_ACn_DCm_PREDIV(val) (MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET)) - -/* - * MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown - * that the 5th bit is always ignored during writes if the current - * MC_CGM_ACn_DCm_PREDIV field has only 4 bits - * - * The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits - * - * This should be changed if any problems occur. - */ -#define MC_CGM_ACn_DCm_PREDIV_MASK (0x001F0000) -#define MC_CGM_ACn_DCm_PREDIV_OFFSET (16) -#define MC_CGM_ACn_DCm_DE (1 << 31) - -/* - * MC_CGM_ACn_SC/MC_CGM_ACn_SS - */ -#define CGM_ACn_SC(cgm_addr,ac) ((cgm_addr + 0x00000800) + ((ac) * 0x20)) -#define CGM_ACn_SS(cgm_addr,ac) ((cgm_addr + 0x00000804) + ((ac) * 0x20)) -#define MC_CGM_ACn_SEL_MASK (0x07000000) -#define MC_CGM_ACn_SEL_SET(source) (MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET)) -#define MC_CGM_ACn_SEL_OFFSET (24) - -#define MC_CGM_ACn_SEL_FIRC (0x0) -#define MC_CGM_ACn_SEL_XOSC (0x1) -#define MC_CGM_ACn_SEL_ARMPLL (0x2) -/* - * According to the manual some PLL can be divided by X (X={1,3,5}): - * PERPLLDIVX, VIDEOPLLDIVX. - */ -#define MC_CGM_ACn_SEL_PERPLLDIVX (0x3) -#define MC_CGM_ACn_SEL_ENETPLL (0x4) -#define MC_CGM_ACn_SEL_DDRPLL (0x5) -#define MC_CGM_ACn_SEL_EXTSRCPAD (0x7) -#define MC_CGM_ACn_SEL_SYSCLK (0x8) -#define MC_CGM_ACn_SEL_VIDEOPLLDIVX (0x9) -#define MC_CGM_ACn_SEL_PERCLK (0xA) - -/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */ -#define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80)) -#define PLLDIG_PLLDV_MFD(div) (PLLDIG_PLLDV_MFD_MASK & (div)) -#define PLLDIG_PLLDV_MFD_MASK (0x000000FF) - -/* - * PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to - * the reference manual. This other value respect the formula 2^[RFDPHIBY+1] - */ -#define PLLDIG_PLLDV_RFDPHI_SET(val) (PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET)) -#define PLLDIG_PLLDV_RFDPHI_MASK (0x003F0000) -#define PLLDIG_PLLDV_RFDPHI_MAXVALUE (0x3F) -#define PLLDIG_PLLDV_RFDPHI_OFFSET (16) - -#define PLLDIG_PLLDV_RFDPHI1_SET(val) (PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET)) -#define PLLDIG_PLLDV_RFDPHI1_MASK (0x7E000000) -#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE (0x3F) -#define PLLDIG_PLLDV_RFDPHI1_OFFSET (25) - -#define PLLDIG_PLLDV_PREDIV_SET(val) (PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET)) -#define PLLDIG_PLLDV_PREDIV_MASK (0x00007000) -#define PLLDIG_PLLDV_PREDIV_MAXVALUE (0x7) -#define PLLDIG_PLLDV_PREDIV_OFFSET (12) - -/* PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD) */ -#define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80)) -#define PLLDIG_PLLFD_MFN_SET(val) (PLLDIG_PLLFD_MFN_MASK & (val)) -#define PLLDIG_PLLFD_MFN_MASK (0x00007FFF) -#define PLLDIG_PLLFD_SMDEN (1 << 30) - -/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */ -#define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80)) -#define PLLDIG_PLLCAL1_NDAC1_SET(val) (PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET)) -#define PLLDIG_PLLCAL1_NDAC1_OFFSET (24) -#define PLLDIG_PLLCAL1_NDAC1_MASK (0x7F000000) - -/* Digital Frequency Synthesizer (DFS) */ -/* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */ -#define DFS0_BASE_ADDR (MC_CGM0_BASE_ADDR + 0x00000040) - -/* DFS DLL Program Register 1 */ -#define DFS_DLLPRG1(pll) (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80)) - -#define DFS_DLLPRG1_V2IGC_SET(val) (DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET)) -#define DFS_DLLPRG1_V2IGC_OFFSET (0) -#define DFS_DLLPRG1_V2IGC_MASK (0x00000007) - -#define DFS_DLLPRG1_LCKWT_SET(val) (DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET)) -#define DFS_DLLPRG1_LCKWT_OFFSET (4) -#define DFS_DLLPRG1_LCKWT_MASK (0x00000030) - -#define DFS_DLLPRG1_DACIN_SET(val) (DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET)) -#define DFS_DLLPRG1_DACIN_OFFSET (6) -#define DFS_DLLPRG1_DACIN_MASK (0x000001C0) - -#define DFS_DLLPRG1_CALBYPEN_SET(val) (DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET)) -#define DFS_DLLPRG1_CALBYPEN_OFFSET (9) -#define DFS_DLLPRG1_CALBYPEN_MASK (0x00000200) - -#define DFS_DLLPRG1_VSETTLCTRL_SET(val) (DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET)) -#define DFS_DLLPRG1_VSETTLCTRL_OFFSET (10) -#define DFS_DLLPRG1_VSETTLCTRL_MASK (0x00000C00) - -#define DFS_DLLPRG1_CPICTRL_SET(val) (DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET)) -#define DFS_DLLPRG1_CPICTRL_OFFSET (12) -#define DFS_DLLPRG1_CPICTRL_MASK (0x00007000) - -/* DFS Control Register (DFS_CTRL) */ -#define DFS_CTRL(pll) (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80)) -#define DFS_CTRL_DLL_LOLIE (1 << 0) -#define DFS_CTRL_DLL_RESET (1 << 1) - -/* DFS Port Status Register (DFS_PORTSR) */ -#define DFS_PORTSR(pll) (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80)) -/* DFS Port Reset Register (DFS_PORTRESET) */ -#define DFS_PORTRESET(pll) (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80)) -#define DFS_PORTRESET_PORTRESET_SET(val) (DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET)) -#define DFS_PORTRESET_PORTRESET_MAXVAL (0xF) -#define DFS_PORTRESET_PORTRESET_MASK (0x0000000F) -#define DFS_PORTRESET_PORTRESET_OFFSET (0) - -/* DFS Divide Register Portn (DFS_DVPORTn) */ -#define DFS_DVPORTn(pll,n) (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4))) - -/* - * The mathematical formula for fdfs_clockout is the following: - * fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) ) - */ -#define DFS_DVPORTn_MFI_SET(val) (DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) ) -#define DFS_DVPORTn_MFN_SET(val) (DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) ) -#define DFS_DVPORTn_MFI_MASK (0x0000FF00) -#define DFS_DVPORTn_MFN_MASK (0x000000FF) -#define DFS_DVPORTn_MFI_MAXVAL (0xFF) -#define DFS_DVPORTn_MFN_MAXVAL (0xFF) -#define DFS_DVPORTn_MFI_OFFSET (8) -#define DFS_DVPORTn_MFN_OFFSET (0) -#define DFS_MAXNUMBER (4) - -#define DFS_PARAMS_Nr (3) - -/* Frequencies are in Hz */ -#define FIRC_CLK_FREQ (48000000) -#define XOSC_CLK_FREQ (40000000) - -#define PLL_MIN_FREQ (650000000) -#define PLL_MAX_FREQ (1300000000) - -#define ARM_PLL_PHI0_FREQ (1000000000) -#define ARM_PLL_PHI1_FREQ (1000000000) -/* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */ -#define ARM_PLL_PHI1_DFS1_EN (1) -#define ARM_PLL_PHI1_DFS1_MFI (3) -#define ARM_PLL_PHI1_DFS1_MFN (194) -/* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */ -#define ARM_PLL_PHI1_DFS2_EN (1) -#define ARM_PLL_PHI1_DFS2_MFI (1) -#define ARM_PLL_PHI1_DFS2_MFN (170) -/* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */ -#define ARM_PLL_PHI1_DFS3_EN (1) -#define ARM_PLL_PHI1_DFS3_MFI (1) -#define ARM_PLL_PHI1_DFS3_MFN (170) -#define ARM_PLL_PHI1_DFS_Nr (3) -#define ARM_PLL_PLLDV_PREDIV (2) -#define ARM_PLL_PLLDV_MFD (50) -#define ARM_PLL_PLLDV_MFN (0) - -#define PERIPH_PLL_PHI0_FREQ (400000000) -#define PERIPH_PLL_PHI1_FREQ (100000000) -#define PERIPH_PLL_PHI1_DFS_Nr (0) -#define PERIPH_PLL_PLLDV_PREDIV (1) -#define PERIPH_PLL_PLLDV_MFD (30) -#define PERIPH_PLL_PLLDV_MFN (0) - -#define ENET_PLL_PHI0_FREQ (500000000) -#define ENET_PLL_PHI1_FREQ (1000000000) -/* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/ -#define ENET_PLL_PHI1_DFS1_EN (1) -#define ENET_PLL_PHI1_DFS1_MFI (2) -#define ENET_PLL_PHI1_DFS1_MFN (219) -/* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/ -#define ENET_PLL_PHI1_DFS2_EN (1) -#define ENET_PLL_PHI1_DFS2_MFI (2) -#define ENET_PLL_PHI1_DFS2_MFN (219) -/* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/ -#define ENET_PLL_PHI1_DFS3_EN (1) -#define ENET_PLL_PHI1_DFS3_MFI (3) -#define ENET_PLL_PHI1_DFS3_MFN (32) -/* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/ -#define ENET_PLL_PHI1_DFS4_EN (1) -#define ENET_PLL_PHI1_DFS4_MFI (2) -#define ENET_PLL_PHI1_DFS4_MFN (0) -#define ENET_PLL_PHI1_DFS_Nr (4) -#define ENET_PLL_PLLDV_PREDIV (2) -#define ENET_PLL_PLLDV_MFD (50) -#define ENET_PLL_PLLDV_MFN (0) - -#define DDR_PLL_PHI0_FREQ (533000000) -#define DDR_PLL_PHI1_FREQ (1066000000) -/* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */ -#define DDR_PLL_PHI1_DFS1_EN (1) -#define DDR_PLL_PHI1_DFS1_MFI (2) -#define DDR_PLL_PHI1_DFS1_MFN (33) -/* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */ -#define DDR_PLL_PHI1_DFS2_EN (1) -#define DDR_PLL_PHI1_DFS2_MFI (2) -#define DDR_PLL_PHI1_DFS2_MFN (33) -/* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */ -#define DDR_PLL_PHI1_DFS3_EN (1) -#define DDR_PLL_PHI1_DFS3_MFI (3) -#define DDR_PLL_PHI1_DFS3_MFN (11) -#define DDR_PLL_PHI1_DFS_Nr (3) -#define DDR_PLL_PLLDV_PREDIV (2) -#define DDR_PLL_PLLDV_MFD (53) -#define DDR_PLL_PLLDV_MFN (6144) - -#define VIDEO_PLL_PHI0_FREQ (600000000) -#define VIDEO_PLL_PHI1_FREQ (0) -#define VIDEO_PLL_PHI1_DFS_Nr (0) -#define VIDEO_PLL_PLLDV_PREDIV (1) -#define VIDEO_PLL_PLLDV_MFD (30) -#define VIDEO_PLL_PLLDV_MFN (0) - -#endif - -#endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-s32v234/mc_me_regs.h b/arch/arm/include/asm/arch-s32v234/mc_me_regs.h deleted file mode 100644 index 1671af4adb3b..000000000000 --- a/arch/arm/include/asm/arch-s32v234/mc_me_regs.h +++ /dev/null @@ -1,198 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__ -#define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__ - -#ifndef __ASSEMBLY__ - -/* MC_ME registers definitions */ - -/* MC_ME_GS */ -#define MC_ME_GS (MC_ME_BASE_ADDR + 0x00000000) - -#define MC_ME_GS_S_SYSCLK_FIRC (0x0 << 0) -#define MC_ME_GS_S_SYSCLK_FXOSC (0x1 << 0) -#define MC_ME_GS_S_SYSCLK_ARMPLL (0x2 << 0) -#define MC_ME_GS_S_STSCLK_DISABLE (0xF << 0) -#define MC_ME_GS_S_FIRC (1 << 4) -#define MC_ME_GS_S_XOSC (1 << 5) -#define MC_ME_GS_S_ARMPLL (1 << 6) -#define MC_ME_GS_S_PERPLL (1 << 7) -#define MC_ME_GS_S_ENETPLL (1 << 8) -#define MC_ME_GS_S_DDRPLL (1 << 9) -#define MC_ME_GS_S_VIDEOPLL (1 << 10) -#define MC_ME_GS_S_MVR (1 << 20) -#define MC_ME_GS_S_PDO (1 << 23) -#define MC_ME_GS_S_MTRANS (1 << 27) -#define MC_ME_GS_S_CRT_MODE_RESET (0x0 << 28) -#define MC_ME_GS_S_CRT_MODE_TEST (0x1 << 28) -#define MC_ME_GS_S_CRT_MODE_DRUN (0x3 << 28) -#define MC_ME_GS_S_CRT_MODE_RUN0 (0x4 << 28) -#define MC_ME_GS_S_CRT_MODE_RUN1 (0x5 << 28) -#define MC_ME_GS_S_CRT_MODE_RUN2 (0x6 << 28) -#define MC_ME_GS_S_CRT_MODE_RUN3 (0x7 << 28) - -/* MC_ME_MCTL */ -#define MC_ME_MCTL (MC_ME_BASE_ADDR + 0x00000004) - -#define MC_ME_MCTL_KEY (0x00005AF0) -#define MC_ME_MCTL_INVERTEDKEY (0x0000A50F) -#define MC_ME_MCTL_RESET (0x0 << 28) -#define MC_ME_MCTL_TEST (0x1 << 28) -#define MC_ME_MCTL_DRUN (0x3 << 28) -#define MC_ME_MCTL_RUN0 (0x4 << 28) -#define MC_ME_MCTL_RUN1 (0x5 << 28) -#define MC_ME_MCTL_RUN2 (0x6 << 28) -#define MC_ME_MCTL_RUN3 (0x7 << 28) - -/* MC_ME_ME */ -#define MC_ME_ME (MC_ME_BASE_ADDR + 0x00000008) - -#define MC_ME_ME_RESET_FUNC (1 << 0) -#define MC_ME_ME_TEST (1 << 1) -#define MC_ME_ME_DRUN (1 << 3) -#define MC_ME_ME_RUN0 (1 << 4) -#define MC_ME_ME_RUN1 (1 << 5) -#define MC_ME_ME_RUN2 (1 << 6) -#define MC_ME_ME_RUN3 (1 << 7) - -/* MC_ME_RUN_PCn */ -#define MC_ME_RUN_PCn(n) (MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n)) - -#define MC_ME_RUN_PCn_RESET (1 << 0) -#define MC_ME_RUN_PCn_TEST (1 << 1) -#define MC_ME_RUN_PCn_DRUN (1 << 3) -#define MC_ME_RUN_PCn_RUN0 (1 << 4) -#define MC_ME_RUN_PCn_RUN1 (1 << 5) -#define MC_ME_RUN_PCn_RUN2 (1 << 6) -#define MC_ME_RUN_PCn_RUN3 (1 << 7) - -/* - * MC_ME_RESET_MC/MC_ME_TEST_MC - * MC_ME_DRUN_MC - * MC_ME_RUNn_MC - */ -#define MC_ME_RESET_MC (MC_ME_BASE_ADDR + 0x00000020) -#define MC_ME_TEST_MC (MC_ME_BASE_ADDR + 0x00000024) -#define MC_ME_DRUN_MC (MC_ME_BASE_ADDR + 0x0000002C) -#define MC_ME_RUNn_MC(n) (MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n)) - -#define MC_ME_RUNMODE_MC_SYSCLK(val) (MC_ME_RUNMODE_MC_SYSCLK_MASK & (val)) -#define MC_ME_RUNMODE_MC_SYSCLK_MASK (0x0000000F) -#define MC_ME_RUNMODE_MC_FIRCON (1 << 4) -#define MC_ME_RUNMODE_MC_XOSCON (1 << 5) -#define MC_ME_RUNMODE_MC_PLL(pll) (1 << (6 + (pll))) -#define MC_ME_RUNMODE_MC_MVRON (1 << 20) -#define MC_ME_RUNMODE_MC_PDO (1 << 23) -#define MC_ME_RUNMODE_MC_PWRLVL0 (1 << 28) -#define MC_ME_RUNMODE_MC_PWRLVL1 (1 << 29) -#define MC_ME_RUNMODE_MC_PWRLVL2 (1 << 30) - -/* MC_ME_DRUN_SEC_CC_I */ -#define MC_ME_DRUN_SEC_CC_I (MC_ME_BASE_ADDR + 0x260) -/* MC_ME_RUNn_SEC_CC_I */ -#define MC_ME_RUNn_SEC_CC_I(n) (MC_ME_BASE_ADDR + 0x270 + (n) * 0x10) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset) ((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET (4) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET (8) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET (12) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK (0x3) - -/* - * ME_PCTLn - * Please note that these registers are 8 bits width, so - * the operations over them should be done using 8 bits operations. - */ -#define MC_ME_PCTLn_RUNPCm(n) ( (n) & MC_ME_PCTLn_RUNPCm_MASK ) -#define MC_ME_PCTLn_RUNPCm_MASK (0x7) - -/* DEC200 Peripheral Control Register */ -#define MC_ME_PCTL39 (MC_ME_BASE_ADDR + 0x000000E4) -/* 2D-ACE Peripheral Control Register */ -#define MC_ME_PCTL40 (MC_ME_BASE_ADDR + 0x000000EB) -/* ENET Peripheral Control Register */ -#define MC_ME_PCTL50 (MC_ME_BASE_ADDR + 0x000000F1) -/* DMACHMUX0 Peripheral Control Register */ -#define MC_ME_PCTL49 (MC_ME_BASE_ADDR + 0x000000F2) -/* CSI0 Peripheral Control Register */ -#define MC_ME_PCTL48 (MC_ME_BASE_ADDR + 0x000000F3) -/* MMDC0 Peripheral Control Register */ -#define MC_ME_PCTL54 (MC_ME_BASE_ADDR + 0x000000F5) -/* FRAY Peripheral Control Register */ -#define MC_ME_PCTL52 (MC_ME_BASE_ADDR + 0x000000F7) -/* PIT0 Peripheral Control Register */ -#define MC_ME_PCTL58 (MC_ME_BASE_ADDR + 0x000000F9) -/* FlexTIMER0 Peripheral Control Register */ -#define MC_ME_PCTL79 (MC_ME_BASE_ADDR + 0x0000010C) -/* SARADC0 Peripheral Control Register */ -#define MC_ME_PCTL77 (MC_ME_BASE_ADDR + 0x0000010E) -/* LINFLEX0 Peripheral Control Register */ -#define MC_ME_PCTL83 (MC_ME_BASE_ADDR + 0x00000110) -/* IIC0 Peripheral Control Register */ -#define MC_ME_PCTL81 (MC_ME_BASE_ADDR + 0x00000112) -/* DSPI0 Peripheral Control Register */ -#define MC_ME_PCTL87 (MC_ME_BASE_ADDR + 0x00000114) -/* CANFD0 Peripheral Control Register */ -#define MC_ME_PCTL85 (MC_ME_BASE_ADDR + 0x00000116) -/* CRC0 Peripheral Control Register */ -#define MC_ME_PCTL91 (MC_ME_BASE_ADDR + 0x00000118) -/* DSPI2 Peripheral Control Register */ -#define MC_ME_PCTL89 (MC_ME_BASE_ADDR + 0x0000011A) -/* SDHC Peripheral Control Register */ -#define MC_ME_PCTL93 (MC_ME_BASE_ADDR + 0x0000011E) -/* VIU0 Peripheral Control Register */ -#define MC_ME_PCTL100 (MC_ME_BASE_ADDR + 0x00000127) -/* HPSMI Peripheral Control Register */ -#define MC_ME_PCTL104 (MC_ME_BASE_ADDR + 0x0000012B) -/* SIPI Peripheral Control Register */ -#define MC_ME_PCTL116 (MC_ME_BASE_ADDR + 0x00000137) -/* LFAST Peripheral Control Register */ -#define MC_ME_PCTL120 (MC_ME_BASE_ADDR + 0x0000013B) -/* MMDC1 Peripheral Control Register */ -#define MC_ME_PCTL162 (MC_ME_BASE_ADDR + 0x00000161) -/* DMACHMUX1 Peripheral Control Register */ -#define MC_ME_PCTL161 (MC_ME_BASE_ADDR + 0x00000162) -/* CSI1 Peripheral Control Register */ -#define MC_ME_PCTL160 (MC_ME_BASE_ADDR + 0x00000163) -/* QUADSPI0 Peripheral Control Register */ -#define MC_ME_PCTL166 (MC_ME_BASE_ADDR + 0x00000165) -/* PIT1 Peripheral Control Register */ -#define MC_ME_PCTL170 (MC_ME_BASE_ADDR + 0x00000169) -/* FlexTIMER1 Peripheral Control Register */ -#define MC_ME_PCTL182 (MC_ME_BASE_ADDR + 0x00000175) -/* IIC2 Peripheral Control Register */ -#define MC_ME_PCTL186 (MC_ME_BASE_ADDR + 0x00000179) -/* IIC1 Peripheral Control Register */ -#define MC_ME_PCTL184 (MC_ME_BASE_ADDR + 0x0000017B) -/* CANFD1 Peripheral Control Register */ -#define MC_ME_PCTL190 (MC_ME_BASE_ADDR + 0x0000017D) -/* LINFLEX1 Peripheral Control Register */ -#define MC_ME_PCTL188 (MC_ME_BASE_ADDR + 0x0000017F) -/* DSPI3 Peripheral Control Register */ -#define MC_ME_PCTL194 (MC_ME_BASE_ADDR + 0x00000181) -/* DSPI1 Peripheral Control Register */ -#define MC_ME_PCTL192 (MC_ME_BASE_ADDR + 0x00000183) -/* TSENS Peripheral Control Register */ -#define MC_ME_PCTL206 (MC_ME_BASE_ADDR + 0x0000018D) -/* CRC1 Peripheral Control Register */ -#define MC_ME_PCTL204 (MC_ME_BASE_ADDR + 0x0000018F) -/* VIU1 Peripheral Control Register */ -#define MC_ME_PCTL208 (MC_ME_BASE_ADDR + 0x00000193) -/* JPEG Peripheral Control Register */ -#define MC_ME_PCTL212 (MC_ME_BASE_ADDR + 0x00000197) -/* H264_DEC Peripheral Control Register */ -#define MC_ME_PCTL216 (MC_ME_BASE_ADDR + 0x0000019B) -/* H264_ENC Peripheral Control Register */ -#define MC_ME_PCTL220 (MC_ME_BASE_ADDR + 0x0000019F) -/* MBIST Peripheral Control Register */ -#define MC_ME_PCTL236 (MC_ME_BASE_ADDR + 0x000001A9) - -/* Core status register */ -#define MC_ME_CS (MC_ME_BASE_ADDR + 0x000001C0) - -#endif - -#endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h deleted file mode 100644 index 34501b2189b3..000000000000 --- a/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ -#define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ - -#define MC_RGM_DES (MC_RGM_BASE_ADDR) -#define MC_RGM_FES (MC_RGM_BASE_ADDR + 0x300) -#define MC_RGM_FERD (MC_RGM_BASE_ADDR + 0x310) -#define MC_RGM_FBRE (MC_RGM_BASE_ADDR + 0x330) -#define MC_RGM_FESS (MC_RGM_BASE_ADDR + 0x340) -#define MC_RGM_DDR_HE (MC_RGM_BASE_ADDR + 0x350) -#define MC_RGM_DDR_HS (MC_RGM_BASE_ADDR + 0x354) -#define MC_RGM_FRHE (MC_RGM_BASE_ADDR + 0x358) -#define MC_RGM_FREC (MC_RGM_BASE_ADDR + 0x600) -#define MC_RGM_FRET (MC_RGM_BASE_ADDR + 0x607) -#define MC_RGM_DRET (MC_RGM_BASE_ADDR + 0x60B) - -/* function reset sources mask */ -#define F_SWT4 0x8000 -#define F_JTAG 0x400 -#define F_FCCU_SOFT 0x40 -#define F_FCCU_HARD 0x20 -#define F_SOFT_FUNC 0x8 -#define F_ST_DONE 0x4 -#define F_EXT_RST 0x1 - -#endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-s32v234/mmdc.h b/arch/arm/include/asm/arch-s32v234/mmdc.h deleted file mode 100644 index 8d74ae026615..000000000000 --- a/arch/arm/include/asm/arch-s32v234/mmdc.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__ -#define __ARCH_ARM_MACH_S32V234_MMDC_H__ - -#define MMDC0 0 -#define MMDC1 1 - -#define MMDC_MDCTL 0x0 -#define MMDC_MDPDC 0x4 -#define MMDC_MDOTC 0x8 -#define MMDC_MDCFG0 0xC -#define MMDC_MDCFG1 0x10 -#define MMDC_MDCFG2 0x14 -#define MMDC_MDMISC 0x18 -#define MMDC_MDSCR 0x1C -#define MMDC_MDREF 0x20 -#define MMDC_MDRWD 0x2C -#define MMDC_MDOR 0x30 -#define MMDC_MDMRR 0x34 -#define MMDC_MDCFG3LP 0x38 -#define MMDC_MDMR4 0x3C -#define MMDC_MDASP 0x40 -#define MMDC_MAARCR 0x400 -#define MMDC_MAPSR 0x404 -#define MMDC_MAEXIDR0 0x408 -#define MMDC_MAEXIDR1 0x40C -#define MMDC_MADPCR0 0x410 -#define MMDC_MADPCR1 0x414 -#define MMDC_MADPSR0 0x418 -#define MMDC_MADPSR1 0x41C -#define MMDC_MADPSR2 0x420 -#define MMDC_MADPSR3 0x424 -#define MMDC_MADPSR4 0x428 -#define MMDC_MADPSR5 0x42C -#define MMDC_MASBS0 0x430 -#define MMDC_MASBS1 0x434 -#define MMDC_MAGENP 0x440 -#define MMDC_MPZQHWCTRL 0x800 -#define MMDC_MPWLGCR 0x808 -#define MMDC_MPWLDECTRL0 0x80C -#define MMDC_MPWLDECTRL1 0x810 -#define MMDC_MPWLDLST 0x814 -#define MMDC_MPODTCTRL 0x818 -#define MMDC_MPRDDQBY0DL 0x81C -#define MMDC_MPRDDQBY1DL 0x820 -#define MMDC_MPRDDQBY2DL 0x824 -#define MMDC_MPRDDQBY3DL 0x828 -#define MMDC_MPDGCTRL0 0x83C -#define MMDC_MPDGCTRL1 0x840 -#define MMDC_MPDGDLST0 0x844 -#define MMDC_MPRDDLCTL 0x848 -#define MMDC_MPRDDLST 0x84C -#define MMDC_MPWRDLCTL 0x850 -#define MMDC_MPWRDLST 0x854 -#define MMDC_MPZQLP2CTL 0x85C -#define MMDC_MPRDDLHWCTL 0x860 -#define MMDC_MPWRDLHWCTL 0x864 -#define MMDC_MPRDDLHWST0 0x868 -#define MMDC_MPRDDLHWST1 0x86C -#define MMDC_MPWRDLHWST1 0x870 -#define MMDC_MPWRDLHWST2 0x874 -#define MMDC_MPWLHWERR 0x878 -#define MMDC_MPDGHWST0 0x87C -#define MMDC_MPDGHWST1 0x880 -#define MMDC_MPDGHWST2 0x884 -#define MMDC_MPDGHWST3 0x888 -#define MMDC_MPPDCMPR1 0x88C -#define MMDC_MPPDCMPR2 0x890 -#define MMDC_MPSWDAR0 0x894 -#define MMDC_MPSWDRDR0 0x898 -#define MMDC_MPSWDRDR1 0x89C -#define MMDC_MPSWDRDR2 0x8A0 -#define MMDC_MPSWDRDR3 0x8A4 -#define MMDC_MPSWDRDR4 0x8A8 -#define MMDC_MPSWDRDR5 0x8AC -#define MMDC_MPSWDRDR6 0x8B0 -#define MMDC_MPSWDRDR7 0x8B4 -#define MMDC_MPMUR0 0x8B8 -#define MMDC_MPDCCR 0x8C0 - -#define MMDC_MPMUR0_FRC_MSR (1 << 11) -#define MMDC_MPZQHWCTRL_ZQ_HW_FOR (1 << 16) - -#endif diff --git a/arch/arm/include/asm/arch-s32v234/siul.h b/arch/arm/include/asm/arch-s32v234/siul.h deleted file mode 100644 index 7572581054a8..000000000000 --- a/arch/arm/include/asm/arch-s32v234/siul.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_SIUL_H__ -#define __ARCH_ARM_MACH_S32V234_SIUL_H__ - -#include "ddr.h" - -#define SIUL2_MIDR1 (SIUL2_BASE_ADDR + 0x00000004) -#define SIUL2_MIDR2 (SIUL2_BASE_ADDR + 0x00000008) -#define SIUL2_DISR0 (SIUL2_BASE_ADDR + 0x00000010) -#define SIUL2_DIRER0 (SIUL2_BASE_ADDR + 0x00000018) -#define SIUL2_DIRSR0 (SIUL2_BASE_ADDR + 0x00000020) -#define SIUL2_IREER0 (SIUL2_BASE_ADDR + 0x00000028) -#define SIUL2_IFEER0 (SIUL2_BASE_ADDR + 0x00000030) -#define SIUL2_IFER0 (SIUL2_BASE_ADDR + 0x00000038) - -#define SIUL2_IFMCR_BASE (SIUL2_BASE_ADDR + 0x00000040) -#define SIUL2_IFMCRn(i) (SIUL2_IFMCR_BASE + 4 * (i)) - -#define SIUL2_IFCPR (SIUL2_BASE_ADDR + 0x000000C0) - -/* SIUL2_MSCR specifications as stated in Reference Manual: - * 0 - 359 Output Multiplexed Signal Configuration Registers - * 512- 1023 Input Multiplexed Signal Configuration Registers */ -#define SIUL2_MSCR_BASE (SIUL2_BASE_ADDR + 0x00000240) -#define SIUL2_MSCRn(i) (SIUL2_MSCR_BASE + 4 * (i)) - -#define SIUL2_IMCR_BASE (SIUL2_BASE_ADDR + 0x00000A40) -#define SIUL2_IMCRn(i) (SIUL2_IMCR_BASE + 4 * (i)) - -#define SIUL2_GPDO_BASE (SIUL2_BASE_ADDR + 0x00001300) -#define SIUL2_GPDOn(i) (SIUL2_GPDO_BASE + 4 * (i)) - -#define SIUL2_GPDI_BASE (SIUL2_BASE_ADDR + 0x00001500) -#define SIUL2_GPDIn(i) (SIUL2_GPDI_BASE + 4 * (i)) - -#define SIUL2_PGPDO_BASE (SIUL2_BASE_ADDR + 0x00001700) -#define SIUL2_PGPDOn(i) (SIUL2_PGPDO_BASE + 2 * (i)) - -#define SIUL2_PGPDI_BASE (SIUL2_BASE_ADDR + 0x00001740) -#define SIUL2_PGPDIn(i) (SIUL2_PGPDI_BASE + 2 * (i)) - -#define SIUL2_MPGPDO_BASE (SIUL2_BASE_ADDR + 0x00001780) -#define SIUL2_MPGPDOn(i) (SIUL2_MPGPDO_BASE + 4 * (i)) - -/* SIUL2_MSCR masks */ -#define SIUL2_MSCR_DDR_DO_TRIM(v) ((v) & 0xC0000000) -#define SIUL2_MSCR_DDR_DO_TRIM_MIN (0 << 30) -#define SIUL2_MSCR_DDR_DO_TRIM_50PS (1 << 30) -#define SIUL2_MSCR_DDR_DO_TRIM_100PS (2 << 30) -#define SIUL2_MSCR_DDR_DO_TRIM_150PS (3 << 30) - -#define SIUL2_MSCR_DDR_INPUT(v) ((v) & 0x20000000) -#define SIUL2_MSCR_DDR_INPUT_CMOS (0 << 29) -#define SIUL2_MSCR_DDR_INPUT_DIFF_DDR (1 << 29) - -#define SIUL2_MSCR_DDR_SEL(v) ((v) & 0x18000000) -#define SIUL2_MSCR_DDR_SEL_DDR3 (0 << 27) -#define SIUL2_MSCR_DDR_SEL_LPDDR2 (2 << 27) - -#define SIUL2_MSCR_DDR_ODT(v) ((v) & 0x07000000) -#define SIUL2_MSCR_DDR_ODT_120ohm (1 << 24) -#define SIUL2_MSCR_DDR_ODT_60ohm (2 << 24) -#define SIUL2_MSCR_DDR_ODT_40ohm (3 << 24) -#define SIUL2_MSCR_DDR_ODT_30ohm (4 << 24) -#define SIUL2_MSCR_DDR_ODT_24ohm (5 << 24) -#define SIUL2_MSCR_DDR_ODT_20ohm (6 << 24) -#define SIUL2_MSCR_DDR_ODT_17ohm (7 << 24) - -#define SIUL2_MSCR_DCYCLE_TRIM(v) ((v) & 0x00C00000) -#define SIUL2_MSCR_DCYCLE_TRIM_NONE (0 << 22) -#define SIUL2_MSCR_DCYCLE_TRIM_LEFT (1 << 22) -#define SIUL2_MSCR_DCYCLE_TRIM_RIGHT (2 << 22) - -#define SIUL2_MSCR_OBE(v) ((v) & 0x00200000) -#define SIUL2_MSCR_OBE_EN (1 << 21) - -#define SIUL2_MSCR_ODE(v) ((v) & 0x00100000) -#define SIUL2_MSCR_ODE_EN (1 << 20) - -#define SIUL2_MSCR_IBE(v) ((v) & 0x00010000) -#define SIUL2_MSCR_IBE_EN (1 << 19) - -#define SIUL2_MSCR_HYS(v) ((v) & 0x00400000) -#define SIUL2_MSCR_HYS_EN (1 << 18) - -#define SIUL2_MSCR_INV(v) ((v) & 0x00020000) -#define SIUL2_MSCR_INV_EN (1 << 17) - -#define SIUL2_MSCR_PKE(v) ((v) & 0x00010000) -#define SIUL2_MSCR_PKE_EN (1 << 16) - -#define SIUL2_MSCR_SRE(v) ((v) & 0x0000C000) -#define SIUL2_MSCR_SRE_SPEED_LOW_50 (0 << 14) -#define SIUL2_MSCR_SRE_SPEED_LOW_100 (1 << 14) -#define SIUL2_MSCR_SRE_SPEED_HIGH_100 (2 << 14) -#define SIUL2_MSCR_SRE_SPEED_HIGH_200 (3 << 14) - -#define SIUL2_MSCR_PUE(v) ((v) & 0x00002000) -#define SIUL2_MSCR_PUE_EN (1 << 13) - -#define SIUL2_MSCR_PUS(v) ((v) & 0x00001800) -#define SIUL2_MSCR_PUS_100K_DOWN (0 << 11) -#define SIUL2_MSCR_PUS_50K_DOWN (1 << 11) -#define SIUL2_MSCR_PUS_100K_UP (2 << 11) -#define SIUL2_MSCR_PUS_33K_UP (3 << 11) - -#define SIUL2_MSCR_DSE(v) ((v) & 0x00000700) -#define SIUL2_MSCR_DSE_240ohm (1 << 8) -#define SIUL2_MSCR_DSE_120ohm (2 << 8) -#define SIUL2_MSCR_DSE_80ohm (3 << 8) -#define SIUL2_MSCR_DSE_60ohm (4 << 8) -#define SIUL2_MSCR_DSE_48ohm (5 << 8) -#define SIUL2_MSCR_DSE_40ohm (6 << 8) -#define SIUL2_MSCR_DSE_34ohm (7 << 8) - -#define SIUL2_MSCR_CRPOINT_TRIM(v) ((v) & 0x000000C0) -#define SIUL2_MSCR_CRPOINT_TRIM_1 (1 << 6) - -#define SIUL2_MSCR_SMC(v) ((v) & 0x00000020) -#define SIUL2_MSCR_MUX_MODE(v) ((v) & 0x0000000f) -#define SIUL2_MSCR_MUX_MODE_ALT1 (0x1) -#define SIUL2_MSCR_MUX_MODE_ALT2 (0x2) -#define SIUL2_MSCR_MUX_MODE_ALT3 (0x3) - -/* UART settings */ -#define SIUL2_UART0_TXD_PAD 12 -#define SIUL2_UART_TXD (SIUL2_MSCR_OBE_EN | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_60ohm | \ - SIUL2_MSCR_SRE_SPEED_LOW_100 | SIUL2_MSCR_MUX_MODE_ALT1) - -#define SIUL2_UART0_MSCR_RXD_PAD 11 -#define SIUL2_UART0_IMCR_RXD_PAD 200 - -#define SIUL2_UART_MSCR_RXD (SIUL2_MSCR_PUE_EN | SIUL2_MSCR_IBE_EN | SIUL2_MSCR_DCYCLE_TRIM_RIGHT) -#define SIUL2_UART_IMCR_RXD (SIUL2_MSCR_MUX_MODE_ALT2) - -/* uSDHC settings */ -#define SIUL2_USDHC_PAD_CTRL_BASE (SIUL2_MSCR_SRE_SPEED_HIGH_200 | SIUL2_MSCR_OBE_EN | \ - SIUL2_MSCR_DSE_34ohm | SIUL2_MSCR_PKE_EN | SIUL2_MSCR_IBE_EN | \ - SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_PUE_EN ) -#define SIUL2_USDHC_PAD_CTRL_CMD (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT1) -#define SIUL2_USDHC_PAD_CTRL_CLK (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2) -#define SIUL2_USDHC_PAD_CTRL_DAT0_3 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2) -#define SIUL2_USDHC_PAD_CTRL_DAT4_7 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT3) - -#endif /*__ARCH_ARM_MACH_S32V234_SIUL_H__ */ diff --git a/board/freescale/s32v234evb/Kconfig b/board/freescale/s32v234evb/Kconfig deleted file mode 100644 index e71dfc4ab228..000000000000 --- a/board/freescale/s32v234evb/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -if TARGET_S32V234EVB - -config SYS_CPU - string - default "armv8" - -config SYS_BOARD - string - default "s32v234evb" - -config SYS_VENDOR - string - default "freescale" - -config SYS_SOC - string - default "s32v234" - -config SYS_CONFIG_NAME - string - default "s32v234evb" - -endif diff --git a/board/freescale/s32v234evb/MAINTAINERS b/board/freescale/s32v234evb/MAINTAINERS deleted file mode 100644 index 62b2e1b264f7..000000000000 --- a/board/freescale/s32v234evb/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -S32V234 Evaluation BOARD -M: Eddy Petrișor eddy.petrisor@gmail.com -S: Maintained -F: arch/arm/cpu/armv8/s32v234/ -F: arch/arm/include/asm/arch-s32v234/ -F: board/freescale/s32v234evb/ -F: include/configs/s32v234evb.h -F: configs/s32v234evb_defconfig diff --git a/board/freescale/s32v234evb/Makefile b/board/freescale/s32v234evb/Makefile deleted file mode 100644 index f6028e127763..000000000000 --- a/board/freescale/s32v234evb/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2013-2015, Freescale Semiconductor, Inc. - -obj-y := clock.o -obj-y += lpddr2.o -obj-y += s32v234evb.o - -######################################################################### diff --git a/board/freescale/s32v234evb/clock.c b/board/freescale/s32v234evb/clock.c deleted file mode 100644 index 21c619fa1adc..000000000000 --- a/board/freescale/s32v234evb/clock.c +++ /dev/null @@ -1,343 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mc_cgm_regs.h> -#include <asm/arch/mc_me_regs.h> -#include <asm/arch/clock.h> - -/* - * Select the clock reference for required pll. - * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL. - * refclk_freq - input referece clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ) - */ -static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq) -{ - u32 clk_src; - u32 pll_idx; - volatile struct src *src = (struct src *)SRC_SOC_BASE_ADDR; - - /* select the pll clock source */ - switch (refclk_freq) { - case FIRC_CLK_FREQ: - clk_src = SRC_GPR1_FIRC_CLK_SOURCE; - break; - case XOSC_CLK_FREQ: - clk_src = SRC_GPR1_XOSC_CLK_SOURCE; - break; - default: - /* The clock frequency for the source clock is unknown */ - return -1; - } - /* - * The hardware definition is not uniform, it has to calculate again - * the recurrence formula. - */ - switch (pll) { - case PERIPH_PLL: - pll_idx = 3; - break; - case ENET_PLL: - pll_idx = 1; - break; - case DDR_PLL: - pll_idx = 2; - break; - default: - pll_idx = pll; - } - - writel(readl(&src->gpr1) | SRC_GPR1_PLL_SOURCE(pll_idx, clk_src), - &src->gpr1); - - return 0; -} - -static void entry_to_target_mode(u32 mode) -{ - writel(mode | MC_ME_MCTL_KEY, MC_ME_MCTL); - writel(mode | MC_ME_MCTL_INVERTEDKEY, MC_ME_MCTL); - while ((readl(MC_ME_GS) & MC_ME_GS_S_MTRANS) != 0x00000000) ; -} - -/* - * Program the pll according to the input parameters. - * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL. - * refclk_freq - input reference clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ) - * freq - expected output frequency for PHY0 - * freq1 - expected output frequency for PHY1 - * dfs_nr - number of DFS modules for current PLL - * dfs - array with the activation dfs field, mfn and mfi - * plldv_prediv - divider of clkfreq_ref - * plldv_mfd - loop multiplication factor divider - * pllfd_mfn - numerator loop multiplication factor divider - * Please consult the PLLDIG chapter of platform manual - * before to use this function. - *) - */ -static int program_pll(enum pll_type pll, u32 refclk_freq, u32 freq0, u32 freq1, - u32 dfs_nr, u32 dfs[][DFS_PARAMS_Nr], u32 plldv_prediv, - u32 plldv_mfd, u32 pllfd_mfn) -{ - u32 i, rfdphi1, rfdphi, dfs_on = 0, fvco; - - /* - * This formula is from platform reference manual (Rev. 1, 6/2015), PLLDIG chapter. - */ - fvco = - (refclk_freq / plldv_prediv) * (plldv_mfd + - pllfd_mfn / (float)20480); - - /* - * VCO should have value in [ PLL_MIN_FREQ, PLL_MAX_FREQ ]. Please consult - * the platform DataSheet in order to determine the allowed values. - */ - - if (fvco < PLL_MIN_FREQ || fvco > PLL_MAX_FREQ) { - return -1; - } - - if (select_pll_source_clk(pll, refclk_freq) < 0) { - return -1; - } - - rfdphi = fvco / freq0; - - rfdphi1 = (freq1 == 0) ? 0 : fvco / freq1; - - writel(PLLDIG_PLLDV_RFDPHI1_SET(rfdphi1) | - PLLDIG_PLLDV_RFDPHI_SET(rfdphi) | - PLLDIG_PLLDV_PREDIV_SET(plldv_prediv) | - PLLDIG_PLLDV_MFD(plldv_mfd), PLLDIG_PLLDV(pll)); - - writel(readl(PLLDIG_PLLFD(pll)) | PLLDIG_PLLFD_MFN_SET(pllfd_mfn) | - PLLDIG_PLLFD_SMDEN, PLLDIG_PLLFD(pll)); - - /* switch on the pll in current mode */ - writel(readl(MC_ME_RUNn_MC(0)) | MC_ME_RUNMODE_MC_PLL(pll), - MC_ME_RUNn_MC(0)); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - - /* Only ARM_PLL, ENET_PLL and DDR_PLL */ - if ((pll == ARM_PLL) || (pll == ENET_PLL) || (pll == DDR_PLL)) { - /* DFS clk enable programming */ - writel(DFS_CTRL_DLL_RESET, DFS_CTRL(pll)); - - writel(DFS_DLLPRG1_CPICTRL_SET(0x5) | - DFS_DLLPRG1_VSETTLCTRL_SET(0x1) | - DFS_DLLPRG1_CALBYPEN_SET(0x0) | - DFS_DLLPRG1_DACIN_SET(0x1) | DFS_DLLPRG1_LCKWT_SET(0x0) | - DFS_DLLPRG1_V2IGC_SET(0x5), DFS_DLLPRG1(pll)); - - for (i = 0; i < dfs_nr; i++) { - if (dfs[i][0]) { - writel(DFS_DVPORTn_MFI_SET(dfs[i][2]) | - DFS_DVPORTn_MFN_SET(dfs[i][1]), - DFS_DVPORTn(pll, i)); - dfs_on |= (dfs[i][0] << i); - } - } - - writel(readl(DFS_CTRL(pll)) & ~DFS_CTRL_DLL_RESET, - DFS_CTRL(pll)); - writel(readl(DFS_PORTRESET(pll)) & - ~DFS_PORTRESET_PORTRESET_SET(dfs_on), - DFS_PORTRESET(pll)); - while ((readl(DFS_PORTSR(pll)) & dfs_on) != dfs_on) ; - } - - entry_to_target_mode(MC_ME_MCTL_RUN0); - - return 0; - -} - -static void aux_source_clk_config(uintptr_t cgm_addr, u8 ac, u32 source) -{ - /* select the clock source */ - writel(MC_CGM_ACn_SEL_SET(source), CGM_ACn_SC(cgm_addr, ac)); -} - -static void aux_div_clk_config(uintptr_t cgm_addr, u8 ac, u8 dc, u32 divider) -{ - /* set the divider */ - writel(MC_CGM_ACn_DCm_DE | MC_CGM_ACn_DCm_PREDIV(divider), - CGM_ACn_DCm(cgm_addr, ac, dc)); -} - -static void setup_sys_clocks(void) -{ - - /* set ARM PLL DFS 1 as SYSCLK */ - writel((readl(MC_ME_RUNn_MC(0)) & ~MC_ME_RUNMODE_MC_SYSCLK_MASK) | - MC_ME_RUNMODE_MC_SYSCLK(0x2), MC_ME_RUNn_MC(0)); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - - /* select sysclks ARMPLL, ARMPLLDFS2, ARMPLLDFS3 */ - writel(MC_ME_RUNMODE_SEC_CC_I_SYSCLK - (0x2, - MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET) | - MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2, - MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET) - | MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2, - MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET), - MC_ME_RUNn_SEC_CC_I(0)); - - /* setup the sys clock divider for CORE_CLK (1000MHz) */ - writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0), - CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)); - - /* setup the sys clock divider for CORE2_CLK (500MHz) */ - writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1), - CGM_SC_DCn(MC_CGM1_BASE_ADDR, 1)); - /* setup the sys clock divider for SYS3_CLK (266 MHz) */ - writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0), - CGM_SC_DCn(MC_CGM0_BASE_ADDR, 0)); - - /* setup the sys clock divider for SYS6_CLK (133 Mhz) */ - writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1), - CGM_SC_DCn(MC_CGM0_BASE_ADDR, 1)); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - -} - -static void setup_aux_clocks(void) -{ - /* - * setup the aux clock divider for PERI_CLK - * (source: PERIPH_PLL_PHI_0/5, PERI_CLK - 80 MHz) - */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 5, MC_CGM_ACn_SEL_PERPLLDIVX); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 5, 0, 4); - - /* setup the aux clock divider for LIN_CLK (40MHz) */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 3, MC_CGM_ACn_SEL_PERPLLDIVX); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 3, 0, 1); - - /* setup the aux clock divider for ENET_TIME_CLK (50MHz) */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 7, MC_CGM_ACn_SEL_ENETPLL); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 7, 1, 9); - - /* setup the aux clock divider for ENET_CLK (50MHz) */ - aux_source_clk_config(MC_CGM2_BASE_ADDR, 2, MC_CGM_ACn_SEL_ENETPLL); - aux_div_clk_config(MC_CGM2_BASE_ADDR, 2, 0, 9); - - /* setup the aux clock divider for SDHC_CLK (50 MHz). */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 15, MC_CGM_ACn_SEL_ENETPLL); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 15, 0, 9); - - /* setup the aux clock divider for DDR_CLK (533MHz) and APEX_SYS_CLK (266MHz) */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 8, MC_CGM_ACn_SEL_DDRPLL); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 0, 0); - /* setup the aux clock divider for DDR4_CLK (133,25MHz) */ - aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 1, 3); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - -} - -static void enable_modules_clock(void) -{ - /* PIT0 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL58); - /* PIT1 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL170); - /* LINFLEX0 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL83); - /* LINFLEX1 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL188); - /* ENET */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL50); - /* SDHC */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL93); - /* IIC0 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL81); - /* IIC1 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL184); - /* IIC2 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL186); - /* MMDC0 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL54); - /* MMDC1 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL162); - - entry_to_target_mode(MC_ME_MCTL_RUN0); -} - -void clock_init(void) -{ - unsigned int arm_dfs[ARM_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = { - {ARM_PLL_PHI1_DFS1_EN, ARM_PLL_PHI1_DFS1_MFN, - ARM_PLL_PHI1_DFS1_MFI}, - {ARM_PLL_PHI1_DFS2_EN, ARM_PLL_PHI1_DFS2_MFN, - ARM_PLL_PHI1_DFS2_MFI}, - {ARM_PLL_PHI1_DFS3_EN, ARM_PLL_PHI1_DFS3_MFN, - ARM_PLL_PHI1_DFS3_MFI} - }; - - unsigned int enet_dfs[ENET_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = { - {ENET_PLL_PHI1_DFS1_EN, ENET_PLL_PHI1_DFS1_MFN, - ENET_PLL_PHI1_DFS1_MFI}, - {ENET_PLL_PHI1_DFS2_EN, ENET_PLL_PHI1_DFS2_MFN, - ENET_PLL_PHI1_DFS2_MFI}, - {ENET_PLL_PHI1_DFS3_EN, ENET_PLL_PHI1_DFS3_MFN, - ENET_PLL_PHI1_DFS3_MFI}, - {ENET_PLL_PHI1_DFS4_EN, ENET_PLL_PHI1_DFS4_MFN, - ENET_PLL_PHI1_DFS4_MFI} - }; - - unsigned int ddr_dfs[DDR_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = { - {DDR_PLL_PHI1_DFS1_EN, DDR_PLL_PHI1_DFS1_MFN, - DDR_PLL_PHI1_DFS1_MFI}, - {DDR_PLL_PHI1_DFS2_EN, DDR_PLL_PHI1_DFS2_MFN, - DDR_PLL_PHI1_DFS2_MFI}, - {DDR_PLL_PHI1_DFS3_EN, DDR_PLL_PHI1_DFS3_MFN, - DDR_PLL_PHI1_DFS3_MFI} - }; - - writel(MC_ME_RUN_PCn_DRUN | MC_ME_RUN_PCn_RUN0 | MC_ME_RUN_PCn_RUN1 | - MC_ME_RUN_PCn_RUN2 | MC_ME_RUN_PCn_RUN3, MC_ME_RUN_PCn(0)); - - /* turn on FXOSC */ - writel(MC_ME_RUNMODE_MC_MVRON | MC_ME_RUNMODE_MC_XOSCON | - MC_ME_RUNMODE_MC_FIRCON | MC_ME_RUNMODE_MC_SYSCLK(0x1), - MC_ME_RUNn_MC(0)); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - - program_pll(ARM_PLL, XOSC_CLK_FREQ, ARM_PLL_PHI0_FREQ, - ARM_PLL_PHI1_FREQ, ARM_PLL_PHI1_DFS_Nr, arm_dfs, - ARM_PLL_PLLDV_PREDIV, ARM_PLL_PLLDV_MFD, ARM_PLL_PLLDV_MFN); - - setup_sys_clocks(); - - program_pll(PERIPH_PLL, XOSC_CLK_FREQ, PERIPH_PLL_PHI0_FREQ, - PERIPH_PLL_PHI1_FREQ, PERIPH_PLL_PHI1_DFS_Nr, NULL, - PERIPH_PLL_PLLDV_PREDIV, PERIPH_PLL_PLLDV_MFD, - PERIPH_PLL_PLLDV_MFN); - - program_pll(ENET_PLL, XOSC_CLK_FREQ, ENET_PLL_PHI0_FREQ, - ENET_PLL_PHI1_FREQ, ENET_PLL_PHI1_DFS_Nr, enet_dfs, - ENET_PLL_PLLDV_PREDIV, ENET_PLL_PLLDV_MFD, - ENET_PLL_PLLDV_MFN); - - program_pll(DDR_PLL, XOSC_CLK_FREQ, DDR_PLL_PHI0_FREQ, - DDR_PLL_PHI1_FREQ, DDR_PLL_PHI1_DFS_Nr, ddr_dfs, - DDR_PLL_PLLDV_PREDIV, DDR_PLL_PLLDV_MFD, DDR_PLL_PLLDV_MFN); - - program_pll(VIDEO_PLL, XOSC_CLK_FREQ, VIDEO_PLL_PHI0_FREQ, - VIDEO_PLL_PHI1_FREQ, VIDEO_PLL_PHI1_DFS_Nr, NULL, - VIDEO_PLL_PLLDV_PREDIV, VIDEO_PLL_PLLDV_MFD, - VIDEO_PLL_PLLDV_MFN); - - setup_aux_clocks(); - - enable_modules_clock(); - -} diff --git a/board/freescale/s32v234evb/lpddr2.c b/board/freescale/s32v234evb/lpddr2.c deleted file mode 100644 index b3775d3763ee..000000000000 --- a/board/freescale/s32v234evb/lpddr2.c +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/siul.h> -#include <asm/arch/lpddr2.h> -#include <asm/arch/mmdc.h> - -volatile int mscr_offset_ck0; - -void lpddr2_config_iomux(uint8_t module) -{ - int i; - - switch (module) { - case DDR0: - mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0); - writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0)); - - writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0)); - writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1)); - - writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0)); - writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1)); - - for (i = _DDR0_DM0; i <= _DDR0_DM3; i++) - writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++) - writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR0_A0; i <= _DDR0_A9; i++) - writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR0_D0; i <= _DDR0_D31; i++) - writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); - break; - case DDR1: - writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0)); - - writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0)); - writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1)); - - writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0)); - writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1)); - - for (i = _DDR1_DM0; i <= _DDR1_DM3; i++) - writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++) - writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR1_A0; i <= _DDR1_A9; i++) - writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR1_D0; i <= _DDR1_D31; i++) - writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); - break; - } -} - -void config_mmdc(uint8_t module) -{ - unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR; - - writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR); - - writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0); - writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1); - writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2); - writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP); - writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC); - writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC); - writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR); - writel(_MDCTL, mmdc_addr + MMDC_MDCTL); - - writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0); - - while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) { - } - - writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR); - - /* Perform ZQ calibration */ - writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL); - writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL); - while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) { - } - - /* Enable MMDC with CS0 */ - writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL); - - /* Complete the initialization sequence as defined by JEDEC */ - writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR); - writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR); - writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR); - writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR); - - /* Set the amount of DRAM */ - /* Set DQS settings based on board type */ - - switch (module) { - case MMDC0: - writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP); - writel(MMDC_MPRDDLCTL_MODULE0_VALUE, - mmdc_addr + MMDC_MPRDDLCTL); - writel(MMDC_MPWRDLCTL_MODULE0_VALUE, - mmdc_addr + MMDC_MPWRDLCTL); - writel(MMDC_MPDGCTRL0_MODULE0_VALUE, - mmdc_addr + MMDC_MPDGCTRL0); - writel(MMDC_MPDGCTRL1_MODULE0_VALUE, - mmdc_addr + MMDC_MPDGCTRL1); - break; - case MMDC1: - writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP); - writel(MMDC_MPRDDLCTL_MODULE1_VALUE, - mmdc_addr + MMDC_MPRDDLCTL); - writel(MMDC_MPWRDLCTL_MODULE1_VALUE, - mmdc_addr + MMDC_MPWRDLCTL); - writel(MMDC_MPDGCTRL0_MODULE1_VALUE, - mmdc_addr + MMDC_MPDGCTRL0); - writel(MMDC_MPDGCTRL1_MODULE1_VALUE, - mmdc_addr + MMDC_MPDGCTRL1); - break; - } - - writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD); - writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC); - writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF); - writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL); - writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR); - -} diff --git a/board/freescale/s32v234evb/s32v234evb.c b/board/freescale/s32v234evb/s32v234evb.c deleted file mode 100644 index f381cfc2ad08..000000000000 --- a/board/freescale/s32v234evb/s32v234evb.c +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013-2015, Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/siul.h> -#include <asm/arch/lpddr2.h> -#include <asm/arch/clock.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <netdev.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -void setup_iomux_ddr(void) -{ - lpddr2_config_iomux(DDR0); - lpddr2_config_iomux(DDR1); - -} - -void ddr_phy_init(void) -{ -} - -void ddr_ctrl_init(void) -{ - config_mmdc(0); - config_mmdc(1); -} - -int dram_init(void) -{ - setup_iomux_ddr(); - - ddr_ctrl_init(); - - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - - return 0; -} - -static void setup_iomux_uart(void) -{ - /* Muxing for linflex */ - /* Replace the magic values after bringup */ - - /* set TXD - MSCR[12] PA12 */ - writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD)); - - /* set RXD - MSCR[11] - PA11 */ - writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD)); - - /* set RXD - IMCR[200] - 200 */ - writel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD)); -} - -static void setup_iomux_enet(void) -{ -} - -static void setup_iomux_i2c(void) -{ -} - -#ifdef CONFIG_SYS_USE_NAND -void setup_iomux_nfc(void) -{ -} -#endif - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {USDHC_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - /* eSDHC1 is always present */ - return 1; -} - -int board_mmc_init(struct bd_info * bis) -{ - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK); - - /* Set iomux PADS for USDHC */ - - /* PK6 pad: uSDHC clk */ - writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150)); - writel(0x3, SIUL2_MSCRn(902)); - - /* PK7 pad: uSDHC CMD */ - writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151)); - writel(0x3, SIUL2_MSCRn(901)); - - /* PK8 pad: uSDHC DAT0 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152)); - writel(0x3, SIUL2_MSCRn(903)); - - /* PK9 pad: uSDHC DAT1 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153)); - writel(0x3, SIUL2_MSCRn(904)); - - /* PK10 pad: uSDHC DAT2 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154)); - writel(0x3, SIUL2_MSCRn(905)); - - /* PK11 pad: uSDHC DAT3 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155)); - writel(0x3, SIUL2_MSCRn(906)); - - /* PK15 pad: uSDHC DAT4 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159)); - writel(0x3, SIUL2_MSCRn(907)); - - /* PL0 pad: uSDHC DAT5 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160)); - writel(0x3, SIUL2_MSCRn(908)); - - /* PL1 pad: uSDHC DAT6 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161)); - writel(0x3, SIUL2_MSCRn(909)); - - /* PL2 pad: uSDHC DAT7 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162)); - writel(0x3, SIUL2_MSCRn(910)); - - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} -#endif - -static void mscm_init(void) -{ - struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR; - int i; - - for (i = 0; i < MSCM_IRSPRC_NUM; i++) - writew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]); -} - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_early_init_f(void) -{ - clock_init(); - mscm_init(); - - setup_iomux_uart(); - setup_iomux_enet(); - setup_iomux_i2c(); -#ifdef CONFIG_SYS_USE_NAND - setup_iomux_nfc(); -#endif - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int checkboard(void) -{ - puts("Board: s32v234evb\n"); - - return 0; -} diff --git a/board/freescale/s32v234evb/s32v234evb.cfg b/board/freescale/s32v234evb/s32v234evb.cfg deleted file mode 100644 index d7f722006312..000000000000 --- a/board/freescale/s32v234evb/s32v234evb.cfg +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015, Freescale Semiconductor, Inc. - */ - -/* - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ -#include <asm/mach-imx/imximage.cfg> - -/* image version */ -IMAGE_VERSION 2 -BOOT_FROM sd - - -/* - * Boot Device : one of qspi, sd: - * qspi: flash_offset: 0x1000 - * sd/mmc: flash_offset: 0x1000 - */ - - -#ifdef CONFIG_IMX_HAB -SECURE_BOOT -#endif diff --git a/configs/s32v234evb_defconfig b/configs/s32v234evb_defconfig deleted file mode 100644 index 656f63f76ab0..000000000000 --- a/configs/s32v234evb_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_S32V234EVB=y -CONFIG_SYS_TEXT_BASE=0x3E800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_MEMTEST_START=0xc0000000 -CONFIG_SYS_MEMTEST_END=0xc7c00000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/s32v234evb/s32v234evb.cfg" -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyLF0 root=/dev/ram rw" -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_MMC=y -CONFIG_CMD_CACHE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_USDHC=y -CONFIG_DM_SERIAL=y -CONFIG_FSL_LINFLEXUART=y -CONFIG_OF_LIBFDT=y diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index f8ea92172e44..07c8dbec2239 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -787,7 +787,7 @@ config FSL_ESDHC_IMX
config FSL_USDHC bool "Freescale/NXP i.MX uSDHC controller support" - depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMXRT || TARGET_S32V234EVB + depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMXRT select FSL_ESDHC_IMX help This enables the Ultra Secured Digital Host Controller enhancements diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h deleted file mode 100644 index 275d92eff783..000000000000 --- a/include/configs/s32v234evb.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015-2016 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale S32V234 EVB board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - -#define CONFIG_S32V234 - -/* Config GIC */ -#define CONFIG_GICV2 -#define GICD_BASE 0x7D001000 -#define GICC_BASE 0x7D002000 - -#define CONFIG_REMAKE_ELF -#undef CONFIG_RUN_FROM_IRAM_ONLY - -#define CONFIG_RUN_FROM_DDR1 -#undef CONFIG_RUN_FROM_DDR0 - -/* Run by default from DDR1 */ -#ifdef CONFIG_RUN_FROM_DDR0 -#define DDR_BASE_ADDR 0x80000000 -#else -#define DDR_BASE_ADDR 0xC0000000 -#endif - -#define CONFIG_MACH_TYPE 4146 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG - -/* SMP Spin Table Definitions */ -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY (1000000000) /* 1000MHz */ -#define CONFIG_SYS_FSL_ERRATUM_A008585 - -/* Size of malloc() pool */ -#ifdef CONFIG_RUN_FROM_IRAM_ONLY -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1 * 1024 * 1024) -#else -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) -#endif - -#define LINFLEXUART_BASE LINFLEXD0_BASE_ADDR - -#define CONFIG_DEBUG_UART_LINFLEXUART -#define CONFIG_DEBUG_UART_BASE LINFLEXUART_BASE - -#define CONFIG_SYS_UART_PORT (1) - -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -#if 0 - -/* Ethernet config */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 -#endif - -#if 0 /* Disable until the FLASH will be implemented */ -#define CONFIG_SYS_USE_NAND -#endif - -#ifdef CONFIG_SYS_USE_NAND -/* Nand Flash Configs */ -#define CONFIG_JFFS2_NAND -#define MTD_NAND_FSL_NFC_SWECC 1 -#define CONFIG_NAND_FSL_NFC -#define CONFIG_SYS_NAND_BASE 0x400E0000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE -#define CONFIG_SYS_NAND_SELECT_DEVICE -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ -#endif - -#define CONFIG_LOADADDR 0xC307FFC0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "boot_scripts=boot.scr.uimg boot.scr\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "console=ttyLF0,115200\0" \ - "fdt_file=s32v234-evb.dtb\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_addr_r=0xC2000000\0" \ - "kernel_addr_r=0xC307FFC0\0" \ - "ramdisk_addr_r=0xC4000000\0" \ - "ramdisk=rootfs.uimg\0"\ - "ip_dyn=yes\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "update_sd_firmware_filename=u-boot.imx\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk}\0" \ - "jtagboot=echo Booting using jtag...; " \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "jtagsdboot=echo Booting loading Linux with ramdisk from SD...; " \ - "run loaduimage; run loadramdisk; run loadfdt;"\ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "boot_net_usb_start=true\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) - -#define CONFIG_BOOTCOMMAND \ - "run distro_bootcmd" - -#include <config_distro_bootcmd.h> -#include <linux/stringify.h> - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_PROMPT "=> " - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -#ifdef CONFIG_RUN_FROM_IRAM_ONLY -#define CONFIG_SYS_MALLOC_BASE (DDR_BASE_ADDR) -#endif - -/* Physical memory map */ -/* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */ -#define PHYS_SDRAM (DDR_BASE_ADDR) -#define PHYS_SDRAM_SIZE (256 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ - - -#define CONFIG_BOOTP_BOOTFILESIZE - -#endif
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Jon Mason jon.mason@broadcom.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/Kconfig | 1 - board/broadcom/bcm958712k/MAINTAINERS | 6 --- board/broadcom/bcmns2/Kconfig | 15 ------- board/broadcom/bcmns2/Makefile | 5 --- board/broadcom/bcmns2/northstar2.c | 62 --------------------------- configs/bcm958712k_defconfig | 14 ------ include/configs/bcm_northstar2.h | 42 ------------------ 7 files changed, 145 deletions(-) delete mode 100644 board/broadcom/bcm958712k/MAINTAINERS delete mode 100644 board/broadcom/bcmns2/Kconfig delete mode 100644 board/broadcom/bcmns2/Makefile delete mode 100644 board/broadcom/bcmns2/northstar2.c delete mode 100644 configs/bcm958712k_defconfig delete mode 100644 include/configs/bcm_northstar2.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 535b71d4df51..2eb714f8a080 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1939,7 +1939,6 @@ source "board/broadcom/bcm968360bg/Kconfig" source "board/broadcom/bcm968580xref/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" -source "board/broadcom/bcmns2/Kconfig" source "board/broadcom/bcmns3/Kconfig" source "board/cavium/thunderx/Kconfig" source "board/cirrus/edb93xx/Kconfig" diff --git a/board/broadcom/bcm958712k/MAINTAINERS b/board/broadcom/bcm958712k/MAINTAINERS deleted file mode 100644 index 024fb1447d23..000000000000 --- a/board/broadcom/bcm958712k/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BCM958712K BOARD -M: Jon Mason jon.mason@broadcom.com -S: Maintained -F: board/broadcom/bcmns2/ -F: include/configs/bcm_northstar2.h -F: configs/bcm958712k_defconfig diff --git a/board/broadcom/bcmns2/Kconfig b/board/broadcom/bcmns2/Kconfig deleted file mode 100644 index 3ac67249c4d7..000000000000 --- a/board/broadcom/bcmns2/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_BCMNS2 - -config SYS_BOARD - default "bcmns2" - -config SYS_VENDOR - default "broadcom" - -config SYS_SOC - default "ns2" - -config SYS_CONFIG_NAME - default "bcm_northstar2" - -endif diff --git a/board/broadcom/bcmns2/Makefile b/board/broadcom/bcmns2/Makefile deleted file mode 100644 index 29274bd106ce..000000000000 --- a/board/broadcom/bcmns2/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2016 Broadcom Ltd. - -obj-y := northstar2.o diff --git a/board/broadcom/bcmns2/northstar2.c b/board/broadcom/bcmns2/northstar2.c deleted file mode 100644 index 91f489aad3f2..000000000000 --- a/board/broadcom/bcmns2/northstar2.c +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Broadcom Ltd. - */ -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <asm/cache.h> -#include <asm/system.h> -#include <asm/armv8/mmu.h> - -static struct mm_region ns2_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0xff80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = ns2_mem_map; - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE); - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - - return 0; -} - -void reset_cpu(ulong addr) -{ - psci_system_reset(); -} diff --git a/configs/bcm958712k_defconfig b/configs/bcm958712k_defconfig deleted file mode 100644 index 74070f555b65..000000000000 --- a/configs/bcm958712k_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_BCMNS2=y -CONFIG_SYS_TEXT_BASE=0x85000000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_IDENT_STRING=" Broadcom Northstar 2" -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTDELAY=5 -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SYS_PROMPT="u-boot> " -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_CONS_INDEX=4 -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/bcm_northstar2.h b/include/configs/bcm_northstar2.h deleted file mode 100644 index fbfab288b372..000000000000 --- a/include/configs/bcm_northstar2.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Broadcom NS2. - */ - -#ifndef __BCM_NORTHSTAR2_H -#define __BCM_NORTHSTAR2_H - -#include <linux/sizes.h> - -#define CONFIG_HOSTNAME "northstar2" - -/* Physical Memory Map */ -#define V2M_BASE 0x80000000 -#define PHYS_SDRAM_1 V2M_BASE - -#define PHYS_SDRAM_1_SIZE (4UL * SZ_1G) -#define PHYS_SDRAM_2_SIZE (4UL * SZ_1G) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* define text_base for U-boot image */ -#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x7ff00) -#define CONFIG_SYS_LOAD_ADDR 0x90000000 -#define CONFIG_SYS_MALLOC_LEN SZ_16M - -/* Serial Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 25000000 -#define CONFIG_SYS_NS16550_COM1 0x66100000 -#define CONFIG_SYS_NS16550_COM2 0x66110000 -#define CONFIG_SYS_NS16550_COM3 0x66120000 -#define CONFIG_SYS_NS16550_COM4 0x66130000 - -/* console configuration */ -#define CONFIG_SYS_CBSIZE SZ_1K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* version string, parser, etc */ - -#endif /* __BCM_NORTHSTAR2_H */
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Ben Whitten ben.whitten@lairdtech.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-at91/Kconfig | 6 - board/laird/wb45n/Kconfig | 12 -- board/laird/wb45n/MAINTAINERS | 6 - board/laird/wb45n/Makefile | 4 - board/laird/wb45n/wb45n.c | 199 ---------------------------------- configs/wb45n_defconfig | 51 --------- include/configs/wb45n.h | 124 --------------------- 7 files changed, 402 deletions(-) delete mode 100644 board/laird/wb45n/Kconfig delete mode 100644 board/laird/wb45n/MAINTAINERS delete mode 100644 board/laird/wb45n/Makefile delete mode 100644 board/laird/wb45n/wb45n.c delete mode 100644 configs/wb45n_defconfig delete mode 100644 include/configs/wb45n.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c78a308f4884..5880e651bafd 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -303,11 +303,6 @@ config TARGET_VINCO select SUPPORT_SPL imply CMD_DM
-config TARGET_WB45N - bool "Support Laird WB45N" - select CPU_ARM926EJS - select SUPPORT_SPL - config TARGET_WB50N bool "Support Laird WB50N" select BOARD_EARLY_INIT_F @@ -358,7 +353,6 @@ source "board/ronetix/pm9g45/Kconfig" source "board/siemens/corvus/Kconfig" source "board/siemens/taurus/Kconfig" source "board/siemens/smartweb/Kconfig" -source "board/laird/wb45n/Kconfig" source "board/laird/wb50n/Kconfig"
config SPL_LDSCRIPT diff --git a/board/laird/wb45n/Kconfig b/board/laird/wb45n/Kconfig deleted file mode 100644 index 2a67337293ef..000000000000 --- a/board/laird/wb45n/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_WB45N - -config SYS_BOARD - default "wb45n" - -config SYS_VENDOR - default "laird" - -config SYS_CONFIG_NAME - default "wb45n" - -endif diff --git a/board/laird/wb45n/MAINTAINERS b/board/laird/wb45n/MAINTAINERS deleted file mode 100644 index 60bb56320103..000000000000 --- a/board/laird/wb45n/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -WB45N CPU MODULE -M: Ben Whitten ben.whitten@lairdtech.com -S: Maintained -F: board/laird/wb45n/ -F: include/configs/wb45n.h -F: configs/wb45n_defconfig diff --git a/board/laird/wb45n/Makefile b/board/laird/wb45n/Makefile deleted file mode 100644 index 2971c6c95286..000000000000 --- a/board/laird/wb45n/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += wb45n.o diff --git a/board/laird/wb45n/wb45n.c b/board/laird/wb45n/wb45n.c deleted file mode 100644 index df6eeb624347..000000000000 --- a/board/laird/wb45n/wb45n.c +++ /dev/null @@ -1,199 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - */ - -#include <common.h> -#include <init.h> -#include <asm/io.h> -#include <asm/arch/at91sam9x5_matrix.h> -#include <asm/arch/at91sam9_smc.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_rstc.h> -#include <asm/arch/clk.h> -#include <asm/arch/gpio.h> -#include <net.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ -static void wb45n_nand_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - unsigned long csa; - - csa = readl(&matrix->ebicsa); - /* Enable CS3 */ - csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; - /* NAND flash on D0 */ - csa &= ~AT91_MATRIX_NFD0_ON_D16; - writel(csa, &matrix->ebicsa); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | - AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), - &smc->cs[3].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode); - - at91_periph_clk_enable(ATMEL_ID_PIOCD); - - /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); - /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); - /* Disable Flash Write Protect Line */ - at91_set_gpio_output(AT91_PIN_PD10, 1); - - at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ - at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ - at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ - at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ -} - -static void wb45n_gpio_hw_init(void) -{ - - /* Configure wifi gpio CHIP_PWD_L */ - at91_set_gpio_output(AT91_PIN_PA28, 0); - - /* Setup USB pins */ - at91_set_gpio_input(AT91_PIN_PB11, 0); - at91_set_gpio_output(AT91_PIN_PB12, 0); - - /* IRQ pin, pullup, deglitch */ - at91_set_gpio_input(AT91_PIN_PB18, 1); - at91_set_gpio_deglitch(AT91_PIN_PB18, 1); -} - -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; - - if (has_emac0()) - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); - - return rc; -} - -int board_early_init_f(void) -{ - at91_seriald_hw_init(); - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - wb45n_gpio_hw_init(); - - wb45n_nand_hw_init(); - - at91_macb_hw_init(); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -#if defined(CONFIG_SPL_BUILD) -#include <spl.h> -#include <nand.h> - -void at91_spl_board_init(void) -{ - /* Setup GPIO first */ - wb45n_gpio_hw_init(); - - /* Bring up NAND */ - wb45n_nand_hw_init(); -} - -void matrix_init(void) -{ - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - unsigned long csa; - - csa = readl(&matrix->ebicsa); - /* Pull ups on D0 - D16 */ - csa &= ~AT91_MATRIX_EBI_DBPU_OFF; - csa |= AT91_MATRIX_EBI_DBPD_OFF; - /* Normal drive strength */ - csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; - /* Multi-port off */ - csa &= ~AT91_MATRIX_MP_ON; - writel(csa, &matrix->ebicsa); -} - -#include <asm/arch/atmel_mpddrc.h> -static void ddr2_conf(struct atmel_mpddrc_config *ddr2) -{ - ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); - - ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | - ATMEL_MPDDRC_CR_NR_ROW_13 | - ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | - ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | - ATMEL_MPDDRC_CR_DQMS_SHARED); - - ddr2->rtr = 0x411; - - ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | - 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); - - ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | - 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | - 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | - 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); - - ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | - 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | - 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | - 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | - 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); -} - -void mem_init(void) -{ - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - struct atmel_mpddrc_config ddr2; - unsigned long csa; - - ddr2_conf(&ddr2); - - /* enable DDR2 clock */ - at91_system_clk_enable(AT91_PMC_DDR); - - /* Chip select 1 is for DDR2/SDRAM */ - csa = readl(&matrix->ebicsa); - csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; - writel(csa, &matrix->ebicsa); - - /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); -} -#endif diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig deleted file mode 100644 index ca47edf32113..000000000000 --- a/configs/wb45n_defconfig +++ /dev/null @@ -1,51 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_AT91=y -CONFIG_SYS_TEXT_BASE=0x23f00000 -CONFIG_TARGET_WB45N=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_MEMTEST_START=0x20000000 -CONFIG_SYS_MEMTEST_END=0x23e00000 -CONFIG_ENV_OFFSET=0xA0000 -CONFIG_SPL_TEXT_BASE=0x300000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0xC0000 -CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH" -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk rw noinitrd mem=64M rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6" -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_BASE=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MEMTEST=y -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_AT91_GPIO=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -# CONFIG_SYS_NAND_USE_FLASH_BBT is not set -CONFIG_NAND_ATMEL=y -CONFIG_PMECC_CAP=4 -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y -CONFIG_ATMEL_USART=y -CONFIG_LZMA=y -CONFIG_LZO=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/wb45n.h b/include/configs/wb45n.h deleted file mode 100644 index cc7a688580ea..000000000000 --- a/include/configs/wb45n.h +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the WB45N CPU Module. - */ - -#ifndef __CONFIG_H__ -#define __CONFIG_H__ - -#include <asm/hardware.h> -#include <linux/stringify.h> - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* serial console */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* NAND flash */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 - -#define CONFIG_RBTREE - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY -#define CONFIG_ETHADDR C0:EE:40:00:00:00 - -/* System */ -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#ifdef CONFIG_SYS_USE_NANDFLASH -/* bootstrap + u-boot + env + linux in nandflash */ - -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \ - "run _mtd; bootm" - -#define MTDIDS_DEFAULT "nand0=atmel_nand" -#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \ - "128K(at91bs)," \ - "512K(u-boot)," \ - "128K(u-boot-env)," \ - "128K(redund-env)," \ - "2560K(kernel-a)," \ - "2560K(kernel-b)," \ - "38912K(rootfs-a)," \ - "38912K(rootfs-b)," \ - "46208K(user)," \ - "512K(logs)" - -#else -#error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH' -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \ - "autoload=no\0" \ - "autostart=no\0" \ - "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ - "\0" - -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x6000 -#define CONFIG_SPL_STACK 0x308000 - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#endif /* __CONFIG_H__ */
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Ben Whitten ben.whitten@lairdtech.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-at91/Kconfig | 9 -- board/laird/wb50n/Kconfig | 12 -- board/laird/wb50n/MAINTAINERS | 6 - board/laird/wb50n/Makefile | 4 - board/laird/wb50n/wb50n.c | 205 ---------------------------------- configs/wb50n_defconfig | 53 --------- include/configs/wb50n.h | 96 ---------------- 7 files changed, 385 deletions(-) delete mode 100644 board/laird/wb50n/Kconfig delete mode 100644 board/laird/wb50n/MAINTAINERS delete mode 100644 board/laird/wb50n/Makefile delete mode 100644 board/laird/wb50n/wb50n.c delete mode 100644 configs/wb50n_defconfig delete mode 100644 include/configs/wb50n.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 5880e651bafd..22f6e4114e8e 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -303,14 +303,6 @@ config TARGET_VINCO select SUPPORT_SPL imply CMD_DM
-config TARGET_WB50N - bool "Support Laird WB50N" - select BOARD_EARLY_INIT_F - select BOARD_LATE_INIT - select CPU_V7A - select SUPPORT_SPL - select ATMEL_SFR - endchoice
config ATMEL_SFR @@ -353,7 +345,6 @@ source "board/ronetix/pm9g45/Kconfig" source "board/siemens/corvus/Kconfig" source "board/siemens/taurus/Kconfig" source "board/siemens/smartweb/Kconfig" -source "board/laird/wb50n/Kconfig"
config SPL_LDSCRIPT default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS diff --git a/board/laird/wb50n/Kconfig b/board/laird/wb50n/Kconfig deleted file mode 100644 index 2e7090ec34b2..000000000000 --- a/board/laird/wb50n/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_WB50N - -config SYS_BOARD - default "wb50n" - -config SYS_VENDOR - default "laird" - -config SYS_CONFIG_NAME - default "wb50n" - -endif diff --git a/board/laird/wb50n/MAINTAINERS b/board/laird/wb50n/MAINTAINERS deleted file mode 100644 index 3d38fc4e9faf..000000000000 --- a/board/laird/wb50n/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -WB50N CPU MODULE -M: Ben Whitten ben.whitten@lairdtech.com -S: Maintained -F: board/laird/wb50n/ -F: include/configs/wb50n.h -F: configs/wb50n_defconfig diff --git a/board/laird/wb50n/Makefile b/board/laird/wb50n/Makefile deleted file mode 100644 index f4c3831db462..000000000000 --- a/board/laird/wb50n/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += wb50n.o diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c deleted file mode 100644 index 9cc21b2abd3c..000000000000 --- a/board/laird/wb50n/wb50n.c +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - */ - -#include <common.h> -#include <init.h> -#include <asm/io.h> -#include <asm/arch/at91_sfr.h> -#include <asm/arch/sama5d3_smc.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/clk.h> -#include <env.h> -#include <micrel.h> -#include <net.h> -#include <netdev.h> -#include <spl.h> -#include <asm/arch/atmel_mpddrc.h> -#include <asm/arch/at91_wdt.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -void wb50n_nand_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - - at91_periph_clk_enable(ATMEL_ID_SMC); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | - AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | - AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), - &smc->cs[3].cycle); - writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | - AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | - AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) | - AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); - - /* Disable Flash Write Protect Line */ - at91_set_pio_output(AT91_PIO_PORTE, 14, 1); -} - -int board_early_init_f(void) -{ - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - at91_periph_clk_enable(ATMEL_ID_PIOD); - at91_periph_clk_enable(ATMEL_ID_PIOE); - - at91_seriald_hw_init(); - - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - wb50n_nand_hw_init(); - - at91_macb_hw_init(); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - /* rx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222); - /* tx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222); - /* rx/tx clock delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; - - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); - - return rc; -} - -#ifdef CONFIG_BOARD_LATE_INIT -#include <linux/ctype.h> -int board_late_init(void) -{ -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - const char *LAIRD_NAME = "lrd_name"; - char name[32], *p; - - strcpy(name, get_cpu_name()); - for (p = name; *p != '\0'; *p = tolower(*p), p++) - ; - strcat(name, "-wb50n"); - env_set(LAIRD_NAME, name); - -#endif - - return 0; -} -#endif - -/* SPL */ -#ifdef CONFIG_SPL_BUILD -void spl_board_init(void) -{ - wb50n_nand_hw_init(); -} - -static void ddr2_conf(struct atmel_mpddrc_config *ddr2) -{ - ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); - - ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 | - ATMEL_MPDDRC_CR_NR_ROW_13 | - ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | - ATMEL_MPDDRC_CR_NDQS_DISABLED | - ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | - ATMEL_MPDDRC_CR_UNAL_SUPPORTED); - - ddr2->rtr = 0x411; - - ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | - 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); - - ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | - 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | - 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | - 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); - - ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | - 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | - 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | - 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | - 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); -} - -void mem_init(void) -{ - struct atmel_mpddrc_config ddr2; - - ddr2_conf(&ddr2); - - configure_ddrcfg_input_buffers(true); - - /* enable MPDDR clock */ - at91_periph_clk_enable(ATMEL_ID_MPDDRC); - at91_system_clk_enable(AT91_PMC_DDR); - - /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); -} - -void at91_pmc_init(void) -{ - u32 tmp; - - tmp = AT91_PMC_PLLAR_29 | - AT91_PMC_PLLXR_PLLCOUNT(0x3f) | - AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1); - at91_plla_init(tmp); - - at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); - - tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA; - at91_mck_init(tmp); -} -#endif diff --git a/configs/wb50n_defconfig b/configs/wb50n_defconfig deleted file mode 100644 index 0ffc5b4d73a1..000000000000 --- a/configs/wb50n_defconfig +++ /dev/null @@ -1,53 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_AT91=y -CONFIG_SYS_TEXT_BASE=0x23f00000 -CONFIG_TARGET_WB50N=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_MEMTEST_START=0x21000000 -CONFIG_SYS_MEMTEST_END=0x22000000 -CONFIG_ENV_OFFSET=0xA0000 -CONFIG_SPL_TEXT_BASE=0x300000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0xC0000 -CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs" -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_BASE=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_AT91_GPIO=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -# CONFIG_SYS_NAND_USE_FLASH_BBT is not set -CONFIG_NAND_ATMEL=y -CONFIG_PMECC_CAP=8 -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_ATMEL_USART=y -CONFIG_LZMA=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h deleted file mode 100644 index b1f3b8452cbf..000000000000 --- a/include/configs/wb50n.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the WB50N CPU Module. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/hardware.h> - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* serial console */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_DBGU - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x310000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -/* NAND flash */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* Ethernet Hardware */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY -#define CONFIG_RGMII -#define CONFIG_ETHADDR C0:EE:40:00:00:00 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ - "autostart=no\0" - -/* bootstrap + u-boot + env in nandflash */ -#define CONFIG_BOOTCOMMAND \ - "nand read 0x22000000 0x000e0000 0x500000; " \ - "bootm" - -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#endif
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Erik van Luijk evanluijk@interact.nl Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-at91/Kconfig | 6 - board/mini-box/picosam9g45/Kconfig | 12 - board/mini-box/picosam9g45/MAINTAINERS | 6 - board/mini-box/picosam9g45/Makefile | 17 -- board/mini-box/picosam9g45/led.c | 22 -- board/mini-box/picosam9g45/picosam9g45.c | 346 ----------------------- configs/picosam9g45_defconfig | 48 ---- include/configs/picosam9g45.h | 118 -------- 8 files changed, 575 deletions(-) delete mode 100644 board/mini-box/picosam9g45/Kconfig delete mode 100644 board/mini-box/picosam9g45/MAINTAINERS delete mode 100644 board/mini-box/picosam9g45/Makefile delete mode 100644 board/mini-box/picosam9g45/led.c delete mode 100644 board/mini-box/picosam9g45/picosam9g45.c delete mode 100644 configs/picosam9g45_defconfig delete mode 100644 include/configs/picosam9g45.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 22f6e4114e8e..1adf09b9a148 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -134,11 +134,6 @@ config TARGET_PM9G45 bool "Ronetix pm9g45 board" select AT91SAM9G45
-config TARGET_PICOSAM9G45 - bool "Mini-box picosam9g45 board" - select AT91SAM9M10G45 - select SUPPORT_SPL - config TARGET_AT91SAM9N12EK bool "Atmel AT91SAM9N12-EK board" select AT91SAM9N12 @@ -338,7 +333,6 @@ source "board/egnite/ethernut5/Kconfig" source "board/esd/meesc/Kconfig" source "board/gardena/smart-gateway-at91sam/Kconfig" source "board/l+g/vinco/Kconfig" -source "board/mini-box/picosam9g45/Kconfig" source "board/ronetix/pm9261/Kconfig" source "board/ronetix/pm9263/Kconfig" source "board/ronetix/pm9g45/Kconfig" diff --git a/board/mini-box/picosam9g45/Kconfig b/board/mini-box/picosam9g45/Kconfig deleted file mode 100644 index 98ec0c457a62..000000000000 --- a/board/mini-box/picosam9g45/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_PICOSAM9G45 - -config SYS_BOARD - default "picosam9g45" - -config SYS_VENDOR - default "mini-box" - -config SYS_CONFIG_NAME - default "picosam9g45" - -endif diff --git a/board/mini-box/picosam9g45/MAINTAINERS b/board/mini-box/picosam9g45/MAINTAINERS deleted file mode 100644 index a8cf01d70380..000000000000 --- a/board/mini-box/picosam9g45/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PICOSAM9G45 BOARD -M: Erik van Luijk evanluijk@interact.nl -S: Maintained -F: board/mini-box/picosam9g45/ -F: include/configs/picosam9g45.h -F: configs/picosam9g45_defconfig diff --git a/board/mini-box/picosam9g45/Makefile b/board/mini-box/picosam9g45/Makefile deleted file mode 100644 index 6e98997a7c31..000000000000 --- a/board/mini-box/picosam9g45/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Makefile for mini-box PICOSAM9G45 (AT91SAM9G45) based board -# (C) Copytight 2015 Inter Act B.V. -# -# Based on: -# U-Boot file: board/atmel/at91sam9m10g45ek/Makefile -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Stelian Pop stelian@popies.net -# Lead Tech Design <www.leadtechdesign.com> - -obj-y += picosam9g45.o -obj-y += led.o diff --git a/board/mini-box/picosam9g45/led.c b/board/mini-box/picosam9g45/led.c deleted file mode 100644 index 8ce8b6bbeac2..000000000000 --- a/board/mini-box/picosam9g45/led.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2007-2008 - * Stelian Pop stelian@popies.net - * Lead Tech Design <www.leadtechdesign.com> - */ - -#include <common.h> -#include <status_led.h> -#include <asm/io.h> -#include <asm/arch/at91sam9g45.h> -#include <asm/arch/clk.h> -#include <asm/arch/gpio.h> - -void coloured_LED_init(void) -{ - at91_periph_clk_enable(ATMEL_ID_PIODE); - - at91_set_gpio_output(CONFIG_GREEN_LED, 1); - - at91_set_gpio_value(CONFIG_GREEN_LED, 1); -} diff --git a/board/mini-box/picosam9g45/picosam9g45.c b/board/mini-box/picosam9g45/picosam9g45.c deleted file mode 100644 index e8e1ac3eb195..000000000000 --- a/board/mini-box/picosam9g45/picosam9g45.c +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board - * (C) Copyright 2015 Inter Act B.V. - * - * Based on: - * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c - * (C) Copyright 2007-2008 - * Stelian Pop stelian@popies.net - * Lead Tech Design <www.leadtechdesign.com> - */ - -#include <common.h> -#include <init.h> -#include <vsprintf.h> -#include <asm/io.h> -#include <asm/arch/clk.h> -#include <asm/arch/at91sam9g45_matrix.h> -#include <asm/arch/at91sam9_smc.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/gpio.h> -#include <asm/arch/clk.h> -#include <lcd.h> -#include <linux/mtd/rawnand.h> -#include <atmel_lcdc.h> -#include <atmel_mci.h> -#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) -#include <net.h> -#endif -#include <netdev.h> -#include <asm/mach-types.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -#if defined(CONFIG_SPL_BUILD) -#include <spl.h> - -void at91_spl_board_init(void) -{ -#ifdef CONFIG_SYS_USE_MMC - at91_mci_hw_init(); -#endif -} - -#include <asm/arch/atmel_mpddrc.h> -static void ddr2_conf(struct atmel_mpddrc_config *ddr2) -{ - ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); - - ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | - ATMEL_MPDDRC_CR_NR_ROW_14 | - ATMEL_MPDDRC_CR_DQMS_SHARED | - ATMEL_MPDDRC_CR_CAS_DDR_CAS3); - - ddr2->rtr = 0x24b; - - ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ - 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ - 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ - 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */ - 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ - 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ - 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ - 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ - - ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ - 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | - 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | - 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); - - ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | - 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | - 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | - 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); -} - -void mem_init(void) -{ - struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; - struct atmel_mpddrc_config ddr2; - unsigned long csa; - - ddr2_conf(&ddr2); - - at91_system_clk_enable(AT91_PMC_DDR); - - /* Chip select 1 is for DDR2/SDRAM */ - csa = readl(&mat->ebicsa); - csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; - csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V; - writel(csa, &mat->ebicsa); - - /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); - ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2); -} -#endif - -#ifdef CONFIG_CMD_USB -static void picosam9g45_usb_hw_init(void) -{ - at91_periph_clk_enable(ATMEL_ID_PIODE); - - at91_set_gpio_output(AT91_PIN_PD1, 0); - at91_set_gpio_output(AT91_PIN_PD3, 0); -} -#endif - -#ifdef CONFIG_MACB -static void picosam9g45_macb_hw_init(void) -{ - struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - - at91_periph_clk_enable(ATMEL_ID_EMAC); - - /* - * Disable pull-up on: - * RXDV (PA15) => PHY normal mode (not Test mode) - * ERX0 (PA12) => PHY ADDR0 - * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 - * - * PHY has internal pull-down - */ - writel(pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA12) | - pin_to_mask(AT91_PIN_PA13), - &pioa->pudr); - - at91_phy_reset(); - - /* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA12) | - pin_to_mask(AT91_PIN_PA13), - &pioa->puer); - - /* And the pins. */ - at91_macb_hw_init(); -} -#endif - -#ifdef CONFIG_LCD - -vidinfo_t panel_info = { - .vl_col = 480, - .vl_row = 272, - .vl_clk = 9000000, - .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | - ATMEL_LCDC_INVFRAME_NORMAL, - .vl_bpix = 3, - .vl_tft = 1, - .vl_hsync_len = 45, - .vl_left_margin = 1, - .vl_right_margin = 1, - .vl_vsync_len = 1, - .vl_upper_margin = 40, - .vl_lower_margin = 1, - .mmio = ATMEL_BASE_LCDC, -}; - - -void lcd_enable(void) -{ - at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ -} - -void lcd_disable(void) -{ - at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */ -} - -static void picosam9g45_lcd_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ - at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ - at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ - at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ - at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ - - at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ - at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ - at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ - at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ - at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ - at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ - at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ - at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ - at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ - at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ - at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ - at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ - at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ - at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ - at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ - at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ - at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ - at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ - at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ - at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ - at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ - at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ - at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ - at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ - - at91_periph_clk_enable(ATMEL_ID_LCDC); - - gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; -} - -#ifdef CONFIG_LCD_INFO -#include <nand.h> -#include <version.h> - -void lcd_show_board_info(void) -{ - ulong dram_size; - int i; - char temp[32]; - - lcd_printf("%s\n", U_BOOT_VERSION); - lcd_printf("(C) 2015 Inter Act B.V.\n"); - lcd_printf("support@interact.nl\n"); - lcd_printf("%s CPU at %s MHz\n", - ATMEL_CPU_NAME, - strmhz(temp, get_cpu_clk_rate())); - - dram_size = 0; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - dram_size += gd->bd->bi_dram[i].size; - lcd_printf(" %ld MB SDRAM\n", dram_size >> 20); -} -#endif /* CONFIG_LCD_INFO */ -#endif - -#ifdef CONFIG_GENERIC_ATMEL_MCI -int board_mmc_init(struct bd_info *bis) -{ - at91_mci_hw_init(); - - return atmel_mci_init((void *)ATMEL_BASE_MCI0); -} -#endif - -int board_early_init_f(void) -{ - at91_seriald_hw_init(); - return 0; -} - -int board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - -#ifdef CONFIG_CMD_USB - picosam9g45_usb_hw_init(); -#endif -#ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 4); -#endif -#ifdef CONFIG_MACB - picosam9g45_macb_hw_init(); -#endif -#ifdef CONFIG_LCD - picosam9g45_lcd_hw_init(); -#endif - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) - + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); - - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -void reset_phy(void) -{ -} -#endif - -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); -#endif - return rc; -} - -/* SPI chip select control */ -#ifdef CONFIG_ATMEL_SPI -#include <spi.h> - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs < 2; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - switch (slave->cs) { - case 1: - at91_set_gpio_output(AT91_PIN_PB18, 0); - break; - case 0: - default: - at91_set_gpio_output(AT91_PIN_PB3, 0); - break; - } -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - switch (slave->cs) { - case 1: - at91_set_gpio_output(AT91_PIN_PB18, 1); - break; - case 0: - default: - at91_set_gpio_output(AT91_PIN_PB3, 1); - break; - } -} -#endif /* CONFIG_ATMEL_SPI */ diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig deleted file mode 100644 index 915c2ba81289..000000000000 --- a/configs/picosam9g45_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_AT91=y -CONFIG_SYS_TEXT_BASE=0x23f00000 -CONFIG_TARGET_PICOSAM9G45=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x4000 -CONFIG_SPL_TEXT_BASE=0x300000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC" -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="U-Boot> " -# CONFIG_CMD_BDI is not set -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_SPL_DM=y -CONFIG_AT91_GPIO=y -CONFIG_ATMEL_USART=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_WDT=y -CONFIG_WDT_AT91=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h deleted file mode 100644 index 77b7ce411f5b..000000000000 --- a/include/configs/picosam9g45.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the mini-box PICOSAM9G45 board. - * (C) Copyright 2015 Inter Act B.V. - * - * Based on: - * U-Boot file: include/configs/at91sam9m10g45ek.h - * (C) Copyright 2007-2008 - * Stelian Pop stelian@popies.net - * Lead Tech Design <www.leadtechdesign.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/hardware.h> - -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ - -/* serial console */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -/* LCD */ -#define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO -#undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO -#define CONFIG_LCD_INFO_BELOW_LOGO -#define CONFIG_ATMEL_LCD -#define CONFIG_ATMEL_LCD_RGB565 -/* board specific(not enough SRAM) */ -#define CONFIG_AT91SAM9G45_LCD_BASE 0x23E00000 - -/* LED */ -#define CONFIG_AT91_LED -#define CONFIG_GREEN_LED AT91_PIN_PD31 /* this is the user1 led */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define PHYS_SDRAM_1 ATMEL_BASE_CS1 /* on DDRSDRC1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_2 ATMEL_BASE_CS6 /* on DDRSDRC0 */ -#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* MMC */ - -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R -#define CONFIG_AT91_WANTS_COMMON_PHY - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#ifdef CONFIG_SYS_USE_MMC -/* bootstrap + u-boot + env + linux in mmc */ - -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \ - "fatload mmc 0:1 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE 0x010000 -#define CONFIG_SPL_STACK 0x310000 - -#define CONFIG_SYS_MONITOR_LEN 0x80000 - -#ifdef CONFIG_SYS_USE_MMC - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_ATMEL_SIZE -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 - -#endif -#endif
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Chris Packham judge.packham@gmail.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/dts/Makefile | 2 - arch/arm/dts/kirkwood-db-88f6281-spi.dts | 48 --------- arch/arm/dts/kirkwood-db-88f6281.dts | 26 ----- arch/arm/dts/kirkwood-db.dtsi | 94 ----------------- arch/arm/mach-kirkwood/Kconfig | 4 - board/Marvell/db-88f6281-bp/.gitignore | 1 - board/Marvell/db-88f6281-bp/Kconfig | 12 --- board/Marvell/db-88f6281-bp/MAINTAINERS | 10 -- board/Marvell/db-88f6281-bp/Makefile | 12 --- board/Marvell/db-88f6281-bp/db-88f6281-bp.c | 106 -------------------- board/Marvell/db-88f6281-bp/kwbimage.cfg.in | 36 ------- configs/db-88f6281-bp-nand_defconfig | 64 ------------ configs/db-88f6281-bp-spi_defconfig | 63 ------------ include/configs/db-88f6281-bp.h | 83 --------------- 14 files changed, 561 deletions(-) delete mode 100644 arch/arm/dts/kirkwood-db-88f6281-spi.dts delete mode 100644 arch/arm/dts/kirkwood-db-88f6281.dts delete mode 100644 arch/arm/dts/kirkwood-db.dtsi delete mode 100644 board/Marvell/db-88f6281-bp/.gitignore delete mode 100644 board/Marvell/db-88f6281-bp/Kconfig delete mode 100644 board/Marvell/db-88f6281-bp/MAINTAINERS delete mode 100644 board/Marvell/db-88f6281-bp/Makefile delete mode 100644 board/Marvell/db-88f6281-bp/db-88f6281-bp.c delete mode 100644 board/Marvell/db-88f6281-bp/kwbimage.cfg.in delete mode 100644 configs/db-88f6281-bp-nand_defconfig delete mode 100644 configs/db-88f6281-bp-spi_defconfig delete mode 100644 include/configs/db-88f6281-bp.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f0944b7590cf..cbaa9f29c1b5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -39,8 +39,6 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += \ kirkwood-atl-sbx81lifxcat.dtb \ kirkwood-blackarmor-nas220.dtb \ kirkwood-d2net.dtb \ - kirkwood-db-88f6281.dtb \ - kirkwood-db-88f6281-spi.dtb \ kirkwood-dns325.dtb \ kirkwood-dockstar.dtb \ kirkwood-dreamplug.dtb \ diff --git a/arch/arm/dts/kirkwood-db-88f6281-spi.dts b/arch/arm/dts/kirkwood-db-88f6281-spi.dts deleted file mode 100644 index 50b1b0d4a535..000000000000 --- a/arch/arm/dts/kirkwood-db-88f6281-spi.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell DB-88F6281-BP Development Board Setup - * - * Saeed Bishara saeed@marvell.com - * Thomas Petazzoni thomas.petazzoni@free-electrons.com - * - */ - -/dts-v1/; - -#include "kirkwood-db-88f6281.dts" - -/ { - aliases { - spi0 = &spi0; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor", "spi-flash"; - reg = <0>; - spi-max-frequency = <50000000>; - mode = <0>; - - partition@u-boot { - reg = <0x00000000 0x00c00000>; - label = "u-boot"; - }; - partition@u-boot-env { - reg = <0x00c00000 0x00040000>; - label = "u-boot-env"; - }; - partition@unused { - reg = <0x00100000 0x00f00000>; - label = "unused"; - }; - }; -}; - -&nand { - status = "disabled"; -}; diff --git a/arch/arm/dts/kirkwood-db-88f6281.dts b/arch/arm/dts/kirkwood-db-88f6281.dts deleted file mode 100644 index 2adb17c955aa..000000000000 --- a/arch/arm/dts/kirkwood-db-88f6281.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell DB-88F6281-BP Development Board Setup - * - * Saeed Bishara saeed@marvell.com - * Thomas Petazzoni thomas.petazzoni@free-electrons.com - * - */ - -/dts-v1/; - -#include "kirkwood-db.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Marvell DB-88F6281-BP Development Board"; - compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood-db.dtsi b/arch/arm/dts/kirkwood-db.dtsi deleted file mode 100644 index b81d8e8298a3..000000000000 --- a/arch/arm/dts/kirkwood-db.dtsi +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell DB-{88F6281,88F6282}-BP Development Board Setup - * - * Saeed Bishara saeed@marvell.com - * Thomas Petazzoni thomas.petazzoni@free-electrons.com - * - * This file contains the definitions that are common between the 6281 - * and 6282 variants of the Marvell Kirkwood Development Board. - */ - -#include "kirkwood.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - aliases { - ethernet0 = ð0; - spi0 = &spi0; - }; - - ocp@f1000000 { - pin-controller@10000 { - pmx_sdio_gpios: pmx-sdio-gpios { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - nr-ports = <2>; - status = "okay"; - }; - - ehci@50000 { - status = "okay"; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio_gpios>; - pinctrl-names = "default"; - wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; -}; - -&nand { - chip-delay = <25>; - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x400000>; - }; - - partition@500000 { - label = "root"; - reg = <0x500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 1d2ba886dd1a..546a3fc00fdc 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -56,9 +56,6 @@ config TARGET_SBx81LIFKW config TARGET_SBx81LIFXCAT bool "Allied Telesis SBx81GP24/SBx81GT24"
-config TARGET_DB_88F6281_BP - bool "Marvell DB-88F6281-BP" - endchoice
config SYS_SOC @@ -81,6 +78,5 @@ source "board/Seagate/nas220/Kconfig" source "board/zyxel/nsa310s/Kconfig" source "board/alliedtelesis/SBx81LIFKW/Kconfig" source "board/alliedtelesis/SBx81LIFXCAT/Kconfig" -source "board/Marvell/db-88f6281-bp/Kconfig"
endif diff --git a/board/Marvell/db-88f6281-bp/.gitignore b/board/Marvell/db-88f6281-bp/.gitignore deleted file mode 100644 index 775b9346b859..000000000000 --- a/board/Marvell/db-88f6281-bp/.gitignore +++ /dev/null @@ -1 +0,0 @@ -kwbimage.cfg diff --git a/board/Marvell/db-88f6281-bp/Kconfig b/board/Marvell/db-88f6281-bp/Kconfig deleted file mode 100644 index 38467399e688..000000000000 --- a/board/Marvell/db-88f6281-bp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DB_88F6281_BP - -config SYS_BOARD - default "db-88f6281-bp" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "db-88f6281-bp" - -endif diff --git a/board/Marvell/db-88f6281-bp/MAINTAINERS b/board/Marvell/db-88f6281-bp/MAINTAINERS deleted file mode 100644 index acf0b051ff54..000000000000 --- a/board/Marvell/db-88f6281-bp/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -DB_88F6820_AMC BOARD -M: Chris Packham judge.packham@gmail.com -S: Maintained -F: arch/arm/dts/kirkwood-db-88f6281.dts -F: arch/arm/dts/kirkwood-db-88f6281-spi.dts -F: arch/arm/dts/kirkwood-db.dtsi -F: board/Marvell/db-88f6281-bp/ -F: include/configs/db-88f6281-bp.h -F: configs/db-88f6281-bp-nand_defconfig -F: configs/db-88f6281-bp-spi_defconfig diff --git a/board/Marvell/db-88f6281-bp/Makefile b/board/Marvell/db-88f6281-bp/Makefile deleted file mode 100644 index 003e9f66d18f..000000000000 --- a/board/Marvell/db-88f6281-bp/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := db-88f6281-bp.o -extra-y := kwbimage.cfg - -quiet_cmd_sed = SED $@ - cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F) - -SEDFLAGS_kwbimage.cfg = -e "s/^#@BOOT_FROM.*/BOOT_FROM $(if $(CONFIG_CMD_NAND),nand,spi)/" -$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ - include/config/auto.conf - $(call if_changed,sed) diff --git a/board/Marvell/db-88f6281-bp/db-88f6281-bp.c b/board/Marvell/db-88f6281-bp/db-88f6281-bp.c deleted file mode 100644 index 62027bd6385e..000000000000 --- a/board/Marvell/db-88f6281-bp/db-88f6281-bp.c +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <linux/bitops.h> -#include <linux/io.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> -#include <asm/arch/mpp.h> -#include <asm/arch/gpio.h> - -#define DB_88F6281_OE_LOW ~(BIT(7)) -#define DB_88F6281_OE_HIGH ~(BIT(15) | BIT(14) | BIT(13) | BIT(4)) -#define DB_88F6281_OE_VAL_LOW BIT(7) -#define DB_88F6281_OE_VAL_HIGH 0 - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - mvebu_config_gpio(DB_88F6281_OE_VAL_LOW, - DB_88F6281_OE_VAL_HIGH, - DB_88F6281_OE_LOW, DB_88F6281_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { -#ifdef CONFIG_CMD_NAND - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, -#else - MPP0_SPI_SCn, - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, -#endif - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, - MPP13_SD_CMD, - MPP14_SD_D0, - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_SATA1_ACTn, - MPP21_SATA0_ACTn, - MPP22_GPIO, - MPP23_GPIO, - MPP24_GPIO, - MPP25_GPIO, - MPP26_GPIO, - MPP27_GPIO, - MPP28_GPIO, - MPP29_GPIO, - MPP30_GPIO, - MPP31_GPIO, - MPP32_GPIO, - MPP33_GPIO, - MPP34_GPIO, - MPP35_GPIO, - MPP36_GPIO, - MPP37_GPIO, - MPP38_GPIO, - MPP39_GPIO, - MPP40_GPIO, - MPP41_GPIO, - MPP42_GPIO, - MPP43_GPIO, - MPP44_GPIO, - MPP45_GPIO, - MPP46_GPIO, - MPP47_GPIO, - MPP48_GPIO, - MPP49_GPIO, - 0 - }; - kirkwood_mpp_conf(kwmpp_config, NULL); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -/* automatically defined by kirkwood config.h */ -void reset_phy(void) -{ -} -#endif diff --git a/board/Marvell/db-88f6281-bp/kwbimage.cfg.in b/board/Marvell/db-88f6281-bp/kwbimage.cfg.in deleted file mode 100644 index 05f8b275f607..000000000000 --- a/board/Marvell/db-88f6281-bp/kwbimage.cfg.in +++ /dev/null @@ -1,36 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -# Boot Media configurations -#@BOOT_FROM - -DATA 0xd00100e0 0x1b1b1b9b -DATA 0xd0020134 0xbbbbbbbb -DATA 0xd0020138 0x00bbbbbb -DATA 0xd0020154 0x00000200 -DATA 0xd002014c 0x00001c00 -DATA 0xd0020148 0x00000001 - -DATA 0xd0001400 0x43000c30 -DATA 0xd0001404 0x39543000 -DATA 0xd0001408 0x22125451 -DATA 0xd000140c 0x00000833 -DATA 0xd0001410 0x000000cc -DATA 0xd0001414 0x00000000 -DATA 0xd0001418 0x00000000 -DATA 0xd000141c 0x00000c52 -DATA 0xd0001420 0x00000044 -DATA 0xd0001424 0x0000f1ff -DATA 0xd0001428 0x00085520 -DATA 0xd000147c 0x00008552 -DATA 0xd0001504 0x0ffffff1 -DATA 0xd0001508 0x10000000 -DATA 0xd000150c 0x0ffffff5 -DATA 0xd0001514 0x00000000 -DATA 0xd000151c 0x00000000 -DATA 0xd0001494 0x84210000 -DATA 0xd0001498 0x00000000 -DATA 0xd000149c 0x0000f40f -DATA 0xd0001480 0x00000001 - -# End of Header extension -DATA 0x0 0x0 diff --git a/configs/db-88f6281-bp-nand_defconfig b/configs/db-88f6281-bp-nand_defconfig deleted file mode 100644 index 4fff3269aff1..000000000000 --- a/configs/db-88f6281-bp-nand_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_TARGET_DB_88F6281_BP=y -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_IDENT_STRING="\nMarvell DB-88F6281-BP" -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-db-88f6281" -# CONFIG_SYS_MALLOC_F is not set -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_DM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)" -CONFIG_ISO_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_NETCONSOLE=y -CONFIG_DM=y -CONFIG_MVSATA_IDE=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHY_MARVELL=y -CONFIG_DM_ETH=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_DM_RTC=y -CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_LZMA=y -CONFIG_LZO=y diff --git a/configs/db-88f6281-bp-spi_defconfig b/configs/db-88f6281-bp-spi_defconfig deleted file mode 100644 index 07e9db7f41b2..000000000000 --- a/configs/db-88f6281-bp-spi_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_TARGET_DB_88F6281_BP=y -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_IDENT_STRING="\nMarvell DB-88F6281-BP" -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-db-88f6281-spi" -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_DM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)" -CONFIG_ISO_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_NETCONSOLE=y -CONFIG_DM=y -CONFIG_MVSATA_IDE=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHY_MARVELL=y -CONFIG_DM_ETH=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_DM_RTC=y -CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_LZMA=y -CONFIG_LZO=y diff --git a/include/configs/db-88f6281-bp.h b/include/configs/db-88f6281-bp.h deleted file mode 100644 index 06a7091be208..000000000000 --- a/include/configs/db-88f6281-bp.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef _CONFIG_DB_88F6281_BP_H -#define _CONFIG_DB_88F6281_BP_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_SYS_TCLK 166666667 -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg - -/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ -#define CONFIG_KIRKWOOD_GPIO 1 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* - * Environment variables configurations - */ -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ -#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE - -/* - * U-Boot bootcode configuration - */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ - -/* size in bytes reserved for initial data */ - -#include <asm/arch/config.h> -/* There is no PHY directly connected so don't ask it for link status */ -#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -/* - * Other required minimal configurations - */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ - -/* - * SDIO/MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MVEBU_MMC -#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE -#endif /* CONFIG_CMD_MMC */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */ - -#endif /* _CONFIG_DB_88F6281_BP_H */
On Wed, 10 Feb 2021, 2:04 AM Tom Rini, trini@konsulko.com wrote:
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Chris Packham judge.packham@gmail.com Signed-off-by: Tom Rini trini@konsulko.com
I did have every intention of finishing off the migration but the reference board I have has gathered plenty of dust. So reluctantly
Acked-by: Chris Packham judge.packham@gmail.com
---
arch/arm/dts/Makefile | 2 - arch/arm/dts/kirkwood-db-88f6281-spi.dts | 48 --------- arch/arm/dts/kirkwood-db-88f6281.dts | 26 ----- arch/arm/dts/kirkwood-db.dtsi | 94 ----------------- arch/arm/mach-kirkwood/Kconfig | 4 - board/Marvell/db-88f6281-bp/.gitignore | 1 - board/Marvell/db-88f6281-bp/Kconfig | 12 --- board/Marvell/db-88f6281-bp/MAINTAINERS | 10 -- board/Marvell/db-88f6281-bp/Makefile | 12 --- board/Marvell/db-88f6281-bp/db-88f6281-bp.c | 106 -------------------- board/Marvell/db-88f6281-bp/kwbimage.cfg.in | 36 ------- configs/db-88f6281-bp-nand_defconfig | 64 ------------ configs/db-88f6281-bp-spi_defconfig | 63 ------------ include/configs/db-88f6281-bp.h | 83 --------------- 14 files changed, 561 deletions(-) delete mode 100644 arch/arm/dts/kirkwood-db-88f6281-spi.dts delete mode 100644 arch/arm/dts/kirkwood-db-88f6281.dts delete mode 100644 arch/arm/dts/kirkwood-db.dtsi delete mode 100644 board/Marvell/db-88f6281-bp/.gitignore delete mode 100644 board/Marvell/db-88f6281-bp/Kconfig delete mode 100644 board/Marvell/db-88f6281-bp/MAINTAINERS delete mode 100644 board/Marvell/db-88f6281-bp/Makefile delete mode 100644 board/Marvell/db-88f6281-bp/db-88f6281-bp.c delete mode 100644 board/Marvell/db-88f6281-bp/kwbimage.cfg.in delete mode 100644 configs/db-88f6281-bp-nand_defconfig delete mode 100644 configs/db-88f6281-bp-spi_defconfig delete mode 100644 include/configs/db-88f6281-bp.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f0944b7590cf..cbaa9f29c1b5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -39,8 +39,6 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += \ kirkwood-atl-sbx81lifxcat.dtb \ kirkwood-blackarmor-nas220.dtb \ kirkwood-d2net.dtb \
kirkwood-db-88f6281.dtb \kirkwood-db-88f6281-spi.dtb \ kirkwood-dns325.dtb \ kirkwood-dockstar.dtb \ kirkwood-dreamplug.dtb \diff --git a/arch/arm/dts/kirkwood-db-88f6281-spi.dts b/arch/arm/dts/kirkwood-db-88f6281-spi.dts deleted file mode 100644 index 50b1b0d4a535..000000000000 --- a/arch/arm/dts/kirkwood-db-88f6281-spi.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/*
- Marvell DB-88F6281-BP Development Board Setup
- Saeed Bishara saeed@marvell.com
- Thomas Petazzoni thomas.petazzoni@free-electrons.com
- */
-/dts-v1/;
-#include "kirkwood-db-88f6281.dts"
-/ {
aliases {spi0 = &spi0;};-};
-&spi0 {
status = "okay";flash@0 {#address-cells = <1>;#size-cells = <1>;compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";reg = <0>;spi-max-frequency = <50000000>;mode = <0>;partition@u-boot {reg = <0x00000000 0x00c00000>;label = "u-boot";};partition@u-boot-env {reg = <0x00c00000 0x00040000>;label = "u-boot-env";};partition@unused {reg = <0x00100000 0x00f00000>;label = "unused";};};-};
-&nand {
status = "disabled";-}; diff --git a/arch/arm/dts/kirkwood-db-88f6281.dts b/arch/arm/dts/kirkwood-db-88f6281.dts deleted file mode 100644 index 2adb17c955aa..000000000000 --- a/arch/arm/dts/kirkwood-db-88f6281.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/*
- Marvell DB-88F6281-BP Development Board Setup
- Saeed Bishara saeed@marvell.com
- Thomas Petazzoni thomas.petazzoni@free-electrons.com
- */
-/dts-v1/;
-#include "kirkwood-db.dtsi" -#include "kirkwood-6281.dtsi"
-/ {
model = "Marvell DB-88F6281-BP Development Board";compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281","marvell,kirkwood"; -};
-&pciec {
status = "okay";-};
-&pcie0 {
status = "okay";-}; diff --git a/arch/arm/dts/kirkwood-db.dtsi b/arch/arm/dts/kirkwood-db.dtsi deleted file mode 100644 index b81d8e8298a3..000000000000 --- a/arch/arm/dts/kirkwood-db.dtsi +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/*
- Marvell DB-{88F6281,88F6282}-BP Development Board Setup
- Saeed Bishara saeed@marvell.com
- Thomas Petazzoni thomas.petazzoni@free-electrons.com
- This file contains the definitions that are common between the 6281
- and 6282 variants of the Marvell Kirkwood Development Board.
- */
-#include "kirkwood.dtsi"
-/ {
memory {device_type = "memory";reg = <0x00000000 0x20000000>; /* 512 MB */};chosen {bootargs = "console=ttyS0,115200n8 earlyprintk";stdout-path = &uart0;};aliases {ethernet0 = ð0;spi0 = &spi0;};ocp@f1000000 {pin-controller@10000 {pmx_sdio_gpios: pmx-sdio-gpios {marvell,pins = "mpp37", "mpp38";marvell,function = "gpio";};};serial@12000 {status = "okay";};sata@80000 {nr-ports = <2>;status = "okay";};ehci@50000 {status = "okay";};mvsdio@90000 {pinctrl-0 = <&pmx_sdio_gpios>;pinctrl-names = "default";wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;status = "okay";};};-};
-&nand {
chip-delay = <25>;status = "okay";partition@0 {label = "uboot";reg = <0x0 0x100000>;};partition@100000 {label = "uImage";reg = <0x100000 0x400000>;};partition@500000 {label = "root";reg = <0x500000 0x1fb00000>;};-};
-&mdio {
status = "okay";ethphy0: ethernet-phy@8 {reg = <8>;};-};
-ð0 {
status = "okay";ethernet0-port@0 {phy-handle = <ðphy0>;};-}; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 1d2ba886dd1a..546a3fc00fdc 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -56,9 +56,6 @@ config TARGET_SBx81LIFKW config TARGET_SBx81LIFXCAT bool "Allied Telesis SBx81GP24/SBx81GT24"
-config TARGET_DB_88F6281_BP
bool "Marvell DB-88F6281-BP"endchoice
config SYS_SOC @@ -81,6 +78,5 @@ source "board/Seagate/nas220/Kconfig" source "board/zyxel/nsa310s/Kconfig" source "board/alliedtelesis/SBx81LIFKW/Kconfig" source "board/alliedtelesis/SBx81LIFXCAT/Kconfig" -source "board/Marvell/db-88f6281-bp/Kconfig"
endif diff --git a/board/Marvell/db-88f6281-bp/.gitignore b/board/Marvell/db-88f6281-bp/.gitignore deleted file mode 100644 index 775b9346b859..000000000000 --- a/board/Marvell/db-88f6281-bp/.gitignore +++ /dev/null @@ -1 +0,0 @@ -kwbimage.cfg diff --git a/board/Marvell/db-88f6281-bp/Kconfig b/board/Marvell/db-88f6281-bp/Kconfig deleted file mode 100644 index 38467399e688..000000000000 --- a/board/Marvell/db-88f6281-bp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DB_88F6281_BP
-config SYS_BOARD
default "db-88f6281-bp"-config SYS_VENDOR
default "Marvell"-config SYS_CONFIG_NAME
default "db-88f6281-bp"-endif diff --git a/board/Marvell/db-88f6281-bp/MAINTAINERS b/board/Marvell/db-88f6281-bp/MAINTAINERS deleted file mode 100644 index acf0b051ff54..000000000000 --- a/board/Marvell/db-88f6281-bp/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -DB_88F6820_AMC BOARD -M: Chris Packham judge.packham@gmail.com -S: Maintained -F: arch/arm/dts/kirkwood-db-88f6281.dts -F: arch/arm/dts/kirkwood-db-88f6281-spi.dts -F: arch/arm/dts/kirkwood-db.dtsi -F: board/Marvell/db-88f6281-bp/ -F: include/configs/db-88f6281-bp.h -F: configs/db-88f6281-bp-nand_defconfig -F: configs/db-88f6281-bp-spi_defconfig diff --git a/board/Marvell/db-88f6281-bp/Makefile b/board/Marvell/db-88f6281-bp/Makefile deleted file mode 100644 index 003e9f66d18f..000000000000 --- a/board/Marvell/db-88f6281-bp/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+
-obj-y := db-88f6281-bp.o -extra-y := kwbimage.cfg
-quiet_cmd_sed = SED $@
cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F)-SEDFLAGS_kwbimage.cfg = -e "s/^#@BOOT_FROM.*/BOOT_FROM $(if $(CONFIG_CMD_NAND),nand,spi)/" -$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
include/config/auto.conf$(call if_changed,sed)diff --git a/board/Marvell/db-88f6281-bp/db-88f6281-bp.c b/board/Marvell/db-88f6281-bp/db-88f6281-bp.c deleted file mode 100644 index 62027bd6385e..000000000000 --- a/board/Marvell/db-88f6281-bp/db-88f6281-bp.c +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+
-#include <common.h> -#include <init.h> -#include <net.h> -#include <linux/bitops.h> -#include <linux/io.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> -#include <asm/arch/mpp.h> -#include <asm/arch/gpio.h>
-#define DB_88F6281_OE_LOW ~(BIT(7)) -#define DB_88F6281_OE_HIGH ~(BIT(15) | BIT(14) | BIT(13) | BIT(4)) -#define DB_88F6281_OE_VAL_LOW BIT(7) -#define DB_88F6281_OE_VAL_HIGH 0
-DECLARE_GLOBAL_DATA_PTR;
-int board_early_init_f(void) -{
mvebu_config_gpio(DB_88F6281_OE_VAL_LOW,DB_88F6281_OE_VAL_HIGH,DB_88F6281_OE_LOW, DB_88F6281_OE_HIGH);/* Multi-Purpose Pins Functionality configuration */static const u32 kwmpp_config[] = {-#ifdef CONFIG_CMD_NAND
MPP0_NF_IO2,MPP1_NF_IO3,MPP2_NF_IO4,MPP3_NF_IO5,-#else
MPP0_SPI_SCn,MPP1_SPI_MOSI,MPP2_SPI_SCK,MPP3_SPI_MISO,-#endif
MPP4_NF_IO6,MPP5_NF_IO7,MPP6_SYSRST_OUTn,MPP7_GPO,MPP8_TW_SDA,MPP9_TW_SCK,MPP10_UART0_TXD,MPP11_UART0_RXD,MPP12_SD_CLK,MPP13_SD_CMD,MPP14_SD_D0,MPP15_SD_D1,MPP16_SD_D2,MPP17_SD_D3,MPP18_NF_IO0,MPP19_NF_IO1,MPP20_SATA1_ACTn,MPP21_SATA0_ACTn,MPP22_GPIO,MPP23_GPIO,MPP24_GPIO,MPP25_GPIO,MPP26_GPIO,MPP27_GPIO,MPP28_GPIO,MPP29_GPIO,MPP30_GPIO,MPP31_GPIO,MPP32_GPIO,MPP33_GPIO,MPP34_GPIO,MPP35_GPIO,MPP36_GPIO,MPP37_GPIO,MPP38_GPIO,MPP39_GPIO,MPP40_GPIO,MPP41_GPIO,MPP42_GPIO,MPP43_GPIO,MPP44_GPIO,MPP45_GPIO,MPP46_GPIO,MPP47_GPIO,MPP48_GPIO,MPP49_GPIO,0};kirkwood_mpp_conf(kwmpp_config, NULL);return 0;-}
-int board_init(void) -{
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;return 0;-}
-#ifdef CONFIG_RESET_PHY_R -/* automatically defined by kirkwood config.h */ -void reset_phy(void) -{ -} -#endif diff --git a/board/Marvell/db-88f6281-bp/kwbimage.cfg.in b/board/Marvell/db-88f6281-bp/kwbimage.cfg.in deleted file mode 100644 index 05f8b275f607..000000000000 --- a/board/Marvell/db-88f6281-bp/kwbimage.cfg.in +++ /dev/null @@ -1,36 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+
-# Boot Media configurations -#@BOOT_FROM
-DATA 0xd00100e0 0x1b1b1b9b -DATA 0xd0020134 0xbbbbbbbb -DATA 0xd0020138 0x00bbbbbb -DATA 0xd0020154 0x00000200 -DATA 0xd002014c 0x00001c00 -DATA 0xd0020148 0x00000001
-DATA 0xd0001400 0x43000c30 -DATA 0xd0001404 0x39543000 -DATA 0xd0001408 0x22125451 -DATA 0xd000140c 0x00000833 -DATA 0xd0001410 0x000000cc -DATA 0xd0001414 0x00000000 -DATA 0xd0001418 0x00000000 -DATA 0xd000141c 0x00000c52 -DATA 0xd0001420 0x00000044 -DATA 0xd0001424 0x0000f1ff -DATA 0xd0001428 0x00085520 -DATA 0xd000147c 0x00008552 -DATA 0xd0001504 0x0ffffff1 -DATA 0xd0001508 0x10000000 -DATA 0xd000150c 0x0ffffff5 -DATA 0xd0001514 0x00000000 -DATA 0xd000151c 0x00000000 -DATA 0xd0001494 0x84210000 -DATA 0xd0001498 0x00000000 -DATA 0xd000149c 0x0000f40f -DATA 0xd0001480 0x00000001
-# End of Header extension -DATA 0x0 0x0 diff --git a/configs/db-88f6281-bp-nand_defconfig b/configs/db-88f6281-bp-nand_defconfig deleted file mode 100644 index 4fff3269aff1..000000000000 --- a/configs/db-88f6281-bp-nand_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_TARGET_DB_88F6281_BP=y -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_IDENT_STRING="\nMarvell DB-88F6281-BP" -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-db-88f6281" -# CONFIG_SYS_MALLOC_F is not set -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_DM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)" -CONFIG_ISO_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_NETCONSOLE=y -CONFIG_DM=y -CONFIG_MVSATA_IDE=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHY_MARVELL=y -CONFIG_DM_ETH=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_DM_RTC=y -CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_LZMA=y -CONFIG_LZO=y diff --git a/configs/db-88f6281-bp-spi_defconfig b/configs/db-88f6281-bp-spi_defconfig deleted file mode 100644 index 07e9db7f41b2..000000000000 --- a/configs/db-88f6281-bp-spi_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_TARGET_DB_88F6281_BP=y -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_IDENT_STRING="\nMarvell DB-88F6281-BP" -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-db-88f6281-spi" -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_DM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)" -CONFIG_ISO_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_NETCONSOLE=y -CONFIG_DM=y -CONFIG_MVSATA_IDE=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHY_MARVELL=y -CONFIG_DM_ETH=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_DM_RTC=y -CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_LZMA=y -CONFIG_LZO=y diff --git a/include/configs/db-88f6281-bp.h b/include/configs/db-88f6281-bp.h deleted file mode 100644 index 06a7091be208..000000000000 --- a/include/configs/db-88f6281-bp.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _CONFIG_DB_88F6281_BP_H -#define _CONFIG_DB_88F6281_BP_H
-/*
- High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_SYS_TCLK 166666667 -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ -#define CONFIG_KIRKWOOD_GPIO 1
-/*
- NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/*
- Environment variables configurations
- */
-#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ -#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-/*
- U-Boot bootcode configuration
- */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */
-/*
- For booting Linux, the board info and command line data
- have to be in the first 8 MB of memory, since this is
- the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
-/* size in bytes reserved for initial data */
-#include <asm/arch/config.h> -/* There is no PHY directly connected so don't ask it for link status */ -#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-/*
- Other required minimal configurations
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-/*
- SDIO/MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC -#define CONFIG_MVEBU_MMC -#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE -#endif /* CONFIG_CMD_MMC */
-/*
- SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/
-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
-#endif /* _CONFIG_DB_88F6281_BP_H */
2.17.1
On Tue, Feb 09, 2021 at 08:03:16AM -0500, Tom Rini wrote:
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Chris Packham judge.packham@gmail.com Signed-off-by: Tom Rini trini@konsulko.com Acked-by: Chris Packham judge.packham@gmail.com
Applied to u-boot/master, thanks!
This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Otavio Salvador otavio@ossystems.com.br Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-imx/mx6/Kconfig | 6 -- board/warp/Kconfig | 9 -- board/warp/MAINTAINERS | 6 -- board/warp/Makefile | 6 -- board/warp/README | 56 ----------- board/warp/imximage.cfg | 123 ------------------------- board/warp/warp.c | 169 ---------------------------------- configs/warp_defconfig | 49 ---------- include/configs/warp.h | 145 ----------------------------- 9 files changed, 569 deletions(-) delete mode 100644 board/warp/Kconfig delete mode 100644 board/warp/MAINTAINERS delete mode 100644 board/warp/Makefile delete mode 100644 board/warp/README delete mode 100644 board/warp/imximage.cfg delete mode 100644 board/warp/warp.c delete mode 100644 configs/warp_defconfig delete mode 100644 include/configs/warp.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 737e305f29f1..410afed075c8 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -642,11 +642,6 @@ config TARGET_WANDBOARD select BOARD_LATE_INIT select SUPPORT_SPL
-config TARGET_WARP - bool "WaRP" - depends on MX6SL - select BOARD_LATE_INIT - config TARGET_XPRESS bool "CCV xPress" depends on MX6UL @@ -746,7 +741,6 @@ source "board/k+p/kp_imx6q_tpc/Kconfig" source "board/udoo/Kconfig" source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" -source "board/warp/Kconfig" source "board/BuR/brppt2/Kconfig"
endif diff --git a/board/warp/Kconfig b/board/warp/Kconfig deleted file mode 100644 index dc0263631906..000000000000 --- a/board/warp/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_WARP - -config SYS_BOARD - default "warp" - -config SYS_CONFIG_NAME - default "warp" - -endif diff --git a/board/warp/MAINTAINERS b/board/warp/MAINTAINERS deleted file mode 100644 index ee2114d08235..000000000000 --- a/board/warp/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -WaRP BOARD -M: Otavio Salvador otavio@ossystems.com.br -S: Maintained -F: board/warp/ -F: include/configs/warp.h -F: configs/warp_defconfig diff --git a/board/warp/Makefile b/board/warp/Makefile deleted file mode 100644 index 3a2373d7bf5b..000000000000 --- a/board/warp/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2014 O.S. Systems Software LTDA. -# Copyright (C) 2014 Kynetics LLC. -# Copyright (C) 2014 Revolution Robotics, Inc. - -obj-y := warp.o diff --git a/board/warp/README b/board/warp/README deleted file mode 100644 index 3cfd22ec761d..000000000000 --- a/board/warp/README +++ /dev/null @@ -1,56 +0,0 @@ -How to Update U-Boot on Warp board ----------------------------------- - -Required software on the host PC: - -- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader - -- dfu-util: http://dfu-util.sourceforge.net/releases/ - -Build U-Boot for Warp: - -$ make mrproper -$ make warp_config -$ make - -This will generate the U-Boot binary called u-boot.imx. - -Put warp board in USB download mode - -Connect a USB to serial adapter between the host PC and warp - -Connect a USB cable between the OTG warp port and the host PC - -Open a terminal program such as minicom - -Copy u-boot.imx to the imx_usb_loader folder. - -Load u-boot.imx via USB: - -$ sudo ./imx_usb u-boot.imx - -Then U-Boot should start and its messages will appear in the console program. - -Use the default environment variables: - -=> env default -f -a -=> saveenv - -Run the DFU command: -=> dfu 0 mmc 0 - -Transfer u-boot.imx that will be flashed into the eMMC: - -$ sudo dfu-util -D u-boot.imx -a boot - -Then on the U-Boot prompt the following message should be seen after a -successful upgrade: - -#DOWNLOAD ... OK -Ctrl+C to exit ... - -Remove power from the warp board. - -Put warp board into normal boot mode - -Power up the board and the new updated U-Boot should boot from eMMC diff --git a/board/warp/imximage.cfg b/board/warp/imximage.cfg deleted file mode 100644 index 619f6aa7b066..000000000000 --- a/board/warp/imximage.cfg +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ -#define __ASSEMBLY__ -#include <config.h> - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ - -BOOT_FROM sd - -/* - * Secure boot support - */ -#ifdef CONFIG__IMX_HAB -CSF CONFIG_CSF_SIZE -#endif - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -DATA 4 0x020c4018 0x00260324 - -DATA 4 0x020c4068 0xffffffff -DATA 4 0x020c406c 0xffffffff -DATA 4 0x020c4070 0xffffffff -DATA 4 0x020c4074 0xffffffff -DATA 4 0x020c4078 0xffffffff -DATA 4 0x020c407c 0xffffffff -DATA 4 0x020c4080 0xffffffff - -DATA 4 0x020e0344 0x00003030 -DATA 4 0x020e0348 0x00003030 -DATA 4 0x020e034c 0x00003030 -DATA 4 0x020e0350 0x00003030 -DATA 4 0x020e030c 0x00000030 -DATA 4 0x020e0310 0x00000030 -DATA 4 0x020e0314 0x00000030 -DATA 4 0x020e0318 0x00000030 -DATA 4 0x020e0300 0x00000030 -DATA 4 0x020e031c 0x00000030 -DATA 4 0x020e0338 0x00000028 -DATA 4 0x020e0320 0x00000030 -DATA 4 0x020e032c 0x00000000 -DATA 4 0x020e033c 0x00000008 -DATA 4 0x020e0340 0x00000008 -DATA 4 0x020e05c4 0x00000030 -DATA 4 0x020e05cc 0x00000030 -DATA 4 0x020e05d4 0x00000030 -DATA 4 0x020e05d8 0x00000030 -DATA 4 0x020e05ac 0x00000030 -DATA 4 0x020e05c8 0x00000030 -DATA 4 0x020e05b0 0x00020000 -DATA 4 0x020e05b4 0x00000000 -DATA 4 0x020e05c0 0x00020000 -DATA 4 0x020e05d0 0x00080000 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b085c 0x1b4700c7 -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b0890 0x00400000 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 -DATA 4 0x021b082c 0xf3333333 -DATA 4 0x021b0830 0xf3333333 -DATA 4 0x021b0834 0xf3333333 -DATA 4 0x021b0838 0xf3333333 -DATA 4 0x021b0848 0x4241444a -DATA 4 0x021b0850 0x3030312b -DATA 4 0x021b083c 0x20000000 -DATA 4 0x021b0840 0x00000000 -DATA 4 0x021b08c0 0x24911492 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b000c 0x33374133 -DATA 4 0x021b0004 0x00020024 -DATA 4 0x021b0010 0x00100A82 -DATA 4 0x021b0014 0x00000093 -DATA 4 0x021b0018 0x00001688 -DATA 4 0x021b002c 0x0f9f26d2 -DATA 4 0x021b0030 0x009f0e10 -DATA 4 0x021b0038 0x00190778 -DATA 4 0x021b0008 0x00000000 -DATA 4 0x021b0040 0x0000004f -DATA 4 0x021b0000 0x83110000 -DATA 4 0x021b001c 0x003f8030 -DATA 4 0x021b001c 0xff0a8030 -DATA 4 0x021b001c 0x82018030 -DATA 4 0x021b001c 0x04028030 -DATA 4 0x021b001c 0x02038030 -DATA 4 0x021b001c 0xff0a8038 -DATA 4 0x021b001c 0x82018038 -DATA 4 0x021b001c 0x04028038 -DATA 4 0x021b001c 0x02038038 -DATA 4 0x021b0800 0xa1310003 -DATA 4 0x021b0020 0x00001800 -DATA 4 0x021b0818 0x00000000 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b0004 0x00025564 -DATA 4 0x021b0404 0x00011006 -DATA 4 0x021b001c 0x00000000 diff --git a/board/warp/warp.c b/board/warp/warp.c deleted file mode 100644 index 85da9c1bd435..000000000000 --- a/board/warp/warp.c +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, 2015 O.S. Systems Software LTDA. - * Copyright (C) 2014 Kynetics LLC. - * Copyright (C) 2014 Revolution Robotics, Inc. - * - * Author: Otavio Salvador otavio@ossystems.com.br - */ - -#include <init.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/io.h> -#include <linux/sizes.h> -#include <common.h> -#include <watchdog.h> -#include <fsl_esdhc_imx.h> -#include <i2c.h> -#include <mmc.h> -#include <usb.h> -#include <power/pmic.h> -#include <power/max77696_pmic.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS | \ - PAD_CTL_LVE) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS | \ - PAD_CTL_LVE) - -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static void setup_iomux_uart(void) -{ - static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC2_BASE_ADDR, 0, 0, 0, 1}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; /* Assume boot SD always present */ -} - -int board_mmc_init(struct bd_info *bis) -{ - static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_RST__USDHC2_RST | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - -int board_usb_phy_mode(int port) -{ - return USB_INIT_DEVICE; -} - -/* I2C1 for PMIC */ -#define I2C_PMIC 0 -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .sda = { - .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC, - .gp = IMX_GPIO_NR(3, 13), - }, - .scl = { - .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC, - .gp = IMX_GPIO_NR(3, 12), - }, -}; - -int power_init_board(void) -{ - struct pmic *p; - int ret; - unsigned int reg; - - ret = power_max77696_init(I2C_PMIC); - if (ret) - return ret; - - p = pmic_get("MAX77696"); - if (!p) - return -EINVAL; - - ret = pmic_reg_read(p, CID, ®); - if (ret) - return ret; - - printf("PMIC: MAX77696 detected, rev=0x%x\n", reg); - - return pmic_probe(p); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - - return 0; -} - -int board_late_init(void) -{ -#ifdef CONFIG_HW_WATCHDOG - hw_watchdog_init(); -#endif - - return 0; -} - -int checkboard(void) -{ - puts("Board: WaRP Board\n"); - - return 0; -} diff --git a/configs/warp_defconfig b/configs/warp_defconfig deleted file mode 100644 index 34acc9e6c844..000000000000 --- a/configs/warp_defconfig +++ /dev/null @@ -1,49 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 -CONFIG_MX6SL=y -CONFIG_TARGET_WARP=y -# CONFIG_CMD_BMODE is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp/imximage.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -# CONFIG_NET is not set -CONFIG_BOUNCE_BUFFER=y -CONFIG_DFU_MMC=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_USDHC=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="FSL" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_WATCHDOG_TIMEOUT_MSECS=30000 -CONFIG_IMX_WATCHDOG=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/warp.h b/include/configs/warp.h deleted file mode 100644 index f17eea117f3a..000000000000 --- a/include/configs/warp.h +++ /dev/null @@ -1,145 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 O.S. Systems Software LTDA. - * Copyright (C) 2014 Kynetics LLC. - * Copyright (C) 2014 Revolution Robotics, Inc. - * - * Author: Otavio Salvador otavio@ossystems.com.br - * - * Configuration settings for the WaRP Board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ - -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE - -/* Watchdog */ - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* VDD voltage 1.65 - 1.95 */ -#define CONFIG_SYS_SD_VOLTAGE 0x00000080 - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG2 port enabled */ -#endif - -#define CONFIG_USBD_HS - -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_MAX77696 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sl-warp.dtb\0" \ - "fdt_addr=0x88000000\0" \ - "initrd_addr=0x83800000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "finduuid=part uuid mmc 0:2 uuid\0" \ - "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#endif /* __CONFIG_H */
participants (12)
-
Chris Packham -
Fabio Estevam -
Harm Berntsen -
Lauri Hintsala -
Lukasz Majewski -
Priyanka Jain -
Rick Thomas -
Simon Glass -
Stefano Babic -
Tim Harvey -
Tom Rini -
Vagrant Cascadian