RE: [U-Boot-Users] Running test code from RAM while having GOT po inting to flash
The hardware engineer is initializing the DDR memory correctly. Otherwise we won't be able to read/write to the memory.
As I understand, the GOT table is used for relocating the exception vectors. I am most likely crashing while copying the fixups or when doing a cache flush.
In start.S, if I disable the ICACHE & do not run the cache POST test which Enables the I-cache and never disables it, I should be fine. Unless its some 852T processor cache bug. We had problem with ICTRL with value of 7. Value of 3 seems to work better. Processor is at 50MHz and memory is at 100MHz with TA line based handshake ( so atomic).
-- Atul
In message 4A062D477D842B4C8FC48EA5AF2D41F2015280DA@us-bv-m23.global.tektronix.net you wrote:
The hardware engineer is initializing the DDR memory correctly. Otherwise we won't be able to read/write to the memory.
Please read the FAQ entry. The fact that you can read and write to this memory does not mean ANYTHING. Even normal memory test routines cannot detect problems that occur only when accessing the memory in burst mode. And this is the critical mode of operation. I bet you crash because of corrupted data when the CPU performs a cache fill when fethcing some code.
As I understand, the GOT table is used for relocating the exception vectors.
But relocation has been completed when you jump to RAM. The GOT does not play any role any more then.
I am most likely crashing while copying the fixups or when doing a cache flush.
More likely during a cache fill.
Best regards,
Wolfgang Denk
participants (2)
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atul.sabharwal＠exgate.tek.com -
Wolfgang Denk