This is mostly copied from "support for TPS65217 PMIC" patches from the old am33xx U-boot tree by Greg Guyyote with additions by Tom Rini, me and others.

Also drop DDR3 voltage level from 1.5V to 1.35V for beaglebone. DDR3 operation is verified at this lower voltage level.

Signed-off-by: Joel A Fernandes joelagnel@ti.com --- arch/arm/cpu/armv7/am33xx/board.c | 134 ++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/am33xx/pmic.h | 76 +++++++++++++++++++ arch/arm/cpu/armv7/am33xx/tps65217.h | 90 +++++++++++++++++++++++ 3 files changed, 300 insertions(+) create mode 100644 arch/arm/cpu/armv7/am33xx/pmic.h create mode 100644 arch/arm/cpu/armv7/am33xx/tps65217.h

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 6de03fd..075295c 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -33,6 +33,8 @@ #include <i2c.h> #include <miiphy.h> #include <cpsw.h> +#include "pmic.h" +#include "tps65217.h"

DECLARE_GLOBAL_DATA_PTR;

@@ -135,6 +137,132 @@ static short inline board_memory_type(void) return EMIF_REG_SDRAM_TYPE_DDR2; }

+/** + * tps65217_reg_read() - Generic function that can read a TPS65217 register + * @src_reg: Source register address + * @src_val: Address of destination variable + */ + +unsigned char tps65217_reg_read(uchar src_reg, uchar *src_val) +{ + if (i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1)) + return 1; + return 0; +} + +/** + * tps65217_reg_write() - Generic function that can write a TPS65217 PMIC + * register or bit field regardless of protection + * level. + * + * @prot_level: Register password protection. + * use PROT_LEVEL_NONE, PROT_LEVEL_1, or PROT_LEVEL_2 + * @dest_reg: Register address to write. + * @dest_val: Value to write. + * @mask: Bit mask (8 bits) to be applied. Function will only + * change bits that are set in the bit mask. + * + * @return: 0 for success, 1 for failure. + */ +int tps65217_reg_write(uchar prot_level, uchar dest_reg, + uchar dest_val, uchar mask) +{ + uchar read_val; + uchar xor_reg; + + /* if we are affecting only a bit field, read dest_reg and apply the mask */ + if (mask != MASK_ALL_BITS) { + if (i2c_read(TPS65217_CHIP_PM, dest_reg, 1, &read_val, 1)) + return 1; + read_val &= (~mask); + read_val |= (dest_val & mask); + dest_val = read_val; + } + + if (prot_level > 0) { + xor_reg = dest_reg ^ PASSWORD_UNLOCK; + if (i2c_write(TPS65217_CHIP_PM, PASSWORD, 1, &xor_reg, 1)) + return 1; + } + + if (i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1)) + return 1; + + if (prot_level == PROT_LEVEL_2) { + if (i2c_write(TPS65217_CHIP_PM, PASSWORD, 1, &xor_reg, 1)) + return 1; + + if (i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1)) + return 1; + } + + return 0; +} + +int tps65217_voltage_update(unsigned char dc_cntrl_reg, unsigned char volt_sel) +{ + if ((dc_cntrl_reg != DEFDCDC1) && (dc_cntrl_reg != DEFDCDC2) + && (dc_cntrl_reg != DEFDCDC3)) + return 1; + + /* set voltage level */ + if (tps65217_reg_write(PROT_LEVEL_2, dc_cntrl_reg, volt_sel, MASK_ALL_BITS)) + return 1; + + /* set GO bit to initiate voltage transition */ + if (tps65217_reg_write(PROT_LEVEL_2, DEFSLEW, DCDC_GO, DCDC_GO)) + return 1; + + return 0; +} + +/* + * voltage switching for MPU frequency switching. + * @module = mpu - 0, core - 1 + * @vddx_op_vol_sel = vdd voltage to set + */ + +#define MPU 0 +#define CORE 1 + +int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel) +{ + uchar buf[4]; + unsigned int reg_offset; + + if(module == MPU) + reg_offset = PMIC_VDD1_OP_REG; + else + reg_offset = PMIC_VDD2_OP_REG; + + /* Select VDDx OP */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + buf[0] &= ~PMIC_OP_REG_CMD_MASK; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + /* Configure VDDx OP Voltage */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + buf[0] &= ~PMIC_OP_REG_SEL_MASK; + buf[0] |= vddx_op_vol_sel; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + if ((buf[0] & PMIC_OP_REG_SEL_MASK ) != vddx_op_vol_sel) + return 1; + + return 0; +} + /* * early system init of muxing and clocks. */ @@ -190,6 +318,12 @@ void s_init(void) gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); gpio_direction_output(GPIO_DDR_VTT_EN, 1); } + /* Set DCDC2 (MPU) voltage to 1.275V */ + if (tps65217_voltage_update(DEFDCDC1, + DCDC_VOLT_SEL_135MV)) { + printf("tps65217_voltage_update failure\n"); + return; + }

config_ddr(board_memory_type()); #endif diff --git a/arch/arm/cpu/armv7/am33xx/pmic.h b/arch/arm/cpu/armv7/am33xx/pmic.h new file mode 100644 index 0000000..e258c44 --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/pmic.h @@ -0,0 +1,76 @@ +/* + * pmic.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef PMIC_h +#define PMIC_H + +/* + * The PMIC on this board is a TPS65910. + */ + +#define PMIC_SR_I2C_ADDR 0x12 +#define PMIC_CTRL_I2C_ADDR 0x2D +/* PMIC Register offsets */ +#define PMIC_VDD1_REG 0x21 +#define PMIC_VDD1_OP_REG 0x22 +#define PMIC_VDD2_REG 0x24 +#define PMIC_VDD2_OP_REG 0x25 +#define PMIC_DEVCTRL_REG 0x3f + +/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */ +#define PMIC_VGAIN_SEL_MASK (0x3 << 6) +#define PMIC_ILMAX_MASK (0x1 << 5) +#define PMIC_TSTEP_MASK (0x7 << 2) +#define PMIC_ST_MASK (0x3) + +#define PMIC_REG_VGAIN_SEL_X1 (0x0 << 6) +#define PMIC_REG_VGAIN_SEL_X1_0 (0x1 << 6) +#define PMIC_REG_VGAIN_SEL_X3 (0x2 << 6) +#define PMIC_REG_VGAIN_SEL_X4 (0x3 << 6) + +#define PMIC_REG_ILMAX_1_0_A (0x0 << 5) +#define PMIC_REG_ILMAX_1_5_A (0x1 << 5) + +#define PMIC_REG_TSTEP_ (0x0 << 2) +#define PMIC_REG_TSTEP_12_5 (0x1 << 2) +#define PMIC_REG_TSTEP_9_4 (0x2 << 2) +#define PMIC_REG_TSTEP_7_5 (0x3 << 2) +#define PMIC_REG_TSTEP_6_25 (0x4 << 2) +#define PMIC_REG_TSTEP_4_7 (0x5 << 2) +#define PMIC_REG_TSTEP_3_12 (0x6 << 2) +#define PMIC_REG_TSTEP_2_5 (0x7 << 2) + +#define PMIC_REG_ST_OFF (0x0) +#define PMIC_REG_ST_ON_HI_POW (0x1) +#define PMIC_REG_ST_OFF_1 (0x2) +#define PMIC_REG_ST_ON_LOW_POW (0x3) + + +/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */ +#define PMIC_OP_REG_SEL (0x7F) + +#define PMIC_OP_REG_CMD_MASK (0x1 << 7) +#define PMIC_OP_REG_CMD_OP (0x0 << 7) +#define PMIC_OP_REG_CMD_SR (0x1 << 7) + +#define PMIC_OP_REG_SEL_MASK (0x7F) +#define PMIC_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */ +#define PMIC_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */ + +/* Device control register . (DEVCTRL_REG) */ +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4) +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4) +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4) + +#endif diff --git a/arch/arm/cpu/armv7/am33xx/tps65217.h b/arch/arm/cpu/armv7/am33xx/tps65217.h new file mode 100644 index 0000000..3197209 --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/tps65217.h @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2011 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __TPS65217_H__ +#define __TPS65217_H__ + +#include <common.h> +#include <i2c.h> + +/* I2C chip address */ +#define TPS65217_CHIP_PM 0x24 + +/* Registers */ +#define CHIPID 0x00 +#define POWER_PATH 0x01 +#define INTERRUPT 0x02 +#define CHGCONFIG0 0x03 +#define CHGCONFIG1 0x04 +#define CHGCONFIG2 0x05 +#define CHGCONFIG3 0x06 +#define WLEDCTRL1 0x07 +#define WLEDCTRL2 0x08 +#define MUXCTRL 0x09 +#define STATUS 0x0A +#define PASSWORD 0x0B +#define PGOOD 0x0C +#define DEFPG 0x0D +#define DEFDCDC1 0x0E +#define DEFDCDC2 0x0F +#define DEFDCDC3 0x10 +#define DEFSLEW 0x11 +#define DEFLDO1 0x12 +#define DEFLDO2 0x13 +#define DEFLS1 0x14 +#define DEFLS2 0x15 +#define ENABLE 0x16 +#define DEFUVLO 0x18 +#define SEQ1 0x19 +#define SEQ2 0x1A +#define SEQ3 0x1B +#define SEQ4 0x1C +#define SEQ5 0x1D +#define SEQ6 0x1E + +#define PROT_LEVEL_NONE 0x00 +#define PROT_LEVEL_1 0x01 +#define PROT_LEVEL_2 0x02 + +#define PASSWORD_LOCK_FOR_WRITE 0x00 +#define PASSWORD_UNLOCK 0x7D + +#define DCDC_GO 0x80 + +#define MASK_ALL_BITS 0xFF + +#define USB_INPUT_CUR_LIMIT_MASK 0x03 +#define USB_INPUT_CUR_LIMIT_100MA 0x00 +#define USB_INPUT_CUR_LIMIT_500MA 0x01 +#define USB_INPUT_CUR_LIMIT_1300MA 0x02 +#define USB_INPUT_CUR_LIMIT_1800MA 0x03 + +#define DCDC_VOLT_SEL_1275MV 0x0F +#define DCDC_VOLT_SEL_135MV 0x12 + +#define LDO_MASK 0x1F +#define LDO_VOLTAGE_OUT_3_3 0x1F + +#define PWR_SRC_USB_BITMASK 0x4 +#define PWR_SRC_AC_BITMASK 0x8 +#endif