Hi Stefano,

Ping..

Thanks, Peng. On Sat, Oct 08, 2016 at 05:03:00PM +0800, Peng Fan wrote:

According to design team, we need to set REFTOP_VBGADJ in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the actually table is as below:

'000" - set REFTOP_VBGADJ[2:0] to 3'b000 '001" - set REFTOP_VBGADJ[2:0] to 3'b001 '010" - set REFTOP_VBGADJ[2:0] to 3'b010 '011" - set REFTOP_VBGADJ[2:0] to 3'b011 '100" - set REFTOP_VBGADJ[2:0] to 3'b100 '101" - set REFTOP_VBGADJ[2:0] to 3'b101 '110" - set REFTOP_VBGADJ[2:0] to 3'b110 '111" - set REFTOP_VBGADJ[2:0] to 3'b111

Signed-off-by: Peng Fan peng.fan@nxp.com Signed-off-by: Bai Ping ping.bai@nxp.com

---

arch/arm/cpu/armv7/mx6/soc.c | 31 ++++++++++++++++++++++++++----- arch/arm/include/asm/arch-mx6/crm_regs.h | 1 + 2 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 7b53bfd..dd94797 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -300,9 +300,17 @@ static void clear_mmdc_ch_mask(void) writel(reg, &mxc_ccm->ccdr); }

+#define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8

static void init_bandgap(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;

• struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
• struct fuse_bank *bank = &ocotp->bank[1];
• struct fuse_bank1_regs *fuse =

• (struct fuse_bank1_regs *)bank->fuse_regs;
  

• uint32_t val;
• /*
  • Ensure the bandgap has stabilized.
  */

@@ -315,13 +323,26 @@ static void init_bandgap(void) */ writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); /*

• * On i.MX6ULL, the LDO 1.2V bandgap voltage is 30mV higher. so set
  

• * VBGADJ bits to 2b'110 to adjust it.
  

• * On i.MX6ULL,we need to set VBGADJ bits according to the
  

• * REFTOP_TRIM[3:0] in fuse table
  

• *	000 - set REFTOP_VBGADJ[2:0] to 3b'110,
  

• *	110 - set REFTOP_VBGADJ[2:0] to 3b'000,
  

• *	001 - set REFTOP_VBGADJ[2:0] to 3b'001,
  

• *	010 - set REFTOP_VBGADJ[2:0] to 3b'010,
  

• *	011 - set REFTOP_VBGADJ[2:0] to 3b'011,
  

• *	100 - set REFTOP_VBGADJ[2:0] to 3b'100,
  

• *	101 - set REFTOP_VBGADJ[2:0] to 3b'101,
  

• *	111 - set REFTOP_VBGADJ[2:0] to 3b'111,
  

  */

• if (is_mx6ull())

• writel(BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ, &anatop->ana_misc0_set);
  

-}

• if (is_mx6ull()) {

• val = readl(&fuse->mem0);
  

• val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
  

• val &= 0x7;
  
  

• writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
  

•        &anatop->ana_misc0_set);
  

• }

+}

#ifdef CONFIG_MX6SL static void set_preclk_from_osc(void) diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index f74737a..29674ce 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -1272,6 +1272,7 @@ struct mxc_ccm_reg {

#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60 +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4

#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)

#define BP_PMU_MISC2_AUDIO_DIV_MSB 23

2.6.2