[PATCH 0/2] mvebu: ddr3: Armada-385 read ODT configuration
We've been doing some finer grained testing on our Armada-385 based platforms and found that on a read the ODT was kicking in 3 clock cycles too early.
It is likely this has gone unnoticed because prior to commit 247c80d6b8ad ("mv_ddr: ddr3: only use active chip-selects when tuning ODT") most systems would have ended up maxing out the read ODT values.
Marvell have been directing us to add 3 to the min/max read calculation and that seems to do the trick. Rather than just adding +3 I've adjusted the existing manipulations.
I've only got access to our x530 platform at the moment so it would be good if anyone with access to other Armada-385 could take this for a spin.
Chris Packham (2): mv_ddr: ddr3: Use correct bitmask for read sample delay mv_ddr: ddr3: Update {min,max}_read_sample calculation
drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
From: Chris Packham chris.packham@alliedtelesis.co.nz
In the Armada 385 functional spec (MV-S109094-00 Rev. C) the read sample delay fields are 5 bits wide. Use the correct bitmask of 0x1f when extracting the value.
Signed-off-by: Chris Packham chris.packham@alliedtelesis.co.nz
[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22] Signed-off-by: Chris Packham judge.packham@gmail.com ---
drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index df832ac6dce0..ce9a47fc2ce0 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -11,7 +11,7 @@ #define VREF_MAX_INDEX 7 #define MAX_VALUE (1024 - 1) #define MIN_VALUE (-MAX_VALUE) -#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0xf) +#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0x1f)
u32 ca_delay; int ddr3_tip_centr_skip_min_win_check = 0;
On 27.05.20 03:31, Chris Packham wrote:
From: Chris Packham chris.packham@alliedtelesis.co.nz
In the Armada 385 functional spec (MV-S109094-00 Rev. C) the read sample delay fields are 5 bits wide. Use the correct bitmask of 0x1f when extracting the value.
Signed-off-by: Chris Packham chris.packham@alliedtelesis.co.nz
[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22] Signed-off-by: Chris Packham judge.packham@gmail.com
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index df832ac6dce0..ce9a47fc2ce0 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -11,7 +11,7 @@ #define VREF_MAX_INDEX 7 #define MAX_VALUE (1024 - 1) #define MIN_VALUE (-MAX_VALUE) -#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0xf) +#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0x1f)
u32 ca_delay; int ddr3_tip_centr_skip_min_win_check = 0;
Viele Grüße, Stefan
From: Chris Packham chris.packham@alliedtelesis.co.nz
Measurements on actual hardware shown that the read ODT is early by 3 clocks. Adjust the calculation to avoid this.
Signed-off-by: Chris Packham chris.packham@alliedtelesis.co.nz
[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22] Signed-off-by: Chris Packham judge.packham@gmail.com ---
drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index ce9a47fc2ce0..58ffb205072e 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -91,8 +91,8 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) min_read_sample = read_sample[cs_num]; }
- min_read_sample = min_read_sample - 1; - max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1; + min_read_sample = min_read_sample + 2; + max_read_sample = max_read_sample + 7 + (max_phase + 1) / 2 + 1; if (min_read_sample >= 0xf) min_read_sample = 0xf; if (max_read_sample >= 0x1f)
Hi Chris,
On Wed, May 27 2020, Chris Packham wrote:
From: Chris Packham chris.packham@alliedtelesis.co.nz
Measurements on actual hardware shown that the read ODT is early by 3 clocks. Adjust the calculation to avoid this.
Signed-off-by: Chris Packham chris.packham@alliedtelesis.co.nz
[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22] Signed-off-by: Chris Packham judge.packham@gmail.com
Tested here on an Armada 385 based system. Running memtester for more than an hour.
Tested-by: Baruch Siach baruch@tkos.co.il
Thanks, baruch
drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index ce9a47fc2ce0..58ffb205072e 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -91,8 +91,8 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) min_read_sample = read_sample[cs_num]; }
- min_read_sample = min_read_sample - 1;
- max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1;
- min_read_sample = min_read_sample + 2;
- max_read_sample = max_read_sample + 7 + (max_phase + 1) / 2 + 1; if (min_read_sample >= 0xf) min_read_sample = 0xf; if (max_read_sample >= 0x1f)
On 27.05.20 03:31, Chris Packham wrote:
From: Chris Packham chris.packham@alliedtelesis.co.nz
Measurements on actual hardware shown that the read ODT is early by 3 clocks. Adjust the calculation to avoid this.
Signed-off-by: Chris Packham chris.packham@alliedtelesis.co.nz
[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22] Signed-off-by: Chris Packham judge.packham@gmail.com
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index ce9a47fc2ce0..58ffb205072e 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -91,8 +91,8 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) min_read_sample = read_sample[cs_num]; }
- min_read_sample = min_read_sample - 1;
- max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1;
- min_read_sample = min_read_sample + 2;
- max_read_sample = max_read_sample + 7 + (max_phase + 1) / 2 + 1; if (min_read_sample >= 0xf) min_read_sample = 0xf; if (max_read_sample >= 0x1f)
Viele Grüße, Stefan
participants (3)
-
Baruch Siach -
Chris Packham -
Stefan Roese