[U-Boot] [PATCH 0/7] Ethernet bringup patchset for DRA7xx EVM
This patch series brings up the CPSW ethernet in DRA7xx EVM and it is based on the master branch on git://git.denx.de/u-boot.git
This patch is also tested with basic boot of Omap 5 and tftp download test with AM335x EVM.
Lokesh Vutla (1): ARM: DRA7xx: Lock DPLL_GMAC
Mugunthan V N (6): drivers: net: cpsw: remove hard coding bd ram for cpsw drivers: net: cpsw: Enable statistics for all port ARM: DRA7xx: Enable GMAC clock control ARM: DRA7xx: Add CPSW support to DRA7xx EVM ARM: DRA7xx: Add CPSW and MDIO pinmux support ARM: DRA7xx: Enable CPSW Ethernet support
arch/arm/cpu/armv7/omap-common/clocks-common.c | 18 +++ arch/arm/cpu/armv7/omap5/hw_data.c | 18 ++- arch/arm/cpu/armv7/omap5/prcm-regs.c | 7 ++ arch/arm/include/asm/arch-omap5/cpu.h | 6 + arch/arm/include/asm/arch-omap5/omap.h | 26 ++++ arch/arm/include/asm/omap_common.h | 10 ++ board/ti/am335x/board.c | 1 + board/ti/dra7xx/evm.c | 150 +++++++++++++++++++++++- board/ti/dra7xx/mux_data.h | 14 +++ board/ti/ti814x/evm.c | 1 + drivers/net/cpsw.c | 5 +- include/configs/dra7xx_evm.h | 19 +++ include/cpsw.h | 1 + 13 files changed, 267 insertions(+), 9 deletions(-)
BD ram address may vary in various SOC, so removing the hardcoding and passing the same information through platform data
Signed-off-by: Mugunthan V N mugunthanvnm@ti.com --- board/ti/am335x/board.c | 1 + board/ti/ti814x/evm.c | 1 + drivers/net/cpsw.c | 4 +--- include/cpsw.h | 1 + 4 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index fdbe26c..53981d2 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -443,6 +443,7 @@ static struct cpsw_platform_data cpsw_data = { .ale_entries = 1024, .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, .mac_control = (1 << 5), .control = cpsw_control, .host_port_num = 0, diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index 6ad3dd8..0a05571 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -215,6 +215,7 @@ static struct cpsw_platform_data cpsw_data = { .ale_entries = 1024, .host_port_reg_ofs = 0x28, .hw_stats_reg_ofs = 0x400, + .bd_ram_ofs = 0x2000, .mac_control = (1 << 5), .control = cpsw_control, .host_port_num = 0, diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 379b679..dc0a2be 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -51,8 +51,6 @@ #define CPDMA_RXCP_VER1 0x160 #define CPDMA_RXCP_VER2 0x260
-#define CPDMA_RAM_ADDR 0x4a102000 - /* Descriptor mode bits */ #define CPDMA_DESC_SOP BIT(31) #define CPDMA_DESC_EOP BIT(30) @@ -984,12 +982,12 @@ int cpsw_register(struct cpsw_platform_data *data) return -ENOMEM; }
- priv->descs = (void *)CPDMA_RAM_ADDR; priv->host_port = data->host_port_num; priv->regs = regs; priv->host_port_regs = regs + data->host_port_reg_ofs; priv->dma_regs = regs + data->cpdma_reg_ofs; priv->ale_regs = regs + data->ale_reg_ofs; + priv->descs = (void *)regs + data->bd_ram_ofs;
int idx = 0;
diff --git a/include/cpsw.h b/include/cpsw.h index 296b0e5..743cb96 100644 --- a/include/cpsw.h +++ b/include/cpsw.h @@ -39,6 +39,7 @@ struct cpsw_platform_data { int ale_entries; /* ale table size */ u32 host_port_reg_ofs; /* cpdma host port registers */ u32 hw_stats_reg_ofs; /* cpsw hw stats counters */ + u32 bd_ram_ofs; /* Buffer Descriptor RAM offset */ u32 mac_control; struct cpsw_slave_data *slave_data; void (*control)(int enabled);
Enable hardware statistics for all ports, enabling only to host port is useless
Signed-off-by: Mugunthan V N mugunthanvnm@ti.com --- drivers/net/cpsw.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index dc0a2be..f1e9f72 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -772,6 +772,7 @@ static int cpsw_init(struct eth_device *dev, bd_t *bis)
/* enable statistics collection only on the host port */ __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); + __raw_writel(0x7, &priv->regs->stat_port_en);
cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
From: Lokesh Vutla lokeshvutla@ti.com
Locking DPLL_GMAC
[mugunthanvnm@ti.com:Configure only if CPSW is selected]
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Mugunthan V N mugunthanvnm@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 18 ++++++++++++++++++ arch/arm/cpu/armv7/omap5/hw_data.c | 11 +++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + arch/arm/include/asm/omap_common.h | 2 ++ 4 files changed, 32 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index ef23127..e26d741 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -212,6 +212,18 @@ static const struct dpll_params *get_ddr_dpll_params return &dpll_data->ddr[sysclk_ind]; }
+#ifdef CONFIG_DRIVER_TI_CPSW +static const struct dpll_params *get_gmac_dpll_params + (struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + + if (!dpll_data->gmac) + return NULL; + return &dpll_data->gmac[sysclk_ind]; +} +#endif + static void do_setup_dpll(u32 const base, const struct dpll_params *params, u8 lock, char *dpll) { @@ -414,6 +426,12 @@ static void setup_dplls(void) params = get_ddr_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy, params, DPLL_LOCK, "ddr"); + +#ifdef CONFIG_DRIVER_TI_CPSW + params = get_gmac_dpll_params(*dplls_data); + do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params, + DPLL_LOCK, "gmac"); +#endif }
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 56cf1f8..c909dcd 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -263,6 +263,16 @@ static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ };
+static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { + {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */ + {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */ + {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + struct dplls omap5_dplls_es1 = { .mpu = mpu_dpll_params_800mhz, .core = core_dpll_params_2128mhz_ddr532, @@ -299,6 +309,7 @@ struct dplls dra7xx_dplls = { .iva = iva_dpll_params_2330mhz_dra7xx, .usb = usb_dpll_params_1920mhz, .ddr = ddr_dpll_params_2128mhz, + .gmac = gmac_dpll_params_2000mhz, };
struct pmic_data palmas = { diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index e839ff5..7793763 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -814,6 +814,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c, .cm_clkmode_dpll_dsp = 0x4a005234, .cm_shadow_freq_config1 = 0x4a005260, + .cm_clkmode_dpll_gmac = 0x4a0052a8,
/* cm1.mpu */ .cm_mpu_mpu_clkctrl = 0x4a005320, diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 0dbe81b..8b4201b 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -89,6 +89,7 @@ struct prcm_regs { u32 cm_ssc_deltamstep_dpll_ddrphy; u32 cm_clkmode_dpll_dsp; u32 cm_shadow_freq_config1; + u32 cm_clkmode_dpll_gmac; u32 cm_mpu_mpu_clkctrl;
/* cm1.dsp */ @@ -499,6 +500,7 @@ struct dplls { const struct dpll_params *iva; const struct dpll_params *usb; const struct dpll_params *ddr; + const struct dpll_params *gmac; };
struct pmic_data {
Enabling CPSW module by enabling GMAC clock control
Signed-off-by: Mugunthan V N mugunthanvnm@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 7 ++++++- arch/arm/cpu/armv7/omap5/prcm-regs.c | 2 ++ arch/arm/include/asm/omap_common.h | 4 ++++ 3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index c909dcd..f659610 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -409,6 +409,9 @@ void enable_basic_clocks(void) (*prcm)->cm_l3init_clkstctrl, (*prcm)->cm_memif_clkstctrl, (*prcm)->cm_l4cfg_clkstctrl, +#ifdef CONFIG_DRIVER_TI_CPSW + (*prcm)->cm_gmac_clkstctrl, +#endif 0 };
@@ -434,6 +437,9 @@ void enable_basic_clocks(void) (*prcm)->cm_wkup_wdtimer2_clkctrl, (*prcm)->cm_l4per_uart3_clkctrl, (*prcm)->cm_l4per_i2c1_clkctrl, +#ifdef CONFIG_DRIVER_TI_CPSW + (*prcm)->cm_gmac_gmac_clkctrl, +#endif 0 };
@@ -490,7 +496,6 @@ void enable_basic_uboot_clocks(void) (*prcm)->cm_l3init_fsusb_clkctrl, 0 }; - do_enable_clocks(clk_domains_essential, clk_modules_hw_auto_essential, clk_modules_explicit_en_essential, diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 7793763..1b4ab84 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -912,6 +912,8 @@ struct prcm_regs const dra7xx_prcm = { .cm_l3init_hsusbhost_clkctrl = 0x4a009340, .cm_l3init_hsusbotg_clkctrl = 0x4a009348, .cm_l3init_hsusbtll_clkctrl = 0x4a009350, + .cm_gmac_clkstctrl = 0x4a0093c0, + .cm_gmac_gmac_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
/* cm2.l4per */ diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 8b4201b..4a4a769 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -356,6 +356,10 @@ struct prcm_regs { /* SCRM stuff, used by some boards */ u32 scrm_auxclk0; u32 scrm_auxclk1; + + /* GMAC Clk Ctrl */ + u32 cm_gmac_gmac_clkctrl; + u32 cm_gmac_clkstctrl; };
struct omap_sys_ctrl_regs {
Adding support for CPSW Ethernet support found in DRA7xx EVM
Signed-off-by: Mugunthan V N mugunthanvnm@ti.com --- arch/arm/cpu/armv7/omap5/prcm-regs.c | 4 + arch/arm/include/asm/arch-omap5/cpu.h | 6 ++ arch/arm/include/asm/arch-omap5/omap.h | 26 ++++++ arch/arm/include/asm/omap_common.h | 4 + board/ti/dra7xx/evm.c | 150 ++++++++++++++++++++++++++++++-- 5 files changed, 185 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 1b4ab84..29129f6 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -394,6 +394,10 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_status = 0x4A002134, + .control_core_mac_id_0_lo = 0x4A002514, + .control_core_mac_id_0_hi = 0x4A002518, + .control_core_mac_id_1_lo = 0x4A00251C, + .control_core_mac_id_1_hi = 0x4A002520, .control_core_mmr_lock1 = 0x4A002540, .control_core_mmr_lock2 = 0x4A002544, .control_core_mmr_lock3 = 0x4A002548, diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 4753f46..347f104 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -116,6 +116,8 @@ struct watchdog { #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */
+#define BIT(x) (1 << (x)) + #define WD_UNLOCK1 0xAAAA #define WD_UNLOCK2 0x5555
@@ -175,4 +177,8 @@ struct watchdog { #define PRM_RSTST (PRM_DEVICE_BASE + 0x4) #define PRM_RSTST_WARM_RESET_MASK 0x7FEA
+/* DRA7XX CPSW Config space */ +#define CPSW_BASE 0x48484000 +#define CPSW_MDIO_BASE 0x48485000 + #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 5e6d82e..929ee67 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -208,6 +208,27 @@ struct s32ktimer { #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0)
+/* IO Delay module defines */ +#define CFG_IO_DELAY_BASE 0x4844A000 +#define CFG_IO_DELAY_LOCK (CFG_IO_DELAY_BASE + 0x02C) + +/* CPSW IO Delay registers*/ +#define CFG_RGMII0_TXCTL (CFG_IO_DELAY_BASE + 0x74C) +#define CFG_RGMII0_TXD0 (CFG_IO_DELAY_BASE + 0x758) +#define CFG_RGMII0_TXD1 (CFG_IO_DELAY_BASE + 0x764) +#define CFG_RGMII0_TXD2 (CFG_IO_DELAY_BASE + 0x770) +#define CFG_RGMII0_TXD3 (CFG_IO_DELAY_BASE + 0x77C) +#define CFG_VIN2A_D13 (CFG_IO_DELAY_BASE + 0xA7C) +#define CFG_VIN2A_D17 (CFG_IO_DELAY_BASE + 0xAAC) +#define CFG_VIN2A_D16 (CFG_IO_DELAY_BASE + 0xAA0) +#define CFG_VIN2A_D15 (CFG_IO_DELAY_BASE + 0xA94) +#define CFG_VIN2A_D14 (CFG_IO_DELAY_BASE + 0xA88) + +#define CFG_IO_DELAY_UNLOCK_KEY 0x0000AAAA +#define CFG_IO_DELAY_LOCK_KEY 0x0000AAAB +#define CFG_IO_DELAY_ACCESS_PATTERN 0x00029000 +#define CFG_IO_DELAY_LOCK_MASK 0x400 + #ifndef __ASSEMBLY__ struct srcomp_params { s8 divide_factor; @@ -224,5 +245,10 @@ struct ctrl_ioregs { u32 ctrl_emif_sdram_config_ext; u32 ctrl_ddr_ctrl_ext_0; }; + +struct io_delay { + u32 addr; + u32 dly; +}; #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 4a4a769..75198cf 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -364,6 +364,10 @@ struct prcm_regs {
struct omap_sys_ctrl_regs { u32 control_status; + u32 control_core_mac_id_0_lo; + u32 control_core_mac_id_0_hi; + u32 control_core_mac_id_1_lo; + u32 control_core_mac_id_1_hi; u32 control_std_fuse_opp_vdd_mpu_2; u32 control_core_mmr_lock1; u32 control_core_mmr_lock2; diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index bf7e091..4cbd162 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -39,12 +39,53 @@ #include <asm/ehci-omap.h> #endif
+#ifdef CONFIG_DRIVER_TI_CPSW +#include <cpsw.h> +#endif + DECLARE_GLOBAL_DATA_PTR;
const struct omap_sysinfo sysinfo = { "Board: DRA7xx\n" };
+/* + * Adjust I/O delays on the Tx control and data lines of each MAC port. This + * is a workaround in order to work properly with the DP83865 PHYs on the EVM. + * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we + * essentially need to counteract the DRA7xx internal delay, and we do this + * by delaying the control and data lines. If not using this PHY, you probably + * don't need to do this stuff! + */ +static void dra7xx_adj_io_delay(const struct io_delay *io_dly) +{ + int i = 0; + u32 reg_val; + u32 delta; + u32 coarse; + u32 fine; + + writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); + + while(io_dly[i].addr) { + writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, + io_dly[i].addr); + delta = io_dly[i].dly; + reg_val = readl(io_dly[i].addr) & 0x3ff; + coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); + coarse = (coarse > 0x1F) ? (0x1F) : (coarse); + fine = (reg_val & 0x1F) + (delta & 0x1F); + fine = (fine > 0x1F) ? (0x1F) : (fine); + reg_val = CFG_IO_DELAY_ACCESS_PATTERN | + CFG_IO_DELAY_LOCK_MASK | + ((coarse << 5) | (fine)); + writel(reg_val, io_dly[i].addr); + i++; + } + + writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); +} + /** * @brief board_init * @@ -58,11 +99,6 @@ int board_init(void) return 0; }
-int board_eth_init(bd_t *bis) -{ - return 0; -} - /** * @brief misc_init_r - Configure EVM board specific configurations * such as power configurations, ethernet initialization as phase2 of @@ -101,3 +137,107 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +#ifdef CONFIG_DRIVER_TI_CPSW + +/* Delay value to add to calibrated value */ +#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) +#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) +#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) +#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) + +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int ret; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + uint32_t ctrl_val; + const struct io_delay io_dly[] = { + {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, + {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, + {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, + {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, + {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, + {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, + {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, + {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, + {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, + {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, + {0} + }; + + /* Adjust IO delay for RGMII tx path */ + dra7xx_adj_io_delay(io_dly); + + /* try reading mac address from efuse */ + mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = mac_lo & 0xFF; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = (mac_lo & 0xFF0000) >> 16; + + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC\n"); + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); + ctrl_val |= 0x22; + writel(ctrl_val, (*ctrl)->control_core_control_io1); + + ret = cpsw_register(&cpsw_data); + if (ret < 0) + printf("Error %d registering CPSW switch\n", ret); + + return ret; +} +#endif
Adding CPSW Slave 0 and MDIO pinmux support for DRA7xx EVM
Signed-off-by: Mugunthan V N mugunthanvnm@ti.com --- board/ti/dra7xx/mux_data.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 338a241..b63fc36 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -53,5 +53,19 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */ {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ + {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ + {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ + {RGMII0_TXC, (M0) }, + {RGMII0_TXCTL, (M0) }, + {RGMII0_TXD3, (M0) }, + {RGMII0_TXD2, (M0) }, + {RGMII0_TXD1, (M0) }, + {RGMII0_TXD0, (M0) }, + {RGMII0_RXC, (IEN | M0) }, + {RGMII0_RXCTL, (IEN | M0) }, + {RGMII0_RXD3, (IEN | M0) }, + {RGMII0_RXD2, (IEN | M0) }, + {RGMII0_RXD1, (IEN | M0) }, + {RGMII0_RXD0, (IEN | M0) }, }; #endif /* _MUX_DATA_DRA7XX_H_ */
Enabling CPSW Ethernet support in DRA7xx EVM.
Signed-off-by: Mugunthan V N mugunthanvnm@ti.com --- include/configs/dra7xx_evm.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index c11f005..ed3aa43 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -44,4 +44,23 @@
#define CONSOLEDEV "ttyO0"
+/* CPSW Ethernet */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 2 + #endif /* __CONFIG_DRA7XX_EVM_H */
On Mon, Jul 08, 2013 at 04:04:36PM +0530, Mugunthan V N wrote:
This patch series brings up the CPSW ethernet in DRA7xx EVM and it is based on the master branch on git://git.denx.de/u-boot.git
This patch is also tested with basic boot of Omap 5 and tftp download test with AM335x EVM.
Lokesh Vutla (1): ARM: DRA7xx: Lock DPLL_GMAC
Mugunthan V N (6): drivers: net: cpsw: remove hard coding bd ram for cpsw drivers: net: cpsw: Enable statistics for all port ARM: DRA7xx: Enable GMAC clock control ARM: DRA7xx: Add CPSW support to DRA7xx EVM ARM: DRA7xx: Add CPSW and MDIO pinmux support ARM: DRA7xx: Enable CPSW Ethernet support
arch/arm/cpu/armv7/omap-common/clocks-common.c | 18 +++ arch/arm/cpu/armv7/omap5/hw_data.c | 18 ++- arch/arm/cpu/armv7/omap5/prcm-regs.c | 7 ++ arch/arm/include/asm/arch-omap5/cpu.h | 6 + arch/arm/include/asm/arch-omap5/omap.h | 26 ++++ arch/arm/include/asm/omap_common.h | 10 ++ board/ti/am335x/board.c | 1 + board/ti/dra7xx/evm.c | 150 +++++++++++++++++++++++- board/ti/dra7xx/mux_data.h | 14 +++ board/ti/ti814x/evm.c | 1 + drivers/net/cpsw.c | 5 +- include/configs/dra7xx_evm.h | 19 +++ include/cpsw.h | 1 + 13 files changed, 267 insertions(+), 9 deletions(-)
Applied to u-boot-ti/master, thanks!
participants (2)
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Mugunthan V N -
Tom Rini