[U-Boot] [PATCH 1/4] fsl-ddr: Fix power-down timing settings
From: Dave Liu daveliu@freescale.com
1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but It should be set to tXP parameter, tXP=max(3CK, 7.5ns) 2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter We are setting the mode register MR0[A12]='1'
Signed-off-by: Dave Liu daveliu@freescale.com --- cpu/mpc8xxx/ddr/ctrl_regs.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 2505041..a92f1a3 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -188,12 +188,13 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) * The DDR3 spec has not tXARD, * we use the tXP instead of it. * tXP=max(3nCK, 7.5ns) for DDR3. - * we use the tXP=6 * spec has not the tAXPD, we use * tAXPD=8, need design to confirm. */ - act_pd_exit_mclk = 6; - pre_pd_exit_mclk = 6; + int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ + act_pd_exit_mclk = picos_to_mclk(tXP); + /* Mode register MR0[A12] is '1' - fast exit */ + pre_pd_exit_mclk = act_pd_exit_mclk; taxpd_mclk = 8; tmrd_mclk = 4; #else /* CONFIG_FSL_DDR2 */
From: Dave Liu daveliu@freescale.com
add the override for write leveling sampling and start time according to specific board.
Signed-off-by: Dave Liu daveliu@freescale.com --- cpu/mpc8xxx/ddr/ctrl_regs.c | 20 ++++++++++++++------ cpu/mpc8xxx/ddr/options.c | 1 + include/asm-ppc/fsl_ddr_sdram.h | 7 ++++++- 3 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index a92f1a3..5e37ca6 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1002,8 +1002,8 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) }
/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ -static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, - unsigned int wrlvl_en) +static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, + const memctl_options_t *popts) { /* * First DQS pulse rising edge after margining mode @@ -1030,8 +1030,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, /* tWL_DQSEN min = 25 nCK, we set it 32 */ wrlvl_dqsen = 0x5; /* - * Write leveling sample time at least need 14 clocks - * due to tWLO = 9, we set it 15 clocks + * Write leveling sample time at least need 6 clocks + * higher than tWLO to allow enough time for progagation + * delay and sampling the prime data bits. */ wrlvl_smpl = 0xf; /* @@ -1044,9 +1045,16 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, * Write leveling start time * The value use for the DQS_ADJUST for the first sample * when write leveling is enabled. - * we set it 1 clock delay */ wrlvl_start = 0x8; + /* + * Override the write leveling sample and start time + * according to specific board + */ + if (popts->wrlvl_override) { + wrlvl_smpl = popts->wrlvl_sample; + wrlvl_start = popts->wrlvl_start; + } }
ddr->ddr_wrlvl_cntl = (0 @@ -1332,7 +1340,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_timing_cfg_5(ddr);
set_ddr_zq_cntl(ddr, zq_en); - set_ddr_wrlvl_cntl(ddr, wrlvl_en); + set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
set_ddr_sr_cntr(ddr, sr_it);
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c index 2e030c1..3dcd33d 100644 --- a/cpu/mpc8xxx/ddr/options.c +++ b/cpu/mpc8xxx/ddr/options.c @@ -198,6 +198,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * meet the tQDSS under different loading. */ popts->wrlvl_en = 1; + popts->wrlvl_override = 0; #endif
/* diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 69b857b..15ab675 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -177,6 +177,11 @@ typedef struct memctl_options_s { unsigned int clk_adjust; /* */ unsigned int cpo_override; unsigned int write_data_delay; /* DQS adjust */ + + unsigned int wrlvl_override; + unsigned int wrlvl_sample; /* Write leveling */ + unsigned int wrlvl_start; + unsigned int half_strength_driver_enable; unsigned int twoT_en; unsigned int threeT_en;
From: Dave Liu daveliu@freescale.com
It may be different settings of Rtt_nom and Rtt_WR for different boards, adding the override provide the capability.
Signed-off-by: Dave Liu daveliu@freescale.com --- cpu/mpc8xxx/ddr/ctrl_regs.c | 10 +++++++--- include/asm-ppc/fsl_ddr_sdram.h | 1 + 2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 5e37ca6..3be7e22 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -576,18 +576,22 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, }
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ -static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr) +static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) { unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
#if defined(CONFIG_FSL_DDR3) - unsigned int rtt_wr = 2; /* 120 ohm Rtt_WR */ + unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ unsigned int srt = 0; /* self-refresh temerature, normal range */ unsigned int asr = 0; /* auto self-refresh disable */ unsigned int cwl = compute_cas_write_latency() - 5; unsigned int pasr = 0; /* partial array self refresh disable */
+ if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + esdmode2 = (0 | ((rtt_wr & 0x3) << 9) | ((srt & 0x1) << 7) @@ -1330,7 +1334,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_sdram_cfg_2(ddr, popts); set_ddr_sdram_mode(ddr, popts, common_dimm, cas_latency, additive_latency); - set_ddr_sdram_mode_2(ddr); + set_ddr_sdram_mode_2(ddr, popts); set_ddr_sdram_interval(ddr, popts, common_dimm); set_ddr_data_init(ddr); set_ddr_sdram_clk_cntl(ddr, popts); diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 15ab675..3216a50 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -192,6 +192,7 @@ typedef struct memctl_options_s { /* Rtt impedance */ unsigned int rtt_override; /* rtt_override enable */ unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ + unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
/* Automatic self refresh */ unsigned int auto_self_refresh_en;
From: Dave Liu daveliu@freescale.com
In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register.
Signed-off-by: Dave Liu daveliu@freescale.com --- cpu/mpc8xxx/ddr/ctrl_regs.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 3be7e22..adc4f6e 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1197,7 +1197,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, /* Don't set up boundaries for other CS * other than CS0, if bank interleaving * is enabled and not CS2+CS3 interleaved. + * But we need to set the ODT_RD_CFG and + * ODT_WR_CFG for CS1_CONFIG here. */ + set_csn_config(i, ddr, popts, dimm_params); break; }
On Dec 16, 2009, at 10:24 AM, Kumar Gala wrote:
From: Dave Liu daveliu@freescale.com
In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register.
Signed-off-by: Dave Liu daveliu@freescale.com
cpu/mpc8xxx/ddr/ctrl_regs.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
applied to 85xx
- k
On Dec 16, 2009, at 10:24 AM, Kumar Gala wrote:
From: Dave Liu daveliu@freescale.com
It may be different settings of Rtt_nom and Rtt_WR for different boards, adding the override provide the capability.
Signed-off-by: Dave Liu daveliu@freescale.com
cpu/mpc8xxx/ddr/ctrl_regs.c | 10 +++++++--- include/asm-ppc/fsl_ddr_sdram.h | 1 + 2 files changed, 8 insertions(+), 3 deletions(-)
applied to 85xx
- k
Dear Kumar Gala,
In message 1260980679-13236-3-git-send-email-galak@kernel.crashing.org you wrote:
From: Dave Liu daveliu@freescale.com
It may be different settings of Rtt_nom and Rtt_WR for different boards, adding the override provide the capability.
I don't understand what this commit message is supposed to say. Can you please explain what this commit is supposed to do?
Best regards,
Wolfgang Denk
On Dec 17, 2009, at 3:20 PM, Wolfgang Denk wrote:
Dear Kumar Gala,
In message 1260980679-13236-3-git-send-email-galak@kernel.crashing.org you wrote:
From: Dave Liu daveliu@freescale.com
It may be different settings of Rtt_nom and Rtt_WR for different boards, adding the override provide the capability.
I don't understand what this commit message is supposed to say. Can you please explain what this commit is supposed to do?
I'll rewrite it. Does the following make sense:
Different boards may require different settings of Dynamic ODT (Rtt_Wr). We provide a means to allow the board specific code to provide its own value of Rtt_wr.
- k
On Dec 16, 2009, at 10:24 AM, Kumar Gala wrote:
From: Dave Liu daveliu@freescale.com
add the override for write leveling sampling and start time according to specific board.
Signed-off-by: Dave Liu daveliu@freescale.com
cpu/mpc8xxx/ddr/ctrl_regs.c | 20 ++++++++++++++------ cpu/mpc8xxx/ddr/options.c | 1 + include/asm-ppc/fsl_ddr_sdram.h | 7 ++++++- 3 files changed, 21 insertions(+), 7 deletions(-)
applied to 85xx
- k
On Dec 16, 2009, at 10:24 AM, Kumar Gala wrote:
From: Dave Liu daveliu@freescale.com
- TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
It should be set to tXP parameter, tXP=max(3CK, 7.5ns) 2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter We are setting the mode register MR0[A12]='1'
Signed-off-by: Dave Liu daveliu@freescale.com
cpu/mpc8xxx/ddr/ctrl_regs.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-)
applied to 85xx
- k
participants (2)
-
Kumar Gala -
Wolfgang Denk