[U-Boot] [PATCH] am335x: cpsw: optimize cpsw_recv to increase network performance
In 48ec5291, only TX path was optimized; this does the same also for RX path. This results in huge increase of TFTP throughput on custom am3352 board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer timeouts.
Signed-off-by: Vladimir Koutny vladimir.koutny@streamunlimited.com Cc: Mugunthan V N mugunthanvnm@ti.com Cc: Joe Hershberger joe.hershberger@gmail.com Cc: Tom Rini trini@ti.com --- drivers/net/cpsw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 39240d9..50167aa 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -914,7 +914,7 @@ static int cpsw_recv(struct eth_device *dev) void *buffer; int len;
- cpsw_update_link(priv); + cpsw_check_link(priv);
while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) { invalidate_dcache_range((unsigned long)buffer, -- 1.7.10.4
On Thursday 28 November 2013 03:08 PM, Vladimir Koutny wrote:
In 48ec5291, only TX path was optimized; this does the same also for RX path. This results in huge increase of TFTP throughput on custom am3352 board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer timeouts.
Signed-off-by: Vladimir Koutny vladimir.koutny@streamunlimited.com Cc: Mugunthan V N mugunthanvnm@ti.com Cc: Joe Hershberger joe.hershberger@gmail.com Cc: Tom Rini trini@ti.com
Acked-by: Mugunthan V N mugunthanvnm@ti.com
Regards Mugunthan V N
On Thu, Nov 28, 2013 at 10:38:40AM +0100, Vladimir Koutny wrote:
In 48ec5291, only TX path was optimized; this does the same also for RX path. This results in huge increase of TFTP throughput on custom am3352 board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer timeouts.
Signed-off-by: Vladimir Koutny vladimir.koutny@streamunlimited.com Cc: Mugunthan V N mugunthanvnm@ti.com Cc: Joe Hershberger joe.hershberger@gmail.com Cc: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
On 04.12.2013 23:05, Tom Rini wrote:
On Thu, Nov 28, 2013 at 10:38:40AM +0100, Vladimir Koutny wrote:
In 48ec5291, only TX path was optimized; this does the same also for RX path. This results in huge increase of TFTP throughput on custom am3352 board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer timeouts.
Signed-off-by: Vladimir Koutny vladimir.koutny@streamunlimited.com Cc: Mugunthan V N mugunthanvnm@ti.com Cc: Joe Hershberger joe.hershberger@gmail.com Cc: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
I just tested on dxr2 (AM3352 based board) with latest mainline U-Boot. And the network performance is a bit better. But not as good as yours. Here my numbers:
Without this patch: ~400 KiB/s With this patch: ~570 KiB/s
Any ideas what might be missing on my platform? Why the speed is not as good?
Thanks, Stefan
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On 12/12/2013 03:34 AM, Stefan Roese wrote:
On 04.12.2013 23:05, Tom Rini wrote:
On Thu, Nov 28, 2013 at 10:38:40AM +0100, Vladimir Koutny wrote:
In 48ec5291, only TX path was optimized; this does the same also for RX path. This results in huge increase of TFTP throughput on custom am3352 board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer timeouts.
Signed-off-by: Vladimir Koutny vladimir.koutny@streamunlimited.com Cc: Mugunthan V N mugunthanvnm@ti.com Cc: Joe Hershberger joe.hershberger@gmail.com Cc: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
I just tested on dxr2 (AM3352 based board) with latest mainline U-Boot. And the network performance is a bit better. But not as good as yours. Here my numbers:
Without this patch: ~400 KiB/s With this patch: ~570 KiB/s
Any ideas what might be missing on my platform? Why the speed is not as good?
I only got a small increase as well until I also grabbed the dcache enable patch. I need to find some time today to clean out the TI queue again.
- -- Tom
On 12/12/13 13:37, Tom Rini wrote:
On 12/12/2013 03:34 AM, Stefan Roese wrote:
I just tested on dxr2 (AM3352 based board) with latest mainline U-Boot. And the network performance is a bit better. But not as good as yours. Here my numbers:
Without this patch: ~400 KiB/s With this patch: ~570 KiB/s
Any ideas what might be missing on my platform? Why the speed is not as good?
I only got a small increase as well until I also grabbed the dcache enable patch. I need to find some time today to clean out the TI queue again.
Good point - indeed I had I/D caches enabled for other reasons already (md5/sha1 caclulations, ..)
Regards, Vlado
On 12.12.2013 14:20, Vladimir Koutny wrote:
On 12/12/13 13:37, Tom Rini wrote:
On 12/12/2013 03:34 AM, Stefan Roese wrote:
I just tested on dxr2 (AM3352 based board) with latest mainline U-Boot. And the network performance is a bit better. But not as good as yours. Here my numbers:
Without this patch: ~400 KiB/s With this patch: ~570 KiB/s
Any ideas what might be missing on my platform? Why the speed is not as good?
I only got a small increase as well until I also grabbed the dcache enable patch. I need to find some time today to clean out the TI queue again.
Good point - indeed I had I/D caches enabled for other reasons already (md5/sha1 caclulations, ..)
Hmmm. I expected that caches are enabled already. Since I didn't see any "D-Cache disabled message" in the startup log.
If this is not that case, then such cache support would be greatly appreciated. :)
Thanks, Stefan
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On 12/12/2013 08:24 AM, Stefan Roese wrote:
On 12.12.2013 14:20, Vladimir Koutny wrote:
On 12/12/13 13:37, Tom Rini wrote:
On 12/12/2013 03:34 AM, Stefan Roese wrote:
I just tested on dxr2 (AM3352 based board) with latest mainline U-Boot. And the network performance is a bit better. But not as good as yours. Here my numbers:
Without this patch: ~400 KiB/s With this patch: ~570 KiB/s
Any ideas what might be missing on my platform? Why the speed is not as good?
I only got a small increase as well until I also grabbed the dcache enable patch. I need to find some time today to clean out the TI queue again.
Good point - indeed I had I/D caches enabled for other reasons already (md5/sha1 caclulations, ..)
Hmmm. I expected that caches are enabled already. Since I didn't see any "D-Cache disabled message" in the startup log.
If this is not that case, then such cache support would be greatly appreciated. :)
Check your logs? Unless you've also got a patched tree you should see "WARNING: Caches disabled" or so, because, yeah, oops, am335x got in with caches disabled, and then I forgot about it.
- -- Tom
On 12.12.2013 14:39, Tom Rini wrote:
Good point - indeed I had I/D caches enabled for other reasons already (md5/sha1 caclulations, ..)
Hmmm. I expected that caches are enabled already. Since I didn't see any "D-Cache disabled message" in the startup log.
If this is not that case, then such cache support would be greatly appreciated. :)
Check your logs? Unless you've also got a patched tree you should see "WARNING: Caches disabled" or so, because, yeah, oops, am335x got in with caches disabled, and then I forgot about it.
This is what I got currently (mainline):
U-Boot 2014.01-rc1-00165-ge03c76c (Dec 12 2013 - 09:26:20)
I2C: ready DRAM: 128 MiB Enable d-cache DFU USB: VID = 0x 908, PID = 0x 2d2 NAND: 256 MiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 Net: cpsw
So caches seem to be enabled, right? Or is i-cache still missing?
Thanks, Stefan
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On 12/12/2013 08:45 AM, Stefan Roese wrote:
On 12.12.2013 14:39, Tom Rini wrote:
Good point - indeed I had I/D caches enabled for other reasons already (md5/sha1 caclulations, ..)
Hmmm. I expected that caches are enabled already. Since I didn't see any "D-Cache disabled message" in the startup log.
If this is not that case, then such cache support would be greatly appreciated. :)
Check your logs? Unless you've also got a patched tree you should see "WARNING: Caches disabled" or so, because, yeah, oops, am335x got in with caches disabled, and then I forgot about it.
This is what I got currently (mainline):
U-Boot 2014.01-rc1-00165-ge03c76c (Dec 12 2013 - 09:26:20)
I2C: ready DRAM: 128 MiB Enable d-cache DFU USB: VID = 0x 908, PID = 0x 2d2 NAND: 256 MiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 Net: cpsw
So caches seem to be enabled, right? Or is i-cache still missing?
Ug, the siemens board code enables dcache on its own. Need to take care of that. That said, it's the same one-liner the rest of the patches do, sans printf. I think you may need to do more investigation.
- -- Tom
On 12.12.2013 14:49, Tom Rini wrote:
Check your logs? Unless you've also got a patched tree you should see "WARNING: Caches disabled" or so, because, yeah, oops, am335x got in with caches disabled, and then I forgot about it.
This is what I got currently (mainline):
U-Boot 2014.01-rc1-00165-ge03c76c (Dec 12 2013 - 09:26:20)
I2C: ready DRAM: 128 MiB Enable d-cache DFU USB: VID = 0x 908, PID = 0x 2d2 NAND: 256 MiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 Net: cpsw
So caches seem to be enabled, right? Or is i-cache still missing?
Ug, the siemens board code enables dcache on its own. Need to take care of that. That said, it's the same one-liner the rest of the patches do, sans printf. I think you may need to do more investigation.
Yes, will do (once the issue gets more pressing).
Thanks, Stefan
participants (4)
-
Mugunthan V N -
Stefan Roese -
Tom Rini -
Vladimir Koutny