[U-Boot] [PATCH 1/9] powerpc/mpc8548cds: Fix booting message
From: chenhui zhao chenhui.zhao@freescale.com
Align the output for PCI. Replace "PCI" with "PCI1".
Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com --- board/freescale/mpc8548cds/mpc8548cds.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index f70a972..8ab9752 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -120,7 +120,7 @@ void lbc_sdram_init(void)
puts("LBC SDRAM: "); print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, - "\n "); + "\n");
/* * Setup SDRAM Base and Option Registers @@ -236,7 +236,7 @@ void pci_init_board(void) law_size_bits(pci_info.io_size), pci_info.law);
pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); - printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", + printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", @@ -261,7 +261,7 @@ void pci_init_board(void) } #endif } else { - printf("PCI: disabled\n"); + printf("PCI1: disabled\n"); }
puts("\n");
From: chenhui zhao chenhui.zhao@freescale.com
Use 33333333Hz for 33MHz, 66666666Hz for 66MHz.
Signed-off-by: Ebony Zhu ebony.zhu@freescale.com Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com --- board/freescale/common/cadmus.c | 8 ++++---- board/freescale/mpc8541cds/mpc8541cds.c | 6 +++--- board/freescale/mpc8548cds/mpc8548cds.c | 4 ++-- board/freescale/mpc8555cds/mpc8555cds.c | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c index db54bc4..50b6e9f 100644 --- a/board/freescale/common/cadmus.c +++ b/board/freescale/common/cadmus.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -61,12 +61,12 @@ get_clock_freq(void) uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
if (pci1_speed == 0) { - return 33000000; + return 33333333; } else if (pci1_speed == 1) { - return 66000000; + return 66666666; } else { /* Really, unknown. Be safe? */ - return 33000000; + return 33333333; } }
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 0d3752d..a314f5c 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * * (C) Copyright 2002 Scott McNutt smcnutt@artesyncp.com * @@ -222,8 +222,8 @@ int checkboard (void)
printf("PCI1: %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64, - (pci1_speed == 33000000) ? "33" : - (pci1_speed == 66000000) ? "66" : "unknown", + (pci1_speed == 33333333) ? "33" : + (pci1_speed == 66666666) ? "66" : "unknown", pci1_clk_sel ? "sync" : "async");
if (pci_dual) { diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 8ab9752..d9f79b9 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -238,8 +238,8 @@ void pci_init_board(void) pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, - (pci_speed == 33333000) ? "33" : - (pci_speed == 66666000) ? "66" : "unknown", + (pci_speed == 33333333) ? "33" : + (pci_speed == 66666666) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 60d1758..4dda331 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -220,8 +220,8 @@ int checkboard (void)
printf("PCI1: %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64, - (pci1_speed == 33000000) ? "33" : - (pci1_speed == 66000000) ? "66" : "unknown", + (pci1_speed == 33333333) ? "33" : + (pci1_speed == 66666666) ? "66" : "unknown", pci1_clk_sel ? "sync" : "async");
if (pci_dual) {
Dear Zhao Chenhui,
In message 1315898131-27710-2-git-send-email-chenhui.zhao@freescale.com you wrote:
From: chenhui zhao chenhui.zhao@freescale.com
Use 33333333Hz for 33MHz, 66666666Hz for 66MHz.
But that's actually wrong. 33333333 Hz is not 33 MHz, but 33.333333 MHz; on the other hand, 33 MHz is 33000000 Hz and not 33333333 Hz.
Best regards,
Wolfgang Denk
On Tue, Sep 13, 2011 at 2:15 AM, Zhao Chenhui chenhui.zhao@freescale.com wrote:
@@ -222,8 +222,8 @@ int checkboard (void)
printf("PCI1: %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64,
- (pci1_speed == 33000000) ? "33" :
- (pci1_speed == 66000000) ? "66" : "unknown",
- (pci1_speed == 33333333) ? "33" :
- (pci1_speed == 66666666) ? "66" : "unknown",
I already told you on the internal mailing list to fix this, because it can never say "unknown". pci1_speed will always equal either 33333333 or 66666666. There is no way it can be set to anything else.
And Wolfgang is right -- this patch doesn't make any sense. Is the problem that pci1_speed is wrong, or is the problem that it's displaying the wrong value?
On 09/13/2011 02:20 PM, Tabi Timur-B04825 wrote:
On Tue, Sep 13, 2011 at 2:15 AM, Zhao Chenhui chenhui.zhao@freescale.com wrote:
@@ -222,8 +222,8 @@ int checkboard (void)
printf("PCI1: %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64,
(pci1_speed == 33000000) ? "33" :(pci1_speed == 66000000) ? "66" : "unknown",
(pci1_speed == 33333333) ? "33" :(pci1_speed == 66666666) ? "66" : "unknown",I already told you on the internal mailing list to fix this, because it can never say "unknown". pci1_speed will always equal either 33333333 or 66666666. There is no way it can be set to anything else.
There's no way it can be 33333000, 66000000, etc. based on the board's crystal?
Not that "unknown" is the right response to those values, of course.
-Scott
Scott Wood wrote:
There's no way it can be 33333000, 66000000, etc. based on the board's crystal?
There is earlier code that sets pci1_speed to 33333333 if the speed is unknown. So the actual value of pci1_speed is limited to those two numbers.
On 09/13/2011 03:03 PM, Timur Tabi wrote:
Scott Wood wrote:
There's no way it can be 33333000, 66000000, etc. based on the board's crystal?
There is earlier code that sets pci1_speed to 33333333 if the speed is unknown. So the actual value of pci1_speed is limited to those two numbers.
So you'll set the speed to 33333333 if the actual speed is 66000000? Even if it's 33000000, why force it to 33333333?
BTW, the PCI spec says things like "33 MHz" and "66 MHz". Is it compliant to have a bus run at 33333333 Hz (without 66MHz capable cards) or at 66666666 Hz?
-Scott
Scott Wood wrote:
So you'll set the speed to 33333333 if the actual speed is 66000000?
I think so.
Even if it's 33000000, why force it to 33333333?
That's a good question. Since the patch doesn't explain why it's making the change, there's no way for anyone to know. That makes it very difficult for people to review the patch, but I'm sure that Chenhui already knows that.
On Tue, Sep 13, 2011 at 03:18:59PM -0500, Timur Tabi wrote:
Scott Wood wrote:
So you'll set the speed to 33333333 if the actual speed is 66000000?
I think so.
Even if it's 33000000, why force it to 33333333?
That's a good question. Since the patch doesn't explain why it's making the change, there's no way for anyone to know. That makes it very difficult for people to review the patch, but I'm sure that Chenhui already knows that.
-- Timur Tabi Linux kernel developer at Freescale
OK. I'll rewrite the description in the patch.
-chenhui
Dear Zhao Chenhui,
In message 1315898131-27710-2-git-send-email-chenhui.zhao@freescale.com you wrote: ...
printf("PCI1: %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64,
(pci1_speed == 33000000) ? "33" :(pci1_speed == 66000000) ? "66" : "unknown",
(pci1_speed == 33333333) ? "33" :(pci1_speed == 66666666) ? "66" : "unknown",
Why cannot you simply write: ... char buf[32]; ... printf("PCI1: %d bit, %s MHz, %ssync\n", (pci1_32) ? 32 : 64, strmhz(buf, pci1_speed), pci1_clk_sel ? "" : "a");
?
Best regards,
Wolfgang Denk
On Tue, Sep 13, 2011 at 10:14:44PM +0200, Wolfgang Denk wrote:
Dear Zhao Chenhui,
In message 1315898131-27710-2-git-send-email-chenhui.zhao@freescale.com you wrote: ...
printf("PCI1: %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64,
(pci1_speed == 33000000) ? "33" :(pci1_speed == 66000000) ? "66" : "unknown",
(pci1_speed == 33333333) ? "33" :(pci1_speed == 66666666) ? "66" : "unknown",Why cannot you simply write:
... char buf[32]; ... printf("PCI1: %d bit, %s MHz, %ssync\n", (pci1_32) ? 32 : 64, strmhz(buf, pci1_speed), pci1_clk_sel ? "" : "a");
?
Best regards,
Wolfgang Denk
Yes. I'll repost it.
-chenhui
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de The only time the world beats a path to your door is when you are in the bathroom.
From: chenhui zhao chenhui.zhao@freescale.com
Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some early version silicons. The default settings of the DDR IO receiver biasing may not work at cold temperature. When a failure occurs, a DDR input latches an incorrect value. The workaround will set the receiver to an acceptable bias point.
Signed-off-by: Gong Chen g.chen@freescale.com Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++++ arch/powerpc/cpu/mpc85xx/ddr-gen2.c | 22 +++++++++++++++++++++- arch/powerpc/include/asm/config_mpc85xx.h | 1 + 3 files changed, 26 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 0478ec1..f0fa0f5 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -96,6 +96,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 puts("Work-around for Erratum IFC A-003399 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) + puts("Work-around for Erratum NMG DDR120 enabled\n"); +#endif return 0; }
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c index 655f99c..a71fb42 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008, 2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -8,6 +8,7 @@
#include <common.h> #include <asm/io.h> +#include <asm/processor.h> #include <asm/fsl_ddr_sdram.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) @@ -19,12 +20,31 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, { unsigned int i; volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + uint svr; +#endif
if (ctrl_num) { printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); return; }
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 + /* + * Set the DDR IO receiver to an acceptable bias point. + * Fixed in Rev 2.1. + */ + svr = get_svr(); + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) { + if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) == + SDRAM_CFG_SDRAM_TYPE_DDR2) + out_be32(&gur->ddrioovcr, 0x90000000); + else + out_be32(&gur->ddrioovcr, 0xA8000000); + } +#endif + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (i == 0) { out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index f9bf80d..a0a12b2 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -62,6 +62,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
#elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1
On Sep 13, 2011, at 2:15 AM, Zhao Chenhui wrote:
From: chenhui zhao chenhui.zhao@freescale.com
Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some early version silicons. The default settings of the DDR IO receiver biasing may not work at cold temperature. When a failure occurs, a DDR input latches an incorrect value. The workaround will set the receiver to an acceptable bias point.
Signed-off-by: Gong Chen g.chen@freescale.com Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++++ arch/powerpc/cpu/mpc85xx/ddr-gen2.c | 22 +++++++++++++++++++++- arch/powerpc/include/asm/config_mpc85xx.h | 1 + 3 files changed, 26 insertions(+), 1 deletions(-)
applied to 85xx
- k
From: chenhui zhao chenhui.zhao@freescale.com
Erratum NMG_eTSEC129 (eTSEC86 in MPC8548 document) applies to some early verion silicons. This workaround detects if the eTSEC Rx logic is properly initialized, and reinitialize the eTSEC Rx logic.
Signed-off-by: Gong Chen g.chen@freescale.com Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 + arch/powerpc/include/asm/config_mpc85xx.h | 1 + drivers/net/tsec.c | 93 +++++++++++++++++++++++++++++ 3 files changed, 98 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index f0fa0f5..2c468bd 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -100,6 +100,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) puts("Work-around for Erratum NMG DDR120 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) + puts("Work-around for Erratum NMG ETSEC129 enabled\n"); +#endif return 0; }
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index a0a12b2..3e32778 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -63,6 +63,7 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 +#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
#elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1 diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 78ffc95..160bc05 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -19,6 +19,7 @@ #include <tsec.h> #include <fsl_mdio.h> #include <asm/errno.h> +#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -43,6 +44,9 @@ static RTXBD rtx __attribute__ ((aligned(8))); #error "rtx must be 64-bit aligned" #endif
+static int tsec_send(struct eth_device *dev, + volatile void *packet, int length); + /* Default initializations for TSEC controllers. */
static struct tsec_info_struct tsec_info[] = { @@ -236,6 +240,87 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); }
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 +/* + * When MACCFG1[Rx_EN] is enabled during system boot as part + * of the eTSEC port initialization sequence, + * the eTSEC Rx logic may not be properly initialized. + */ +void redundant_init(struct eth_device *dev) +{ + struct tsec_private *priv = dev->priv; + tsec_t *regs = priv->regs; + uint t, count = 0; + int fail = 1; + static const u8 pkt[] = { + 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25, + 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01, + 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1, + 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00, + 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, + 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, + 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, + 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, + 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, + 0x71, 0x72}; + + /* Enable promiscuous mode */ + setbits_be32(®s->rctrl, 0x8); + /* Enable loopback mode */ + setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); + /* Enable transmit and receive */ + setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); + + /* Tell the DMA it is clear to go */ + setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); + out_be32(®s->tstat, TSTAT_CLEAR_THALT); + out_be32(®s->rstat, RSTAT_CLEAR_RHALT); + clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); + + do { + tsec_send(dev, (void *)pkt, sizeof(pkt)); + + /* Wait for buffer to be received */ + for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) { + if (t >= 10 * TOUT_LOOP) { + printf("%s: tsec: rx error\n", dev->name); + break; + } + } + + if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt))) + fail = 0; + + rtx.rxbd[rxIdx].length = 0; + rtx.rxbd[rxIdx].status = + RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); + rxIdx = (rxIdx + 1) % PKTBUFSRX; + + if (in_be32(®s->ievent) & IEVENT_BSY) { + out_be32(®s->ievent, IEVENT_BSY); + out_be32(®s->rstat, RSTAT_CLEAR_RHALT); + } + if (fail) { + printf("loopback recv packet error!\n"); + clrbits_be32(®s->maccfg1, MACCFG1_RX_EN); + udelay(1000); + setbits_be32(®s->maccfg1, MACCFG1_RX_EN); + } + } while ((count++ < 4) && (fail == 1)); + + if (fail) + panic("eTSEC init fail!\n"); + /* Disable promiscuous mode */ + clrbits_be32(®s->rctrl, 0x8); + /* Disable loopback mode */ + clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); +} +#endif + /* Set up the buffers and their descriptors, and bring up the * interface */ @@ -248,6 +333,9 @@ static void startup_tsec(struct eth_device *dev) /* reset the indices to zero */ rxIdx = 0; txIdx = 0; +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 + uint svr; +#endif
/* Point to the buffer descriptors */ out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx])); @@ -269,6 +357,11 @@ static void startup_tsec(struct eth_device *dev) } rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 + svr = get_svr(); + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) + redundant_init(dev); +#endif /* Enable Transmit and Receive */ setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
On Sep 13, 2011, at 2:15 AM, Zhao Chenhui wrote:
From: chenhui zhao chenhui.zhao@freescale.com
Erratum NMG_eTSEC129 (eTSEC86 in MPC8548 document) applies to some early verion silicons. This workaround detects if the eTSEC Rx logic is properly initialized, and reinitialize the eTSEC Rx logic.
Signed-off-by: Gong Chen g.chen@freescale.com Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 + arch/powerpc/include/asm/config_mpc85xx.h | 1 + drivers/net/tsec.c | 93 +++++++++++++++++++++++++++++ 3 files changed, 98 insertions(+), 0 deletions(-)
applied to 85xx
- k
From: chenhui zhao chenhui.zhao@freescale.com
Add board_eth_init(). PCIe network card is also supported. Put RGMII init after tsec_eth_init(). Skip initializing eTSEC3 and eTSEC4 with Carrier boards prior to ver 1.3.
Signed-off-by: Ebony Zhu ebony.zhu@freescale.com Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com --- board/freescale/mpc8548cds/mpc8548cds.c | 65 +++++++++++++++++++++++++++--- include/configs/MPC8548CDS.h | 2 + 2 files changed, 60 insertions(+), 7 deletions(-)
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index d9f79b9..99c86ac 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -33,6 +33,9 @@ #include <miiphy.h> #include <libfdt.h> #include <fdt_support.h> +#include <tsec.h> +#include <fsl_mdio.h> +#include <netdev.h>
#include "../common/cadmus.h" #include "../common/eeprom.h" @@ -287,7 +290,7 @@ void pci_init_board(void) fsl_pcie_init_board(first_free_busno); }
-int last_stage_init(void) +void configure_rgmii(void) { unsigned short temp;
@@ -295,29 +298,77 @@ int last_stage_init(void) /* This is needed to get the RGMII working for the 1.3+ * CDS cards */ if (get_board_version() == 0x13) { - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 29, 18);
- miiphy_read(CONFIG_TSEC1_NAME, + miiphy_read(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, &temp);
temp = (temp & 0xf03f); temp |= 2 << 9; /* 36 ohm */ temp |= 2 << 6; /* 39 ohm */
- miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, temp);
- miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 29, 3);
- miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, 0x8000); }
- return 0; + return; }
+#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif +#ifdef CONFIG_TSEC3 + /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */ + if (get_board_version() >= 0x13) { + SET_STD_TSEC_INFO(tsec_info[num], 3); + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; + num++; + } +#endif +#ifdef CONFIG_TSEC4 + /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */ + if (get_board_version() >= 0x13) { + SET_STD_TSEC_INFO(tsec_info[num], 4); + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; + num++; + } +#endif + + if (!num) { + printf("No TSECs initialized\n"); + + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + configure_rgmii(); + + return pci_eth_init(bis); +} +#endif
#if defined(CONFIG_OF_BOARD_SETUP) void ft_pci_setup(void *blob, bd_t *bd) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index aca77ff..64745e1 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -405,6 +405,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC
+#define CONFIG_PHY_MARVELL + #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2
On Sep 13, 2011, at 2:15 AM, Zhao Chenhui wrote:
From: chenhui zhao chenhui.zhao@freescale.com
Add board_eth_init(). PCIe network card is also supported. Put RGMII init after tsec_eth_init(). Skip initializing eTSEC3 and eTSEC4 with Carrier boards prior to ver 1.3.
Signed-off-by: Ebony Zhu ebony.zhu@freescale.com Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com
board/freescale/mpc8548cds/mpc8548cds.c | 65 +++++++++++++++++++++++++++--- include/configs/MPC8548CDS.h | 2 + 2 files changed, 60 insertions(+), 7 deletions(-)
applied to 85xx
- k
From: chenhui zhao chenhui.zhao@freescale.com
-Increase the size of malloc space. -Enable e1000 network card. -Change the location of env address. -Use hwconfig to turn off ECC.
Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com --- include/configs/MPC8548CDS.h | 14 +++++++++++--- 1 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 64745e1..2760af0 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -86,6 +86,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
@@ -162,6 +163,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_HWCONFIG /* enable hwconfig */
/* * SDRAM on the Local Bus @@ -276,7 +278,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */ #define CONFIG_CONS_INDEX 2 @@ -382,6 +384,7 @@ extern unsigned long get_clock_freq(void);
#undef CONFIG_EEPRO100 #undef CONFIG_TULIP +#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -430,8 +433,12 @@ extern unsigned long get_clock_freq(void); * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ #define CONFIG_ENV_SIZE 0x2000
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -532,6 +539,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ecc=off\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \
On Tue, Sep 13, 2011 at 2:15 AM, Zhao Chenhui chenhui.zhao@freescale.com wrote:
From: chenhui zhao chenhui.zhao@freescale.com
-Increase the size of malloc space. -Enable e1000 network card. -Change the location of env address. -Use hwconfig to turn off ECC.
Please repost this patch with a detailed explanation as to why these changes are being made. Why do you need more malloc space? Why enable only the E1000 card? What's wrong with the current environment address? And why does the default hwconfig need to turn off ECC?
Dear Zhao Chenhui,
In message 1315898131-27710-6-git-send-email-chenhui.zhao@freescale.com you wrote:
From: chenhui zhao chenhui.zhao@freescale.com
-Increase the size of malloc space. -Enable e1000 network card. -Change the location of env address. -Use hwconfig to turn off ECC.
Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com
include/configs/MPC8548CDS.h | 14 +++++++++++--- 1 files changed, 11 insertions(+), 3 deletions(-)
Checkpatch says:
total: 0 errors, 1 warnings, 50 lines checked
Please clean up and resubmit. Thanks.
Best regards,
Wolfgang Denk
On Oct 6, 2011, at 4:33 PM, Wolfgang Denk wrote:
Dear Zhao Chenhui,
In message 1315898131-27710-6-git-send-email-chenhui.zhao@freescale.com you wrote:
From: chenhui zhao chenhui.zhao@freescale.com
-Increase the size of malloc space. -Enable e1000 network card. -Change the location of env address. -Use hwconfig to turn off ECC.
Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com
include/configs/MPC8548CDS.h | 14 +++++++++++--- 1 files changed, 11 insertions(+), 3 deletions(-)
Checkpatch says:
total: 0 errors, 1 warnings, 50 lines checked
Please clean up and resubmit. Thanks.
Best regards,
Wolfgang Denk
I don't agree with this checkpatch warning. The extra space adds to readability so leaving this alone.
- k
Dear Kumar Gala,
In message 9C8CC940-A952-4323-8A48-BD6FB389AB05@kernel.crashing.org you wrote:
total: 0 errors, 1 warnings, 50 lines checked
I don't agree with this checkpatch warning. The extra space adds to = readability so leaving this alone.
Indentation must be done by TABs. Single spaces are not allowed.
Please fix.
Best regards,
Wolfgang Denk
On Sep 13, 2011, at 2:15 AM, Zhao Chenhui wrote:
From: chenhui zhao chenhui.zhao@freescale.com
-Increase the size of malloc space. -Enable e1000 network card. -Change the location of env address. -Use hwconfig to turn off ECC.
Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com
include/configs/MPC8548CDS.h | 14 +++++++++++--- 1 files changed, 11 insertions(+), 3 deletions(-)
applied to 85xx
- k
From: chenhui zhao chenhui.zhao@freescale.com
The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document. Any local bus transaction may fail during LBIU resynchronization process when the clock divider [CLKDIV] is changing. Ensure there is no transaction on the local bus for at least 100 microseconds after changing clock divider LCRR[CLKDIV].
Refer to the erratum LBIU3 of mpc8548.
Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + 3 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 2c468bd..6011f66 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -104,6 +104,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) puts("Work-around for Erratum NMG ETSEC129 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 + puts("Work-around for Erratum NMG_LBC103 enabled\n"); +#endif return 0; }
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 27f836c..d9e9069 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -454,6 +454,9 @@ skip_l2: clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); __raw_readl(&lbc->lcrr); isync(); +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 + udelay(100); +#endif #endif
#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 3e32778..e961e44 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 +#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
#elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1
On Sep 13, 2011, at 2:15 AM, Zhao Chenhui wrote:
From: chenhui zhao chenhui.zhao@freescale.com
The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document. Any local bus transaction may fail during LBIU resynchronization process when the clock divider [CLKDIV] is changing. Ensure there is no transaction on the local bus for at least 100 microseconds after changing clock divider LCRR[CLKDIV].
Refer to the erratum LBIU3 of mpc8548.
Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + 3 files changed, 7 insertions(+), 0 deletions(-)
applied to 85xx
- k
From: chenhui zhao chenhui.zhao@freescale.com
- Fix config according to system address map in the manual. - Rework tlb and law tables. - Remove unnecessary macros.
Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com --- board/freescale/mpc8548cds/law.c | 19 +++++---- board/freescale/mpc8548cds/mpc8548cds.c | 8 ++-- board/freescale/mpc8548cds/tlb.c | 67 ++++++++++++++++--------------- include/configs/MPC8548CDS.h | 56 ++++++++++++------------- 4 files changed, 76 insertions(+), 74 deletions(-)
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index 5b6943d..f0de509 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -31,13 +31,14 @@ * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0x8000_0000 0x8fff_ffff PCI1 MEM 256M + * 0x9000_0000 0x9fff_ffff PCI2 MEM 256M * 0xa000_0000 0xbfff_ffff PCIe MEM 512M * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe10f_ffff PCI1 IO 1M - * 0xe280_0000 0xe20f_ffff PCI2 IO 1M - * 0xe300_0000 0xe30f_ffff PCIe IO 1M + * 0xe000_0000 0xe00f_ffff CCSR 1M + * 0xe200_0000 0xe27f_ffff PCI1 IO 8M + * 0xe280_0000 0xe2ff_ffff PCI2 IO 8M + * 0xe300_0000 0xe3ff_ffff PCIe IO 16M * 0xf000_0000 0xf3ff_ffff SDRAM 64M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -52,11 +53,11 @@
struct law_entry law_table[] = { #ifdef CONFIG_SYS_PCI2_MEM_PHYS - SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2), #endif - /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + /* LBC window - maps 256M */ + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 99c86ac..65da881 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -53,10 +53,10 @@ int checkboard (void)
uint cpu_board_rev = get_cpu_board_revision ();
- printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", - get_board_version (), pci_slot); - - printf ("CPU Board Revision %d.%d (0x%04x)\n", + puts("Board: MPC8548CDS"); + printf(" Carrier Rev: 0x%02x, PCI Slot %d\n", + get_board_version(), pci_slot); + printf(" Daughtercard Rev: %d.%d (0x%04x)\n", MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); /* diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index b2c1b31..032d0e1 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -41,63 +41,66 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
+ /* TLB 1 */ /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. + * Entry 0: 16M Non-cacheable, guarded + * 0xff00_0000 16M FLASH(cover boot page) */ - SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1),
/* - * TLB 1: 1G Non-cacheable, guarded - * 0x80000000 1G PCI1/PCIE 8,9,a,b + * Entry 1: 1M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1G, 1), + 0, 1, BOOKE_PAGESZ_1M, 1),
/* - * TLB 2: 256M Non-cacheable, guarded + * Entry 2: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, + CONFIG_SYS_LBC_SDRAM_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 2, BOOKE_PAGESZ_64M, 1),
/* - * TLB 3: 256M Non-cacheable, guarded + * Entry 3: 1M Non-cacheable, guarded + * 0xf800_0000 1M CADMUS registers */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), + 0, 3, BOOKE_PAGESZ_1M, 1),
/* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 1M PCI1 IO - * 0xe210_0000 1M PCI2 IO - * 0xe300_0000 1M PCIe IO + * Entry 4: 1G Non-cacheable, guarded + * 0x8000_0000 256G PCI1 MEM + * 0x9000_0000 256M PCI2 MEM + * 0xa000_0000 512M PCIe MEM */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), + 0, 4, BOOKE_PAGESZ_1G, 1),
/* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM + * Entry 5: 32M Non-cacheable, guarded + * 0xe200_0000 8M PCI1 IO + * 0xe280_0000 8M PCI2 IO */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_CACHE_BASE, CONFIG_SYS_LBC_CACHE_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_16M, 1),
/* - * TLB 7: 64M Non-cacheable, guarded - * 0xf8000000 64M CADMUS registers, relocated L2SRAM + * Entry 6: 32M Non-cacheable, guarded + * 0xe300_0000 16M PCIe IO */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_64M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 2760af0..235c7bb 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -141,16 +141,20 @@ extern unsigned long get_clock_freq(void); * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx */
-#define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ +#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BR0_PRELIM 0xff801001 -#define CONFIG_SYS_BR1_PRELIM 0xff001001 +#define CONFIG_SYS_BR0_PRELIM \ + (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800000)) \ + | BR_PS_16 | BR_V) +#define CONFIG_SYS_BR1_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR0_PRELIM 0xff806e65 #define CONFIG_SYS_OR1_PRELIM 0xff806e65
-#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_FLASH_BANKS_LIST \ + {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ #undef CONFIG_SYS_FLASH_CHECKSUM @@ -168,12 +172,8 @@ extern unsigned long get_clock_freq(void); /* * SDRAM on the Local Bus */ -#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ -#define CONFIG_SYS_LBC_CACHE_SIZE 64 -#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ -#define CONFIG_SYS_LBC_NONCACHE_SIZE 64 - -#define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/* @@ -194,7 +194,9 @@ extern unsigned long get_clock_freq(void); * FIXME: the top 17 bits of BR2. */
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861 +#define CONFIG_SYS_BR2_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ + | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
/* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. @@ -265,15 +267,15 @@ extern unsigned long get_clock_freq(void); #define CONFIG_FSL_CADMUS
#define CADMUS_BASE_ADDR 0xf8000000 -#define CONFIG_SYS_BR3_PRELIM 0xf8000801 +#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR +#define CONFIG_SYS_BR3_PRELIM \ + (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
#define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ - #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
@@ -326,27 +328,24 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ -#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ - #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
#ifdef CONFIG_PCI2 -#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI2_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCI2_MEM_BUS 0x90000000 +#define CONFIG_SYS_PCI2_MEM_PHYS 0x90000000 +#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCI2_IO_SIZE 0x00800000 /* 8M */ #endif
#ifdef CONFIG_PCIE1 @@ -358,15 +357,14 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCIE1_IO_SIZE 0x01000000 /* 16M */ #endif
/* * RapidIO MMU */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 -#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#ifdef CONFIG_LEGACY
On Sep 13, 2011, at 2:15 AM, Zhao Chenhui wrote:
From: chenhui zhao chenhui.zhao@freescale.com
- Fix config according to system address map in the manual.
- Rework tlb and law tables.
- Remove unnecessary macros.
Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com
board/freescale/mpc8548cds/law.c | 19 +++++---- board/freescale/mpc8548cds/mpc8548cds.c | 8 ++-- board/freescale/mpc8548cds/tlb.c | 67 ++++++++++++++++--------------- include/configs/MPC8548CDS.h | 56 ++++++++++++------------- 4 files changed, 76 insertions(+), 74 deletions(-)
with which manual? If its the board manual that isn't correct, the one in the board manual is just an example.
- k
On Fri, Oct 07, 2011 at 10:17:28AM -0500, Kumar Gala wrote:
On Sep 13, 2011, at 2:15 AM, Zhao Chenhui wrote:
From: chenhui zhao chenhui.zhao@freescale.com
- Fix config according to system address map in the manual.
- Rework tlb and law tables.
- Remove unnecessary macros.
Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com
board/freescale/mpc8548cds/law.c | 19 +++++---- board/freescale/mpc8548cds/mpc8548cds.c | 8 ++-- board/freescale/mpc8548cds/tlb.c | 67 ++++++++++++++++--------------- include/configs/MPC8548CDS.h | 56 ++++++++++++------------- 4 files changed, 76 insertions(+), 74 deletions(-)
with which manual? If its the board manual that isn't correct, the one in the board manual is just an example.
- k
It's "MPC8548E Configurable Development System Reference Manual". I made some minor changes to address map, including reserving 256M memory space for PCI2, enlarging the size of PCI IO space.
-chenhui
On Sat, Oct 08, 2011 at 03:02:18PM +0800, Zhao Chenhui wrote:
On Fri, Oct 07, 2011 at 10:17:28AM -0500, Kumar Gala wrote:
On Sep 13, 2011, at 2:15 AM, Zhao Chenhui wrote:
From: chenhui zhao chenhui.zhao@freescale.com
- Fix config according to system address map in the manual.
- Rework tlb and law tables.
- Remove unnecessary macros.
Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com
board/freescale/mpc8548cds/law.c | 19 +++++---- board/freescale/mpc8548cds/mpc8548cds.c | 8 ++-- board/freescale/mpc8548cds/tlb.c | 67 ++++++++++++++++--------------- include/configs/MPC8548CDS.h | 56 ++++++++++++------------- 4 files changed, 76 insertions(+), 74 deletions(-)
with which manual? If its the board manual that isn't correct, the one in the board manual is just an example.
- k
It's "MPC8548E Configurable Development System Reference Manual". I made some minor changes to address map, including reserving 256M memory space for PCI2, enlarging the size of PCI IO space.
-chenhui
Fixed typo in the comments of tlb.c and reposted.
-chenhui
From: chenhui zhao chenhui.zhao@freescale.com
Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com --- boards.cfg | 1 + include/configs/MPC8548CDS.h | 52 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 0 deletions(-)
diff --git a/boards.cfg b/boards.cfg index 8bf69e3..64a39f8 100644 --- a/boards.cfg +++ b/boards.cfg @@ -568,6 +568,7 @@ MPC8541CDS powerpc mpc85xx mpc8541cds freesca MPC8541CDS_legacy powerpc mpc85xx mpc8541cds freescale - MPC8541CDS:LEGACY MPC8544DS powerpc mpc85xx mpc8544ds freescale MPC8548CDS powerpc mpc85xx mpc8548cds freescale - MPC8548CDS +MPC8548CDS_36BIT powerpc mpc85xx mpc8548cds freescale - MPC8548CDS:36BIT MPC8548CDS_legacy powerpc mpc85xx mpc8548cds freescale - MPC8548CDS:LEGACY MPC8555CDS powerpc mpc85xx mpc8555cds freescale - MPC8555CDS MPC8555CDS_legacy powerpc mpc85xx mpc8555cds freescale - MPC8555CDS:LEGACY diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 235c7bb..b4e11b0 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -29,6 +29,10 @@ #ifndef __CONFIG_H #define __CONFIG_H
+#ifdef CONFIG_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -74,6 +78,11 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_ENABLE_36BIT_PHYS 1
+#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000
@@ -142,7 +151,11 @@ extern unsigned long get_clock_freq(void); */
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull +#else #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif
#define CONFIG_SYS_BR0_PRELIM \ (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800000)) \ @@ -173,7 +186,11 @@ extern unsigned long get_clock_freq(void); * SDRAM on the Local Bus */ #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull +#else #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE +#endif #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/* @@ -267,7 +284,11 @@ extern unsigned long get_clock_freq(void); #define CONFIG_FSL_CADMUS
#define CADMUS_BASE_ADDR 0xf8000000 +#ifdef CONFIG_PHYS_64BIT +#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull +#else #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR +#endif #define CONFIG_SYS_BR3_PRELIM \ (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 @@ -329,34 +350,61 @@ extern unsigned long get_clock_freq(void); * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull +#else #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#endif #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull +#else #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#endif #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
#ifdef CONFIG_PCI2 #define CONFIG_SYS_PCI2_MEM_VIRT 0x90000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCI2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS 0xc10000000ull +#else #define CONFIG_SYS_PCI2_MEM_BUS 0x90000000 #define CONFIG_SYS_PCI2_MEM_PHYS 0x90000000 +#endif #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCI2_IO_PHYS 0xfe2800000ull +#else #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 +#endif #define CONFIG_SYS_PCI2_IO_SIZE 0x00800000 /* 8M */ #endif
#ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_NAME "Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull +#else #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull +#else #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 +#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x01000000 /* 16M */ #endif
@@ -364,7 +412,11 @@ extern unsigned long get_clock_freq(void); * RapidIO MMU */ #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull +#else #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 +#endif #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#ifdef CONFIG_LEGACY
On Sep 13, 2011, at 2:15 AM, Zhao Chenhui wrote:
From: chenhui zhao chenhui.zhao@freescale.com
Align the output for PCI. Replace "PCI" with "PCI1".
Signed-off-by: Zhao Chenhui chenhui.zhao@freescale.com
board/freescale/mpc8548cds/mpc8548cds.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)
applied to 85xx
- k
participants (7)
-
Kumar Gala -
Scott Wood -
Tabi Timur-B04825 -
Timur Tabi -
Wolfgang Denk -
Zhao Chenhui -
Zhao Chenhui