On Thu, Feb 14, 2013 at 3:58 PM, Gabe Black gabeblack@google.com wrote:

Acked-by: Gabe Black gabeblack@chromium.org

On Thu, Feb 14, 2013 at 6:18 AM, Simon Glass sjg@chromium.org wrote:

...

These are no longer used and should be removed.

Signed-off-by: Simon Glass sjg@chromium.org Acked-by: Graeme Russ graeme.russ@gmail.com

Applied to x86/master.

...

---

Changes in v2: None

board/eNET/Makefile | 52 ---- board/eNET/eNET.c | 284 --------------------- board/eNET/eNET_pci.c | 128 ---------- board/eNET/eNET_start.S | 30 --- board/eNET/eNET_start16.S | 87 ------- board/eNET/hardware.h | 36 --- boards.cfg | 2 - include/configs/eNET.h | 619

---

8 files changed, 1238 deletions(-) delete mode 100644 board/eNET/Makefile delete mode 100644 board/eNET/eNET.c delete mode 100644 board/eNET/eNET_pci.c delete mode 100644 board/eNET/eNET_start.S delete mode 100644 board/eNET/eNET_start16.S delete mode 100644 board/eNET/hardware.h delete mode 100644 include/configs/eNET.h

diff --git a/board/eNET/Makefile b/board/eNET/Makefile deleted file mode 100644 index ad1c5b1..0000000 --- a/board/eNET/Makefile +++ /dev/null @@ -1,52 +0,0 @@ -# -# (C) Copyright 2008 -# Graeme Russ, graeme.russ@gmail.com. -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -#

-include $(TOPDIR)/config.mk

-LIB = $(obj)lib$(BOARD).o

-COBJS-y += eNET.o -COBJS-$(CONFIG_PCI) += eNET_pci.o -SOBJS-y += eNET_start16.o -SOBJS-y += eNET_start.o

-SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

-$(LIB): $(obj).depend $(OBJS) $(SOBJS)

•   $(call cmd_link_o_target, $(OBJS) $(SOBJS))
  

-#########################################################################

-# defines $(obj).depend target -include $(SRCTREE)/rules.mk

-sinclude $(obj).depend

-######################################################################### diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c deleted file mode 100644 index 2f26470..0000000 --- a/board/eNET/eNET.c +++ /dev/null @@ -1,284 +0,0 @@ -/*

• • (C) Copyright 2008
• • Graeme Russ, graeme.russ@gmail.com.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#include <common.h> -#include <asm/io.h> -#include <asm/arch/sc520.h> -#include <net.h> -#include <netdev.h>

-#ifdef CONFIG_HW_WATCHDOG -#include <watchdog.h> -#endif

-#include "hardware.h"

-DECLARE_GLOBAL_DATA_PTR;

-unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;

-static void enet_timer_isr(void); -static void enet_toggle_run_led(void); -static void enet_setup_pars(void);

-/*

• • Miscellaneous platform dependent initializations
• */

-int board_early_init_f(void) -{

•   u16 pio_out_cfg = 0x0000;
  

•   /* Configure General Purpose Bus timing */
  

•   writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
  

•   writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
  

•   writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
  

•   writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
  

•   writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
  

•   writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
  

•   writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
  

•   /* Configure Programmable Input/Output Pins */
  

•   writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
  

•   writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
  

•   writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
  

•   writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
  

•   writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
  

•   writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
  

•   /*
  

•    * Turn off top board
  

•    * Set StrataFlash chips to 16-bit width
  

•    * Set StrataFlash chips to normal (non reset/power down) mode
  

•    */
  

•   pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
  

•   pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
  

•   pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
  

•   pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
  

•   writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
  

•   /* Turn off auxiliary power output */
  

•   writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
  

•   /* Clear FPGA program mode */
  

•   writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
  

•   enet_setup_pars();
  

•   /* Disable Watchdog */
  

•   writew(0x3333, &sc520_mmcr->wdtmrctl);
  

•   writew(0xcccc, &sc520_mmcr->wdtmrctl);
  

•   writew(0x0000, &sc520_mmcr->wdtmrctl);
  

•   /* Chip Select Configuration */
  

•   writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
  

•   writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
  

•   writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
  

•   writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
  

•   writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
  

•   writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
  

•   writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
  

•   writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
  

•   /* enable posted-writes */
  

•   writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
  

•   return 0;
  

-}

-static void enet_setup_pars(void) -{

•   /*
  

•    * PARs 11 and 12 are 2MB SRAM @ 0x19000000
  

•    *
  

•    * These are setup now because older version of U-Boot have them
  

•    * mapped to a different PAR which gets clobbered which prevents
  

•    * using SRAM for warm-booting a new image
  

•    */
  

•   writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
  

•   writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
  

•   /* PARs 0 and 1 are Compact Flash slots (4kB each) */
  

•   writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
  

•   writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
  

•   /* PAR 2 is used for Cache-As-RAM */
  

•   /*
  

•    * PARs 5 through 8 are additional NS16550 UARTS
  

•    * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
  

•    */
  

•   writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
  

•   writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
  

•   writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
  

•   writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
  

•   /* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
  

•   writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
  

•   writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
  

•   /* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
  

•   writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
  

•   /*
  

•    * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
  

•    * Already configured in board_init16 (eNET_start16.S)
  

•    *
  

•    * PAR 15 is Boot ROM
  

•    * Already configured in board_init16 (eNET_start16.S)
  

•    */
  

-}

-int board_early_init_r(void) -{

•   /* CPU Speed to 100MHz */
  

•   gd->cpu_clk = 100000000;
  

•   /* Crystal is 33.000MHz */
  

•   gd->bus_clk = 33000000;
  

•   return 0;
  

-}

-void show_boot_progress(int val) -{

•   uchar led_mask;
  

•   led_mask = 0x00;
  

•   if (val < 0)
  

•           led_mask |= LED_ERR_BITMASK;
  

•   led_mask |= (uchar)(val & 0x001f);
  

•   outb(led_mask, LED_LATCH_ADDRESS);
  

-}

-int last_stage_init(void) -{

•   outb(0x00, LED_LATCH_ADDRESS);
  

•   register_timer_isr(enet_timer_isr);
  

•   printf("Serck Controls eNET\n");
  

•   return 0;
  

-}

-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{

•   if (banknum == 0) {     /* non-CFI boot flash */
  

•           info->portwidth = FLASH_CFI_8BIT;
  

•           info->chipwidth = FLASH_CFI_BY8;
  

•           info->interface = FLASH_CFI_X8;
  

•           return 1;
  

•   } else {
  

•           return 0;
  

•   }
  

-}

-int board_eth_init(bd_t *bis) -{

•   return pci_eth_init(bis);
  

-}

-void setup_pcat_compatibility() -{

•   /* disable global interrupt mode */
  

•   writeb(0x40, &sc520_mmcr->picicr);
  

•   /* set all irqs to edge */
  

•   writeb(0x00, &sc520_mmcr->pic_mode[0]);
  

•   writeb(0x00, &sc520_mmcr->pic_mode[1]);
  

•   writeb(0x00, &sc520_mmcr->pic_mode[2]);
  

•   /*
  

•    *  active low polarity on PIC interrupt pins,
  

•    *  active high polarity on all other irq pins
  

•    */
  

•   writew(0x0000, &sc520_mmcr->intpinpol);
  

•   /*
  

•    * PIT 0 -> IRQ0
  

•    * RTC -> IRQ8
  

•    * FP error -> IRQ13
  

•    * UART1 -> IRQ4
  

•    * UART2 -> IRQ3
  

•    */
  

•   writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
  

•   writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
  

•   writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
  

•   writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
  

•   writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
  

•   /* Disable all other interrupt sources */
  

•   writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
  

•   writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
  

•   writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
  

•   writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
  

•   writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
  

•   writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
  

•   writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
  

•   writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
  

•   writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
  

-}

-void enet_timer_isr(void) -{

•   static long enet_ticks;
  

•   enet_ticks++;
  

•   /* Toggle Watchdog every 100ms */
  

•   if ((enet_ticks % 100) == 0)
  

•           hw_watchdog_reset();
  

•   /* Toggle Run LED every 500ms */
  

•   if ((enet_ticks % 500) == 0)
  

•           enet_toggle_run_led();
  

-}

-void hw_watchdog_reset(void) -{

•   /* Watchdog Reset must be atomic */
  

•   long flag = disable_interrupts();
  

•   if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
  

•           sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
  

•   else
  

•           sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
  

•   if (flag)
  

•           enable_interrupts();
  

-}

-void enet_toggle_run_led(void) -{

•   unsigned char leds_state = inb(LED_LATCH_ADDRESS);
  

•   if (leds_state & LED_RUN_BITMASK)
  

•           outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS);
  

•   else
  

•           outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
  

-} diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c deleted file mode 100644 index 5af4ef7..0000000 --- a/board/eNET/eNET_pci.c +++ /dev/null @@ -1,128 +0,0 @@ -/*

• • (C) Copyright 2008,2009
• • Graeme Russ, graeme.russ@gmail.com
• • (C) Copyright 2002
• • Daniel Engström, Omicron Ceti AB, daniel@omicron.se
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#include <common.h> -#include <pci.h> -#include <asm/pci.h> -#include <asm/arch/pci.h>

-static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{

•   /* a configurable lists of IRQs to steal when we need one */
  

•   static int irq_list[] = {
  

•           CONFIG_SYS_FIRST_PCI_IRQ,
  

•           CONFIG_SYS_SECOND_PCI_IRQ,
  

•           CONFIG_SYS_THIRD_PCI_IRQ,
  

•           CONFIG_SYS_FORTH_PCI_IRQ
  

•   };
  

•   static int next_irq_index;
  

•   uchar tmp_pin;
  

•   int pin;
  

•   pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
  

•   pin = tmp_pin;
  

•   pin -= 1; /* PCI config space use 1-based numbering */
  

•   if (pin == -1)
  

•           return; /* device use no irq */
  

•   /* map device number +  pin to a pin on the sc520 */
  

•   switch (PCI_DEV(dev)) {
  

•   case 12:        /* First Ethernet Chip */
  

•           pin += SC520_PCI_INTA;
  

•           break;
  

•   case 13:        /* Second Ethernet Chip */
  

•           pin += SC520_PCI_INTB;
  

•           break;
  

•   default:
  

•           return;
  

•   }
  

•   pin &= 3; /* wrap around */
  

•   if (sc520_pci_ints[pin] == -1) {
  

•           /* re-route one interrupt for us */
  

•           if (next_irq_index > 3)
  

•                   return;
  

•           if (pci_sc520_set_irq(pin, irq_list[next_irq_index]))
  

•                   return;
  

•           next_irq_index++;
  

•   }
  

•   if (-1 != sc520_pci_ints[pin])
  

•           pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
  

•                                      sc520_pci_ints[pin]);
  

•   printf("fixup_irq: device %d pin %c irq %d\n",
  

•          PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
  

-}

-static struct pci_controller enet_hose = {

•   fixup_irq: pci_enet_fixup_irq,
  

-};

-void pci_init_board(void) -{

•   pci_sc520_init(&enet_hose);
  

-}

-int pci_set_regions(struct pci_controller *hose) -{

•   /* System memory space */
  

•   pci_set_region(hose->regions + 0,
  

•                  SC520_PCI_MEMORY_BUS,
  

•                  SC520_PCI_MEMORY_PHYS,
  

•                  SC520_PCI_MEMORY_SIZE,
  

•                  PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  

•   /* ISA/PCI memory space */
  

•   pci_set_region(hose->regions + 1,
  

•                  SC520_ISA_MEM_BUS,
  

•                  SC520_ISA_MEM_PHYS,
  

•                  SC520_ISA_MEM_SIZE,
  

•                  PCI_REGION_MEM);
  

•   /* PCI I/O space */
  

•   pci_set_region(hose->regions + 2,
  

•                  SC520_PCI_IO_BUS,
  

•                  SC520_PCI_IO_PHYS,
  

•                  SC520_PCI_IO_SIZE,
  

•                  PCI_REGION_IO);
  

•   /* ISA/PCI I/O space */
  

•   pci_set_region(hose->regions + 3,
  

•                  SC520_ISA_IO_BUS,
  

•                  SC520_ISA_IO_PHYS,
  

•                  SC520_ISA_IO_SIZE,
  

•                  PCI_REGION_IO);
  

•   return 4;
  

-} diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S deleted file mode 100644 index 0dec7ea..0000000 --- a/board/eNET/eNET_start.S +++ /dev/null @@ -1,30 +0,0 @@ -/*

• • (C) Copyright 2008
• • Graeme Russ, graeme.russ@gmail.com.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#include "hardware.h"

-/* board early intialization */ -.globl early_board_init -early_board_init:

•   /* No 32-bit board specific initialisation */
  

•   jmp     early_board_init_ret
  

diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S deleted file mode 100644 index 5e3f44c..0000000 --- a/board/eNET/eNET_start16.S +++ /dev/null @@ -1,87 +0,0 @@ -/*

• • (C) Copyright 2008
• • Graeme Russ, graeme.russ@gmail.com.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-/*

• • 16bit initialization code.
• • This code have to map the area of the boot flash
• • that is used by U-boot to its final destination.
• */

-#include "config.h" -#include "hardware.h" -#include <asm/arch/sc520.h> -#include <generated/asm-offsets.h>

-.text -.section .start16, "ax" -.code16 -.globl board_init16 -board_init16:

•   /* Alias MMCR to 0xdf000 */
  

•   movw    $0xfffc, %dx
  

•   movl    $0x800df0cb, %eax
  

•   outl    %eax, %dx
  

•   /* Set ds to point to MMCR alias */
  

•   movw    $0xdf00, %ax
  

•   movw    %ax, %ds
  

•   /* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
  

•   movl    $GENERATED_SC520_PAR14, %edi
  

•   movl    $CONFIG_SYS_SC520_BOOTCS_PAR, %eax
  

•   movl    %eax, (%di)
  

•   /* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
  

•   movl    $GENERATED_SC520_PAR15, %edi
  

•   movl    $CONFIG_SYS_SC520_LLIO_PAR, %eax
  

•   movl    %eax, (%di)
  

•   /* Disabe MMCR alias */
  

•   movw    $0xfffc, %dx
  

•   movl    $0x000000cb, %eax
  

•   outl    %eax, %dx
  

•   jmp     board_init16_ret
  

-.section .bios, "ax" -.code16 -.globl realmode_reset -.hidden realmode_reset -.type realmode_reset, @function -realmode_reset:

•   /* Alias MMCR to 0xdf000 */
  

•   movw    $0xfffc, %dx
  

•   movl    $0x800df0cb, %eax
  

•   outl    %eax, %dx
  

•   /* Set ds to point to MMCR alias */
  

•   movw    $0xdf00, %ax
  

•   movw    %ax, %ds
  

•   /* issue software reset thorugh MMCR */
  

•   movl    $0xd72, %edi
  

•   movb    $0x01, %al
  

•   movb    %al, (%di)
  

-1: hlt

•   jmp     1
  

diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h deleted file mode 100644 index dec2cd8..0000000 --- a/board/eNET/hardware.h +++ /dev/null @@ -1,36 +0,0 @@ -/*

• • (C) Copyright 2008
• • Graeme Russ, graeme.russ@gmail.com.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#ifndef HARDWARE_H_ -#define HARDWARE_H_

-#define LED_LATCH_ADDRESS 0x1002 -#define LED_RUN_BITMASK 0x01 -#define LED_1_BITMASK 0x02 -#define LED_2_BITMASK 0x04 -#define LED_RX_BITMASK 0x08 -#define LED_TX_BITMASK 0x10 -#define LED_ERR_BITMASK 0x20 -#define WATCHDOG_PIO_BIT 0x8000

-#endif /* HARDWARE_H_ */ diff --git a/boards.cfg b/boards.cfg index cd220af..b1319aa 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1123,7 +1123,5 @@ gr_ep2s60 sparc leon3

•               gaisler
  

grsim sparc leon3 - gaisler gr_xc3s_1500 sparc leon3 - gaisler coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0x01110000 -eNET x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x38040000 -eNET_SRAM x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x19000000 # Target ARCH CPU Board name Vendor SoC Options

######################################################################################################################## diff --git a/include/configs/eNET.h b/include/configs/eNET.h deleted file mode 100644 index 28cf95b..0000000 --- a/include/configs/eNET.h +++ /dev/null @@ -1,619 +0,0 @@ -/*

• • (C) Copyright 2008
• • Graeme Russ, graeme.russ@gmail.com.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#include <asm/ibmpc.h> -/*

• • board/config.h - configuration options, board specific
• */

-#ifndef __CONFIG_H -#define __CONFIG_H

-/*

• • High Level Configuration Options
• • (easy to change)
• */

-#define CONFIG_SYS_SC520 -#define CONFIG_SYS_SC520_SSI -#define CONFIG_SHOW_BOOT_PROGRESS -#define CONFIG_LAST_STAGE_INIT

-/*-----------------------------------------------------------------------

• • Watchdog Configuration
• • NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
• • bottom (processor) board MUST be removed!
• */

-#undef CONFIG_WATCHDOG -#define CONFIG_HW_WATCHDOG

-/*-----------------------------------------------------------------------

• • Real Time Clock Configuration
• */

-#define CONFIG_RTC_MC146818 -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0

-/*-----------------------------------------------------------------------

• • Serial Configuration
• */

-#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 1843200 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \

•                                            9600, 19200, 38400,
  

115200} -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_NS16550_COM2 UART1_BASE -#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE) -#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE) -#define CONFIG_SYS_NS16550_PORT_MAPPED

-/*-----------------------------------------------------------------------

• • Video Configuration
• */

-#undef CONFIG_VIDEO -#undef CONFIG_CFB_CONSOLE

-/*-----------------------------------------------------------------------

• • Command line configuration.
• */

-#include <config_cmd_default.h>

-#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IMLS -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ITEST -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_SETGETDCR -#define CONFIG_CMD_SOURCE -#define CONFIG_CMD_XIMG -#define CONFIG_CMD_ZBOOT

-#define CONFIG_BOOTDELAY 15 -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"

-#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 -#define CONFIG_KGDB_SER_INDEX 2 -#endif

-/*

• • Miscellaneous configurable options
• */

-#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "boot > " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE

• \

•                                            sizeof(CONFIG_SYS_PROMPT)
  

• \

•                                            16)
  

-#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

-#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x01000000 -#define CONFIG_SYS_LOAD_ADDR 0x100000 -#define CONFIG_SYS_HZ 1000

-/*-----------------------------------------------------------------------

• • SDRAM Configuration
• */

-#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18 -#define CONFIG_SYS_SDRAM_REFRESH_RATE 156 -#define CONFIG_NR_DRAM_BANKS 4

-/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/ -#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY -#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T

-/*-----------------------------------------------------------------------

• • CPU Features
• */

-#define CONFIG_SYS_SC520_HIGH_SPEED 0 -#define CONFIG_SYS_SC520_RESET -#define CONFIG_SYS_SC520_TIMER -#undef CONFIG_SYS_GENERIC_TIMER -#define CONFIG_SYS_PCAT_INTERRUPTS -#define CONFIG_SYS_NUM_IRQS 16 -#define CONFIG_SYS_PC_BIOS -#define CONFIG_SYS_PCI_BIOS -#define CONFIG_SYS_X86_REALMODE -#define CONFIG_SYS_X86_ISR_TIMER

-/*-----------------------------------------------------------------------

• • Memory organization:
• • 32kB Stack
• • 16kB Cache-As-RAM @ 0x19200000
• • 256kB Monitor
• • (128kB + Environment Sector Size) malloc pool
• */

-#define CONFIG_SYS_STACK_SIZE (32 * 1024) -#define CONFIG_SYS_CAR_ADDR 0x19200000 -#define CONFIG_SYS_CAR_SIZE (16 * 1024) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + \

•                                            128*1024)
  

-/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE

-/*-----------------------------------------------------------------------

• • FLASH configuration
• • 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
• • 16MB StrataFlash #1 @ 0x10000000
• • 16MB StrataFlash #2 @ 0x11000000
• */

-#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_MAX_FLASH_BANKS 3 -#define CONFIG_SYS_FLASH_BASE 0x38000000 -#define CONFIG_SYS_FLASH_BASE_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE_2 0x11000000 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \

•                                            CONFIG_SYS_FLASH_BASE_1,
  

\

•                                            CONFIG_SYS_FLASH_BASE_2}
  

-#define CONFIG_SYS_FLASH_EMPTY_INFO -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_SYS_FLASH_LEGACY_512Kx8 -#define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */

-/*-----------------------------------------------------------------------

• • Environment configuration
• • • Boot flash is 512kB with 64kB sectors
• • • StrataFlash is 32MB with 128kB sectors
• • • Redundant embedded environment is 25% of the Boot flash
• • • Redundant StrataFlash environment is <1% of the StrataFlash
• • • Environment is therefore located in StrataFlash
• • • Primary copy is located in first sector of first flash
• • • Redundant copy is located in second sector of first flash
• • • Stack is only 32kB, so environment size is limited to 4kB
• */

-#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x01000 -#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \

•                                            CONFIG_ENV_SECT_SIZE)
  

-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE

-/*-----------------------------------------------------------------------

• • PCI configuration
• */

-#define CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_SYS_FIRST_PCI_IRQ 10 -#define CONFIG_SYS_SECOND_PCI_IRQ 9 -#define CONFIG_SYS_THIRD_PCI_IRQ 11 -#define CONFIG_SYS_FORTH_PCI_IRQ 15

-/*-----------------------------------------------------------------------

• • Network device (TRL8100B) support
• */

-#define CONFIG_RTL8139

-/*-----------------------------------------------------------------------

• • BOOTCS Control (for AM29LV040B-120JC)
• • 000 0 00 0 000 11 0 011 }- 0x0033
• • \ / | | | \ / | | \ /
• • | | | | | | | |
• • | | | | | | | +---- 3 Wait States (First Access)
• • | | | | | | +------- Reserved
• • | | | | | +--------- 3 Wait States (Subsequent Access)
• • | | | | +------------- Reserved
• • | | | +---------------- Non-Paged Mode
• • | | +------------------ 8 Bit Wide
• • | +--------------------- GP Bus
• • +------------------------ Reserved
• */

-#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033

-/*-----------------------------------------------------------------------

• • ROMCS Control (for E28F128J3A-150 StrataFlash)
• • 000 0 01 1 000 01 0 101 }- 0x0615
• • \ / | | | \ / | | \ /
• • | | | | | | | |
• • | | | | | | | +---- 5 Wait States (First Access)
• • | | | | | | +------- Reserved
• • | | | | | +--------- 1 Wait State (Subsequent Access)
• • | | | | +------------- Reserved
• • | | | +---------------- Paged Mode
• • | | +------------------ 16 Bit Wide
• • | +--------------------- GP Bus
• • +------------------------ Reserved
• */

-#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615 -#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615

-/*-----------------------------------------------------------------------

• • SC520 General Purpose Bus configuration
• • Chip Select Offset 1 Clock Cycle
• • Chip Select Pulse Width 8 Clock Cycles
• • Chip Select Read Offset 2 Clock Cycles
• • Chip Select Read Width 6 Clock Cycles
• • Chip Select Write Offset 2 Clock Cycles
• • Chip Select Write Width 6 Clock Cycles
• • Chip Select Recovery Time 2 Clock Cycles
• • Timing Diagram (from SC520 Register Set Manual - Order #22005B)
• • |<-------------General Purpose Bus Cycle---------------->|
• • | |
• • ----------------------__________________/------------------
• • |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
• • ------------------------_______________/-------------------
• • |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
• • --------------------------_______________/-----------------
• • |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
• • ________/-----------_______________________________________
• • |<--->|<--------->|

• •  ^         ^
    

• • (GPALEOFF + 1) |

• •            |
    

• •     (GPALEW + 1)
    

• */

-#define CONFIG_SYS_SC520_GPCSOFF 0x00 -#define CONFIG_SYS_SC520_GPCSPW 0x07 -#define CONFIG_SYS_SC520_GPRDOFF 0x01 -#define CONFIG_SYS_SC520_GPRDW 0x05 -#define CONFIG_SYS_SC520_GPWROFF 0x01 -#define CONFIG_SYS_SC520_GPWRW 0x05 -#define CONFIG_SYS_SC520_GPCSRT 0x01

-/*-----------------------------------------------------------------------

• • SC520 Programmable I/O configuration
• • Pin Mode Dir. Description

• • ---

• • PIO0 PIO Output Unused
• • PIO1 GPBHE# Output GP Bus Byte High Enable (active low)
• • PIO2 PIO Output Auxiliary power output enable
• • PIO3 GPAEN Output GP Bus Address Enable
• • PIO4 PIO Output Top Board Enable (active low)
• • PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode)
• • PIO6 PIO Input Data output of Power Supply ADC
• • PIO7 PIO Output Clock input to Power Supply ADC
• • PIO8 PIO Output Chip Select input of Power Supply ADC
• • PIO9 PIO Output StrataFlash 1 Reset / Power Down (active

low)

• • PIO10 PIO Output StrataFlash 2 Reset / Power Down (active

low)

• • PIO11 PIO Input StrataFlash 1 Status
• • PIO12 PIO Input StrataFlash 2 Status
• • PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low)
• • PIO14 PIO Input Low Input Voltage Warning (active low)
• • PIO15 PIO Output Watchdog (must toggle at least every 1.6s)
• • PIO16 PIO Input Power Fail
• • PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low)
• • PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low)
• • PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low)
• • PIO20 GPIRQ3 Input UART D IRQ
• • PIO21 GPIRQ2 Input UART C IRQ
• • PIO22 GPIRQ1 Input UART B IRQ
• • PIO23 GPIRQ0 Input UART A IRQ
• • PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable
• • PIO25 PIO Input Battery OK Indication
• • PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access
• • PIO27 GPCS0# Output SRAM 1 Chip Select
• • PIO28 PIO Input Top Board UART CTS
• • PIO29 PIO Output FPGA Program Mode (active low)
• • PIO30 PIO Input FPGA Initialised (active low)
• • PIO31 PIO Input FPGA Done (active low)
• */

-#define CONFIG_SYS_SC520_PIOPFS15_0 0x200a -#define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe -#define CONFIG_SYS_SC520_PIODIR15_0 0x87bf -#define CONFIG_SYS_SC520_PIODIR31_16 0x2900

-/*-----------------------------------------------------------------------

• • PIO Pin defines
• */

-#define CONFIG_SYS_ENET_AUX_PWR 0x0004 -#define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010 -#define CONFIG_SYS_ENET_SF_WIDTH 0x0020 -#define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040 -#define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080 -#define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100 -#define CONFIG_SYS_ENET_SF1_MODE 0x0200 -#define CONFIG_SYS_ENET_SF2_MODE 0x0400 -#define CONFIG_SYS_ENET_SF1_STATUS 0x0800 -#define CONFIG_SYS_ENET_SF2_STATUS 0x1000 -#define CONFIG_SYS_ENET_PWR_STATUS 0x4000 -#define CONFIG_SYS_ENET_WATCHDOG 0x8000

-#define CONFIG_SYS_ENET_PWR_FAIL 0x0001 -#define CONFIG_SYS_ENET_BAT_OK 0x0200 -#define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000 -#define CONFIG_SYS_ENET_FPGA_PROG 0x2000 -#define CONFIG_SYS_ENET_FPGA_INIT 0x4000 -#define CONFIG_SYS_ENET_FPGA_DONE 0x8000

-/*-----------------------------------------------------------------------

• • Chip Select Pin Function Select
• • 1 1 1 1 1 0 0 0 }- 0xf8
• • | | | | | | | |
• • | | | | | | | +--- Reserved
• • | | | | | | +----- GPCS1_SEL = ROMCS1#
• • | | | | | +------- GPCS2_SEL = ROMCS2#
• • | | | | +--------- GPCS3_SEL = GPCS3
• • | | | +----------- GPCS4_SEL = GPCS4
• • | | +------------- GPCS5_SEL = GPCS5
• • | +--------------- GPCS6_SEL = GPCS6
• • +----------------- GPCS7_SEL = GPCS7
• */

-#define CONFIG_SYS_SC520_CSPFS 0xf8

-/*-----------------------------------------------------------------------

• • Clock Select (CLKTIMER[CLKTEST] pin)
• • 0 111 00 1 0 }- 0x72
• • | \ / | | |
• • | | | | +--- Pin Disabled
• • | | | +----- Pin is an output
• • | | +------- Reserved
• • | +----------- Disabled (pin stays Low)
• • +-------------- Reserved
• */

-#define CONFIG_SYS_SC520_CLKSEL 0x72

-/*-----------------------------------------------------------------------

• • Address Decode Control
• • 0 00 0 0 0 0 0 }- 0x00
• • | | | | | | |
• • | | | | | | +--- Integrated UART 1 is enabled
• • | | | | | +----- Integrated UART 2 is enabled
• • | | | | +------- Integrated RTC is enabled
• • | | | +--------- Reserved
• • | | +----------- I/O Hole accesses are forwarded to the external GP

bus

• • | +------------- Reserved
• • +---------------- Write-protect violations do not generate an IRQ
• */

-#define CONFIG_SYS_SC520_ADDDECCTL 0x00

-/*-----------------------------------------------------------------------

• • UART Control
• • 00000 1 1 1 }- 0x07
• • ___/ | | |
• • | | | +--- Transmit TC interrupt enable
• • | | +----- Receive TC interrupt enable
• • | +------- 1.8432 MHz
• • +----------- Reserved
• */

-#define CONFIG_SYS_SC520_UART1CTL 0x07 -#define CONFIG_SYS_SC520_UART2CTL 0x07

-/*-----------------------------------------------------------------------

• • System Arbiter Control
• • 00000 1 1 0 }- 0x06
• • ___/ | | |
• • | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
• • | | +----- The system arbiter operates in concurrent mode
• • | +------- Park the PCI bus on the last master that acquired the

bus

• • +----------- Reserved
• */

-#define CONFIG_SYS_SC520_SYSARBCTL 0x06

-/*-----------------------------------------------------------------------

• • System Arbiter Master Enable
• • 00000000000 0 0 0 1 1 }- 0x06
• • _________/ | | | | |

• •  |      | | | | +--- PCI master REQ0 enabled (Ethernet 1)
    

• •  |      | | | +----- PCI master REQ1 enabled (Ethernet 2)
    

• •  |      | | +------- PCI master REQ2 disabled
    

• •  |      | +--------- PCI master REQ3 disabled
    

• •  |      +----------- PCI master REQ4 disabled
    

• •  +------------------ Reserved
    

• */

-#define CONFIG_SYS_SC520_SYSARBMENB 0x0003

-/*-----------------------------------------------------------------------

• • System Arbiter Master Enable
• • 0 0000 0 00 0000 1 000 }- 0x06
• • | __/ | | __/ | _/
• • | | | | | | +---- Reserved
• • | | | | | +------- Enable CPU-to-PCI bus write posting
• • | | | | +---------- Reserved
• • | | | +-------------- PCI bus reads to SDRAM are not automatically
• • | | | retried
• • | | +----------------- Target read FIFOs are not snooped during

write

• • | | transactions
• • | +-------------------- Reserved
• • +------------------------ Deassert the PCI bus reset signal
• */

-#define CONFIG_SYS_SC520_HBCTL 0x08

-/*-----------------------------------------------------------------------

• • PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
• • 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
• • \ / | | | | ----+----/ -----+------/
• • | | | | | | +---------- Start at 0x38000000
• • | | | | | +----------------------- 512kB Region Size
• • | | | | | ((7 + 1) * 64kB)
• • | | | | +------------------------------ 64kB Page Size
• • | | | +-------------------------------- Writes Enabled (So it can be
• • | | | reprogrammed!)
• • | | +---------------------------------- Caching Disabled
• • | +------------------------------------ Execution Enabled
• • +--------------------------------------- BOOTCS
• */

-#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800

-/*-----------------------------------------------------------------------

• • Cache-As-RAM (Targets Boot Flash)
• • 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
• • \ / | | | | --+--/ -------+--------/
• • | | | | | | +------------ Start at 0x19200000
• • | | | | | +------------------------- 64k Region Size
• • | | | | | ((15 + 1) * 4kB)
• • | | | | +------------------------------ 4kB Page Size
• • | | | +-------------------------------- Writes Enabled
• • | | +---------------------------------- Caching Enabled
• • | +------------------------------------ Execution Prevented
• • +--------------------------------------- BOOTCS
• */

-#define CONFIG_SYS_SC520_CAR_PAR 0x903d9200

-/*-----------------------------------------------------------------------

• • PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000,

GPCS6

• • 001 110 0 000100000 0001000000000000 }- 0x38201000
• • \ / \ / | ---+---/ ------+-------/
• • | | | | +----------- Start at 0x00001000
• • | | | +------------------------ 33 Bytes (0x20 + 1)
• • | | +------------------------------ Ignored
• • | +--------------------------------- GPCS6
• • +------------------------------------- GP Bus I/O
• */

-#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000

-/*-----------------------------------------------------------------------

• • PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
• • PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
• • 010 101 0 0000000 100000000000000000 }- 0x54020000
• • 010 111 0 0000000 100000000000000001 }- 0x5c020001
• • \ / \ / | --+--/ -------+--------/
• • | | | | +------------ Start at 0x200000000
• • | | | | 0x200010000
• • | | | +------------------------- 4kB Region Size
• • | | | ((0 + 1) * 4kB)
• • | | +------------------------------ 4k Page Size
• • | +--------------------------------- GPCS5
• • | GPCS7
• • +------------------------------------- GP Bus Memory
• */

-#define CONFIG_SYS_SC520_CF1_PAR 0x54020000 -#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001

-/*-----------------------------------------------------------------------

• • PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
• • PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
• • PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
• • PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
• • 001 000 0 000000111 0001001111111000 }- 0x200713f8
• • 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
• • 001 011 0 000000111 0001001011111000 }- 0x300711f8
• • 001 011 0 000000111 0001001011111000 }- 0x340710f8
• • \ / \ / | ---+---/ ------+-------/
• • | | | | +----------- Start at 0x013f8
• • | | | | 0x012f8
• • | | | | 0x011f8
• • | | | | 0x010f8
• • | | | +------------------------ 33 Bytes (32 + 1)
• • | | +------------------------------ Ignored
• • | +--------------------------------- GPCS6
• • +------------------------------------- GP Bus I/O
• */

-#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8 -#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8 -#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8 -#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8

-/*-----------------------------------------------------------------------

• • PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
• • PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
• • 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
• • 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
• • \ / | | | | ----+----/ -----+------/
• • | | | | | | +---------- Start at 0x10000000
• • | | | | | | 0x11000000
• • | | | | | +----------------------- 16MB Region Size
• • | | | | | ((255 + 1) * 64kB)
• • | | | | +------------------------------ 64kB Page Size
• • | | | +-------------------------------- Writes Enabled
• • | | +---------------------------------- Caching Disabled
• • | +------------------------------------ Execution Enabled
• • +--------------------------------------- ROMCS1

• •                                       ROMCS2
    

• */

-#define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000 -#define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100

-/*-----------------------------------------------------------------------

• • PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
• • PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
• • 010 000 1 00000001111 01100100000000 }- 0x4203d900
• • 010 011 1 00000001111 01100100010000 }- 0x4e03d910
• • \ / \ / | ----+----/ -----+------/
• • | | | | +---------- Start at 0x19000000
• • | | | | 0x19100000
• • | | | +----------------------- 1MB Region Size
• • | | | ((15 + 1) * 64kB)
• • | | +------------------------------ 64kB Page Size
• • | +--------------------------------- GPCS0
• • | GPCS3
• • +------------------------------------- GP Bus Memory
• */

-#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900 -#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910

-/*-----------------------------------------------------------------------

• • PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
• • 010 100 0 00000000 11000000100000000 }- 0x50018100
• • \ / \ / | ---+--/ -------+-------/
• • | | | | +----------- Start at 0x18100000
• • | | | +------------------------ 4kB Region Size
• • | | | ((0 + 1) * 4kB)
• • | | +------------------------------ 4kB Page Size
• • | +--------------------------------- GPCS4
• • +------------------------------------- GP Bus Memory
• */

-#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100

-#endif /* __CONFIG_H */

1.8.1

Acked-by: Gabe Black gabeblack@chromium.org

On Thu, Feb 14, 2013 at 6:18 AM, Simon Glass sjg@chromium.org wrote:

This x86 CPU variant is no longer required as the boards that use it have been removed.

Signed-off-by: Simon Glass sjg@chromium.org Acked-by: Graeme Russ graeme.russ@gmail.com

---

Changes in v2: None

arch/x86/cpu/sc520/Makefile | 58 ---- arch/x86/cpu/sc520/asm-offsets.c | 45 --- arch/x86/cpu/sc520/sc520.c | 66 ----- arch/x86/cpu/sc520/sc520_car.S | 94 ------- arch/x86/cpu/sc520/sc520_pci.c | 142 ---------- arch/x86/cpu/sc520/sc520_reset.c | 40 --- arch/x86/cpu/sc520/sc520_sdram.c | 479

---

arch/x86/cpu/sc520/sc520_ssi.c | 93 ------- arch/x86/cpu/sc520/sc520_timer.c | 89 ------ arch/x86/include/asm/arch-sc520/pci.h | 79 ------ arch/x86/include/asm/arch-sc520/sc520.h | 372 ------------------------- arch/x86/include/asm/arch-sc520/ssi.h | 34 --- 12 files changed, 1591 deletions(-) delete mode 100644 arch/x86/cpu/sc520/Makefile delete mode 100644 arch/x86/cpu/sc520/asm-offsets.c delete mode 100644 arch/x86/cpu/sc520/sc520.c delete mode 100644 arch/x86/cpu/sc520/sc520_car.S delete mode 100644 arch/x86/cpu/sc520/sc520_pci.c delete mode 100644 arch/x86/cpu/sc520/sc520_reset.c delete mode 100644 arch/x86/cpu/sc520/sc520_sdram.c delete mode 100644 arch/x86/cpu/sc520/sc520_ssi.c delete mode 100644 arch/x86/cpu/sc520/sc520_timer.c delete mode 100644 arch/x86/include/asm/arch-sc520/pci.h delete mode 100644 arch/x86/include/asm/arch-sc520/sc520.h delete mode 100644 arch/x86/include/asm/arch-sc520/ssi.h

diff --git a/arch/x86/cpu/sc520/Makefile b/arch/x86/cpu/sc520/Makefile deleted file mode 100644 index f462264..0000000 --- a/arch/x86/cpu/sc520/Makefile +++ /dev/null @@ -1,58 +0,0 @@ -# -# (C) Copyright 2008 -# Graeme Russ, graeme.russ@gmail.com. -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -#

-include $(TOPDIR)/config.mk

-LIB := $(obj)lib$(SOC).o

-COBJS-$(CONFIG_SYS_SC520) += sc520.o -COBJS-$(CONFIG_PCI) += sc520_pci.o -COBJS-$(CONFIG_SYS_SC520_RESET) += sc520_reset.o -COBJS-$(CONFIG_SYS_SC520) += sc520_sdram.o -COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o -COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o

-SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o

-SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

-all: $(obj).depend $(LIB)

-$(LIB): $(OBJS)

•   $(call cmd_link_o_target, $(OBJS))
  

-#########################################################################

-# defines $(obj).depend target -include $(SRCTREE)/rules.mk

-sinclude $(obj).depend

-######################################################################### \ No newline at end of file diff --git a/arch/x86/cpu/sc520/asm-offsets.c b/arch/x86/cpu/sc520/asm-offsets.c deleted file mode 100644 index 794f00c..0000000 --- a/arch/x86/cpu/sc520/asm-offsets.c +++ /dev/null @@ -1,45 +0,0 @@ -/*

• • Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
• • This program is used to generate definitions needed by
• • assembly language modules.
• • We use the technique used in the OSF Mach kernel code:
• • generate asm statements containing #defines,
• • compile this file to assembler, and then extract the
• • #defines from the assembly-language output.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License
• • as published by the Free Software Foundation; either version
• • 2 of the License, or (at your option) any later version.
• */

-#include <common.h> -#include <asm/arch/sc520.h>

-#include <linux/kbuild.h>

-int main(void) -{

•   DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off));
  

•   DEFINE(GENERATED_SC520_PAR0, offsetof(struct sc520_mmcr, par[0]));
  

•   DEFINE(GENERATED_SC520_PAR1, offsetof(struct sc520_mmcr, par[1]));
  

•   DEFINE(GENERATED_SC520_PAR2, offsetof(struct sc520_mmcr, par[2]));
  

•   DEFINE(GENERATED_SC520_PAR3, offsetof(struct sc520_mmcr, par[3]));
  

•   DEFINE(GENERATED_SC520_PAR4, offsetof(struct sc520_mmcr, par[4]));
  

•   DEFINE(GENERATED_SC520_PAR5, offsetof(struct sc520_mmcr, par[5]));
  

•   DEFINE(GENERATED_SC520_PAR6, offsetof(struct sc520_mmcr, par[6]));
  

•   DEFINE(GENERATED_SC520_PAR7, offsetof(struct sc520_mmcr, par[7]));
  

•   DEFINE(GENERATED_SC520_PAR8, offsetof(struct sc520_mmcr, par[8]));
  

•   DEFINE(GENERATED_SC520_PAR9, offsetof(struct sc520_mmcr, par[9]));
  

•   DEFINE(GENERATED_SC520_PAR10, offsetof(struct sc520_mmcr,
  

par[10]));

•   DEFINE(GENERATED_SC520_PAR11, offsetof(struct sc520_mmcr,
  

par[11]));

•   DEFINE(GENERATED_SC520_PAR12, offsetof(struct sc520_mmcr,
  

par[12]));

•   DEFINE(GENERATED_SC520_PAR13, offsetof(struct sc520_mmcr,
  

par[13]));

•   DEFINE(GENERATED_SC520_PAR14, offsetof(struct sc520_mmcr,
  

par[14]));

•   DEFINE(GENERATED_SC520_PAR15, offsetof(struct sc520_mmcr,
  

par[15]));

•   return 0;
  

-} diff --git a/arch/x86/cpu/sc520/sc520.c b/arch/x86/cpu/sc520/sc520.c deleted file mode 100644 index 3fe85e7..0000000 --- a/arch/x86/cpu/sc520/sc520.c +++ /dev/null @@ -1,66 +0,0 @@ -/*

• • (C) Copyright 2008-2011
• • Graeme Russ, graeme.russ@gmail.com
• • (C) Copyright 2002
• • Daniel Engström, Omicron Ceti AB, daniel@omicron.se
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#include <common.h> -#include <asm/io.h> -#include <asm/processor-flags.h> -#include <asm/arch/sc520.h>

-DECLARE_GLOBAL_DATA_PTR;

-sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;

-int cpu_init_f(void) -{

•   if (CONFIG_SYS_SC520_HIGH_SPEED) {
  

•           /* set it to 133 MHz and write back */
  

•           writeb(0x02, &sc520_mmcr->cpuctl);
  

•           gd->cpu_clk = 133000000;
  

•   } else {
  

•           /* set it to 100 MHz and write back */
  

•           writeb(0x01, &sc520_mmcr->cpuctl);
  

•           gd->cpu_clk = 100000000;
  

•   }
  

•   /* wait at least one millisecond */
  

•   asm("movl       $0x2000, %%ecx\n"
  

•       "0:         pushl %%ecx\n"
  

•       "popl       %%ecx\n"
  

•       "loop 0b\n" : : : "ecx");
  

•   return x86_cpu_init_f();
  

-}

-int cpu_init_r(void) -{

•   /* Disable the PAR used for CAR */
  

•   writel(0x0000000, &sc520_mmcr->par[2]);
  

•   /* turn on the SDRAM write buffer */
  

•   writeb(0x11, &sc520_mmcr->dbctl);
  

•   return x86_cpu_init_r();
  

-} diff --git a/arch/x86/cpu/sc520/sc520_car.S b/arch/x86/cpu/sc520/sc520_car.S deleted file mode 100644 index c04cc1f..0000000 --- a/arch/x86/cpu/sc520/sc520_car.S +++ /dev/null @@ -1,94 +0,0 @@ -/*

• • (C) Copyright 2010-2011
• • Graeme Russ, graeme.russ@gmail.com
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#include <config.h> -#include <asm/processor-flags.h> -#include <asm/arch/sc520.h> -#include <generated/asm-offsets.h>

-.section .text

-.globl car_init -car_init:

•   /*
  

•    * How to enable Cache-As-RAM for the AMD Elan SC520:
  

•    *  1. Turn off the CPU Cache (may not be strictly required)
  

•    *  2. Set code execution PAR (usually the BOOTCS region) to be
  

•    *     non-cachable
  

•    *  3. Create a Cachable PAR Region for an area of memory which is
  

•    *       a) NOT where the code is being executed
  

•    *       b) NOT SDRAM (Controller not initialised yet)
  

•    *       c) WILL response to read requests
  

•    *     The easiest way to do this is to create a second BOOTCS
  

•    *     PAR mappnig with an address != the PAR in step 2
  

•    *  4. Issue a wbinvd to invalidate the CPU cache
  

•    *  5. Turn on the CPU Cache
  

•    *  6. Read 16kB from the cached PAR region setup in step 3
  

•    *  7. Turn off the CPU Cache (but DO NOT issue a wbinvd)
  

•    *
  

•    * The following code uses PAR2 as the cached PAR (PAR0 and PAR1
  

•    * are avoided as these are the only two PARs which can be used
  

•    * as PCI BUS Memory regions which the board might require)
  

•    *
  

•    * The configuration of PAR2 must be set in the board configuration
  

•    * file as CONFIG_SYS_SC520_CAR_PAR
  

•    */
  

•   /* Configure Cache-As-RAM PAR */
  

•   movl    $CONFIG_SYS_SC520_CAR_PAR, %eax
  

•   movl    $(SC520_MMCR_BASE + GENERATED_SC520_PAR2), %edi
  

•   movl    %eax, (%edi)
  

•   /* Trash the cache then turn it on */
  

•   wbinvd
  

•   movl    %cr0, %eax
  

•   andl    $~(X86_CR0_NW | X86_CR0_CD), %eax
  

•   movl    %eax, %cr0
  

•   /*
  

•    * The cache is now enabled and empty. Map a region of memory to
  

•    * it by reading that region.
  

•    */
  

•   movl    $CONFIG_SYS_CAR_ADDR, %esi
  

•   movl    $CONFIG_SYS_CAR_SIZE, %ecx
  

•   shrl    $2, %ecx                        /* we are reading longs */
  

•   cld
  

•   rep     lodsl
  

•   /* Turn off the cache, but don't trash it */
  

•   movl    %cr0, %eax
  

•   orl     $(X86_CR0_NW | X86_CR0_CD), %eax
  

•   movl    %eax, %cr0
  

•   /* Clear the CAR region */
  

•   xorl    %eax, %eax
  

•   movl    $CONFIG_SYS_CAR_ADDR, %edi
  

•   movl    $CONFIG_SYS_CAR_SIZE, %ecx
  

•   shrl    $2, %ecx                        /* we are writing longs */
  

•   rep     stosl
  

•   /*
  

•    * Done - We should now have CONFIG_SYS_CAR_SIZE bytes of
  

•    * Cache-As-RAM
  

•    */
  

•   jmp     car_init_ret
  

diff --git a/arch/x86/cpu/sc520/sc520_pci.c b/arch/x86/cpu/sc520/sc520_pci.c deleted file mode 100644 index 52d07c1..0000000 --- a/arch/x86/cpu/sc520/sc520_pci.c +++ /dev/null @@ -1,142 +0,0 @@ -/*

• • (C) Copyright 2008-2011
• • Graeme Russ, graeme.russ@gmail.com
• • (C) Copyright 2002
• • Daniel Engström, Omicron Ceti AB, daniel@omicron.se
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#include <common.h> -#include <pci.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <asm/arch/pci.h> -#include <asm/arch/sc520.h>

-static struct {

•   u8 priority;
  

•   u16 level_reg;
  

•   u8 level_bit;
  

-} sc520_irq[] = {

•   { SC520_IRQ0,  0, 0x01 },
  

•   { SC520_IRQ1,  0, 0x02 },
  

•   { SC520_IRQ2,  1, 0x02 },
  

•   { SC520_IRQ3,  0, 0x08 },
  

•   { SC520_IRQ4,  0, 0x10 },
  

•   { SC520_IRQ5,  0, 0x20 },
  

•   { SC520_IRQ6,  0, 0x40 },
  

•   { SC520_IRQ7,  0, 0x80 },
  

•   { SC520_IRQ8,  1, 0x01 },
  

•   { SC520_IRQ9,  1, 0x02 },
  

•   { SC520_IRQ10, 1, 0x04 },
  

•   { SC520_IRQ11, 1, 0x08 },
  

•   { SC520_IRQ12, 1, 0x10 },
  

•   { SC520_IRQ13, 1, 0x20 },
  

•   { SC520_IRQ14, 1, 0x40 },
  

•   { SC520_IRQ15, 1, 0x80 }
  

-};

-/* The interrupt used for PCI INTA-INTD */ -int sc520_pci_ints[15] = {

•   -1, -1, -1, -1, -1, -1, -1, -1,
  

•           -1, -1, -1, -1, -1, -1, -1
  

-};

-/* utility function to configure a pci interrupt */ -int pci_sc520_set_irq(int pci_pin, int irq) -{

•   int i;
  

•   u8 tmpb;
  

•   u16 tmpw;
  

•   debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
  

•   if (irq < 0 || irq > 15)
  

•           return -1; /* illegal irq */
  

•   if (pci_pin < 0 || pci_pin > 15)
  

•           return -1; /* illegal pci int pin */
  

•   /* first disable any non-pci interrupt source that use
  

•    * this level */
  

•   /* PCI interrupt mapping (A through D)*/
  

•   for (i = 0; i <= 3 ; i++) {
  

•           tmpb = readb(&sc520_mmcr->pci_int_map[i]);
  

•           if (tmpb == sc520_irq[irq].priority)
  

•                   writeb(SC520_IRQ_DISABLED,
  

&sc520_mmcr->pci_int_map[i]);

•   }
  

•   /* GP IRQ interrupt mapping */
  

•   for (i = 0; i <= 10 ; i++) {
  

•           tmpb = readb(&sc520_mmcr->gp_int_map[i]);
  

•           if (tmpb == sc520_irq[irq].priority)
  

•                   writeb(SC520_IRQ_DISABLED,
  

&sc520_mmcr->gp_int_map[i]);

•   }
  

•   /* Set the trigger to level */
  

•   tmpb = readb(&sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
  

•   tmpb |= sc520_irq[irq].level_bit;
  

•   writeb(tmpb, &sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
  

•   if (pci_pin < 4) {
  

•           /* PCI INTA-INTD */
  

•           /* route the interrupt */
  

•           writeb(sc520_irq[irq].priority,
  

•                           &sc520_mmcr->pci_int_map[pci_pin]);
  

•   } else {
  

•           /* GPIRQ0-GPIRQ10 used for additional PCI INTS */
  

•           writeb(sc520_irq[irq].priority,
  

•                           &sc520_mmcr->gp_int_map[pci_pin - 4]);
  

•           /* also set the polarity in this case */
  

•           tmpw = readw(&sc520_mmcr->intpinpol);
  

•           tmpw |= (1 << (pci_pin-4));
  

•           writew(tmpw, &sc520_mmcr->intpinpol);
  

•   }
  

•   /* register the pin */
  

•   sc520_pci_ints[pci_pin] = irq;
  

•   return 0; /* OK */
  

-}

-void pci_sc520_init(struct pci_controller *hose) -{

•   hose->first_busno = 0;
  

•   hose->last_busno = 0xff;
  

•   hose->region_count = pci_set_regions(hose);
  

•   pci_setup_type1(hose);
  

•   pci_register_hose(hose);
  

•   hose->last_busno = pci_hose_scan(hose);
  

•   /* enable target memory acceses on host brige */
  

•   pci_write_config_word(0, PCI_COMMAND,
  

•                         PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  

-} diff --git a/arch/x86/cpu/sc520/sc520_reset.c b/arch/x86/cpu/sc520/sc520_reset.c deleted file mode 100644 index 137af97..0000000 --- a/arch/x86/cpu/sc520/sc520_reset.c +++ /dev/null @@ -1,40 +0,0 @@ -/*

• • (C) Copyright 2011
• • Graeme Russ, graeme.russ@gmail.com
• • (C) Copyright 2002
• • Daniel Engström, Omicron Ceti AB, daniel@omicron.se
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#include <common.h> -#include <asm/io.h> -#include <asm/arch/sc520.h>

-DECLARE_GLOBAL_DATA_PTR;

-void reset_cpu(ulong addr) -{

•   printf("Resetting using SC520 MMCR\n");
  

•   /* Write a '1' to the SYS_RST of the RESCFG MMCR */
  

•   writeb(0x01, &sc520_mmcr->rescfg);
  

•   /* NOTREACHED */
  

-} diff --git a/arch/x86/cpu/sc520/sc520_sdram.c b/arch/x86/cpu/sc520/sc520_sdram.c deleted file mode 100644 index 9dc1334..0000000 --- a/arch/x86/cpu/sc520/sc520_sdram.c +++ /dev/null @@ -1,479 +0,0 @@ -/*

• • (C) Copyright 2010,2011
• • Graeme Russ, graeme.russ@gmail.com
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#include <common.h> -#include <asm/io.h> -#include <asm/processor-flags.h> -#include <asm/arch/sc520.h>

-DECLARE_GLOBAL_DATA_PTR;

-struct sc520_sdram_info {

•   u8 banks;
  

•   u8 columns;
  

•   u8 rows;
  

•   u8 size;
  

-};

-static void sc520_sizemem(void); -static void sc520_set_dram_timing(void); -static void sc520_set_dram_refresh_rate(void); -static void sc520_enable_dram_refresh(void); -static void sc520_enable_sdram(void);

-int dram_init_f(void) -{

•   sc520_sizemem();
  

•   sc520_set_dram_timing();
  

•   sc520_set_dram_refresh_rate();
  

•   sc520_enable_dram_refresh();
  

•   sc520_enable_sdram();
  

•   return 0;
  

-}

-static inline void sc520_dummy_write(void) -{

•   writew(0x0000, CACHELINESZ);
  

-} -static inline void sc520_issue_sdram_op_mode_select(u8 command) -{

•   writeb(command, &sc520_mmcr->drcctl);
  

•   sc520_dummy_write();
  

-}

-static inline int check_long(u32 test_long) -{

•   u8 i;
  

•   u8 tmp_byte = (u8)(test_long & 0x000000ff);
  

•   for (i = 1; i < 4; i++) {
  

•           if ((u8)((test_long >> (i * 8)) & 0x000000ff) != tmp_byte)
  

•                           return -1;
  

•   }
  

•   return 0;
  

-}

-static inline int write_and_test(u32 data, u32 address) -{

•   writel(data, address);
  

•   if (readl(address) == data)
  

•           return 0; /* Good */
  

•   else
  

•           return -1; /* Bad */
  

-}

-static void sc520_enable_sdram(void) -{

•   u32 par_config;
  

•   /* Enable Writes, Caching and Code Execution to SDRAM */
  

•   par_config = readl(&sc520_mmcr->par[3]);
  

•   par_config &= ~(SC520_PAR_EXEC_DIS |
  

•                   SC520_PAR_CACHE_DIS |
  

•                   SC520_PAR_WRITE_DIS);
  

•   writel(par_config, &sc520_mmcr->par[3]);
  

•   par_config = readl(&sc520_mmcr->par[4]);
  

•   par_config &= ~(SC520_PAR_EXEC_DIS |
  

•                   SC520_PAR_CACHE_DIS |
  

•                   SC520_PAR_WRITE_DIS);
  

•   writel(par_config, &sc520_mmcr->par[4]);
  

-}

-static void sc520_set_dram_timing(void) -{

•   u8 drctmctl = 0x00;
  

-#if defined CONFIG_SYS_SDRAM_DRCTMCTL

•   /* just have your hardware designer _GIVE_ you what you need here!
  

*/

•   drctmctl = CONFIG_SYS_SDRAM_DRCTMCTL;
  

-#else

•   switch (CONFIG_SYS_SDRAM_RAS_CAS_DELAY) {
  

•   case 2:
  

•           break;
  

•   case 3:
  

•           drctmctl |= 0x01;
  

•           break;
  

•   case 4:
  

•   default:
  

•           drctmctl |= 0x02;
  

•           break;
  

•   }
  

•   switch (CONFIG_SYS_SDRAM_PRECHARGE_DELAY) {
  

•   case 2:
  

•           break;
  

•   case 3:
  

•           drctmctl |= 0x04;
  

•           break;
  

•   case 4:
  

•   default:
  

•           drctmctl |= 0x08;
  

•           break;
  

•   case 6:
  

•           drctmctl |= 0x0c;
  

•           break;
  

•   }
  

•   switch (CONFIG_SYS_SDRAM_CAS_LATENCY) {
  

•   case 2:
  

•           break;
  

•   case 3:
  

•   default:
  

•           drctmctl |= 0x10;
  

•           break;
  

•   }
  

-#endif

•   writeb(drctmctl, &sc520_mmcr->drctmctl);
  

•   /* Issue load mode register command */
  

•   sc520_issue_sdram_op_mode_select(0x03);
  

-}

-static void sc520_set_dram_refresh_rate(void) -{

•   u8 drctl;
  

•   drctl = readb(&sc520_mmcr->drcctl);
  

•   drctl &= 0xcf;
  

•   switch (CONFIG_SYS_SDRAM_REFRESH_RATE) {
  

•   case 78:
  

•           break;
  

•   case 156:
  

•   default:
  

•           drctl |= 0x10;
  

•           break;
  

•   case 312:
  

•           drctl |= 0x20;
  

•           break;
  

•   case 624:
  

•           drctl |= 0x30;
  

•           break;
  

•   }
  

•   writeb(drctl, &sc520_mmcr->drcctl);
  

-}

-static void sc520_enable_dram_refresh(void) -{

•   u8 drctl;
  

•   drctl = readb(&sc520_mmcr->drcctl);
  

•   drctl &= 0x30; /* keep refresh rate */
  

•   drctl |= 0x08; /* enable refresh, normal mode */
  

•   writeb(drctl, &sc520_mmcr->drcctl);
  

-}

-static void sc520_get_bank_info(int bank, struct sc520_sdram_info *bank_info) -{

•   u32 col_data;
  

•   u32 row_data;
  

•   u32 drcbendadr;
  

•   u16 drccfg;
  

•   u8 banks = 0x00;
  

•   u8 columns = 0x00;
  

•   u8 rows = 0x00;
  

•   bank_info->banks = 0x00;
  

•   bank_info->columns = 0x00;
  

•   bank_info->rows = 0x00;
  

•   bank_info->size = 0x00;
  

•   if ((bank < 0) || (bank > 3)) {
  

•           printf("Bad Bank ID\n");
  

•           return;
  

•   }
  

•   /* Save configuration */
  

•   drcbendadr = readl(&sc520_mmcr->drcbendadr);
  

•   drccfg = readw(&sc520_mmcr->drccfg);
  

•   /* Setup SDRAM Bank to largest possible size */
  

•   writew(0x000b << (bank * 4), &sc520_mmcr->drccfg);
  

•   /* Set ending address for this bank */
  

•   writel(0x000000ff << (bank * 8), &sc520_mmcr->drcbendadr);
  

•   /* write col 11 wrap adr */
  

•   if (write_and_test(COL11_DATA, COL11_ADR) != 0)
  

•           goto restore_and_exit;
  

•   /* write col 10 wrap adr */
  

•   if (write_and_test(COL10_DATA, COL10_ADR) != 0)
  

•           goto restore_and_exit;
  

•   /* write col 9 wrap adr */
  

•   if (write_and_test(COL09_DATA, COL09_ADR) != 0)
  

•           goto restore_and_exit;
  

•   /* write col 8 wrap adr */
  

•   if (write_and_test(COL08_DATA, COL08_ADR) != 0)
  

•           goto restore_and_exit;
  

•   col_data = readl(COL11_ADR);
  

•   /* All four bytes in the read long must be the same */
  

•   if (check_long(col_data) < 0)
  

•           goto restore_and_exit;
  

•   if ((col_data >= COL08_DATA) && (col_data <= COL11_DATA))
  

•           columns = (u8)(col_data & 0x000000ff);
  

•   else
  

•           goto restore_and_exit;
  

•   /* write row 14 wrap adr */
  

•   if (write_and_test(ROW14_DATA, ROW14_ADR) != 0)
  

•           goto restore_and_exit;
  

•   /* write row 13 wrap adr */
  

•   if (write_and_test(ROW13_DATA, ROW13_ADR) != 0)
  

•           goto restore_and_exit;
  

•   /* write row 12 wrap adr */
  

•   if (write_and_test(ROW12_DATA, ROW12_ADR) != 0)
  

•           goto restore_and_exit;
  

•   /* write row 11 wrap adr */
  

•   if (write_and_test(ROW11_DATA, ROW11_ADR) != 0)
  

•           goto restore_and_exit;
  

•   if (write_and_test(ROW10_DATA, ROW10_ADR) != 0)
  

•           goto restore_and_exit;
  

•   /*
  

•    * read data @ row 12 wrap adr to determine number of banks,
  

•    * and read data @ row 14 wrap adr to determine number of rows.
  

•    * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
  

•    * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
  

•    * if data @ row 12 wrap == 11 or 12, we have 4 banks,
  

•    */
  

•   row_data = readl(ROW12_ADR);
  

•   /* All four bytes in the read long must be the same */
  

•   if (check_long(row_data) != 0)
  

•           goto restore_and_exit;
  

•   switch (row_data) {
  

•   case ROW10_DATA:
  

•           banks = 2;
  

•           break;
  

•   case ROW11_DATA:
  

•   case ROW12_DATA:
  

•           banks = 4;
  

•           break;
  

•   default:
  

•           goto restore_and_exit;
  

•   }
  

•   row_data = readl(ROW14_ADR);
  

•   /* All four bytes in the read long must be the same */
  

•   if (check_long(row_data) != 0)
  

•           goto restore_and_exit;
  

•   switch (row_data) {
  

•   case ROW11_DATA:
  

•   case ROW12_DATA:
  

•   case ROW13_DATA:
  

•   case ROW14_DATA:
  

•           rows = (u8)(row_data & 0x000000ff);
  

•           break;
  

•   default:
  

•           goto restore_and_exit;
  

•   }
  

•   bank_info->banks = banks;
  

•   bank_info->columns = columns;
  

•   bank_info->rows = rows;
  

•   if ((bank_info->banks != 0) &&
  

•       (bank_info->columns != 0) &&
  

•       (bank_info->rows != 0)) {
  

•           bank_info->size = bank_info->rows;
  

•           bank_info->size >>= (11 - bank_info->columns);
  

•           bank_info->size++;
  

•   }
  

-restore_and_exit:

•   /* Restore configuration */
  

•   writel(drcbendadr, &sc520_mmcr->drcbendadr);
  

•   writew(drccfg, &sc520_mmcr->drccfg);
  

-}

-static void sc520_setup_sizemem(void) -{

•   u8 i;
  

•   /* Disable write buffer */
  

•   writeb(0x00, &sc520_mmcr->dbctl);
  

•   /* Disable ECC */
  

•   writeb(0x00, &sc520_mmcr->eccctl);
  

•   /* Set slowest SDRAM timing */
  

•   writeb(0x1e, &sc520_mmcr->drctmctl);
  

•   /* Issue a NOP to all SDRAM banks */
  

•   sc520_issue_sdram_op_mode_select(0x01);
  

•   /* Delay for 100 microseconds */
  

•   udelay(100);
  

•   /* Issue 'All Banks Precharge' command */
  

•   sc520_issue_sdram_op_mode_select(0x02);
  

•   /* Issue 2 'Auto Refresh Enable' command */
  

•   sc520_issue_sdram_op_mode_select(0x04);
  

•   sc520_dummy_write();
  

•   /* Issue 'Load Mode Register' command */
  

•   sc520_issue_sdram_op_mode_select(0x03);
  

•   /* Issue 8 more 'Auto Refresh Enable' commands */
  

•   sc520_issue_sdram_op_mode_select(0x04);
  

•   for (i = 0; i < 7; i++)
  

•           sc520_dummy_write();
  

•   /* Set control register to 'Normal Mode' */
  

•   writeb(0x00, &sc520_mmcr->drcctl);
  

-}

-static void sc520_sizemem(void) -{

•   struct sc520_sdram_info sdram_info[4];
  

•   u8 bank_config = 0x00;
  

•   u8 end_addr = 0x00;
  

•   u16 drccfg = 0x0000;
  

•   u32 drcbendadr = 0x00000000;
  

•   u8 i;
  

•   /* Use PARs to disable caching of maximum allowable 256MB SDRAM */
  

•   writel(SC520_SDRAM1_PAR | SC520_PAR_CACHE_DIS,
  

&sc520_mmcr->par[3]);

•   writel(SC520_SDRAM2_PAR | SC520_PAR_CACHE_DIS,
  

&sc520_mmcr->par[4]);

•   sc520_setup_sizemem();
  

•   gd->ram_size = 0;
  

•   /* Size each SDRAM bank */
  

•   for (i = 0; i <= 3; i++) {
  

•           sc520_get_bank_info(i, &sdram_info[i]);
  

•           if (sdram_info[i].banks != 0) {
  

•                   /* Update Configuration register */
  

•                   bank_config = sdram_info[i].columns - 8;
  

•                   if (sdram_info[i].banks == 4)
  

•                           bank_config |= 0x08;
  

•                   drccfg |= bank_config << (i * 4);
  

•                   /* Update End Address register */
  

•                   end_addr += sdram_info[i].size;
  

•                   drcbendadr |= (end_addr | 0x80) << (i * 8);
  

•                   gd->ram_size += sdram_info[i].size << 22;
  

•           }
  

•           /* Issue 'All Banks Precharge' command */
  

•           sc520_issue_sdram_op_mode_select(0x02);
  

•           /* Set control register to 'Normal Mode' */
  

•           writeb(0x00, &sc520_mmcr->drcctl);
  

•   }
  

•   writel(drcbendadr, &sc520_mmcr->drcbendadr);
  

•   writew(drccfg, &sc520_mmcr->drccfg);
  

•   /* Clear PARs preventing caching of SDRAM */
  

•   writel(0x00000000, &sc520_mmcr->par[3]);
  

•   writel(0x00000000, &sc520_mmcr->par[4]);
  

-}

-int dram_init(void) -{

•   ulong dram_ctrl;
  

•   ulong dram_present = 0x00000000;
  

•   /*
  

•    * We read-back the configuration of the dram
  

•    * controller that the assembly code wrote
  

•    */
  

•   dram_ctrl = readl(&sc520_mmcr->drcbendadr);
  

•   gd->bd->bi_dram[0].start = 0;
  

•   if (dram_ctrl & 0x80) {
  

•           /* bank 0 enabled */
  

•           gd->bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
  

•           dram_present = gd->bd->bi_dram[1].start;
  

•           gd->bd->bi_dram[0].size = gd->bd->bi_dram[1].start;
  

•   } else {
  

•           gd->bd->bi_dram[0].size = 0;
  

•           gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start;
  

•   }
  

•   if (dram_ctrl & 0x8000) {
  

•           /* bank 1 enabled */
  

•           gd->bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
  

•           dram_present = gd->bd->bi_dram[2].start;
  

•           gd->bd->bi_dram[1].size = gd->bd->bi_dram[2].start -
  

•                           gd->bd->bi_dram[1].start;
  

•   } else {
  

•           gd->bd->bi_dram[1].size = 0;
  

•           gd->bd->bi_dram[2].start = gd->bd->bi_dram[1].start;
  

•   }
  

•   if (dram_ctrl & 0x800000) {
  

•           /* bank 2 enabled */
  

•           gd->bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
  

•           dram_present = gd->bd->bi_dram[3].start;
  

•           gd->bd->bi_dram[2].size = gd->bd->bi_dram[3].start -
  

•                           gd->bd->bi_dram[2].start;
  

•   } else {
  

•           gd->bd->bi_dram[2].size = 0;
  

•           gd->bd->bi_dram[3].start = gd->bd->bi_dram[2].start;
  

•   }
  

•   if (dram_ctrl & 0x80000000) {
  

•           /* bank 3 enabled */
  

•           dram_present  = (dram_ctrl & 0x7f000000) >> 2;
  

•           gd->bd->bi_dram[3].size = dram_present -
  

•                           gd->bd->bi_dram[3].start;
  

•   } else {
  

•           gd->bd->bi_dram[3].size = 0;
  

•   }
  

•   gd->ram_size = dram_present;
  

•   return 0;
  

-} diff --git a/arch/x86/cpu/sc520/sc520_ssi.c b/arch/x86/cpu/sc520/sc520_ssi.c deleted file mode 100644 index cc601e5..0000000 --- a/arch/x86/cpu/sc520/sc520_ssi.c +++ /dev/null @@ -1,93 +0,0 @@ -/*

• • (C) Copyright 2002
• • Daniel Engström, Omicron Ceti AB, daniel@omicron.se
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#include <common.h> -#include <asm/io.h> -#include <asm/arch/ssi.h> -#include <asm/arch/sc520.h>

-int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) -{

•   u8 temp = 0;
  

•   if (freq >= 8192)
  

•           temp |= CTL_CLK_SEL_4;
  

•   else if (freq >= 4096)
  

•           temp |= CTL_CLK_SEL_8;
  

•   else if (freq >= 2048)
  

•           temp |= CTL_CLK_SEL_16;
  

•   else if (freq >= 1024)
  

•           temp |= CTL_CLK_SEL_32;
  

•   else if (freq >= 512)
  

•           temp |= CTL_CLK_SEL_64;
  

•   else if (freq >= 256)
  

•           temp |= CTL_CLK_SEL_128;
  

•   else if (freq >= 128)
  

•           temp |= CTL_CLK_SEL_256;
  

•   else
  

•           temp |= CTL_CLK_SEL_512;
  

•   if (!lsb_first)
  

•           temp |= MSBF_ENB;
  

•   if (inv_clock)
  

•           temp |= CLK_INV_ENB;
  

•   if (inv_phase)
  

•           temp |= PHS_INV_ENB;
  

•   writeb(temp, &sc520_mmcr->ssictl);
  

•   return 0;
  

-}

-u8 ssi_txrx_byte(u8 data) -{

•   writeb(data, &sc520_mmcr->ssixmit);
  

•   while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
  

•           ;
  

•   writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd);
  

•   while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
  

•           ;
  

•   return readb(&sc520_mmcr->ssircv);
  

-}

-void ssi_tx_byte(u8 data) -{

•   writeb(data, &sc520_mmcr->ssixmit);
  

•   while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
  

•           ;
  

•   writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd);
  

-}

-u8 ssi_rx_byte(void) -{

•   while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
  

•           ;
  

•   writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd);
  

•   while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
  

•           ;
  

•   return readb(&sc520_mmcr->ssircv);
  

-} diff --git a/arch/x86/cpu/sc520/sc520_timer.c b/arch/x86/cpu/sc520/sc520_timer.c deleted file mode 100644 index 41f121f..0000000 --- a/arch/x86/cpu/sc520/sc520_timer.c +++ /dev/null @@ -1,89 +0,0 @@ -/*

• • (C) Copyright 2008-2011
• • Graeme Russ, graeme.russ@gmail.com
• • (C) Copyright 2002
• • Daniel Engström, Omicron Ceti AB, daniel@omicron.se
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#include <common.h> -#include <asm/io.h> -#include <asm/interrupt.h> -#include <asm/arch/sc520.h>

-void sc520_timer_isr(void) -{

•   /* Ack the GP Timer Interrupt */
  

•   writeb(0x02, &sc520_mmcr->gptmrsta);
  

-}

-int timer_init(void) -{

•   /* Register the SC520 specific timer interrupt handler */
  

•   register_timer_isr(sc520_timer_isr);
  

•   /* Install interrupt handler for GP Timer 1 */
  

•   irq_install_handler (0, timer_isr, NULL);
  

•   /* Map GP Timer 1 to Master PIC IR0  */
  

•   writeb(0x01, &sc520_mmcr->gp_tmr_int_map[1]);
  

•   /* Disable GP Timers 1 & 2 - Allow configuration writes */
  

•   writew(0x4000, &sc520_mmcr->gptmr1ctl);
  

•   writew(0x4000, &sc520_mmcr->gptmr2ctl);
  

•   /* Reset GP Timers 1 & 2 */
  

•   writew(0x0000, &sc520_mmcr->gptmr1cnt);
  

•   writew(0x0000, &sc520_mmcr->gptmr2cnt);
  

•   /* Setup GP Timer 2 as a 100kHz (10us) prescaler */
  

•   writew(83, &sc520_mmcr->gptmr2maxcmpa);
  

•   writew(0xc001, &sc520_mmcr->gptmr2ctl);
  

•   /* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
  

•   writew(100, &sc520_mmcr->gptmr1maxcmpa);
  

•   writew(0xe009, &sc520_mmcr->gptmr1ctl);
  

•   unmask_irq(0);
  

•   /* Clear the GP Timer 1 status register to get the show rolling*/
  

•   writeb(0x02, &sc520_mmcr->gptmrsta);
  

•   return 0;
  

-}

-/* Allow boards to override udelay implementation */ -void __udelay(unsigned long usec)

•   __attribute__((weak, alias("sc520_udelay")));
  

-void sc520_udelay(unsigned long usec) -{

•   int m = 0;
  

•   long u;
  

•   readw(&sc520_mmcr->swtmrmilli);
  

•   readw(&sc520_mmcr->swtmrmicro);
  

•   do {
  

•           m += readw(&sc520_mmcr->swtmrmilli);
  

•           u = readw(&sc520_mmcr->swtmrmicro) + (m * 1000);
  

•   } while (u < usec);
  

-} diff --git a/arch/x86/include/asm/arch-sc520/pci.h b/arch/x86/include/asm/arch-sc520/pci.h deleted file mode 100644 index 12ba656..0000000 --- a/arch/x86/include/asm/arch-sc520/pci.h +++ /dev/null @@ -1,79 +0,0 @@ -/*

• • (C) Copyright 2002
• • Daniel Engström, Omicron Ceti AB daniel@omicron.se.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#ifndef _ASM_IC_SC520_PCI_H_ -#define _ASM_IC_SC520_PCI_H_ 1

-/* bus mapping constants (used for PCI core initialization) */

                                                           /* bus

mapping constants */ -#define SC520_REG_ADDR 0x00000cf8 -#define SC520_REG_DATA 0x00000cfc

-#define SC520_ISA_MEM_PHYS 0x00000000 -#define SC520_ISA_MEM_BUS 0x00000000 -#define SC520_ISA_MEM_SIZE 0x01000000

-#define SC520_ISA_IO_PHYS 0x00000000 -#define SC520_ISA_IO_BUS 0x00000000 -#define SC520_ISA_IO_SIZE 0x00001000

-/* PCI I/O space from 0x1000 to 0xdfff

• • (make 0xe000-0xfdff available for stuff like PCCard boot) */

-#define SC520_PCI_IO_PHYS 0x00001000 -#define SC520_PCI_IO_BUS 0x00001000 -#define SC520_PCI_IO_SIZE 0x0000d000

-/* system memory from 0x00000000 to 0x0fffffff */ -#define SC520_PCI_MEMORY_PHYS 0x00000000 -#define SC520_PCI_MEMORY_BUS 0x00000000 -#define SC520_PCI_MEMORY_SIZE 0x10000000

-/* PCI bus memory from 0x10000000 to 0x26ffffff

• • (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */

-#define SC520_PCI_MEM_PHYS 0x10000000 -#define SC520_PCI_MEM_BUS 0x10000000 -#define SC520_PCI_MEM_SIZE 0x17000000

-/* pin number used for PCI interrupt mappings */ -#define SC520_PCI_INTA 0 -#define SC520_PCI_INTB 1 -#define SC520_PCI_INTC 2 -#define SC520_PCI_INTD 3 -#define SC520_PCI_GPIRQ0 4 -#define SC520_PCI_GPIRQ1 5 -#define SC520_PCI_GPIRQ2 6 -#define SC520_PCI_GPIRQ3 7 -#define SC520_PCI_GPIRQ4 8 -#define SC520_PCI_GPIRQ5 9 -#define SC520_PCI_GPIRQ6 10 -#define SC520_PCI_GPIRQ7 11 -#define SC520_PCI_GPIRQ8 12 -#define SC520_PCI_GPIRQ9 13 -#define SC520_PCI_GPIRQ10 14

-extern int sc520_pci_ints[];

-void pci_sc520_init(struct pci_controller *hose); -int pci_set_regions(struct pci_controller *hose); -int pci_sc520_set_irq(int pci_pin, int irq);

-#endif diff --git a/arch/x86/include/asm/arch-sc520/sc520.h b/arch/x86/include/asm/arch-sc520/sc520.h deleted file mode 100644 index 9dc29d3..0000000 --- a/arch/x86/include/asm/arch-sc520/sc520.h +++ /dev/null @@ -1,372 +0,0 @@ -/*

• • (C) Copyright 2002
• • Daniel Engström, Omicron Ceti AB daniel@omicron.se.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#ifndef _ASM_IC_SC520_H_ -#define _ASM_IC_SC520_H_ 1

-#ifndef __ASSEMBLY__

-void init_sc520(void); -unsigned long init_sc520_dram(void); -void sc520_udelay(unsigned long usec);

-/* Memory mapped configuration registers */ -typedef struct sc520_mmcr {

•   u16 revid;      /* ElanSC520 microcontroller revision id */
  

•   u8  cpuctl;     /* am5x86 CPU control  */
  

•   u8  pad_0x003[0x0d];
  

•   u8  drcctl;             /* SDRAM control */
  

•   u8  pad_0x011[0x01];
  

•   u8  drctmctl;           /* SDRAM timing control */
  

•   u8  pad_0x013[0x01];
  

•   u16 drccfg;             /* SDRAM bank configuration*/
  

•   u8  pad_0x016[0x02];
  

•   u32 drcbendadr;         /* SDRAM bank 0-3 ending address*/
  

•   u8  pad_0x01c[0x04];
  

•   u8  eccctl;             /* ECC control */
  

•   u8  eccsta;             /* ECC status */
  

•   u8  eccckbpos;          /* ECC check bit position */
  

•   u8  ecccktest;          /* ECC Check Code Test */
  

•   u32 eccsbadd;           /* ECC single-bit error address */
  

•   u32 eccmbadd;           /* ECC multi-bit error address */
  

•   u8  pad_0x02c[0x14];
  

•   u8  dbctl;              /* SDRAM buffer control */
  

•   u8  pad_0x041[0x0f];
  

•   u16 bootcsctl;          /* /BOOTCS control */
  

•   u8  pad_0x052[0x02];
  

•   u16 romcs1ctl;          /* /ROMCS1 control */
  

•   u16 romcs2ctl;          /* /ROMCS2 control */
  

•   u8  pad_0x058[0x08];
  

•   u16 hbctl;              /* host bridge control */
  

•   u16 hbtgtirqctl;        /* host bridge target interrupt control */
  

•   u16 hbtgtirqsta;        /* host bridge target interrupt status */
  

•   u16 hbmstirqctl;        /* host bridge target interrupt control */
  

•   u16 hbmstirqsta;        /* host bridge master interrupt status */
  

•   u8  pad_0x06a[0x02];
  

•   u32 mstintadd;          /* host bridge master interrupt address */
  

•   u8  sysarbctl;          /* system arbiter control */
  

•   u8  pciarbsta;          /* PCI bus arbiter status */
  

•   u16 sysarbmenb;         /* system arbiter master enable */
  

•   u32 arbprictl;          /* arbiter priority control */
  

•   u8  pad_0x078[0x08];
  

•   u8  adddecctl;          /* address decode control */
  

•   u8  pad_0x081[0x01];
  

•   u16 wpvsta;             /* write-protect violation status */
  

•   u8  pad_0x084[0x04];
  

•   u32 par[16];            /* programmable address regions */
  

•   u8  pad_0x0c8[0x0b38];
  

•   u8  gpecho;             /* GP echo mode */
  

•   u8  gpcsdw;             /* GP chip select data width */
  

•   u16 gpcsqual;           /* GP chip select qualification */
  

•   u8  pad_0xc04[0x4];
  

•   u8  gpcsrt;             /* GP chip select recovery time */
  

•   u8  gpcspw;             /* GP chip select pulse width */
  

•   u8  gpcsoff;            /* GP chip select offset */
  

•   u8  gprdw;              /* GP read pulse width */
  

•   u8  gprdoff;            /* GP read offset */
  

•   u8  gpwrw;              /* GP write pulse width */
  

•   u8  gpwroff;            /* GP write offset */
  

•   u8  gpalew;             /* GP ale pulse width */
  

•   u8  gpaleoff;           /* GP ale offset */
  

•   u8  pad_0xc11[0x0f];
  

•   u16 piopfs15_0;         /* PIO15-PIO0 pin function select */
  

•   u16 piopfs31_16;        /* PIO31-PIO16 pin function select */
  

•   u8  cspfs;              /* chip select pin function select */
  

•   u8  pad_0xc25[0x01];
  

•   u8  clksel;             /* clock select */
  

•   u8  pad_0xc27[0x01];
  

•   u16 dsctl;              /* drive strength control */
  

•   u16 piodir15_0;         /* PIO15-PIO0 direction */
  

•   u16 piodir31_16;        /* PIO31-PIO16 direction */
  

•   u8  pad_0xc2e[0x02];
  

•   u16 piodata15_0 ;       /* PIO15-PIO0 data */
  

•   u16 piodata31_16;       /* PIO31-PIO16 data */
  

•   u16 pioset15_0;         /* PIO15-PIO0 set */
  

•   u16 pioset31_16;        /* PIO31-PIO16 set */
  

•   u16 pioclr15_0;         /* PIO15-PIO0 clear */
  

•   u16 pioclr31_16;        /* PIO31-PIO16 clear */
  

•   u8  pad_0xc3c[0x24];
  

•   u16 swtmrmilli;         /* software timer millisecond count */
  

•   u16 swtmrmicro;         /* software timer microsecond count */
  

•   u8  swtmrcfg;           /* software timer configuration */
  

•   u8  pad_0xc65[0x0b];
  

•   u8  gptmrsta;           /* GP timers status register */
  

•   u8  pad_0xc71;
  

•   u16 gptmr0ctl;          /* GP timer 0 mode/control */
  

•   u16 gptmr0cnt;          /* GP timer 0 count */
  

•   u16 gptmr0maxcmpa;      /* GP timer 0 maxcount compare A */
  

•   u16 gptmr0maxcmpb;      /* GP timer 0 maxcount compare B */
  

•   u16 gptmr1ctl;          /* GP timer 1 mode/control */
  

•   u16 gptmr1cnt;          /* GP timer 1 count */
  

•   u16 gptmr1maxcmpa;      /* GP timer 1 maxcount compare A */
  

•   u16 gptmr1maxcmpb;      /* GP timer 1 maxcount compare B*/
  

•   u16 gptmr2ctl;          /* GP timer 2 mode/control */
  

•   u16 gptmr2cnt;          /* GP timer 2 count */
  

•   u8  pad_0xc86[0x08];
  

•   u16 gptmr2maxcmpa;      /* GP timer 2 maxcount compare A */
  

•   u8  pad_0xc90[0x20];
  

•   u16 wdtmrctl;           /* watchdog timer control */
  

•   u16 wdtmrcntl;          /* watchdog timer count low */
  

•   u16 wdtmrcnth;          /* watchdog timer count high */
  

•   u8  pad_0xcb6[0x0a];
  

•   u8  uart1ctl;           /* UART 1 general control */
  

•   u8  uart1sta;           /* UART 1 general status */
  

•   u8  uart1fcrshad;       /* UART 1 FIFO control shadow */
  

•   u8  pad_0xcc3[0x01];
  

•   u8  uart2ctl;           /* UART 2 general control */
  

•   u8  uart2sta;           /* UART 2 general status */
  

•   u8  uart2fcrshad;       /* UART 2 FIFO control shadow */
  

•   u8  pad_0xcc7[0x09];
  

•   u8  ssictl;             /* SSI control */
  

•   u8  ssixmit;            /* SSI transmit */
  

•   u8  ssicmd;             /* SSI command */
  

•   u8  ssista;             /* SSI status */
  

•   u8  ssircv;             /* SSI receive */
  

•   u8  pad_0xcd5[0x2b];
  

•   u8  picicr;             /* interrupt control */
  

•   u8  pad_0xd01[0x01];
  

•   u8  pic_mode[3];        /* PIC interrupt mode */
  

•   u8  pad_0xd05[0x03];
  

•   u16 swint16_1;          /* software interrupt 16-1 control */
  

•   u8  swint22_17;         /* software interrupt 22-17/NMI control */
  

•   u8  pad_0xd0b[0x05];
  

•   u16 intpinpol;          /* interrupt pin polarity */
  

•   u8  pad_0xd12[0x02];
  

•   u16 pcihostmap;         /* PCI host bridge interrupt mapping */
  

•   u8  pad_0xd16[0x02];
  

•   u16 eccmap;             /* ECC interrupt mapping */
  

•   u8  gp_tmr_int_map[3];  /* GP timer interrupt mapping */
  

•   u8  pad_0xd1d[0x03];
  

•   u8  pit_int_map[3];     /* PIT interrupt mapping */
  

•   u8  pad_0xd23[0x05];
  

•   u8  uart_int_map[2];    /* UART interrupt mapping */
  

•   u8  pad_0xd2a[0x06];
  

•   u8  pci_int_map[4];     /* PCI interrupt mapping (A through D)*/
  

•   u8  pad_0xd34[0x0c];
  

•   u8  dmabcintmap;        /* DMA buffer chaining interrupt mapping */
  

•   u8  ssimap;             /* SSI interrupt mapping register */
  

•   u8  wdtmap;             /* watchdog timer interrupt mapping */
  

•   u8  rtcmap;             /* RTC interrupt mapping register */
  

•   u8  wpvmap;             /* write-protect interrupt mapping */
  

•   u8  icemap;             /* AMDebug JTAG Rx/Tx interrupt mapping */
  

•   u8  ferrmap;            /* floating point error interrupt mapping
  

*/

•   u8  pad_0xd47[0x09];
  

•   u8  gp_int_map[11];     /* GP IRQ interrupt mapping */
  

•   u8  pad_0xd5b[0x15];
  

•   u8  sysinfo;            /* system board information */
  

•   u8  pad_0xd71[0x01];
  

•   u8  rescfg;             /* reset configuration */
  

•   u8  pad_0xd73[0x01];
  

•   u8  ressta;             /* reset status */
  

•   u8  pad_0xd75[0x0b];
  

•   u8  gpdmactl;           /* GP-DMA Control */
  

•   u8  gpdmammio;          /* GP-DMA memory-mapped I/O */
  

•   u16 gpdmaextchmapa;     /* GP-DMA resource channel map a */
  

•   u16 gpdmaextchmapb;     /* GP-DMA resource channel map b */
  

•   u8  gp_dma_ext_pg_0;    /* GP-DMA channel extended page 0 */
  

•   u8  gp_dma_ext_pg_1;    /* GP-DMA channel extended page 0 */
  

•   u8  gp_dma_ext_pg_2;    /* GP-DMA channel extended page 0 */
  

•   u8  gp_dma_ext_pg_3;    /* GP-DMA channel extended page 0 */
  

•   u8  gp_dma_ext_pg_5;    /* GP-DMA channel extended page 0 */
  

•   u8  gp_dma_ext_pg_6;    /* GP-DMA channel extended page 0 */
  

•   u8  gp_dma_ext_pg_7;    /* GP-DMA channel extended page 0 */
  

•   u8  pad_0xd8d[0x03];
  

•   u8  gpdmaexttc3;        /* GP-DMA channel 3 extender transfer
  

count */

•   u8  gpdmaexttc5;        /* GP-DMA channel 5 extender transfer
  

count */

•   u8  gpdmaexttc6;        /* GP-DMA channel 6 extender transfer
  

count */

•   u8  gpdmaexttc7;        /* GP-DMA channel 7 extender transfer
  

count */

•   u8  pad_0xd94[0x4];
  

•   u8  gpdmabcctl;         /* buffer chaining control */
  

•   u8  gpdmabcsta;         /* buffer chaining status */
  

•   u8  gpdmabsintenb;      /* buffer chaining interrupt enable */
  

•   u8  gpdmabcval;         /* buffer chaining valid */
  

•   u8  pad_0xd9c[0x04];
  

•   u16 gpdmanxtaddl3;      /* GP-DMA channel 3 next address low */
  

•   u16 gpdmanxtaddh3;      /* GP-DMA channel 3 next address high */
  

•   u16 gpdmanxtaddl5;      /* GP-DMA channel 5 next address low */
  

•   u16 gpdmanxtaddh5;      /* GP-DMA channel 5 next address high */
  

•   u16 gpdmanxtaddl6;      /* GP-DMA channel 6 next address low */
  

•   u16 gpdmanxtaddh6;      /* GP-DMA channel 6 next address high */
  

•   u16 gpdmanxtaddl7;      /* GP-DMA channel 7 next address low */
  

•   u16 gpdmanxtaddh7;      /* GP-DMA channel 7 next address high */
  

•   u16 gpdmanxttcl3;       /* GP-DMA channel 3 next transfer count
  

low */

•   u16 gpdmanxttch3;       /* GP-DMA channel 3 next transfer count
  

high */

•   u16 gpdmanxttcl5;       /* GP-DMA channel 5 next transfer count
  

low */

•   u16 gpdmanxttch5;       /* GP-DMA channel 5 next transfer count
  

high */

•   u16 gpdmanxttcl6;       /* GP-DMA channel 6 next transfer count
  

low */

•   u16 gpdmanxttch6;       /* GP-DMA channel 6 next transfer count
  

high */

•   u16 gpdmanxttcl7;       /* GP-DMA channel 7 next transfer count
  

low */

•   u16 gpdmanxttch7;       /* GP-DMA channel 7 next transfer count
  

high */

•   u8  pad_0xdc0[0x0240];
  

-} sc520_mmcr_t;

-extern sc520_mmcr_t *sc520_mmcr;

-#endif

-/* Memory Mapped Control Registers (MMCR) Base Address */ -#define SC520_MMCR_BASE 0xfffef000

-/*

• • PARs for maximum allowable 256MB of SDRAM @ 0x00000000
• • Two PARs are required due to maximum PAR size of 128MB
• • These are used in the SDRAM sizing code to disable caching
• • 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000
• • 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800
• • \ / | | | | ----+----/ -----+------/
• • | | | | | | +---------- Start at 0x00000000
• • | | | | | | 0x08000000
• • | | | | | +----------------------- 128MB Region Size
• • | | | | | ((2047 + 1) * 64kB)
• • | | | | +------------------------------ 64kB Page Size
• • | | | +-------------------------------- Writes Enabled
• • | | +---------------------------------- Caching Enabled
• • | +------------------------------------ Execution Enabled
• • +--------------------------------------- SDRAM
• */

-#define SC520_SDRAM1_PAR 0xe3ffc000 -#define SC520_SDRAM2_PAR 0xe3ffc800

-#define SC520_PAR_WRITE_DIS 0x04000000 -#define SC520_PAR_CACHE_DIS 0x08000000 -#define SC520_PAR_EXEC_DIS 0x10000000

-/*

• • Programmable Address Regions to cover 256MB SDRAM (Maximum supported)
• • required for DRAM sizing code
• */

-/* MMCR Register bits (not all of them :) ) */

-/* SSI Stuff */ -#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */ -#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */ -#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */ -#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */ -#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */ -#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */ -#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */ -#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */

-#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */ -#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */ -#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */ -#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */

-#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */ -#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */ -#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */ -#define SSISTA_BSY 0x02 /* SSI Busy */ -#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */

-/* BITS for SC520_ADDDECCTL: */ -#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */ -#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */ -#define RTC_DIS 0x04 /* RTC Disable */ -#define UART2_DIS 0x02 /* UART2 Disable */ -#define UART1_DIS 0x01 /* UART1 Disable */

-/*

• • Defines used for SDRAM Sizing (number of columns and rows)
• • Refer to section 10.6.4 - SDRAM Sizing Algorithm in the
• • Elan SC520 Microcontroller User's Manual (Order #22004B)
• */

-#define CACHELINESZ 0x00000010

-#define COL11_ADR 0x0e001e00 -#define COL10_ADR 0x0e000e00 -#define COL09_ADR 0x0e000600 -#define COL08_ADR 0x0e000200 -#define COL11_DATA 0x0b0b0b0b -#define COL10_DATA 0x0a0a0a0a -#define COL09_DATA 0x09090909 -#define COL08_DATA 0x08080808

-#define ROW14_ADR 0x0f000000 -#define ROW13_ADR 0x07000000 -#define ROW12_ADR 0x03000000 -#define ROW11_ADR 0x01000000 -#define ROW10_ADR 0x00000000 -#define ROW14_DATA 0x3f3f3f3f -#define ROW13_DATA 0x1f1f1f1f -#define ROW12_DATA 0x0f0f0f0f -#define ROW11_DATA 0x07070707 -#define ROW10_DATA 0xaaaaaaaa

-/* 0x28000000 - 0x3fffffff is used by the flash banks */

-/* 0x40000000 - 0xffffffff is not adressable by the SC520 */

-/* priority numbers used for interrupt channel mappings */ -#define SC520_IRQ_DISABLED 0 -#define SC520_IRQ0 1 -#define SC520_IRQ1 2 -#define SC520_IRQ2 4 /* same as IRQ9 */ -#define SC520_IRQ3 11 -#define SC520_IRQ4 12 -#define SC520_IRQ5 13 -#define SC520_IRQ6 21 -#define SC520_IRQ7 22 -#define SC520_IRQ8 3 -#define SC520_IRQ9 4 -#define SC520_IRQ10 5 -#define SC520_IRQ11 6 -#define SC520_IRQ12 7 -#define SC520_IRQ13 8 -#define SC520_IRQ14 9 -#define SC520_IRQ15 10

-#endif diff --git a/arch/x86/include/asm/arch-sc520/ssi.h b/arch/x86/include/asm/arch-sc520/ssi.h deleted file mode 100644 index bd48eab..0000000 --- a/arch/x86/include/asm/arch-sc520/ssi.h +++ /dev/null @@ -1,34 +0,0 @@ -/*

• • (C) Copyright 2008
• • Graeme Russ graeme.russ@gmail.com.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

-#ifndef _ASM_IC_SSI_H_ -#define _ASM_IC_SSI_H_ 1

-int ssi_set_interface(int, int, int, int); -void ssi_chip_select(int); -u8 ssi_txrx_byte(u8); -void ssi_tx_byte(u8); -u8 ssi_rx_byte(void);

-#endif

1.8.1