Hello list,

inside the automatic U-Boot patch tracking system a new ticket [DNX#2006072742000035] was created:

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All,

The default pipeline depth of 83xx CSB is 1 outstanding transcation. If change it to 4, the CSB performace will improve. Change the DMA transfer with cache line burst read/write The DMA performance improved 6x.

CHANGELOG:

• improve the coherency system bus performance and improve the DMA transfer performace. Patch by Dave Liu, 21 July 2006

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 20bba6c..2eea221 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -257,9 +257,7 @@ int dma_xfer(void *dest, u32 count, void __asm__ __volatile__ ("isync");

    /* init direct transfer, clear CS bit */

•   dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
  

•                   DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
  

•                   DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
  

•   dmamr0 = DMA_CHANNEL_TRANSFER_MODE_DIRECT;
  
    dma->dmamr0 = swab32(dmamr0);
  
  

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 6ed0992..8366cb7 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -69,7 +69,8 @@ #endif #ifdef CFG_SICRL im->sysconf.sicrl = CFG_SICRL; #endif

•   /* Set CSB bus pipeline depth */
  

•   im->arbiter.acr |= ACR_PIPE_DEP_IS_03;
    /*
     * Memory Controller:
     */
  
  

diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index c2b4c5c..24191c5 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -371,6 +371,7 @@ typedef struct arbiter8349 { u32 acr; /* Arbiter Configuration Register */ #define ACR_COREDIS 0x10000000 /* Core disable. */ #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */ +#define ACR_PIPE_DEP_IS_03 0x00030000 /* Pipeline depth is 4 */ #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */ #define ACR_RPTCNT 0x00000700 /* Repeat count. */ #define ACR_APARK 0x00000030 /* Address parking. */

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