[U-Boot-Users] waiting for timeouts in FPGA code?
Hi there ,
in the U-Boot FPGA code timeouts are realized by
if (get_timer (ts) > CFG_FPGA_WAIT{_INIT}) ...
while CFG_FPGA_WAIT{_INIT} is supposed to be the timeout in milliseconds. This does not work for the AT91RM9200. Instead of using
#define CFG_FPGA_WAIT 10
I have to use
#define CFG_FPGA_WAIT CFG_HZ/10
Is CFG_HZ defined for all other architectures? Should we use CFG_HZ instead of hardcoded numbers?
Thanks.
In message 403B84DB.40900@imc-berlin.de you wrote:
in the U-Boot FPGA code timeouts are realized by
if (get_timer (ts) > CFG_FPGA_WAIT{_INIT}) ...
while CFG_FPGA_WAIT{_INIT} is supposed to be the timeout in milliseconds.
Then this design is broken; get_timer() returns the number of timer ticks (= CFG_HZ per second). This is only milliseconds for CFG_HZ == 1000.
This does not work for the AT91RM9200. Instead of using
#define CFG_FPGA_WAIT 10
I have to use
#define CFG_FPGA_WAIT CFG_HZ/10
Note that this is ten times as long as the original timeout.
Is CFG_HZ defined for all other architectures?
It is supposed to be defined. But many boards define it incorrectly.
Should we use CFG_HZ instead of hardcoded numbers?
Definitely.
Best regards,
Wolfgang Denk
Wolfgang Denk wrote:
In message 403B84DB.40900@imc-berlin.de you wrote:
in the U-Boot FPGA code timeouts are realized by
if (get_timer (ts) > CFG_FPGA_WAIT{_INIT}) ...
while CFG_FPGA_WAIT{_INIT} is supposed to be the timeout in milliseconds.
Then this design is broken; get_timer() returns the number of timer ticks (= CFG_HZ per second). This is only milliseconds for CFG_HZ == 1000.
So I does not matter how fast the timer ticks as long as CFG_HZ is set to the correct value and timeouts are based on CFG_HZ. Correct?
This does not work for the AT91RM9200. Instead of using
#define CFG_FPGA_WAIT 10
I have to use
#define CFG_FPGA_WAIT CFG_HZ/10
Note that this is ten times as long as the original timeout.
Of course. Typo.
Is CFG_HZ defined for all other architectures?
It is supposed to be defined. But many boards define it incorrectly.
Should we use CFG_HZ instead of hardcoded numbers?
Definitely.
Hmm. But that means that when we change e.g. the above mentioned FPGA code to use CFG_HZ that we might break these archictectures !?
In message 403C6563.3020806@imc-berlin.de you wrote:
while CFG_FPGA_WAIT{_INIT} is supposed to be the timeout in milliseconds.
Then this design is broken; get_timer() returns the number of timer ticks (= CFG_HZ per second). This is only milliseconds for CFG_HZ == 1000.
So I does not matter how fast the timer ticks as long as CFG_HZ is set to the correct value and timeouts are based on CFG_HZ. Correct?
Intheory, yes. Unless CFG_HZ is insane and causes integer arithmetics overflow.
It is supposed to be defined. But many boards define it incorrectly.
Should we use CFG_HZ instead of hardcoded numbers?
Definitely.
Hmm. But that means that when we change e.g. the above mentioned FPGA code to use CFG_HZ that we might break these archictectures !?
Indeed. Do you know a better way? I don't. So let's do this right first, and then clean up any mess that you unsheathe.
Best regards,
Wolfgang Denk
Wolfgang Denk wrote:
Is CFG_HZ defined for all other architectures?
It is supposed to be defined. But many boards define it incorrectly.
Should we use CFG_HZ instead of hardcoded numbers?
Definitely.
Here we go:
* Patch by Steven Scholz, 25 Feb 2004: - Timeouts in FPGA code should be based on CFG_HZ - Minor cleanup in code for Altera FPGA ACEX1K
BTW: I just noticed that loads of timeouts (e.g. CFG_FLASH_ERASE_TOUT) are _not_ defined using CFG_HZ ...
In message 403C99F3.309@imc-berlin.de you wrote:
Here we go:
- Patch by Steven Scholz, 25 Feb 2004:
- Timeouts in FPGA code should be based on CFG_HZ
- Minor cleanup in code for Altera FPGA ACEX1K
Added, thanks.
BTW: I just noticed that loads of timeouts (e.g. CFG_FLASH_ERASE_TOUT) are _not_ defined using CFG_HZ ...
Argh.. :-(
Best regards,
Wolfgang Denk
participants (2)
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Steven Scholz -
Wolfgang Denk