Re: [U-Boot] Coldfire: MCF5271: Periodic HW watchdog petting and sleep function does not work.
Richard Retanubun wrote:
Hi TC,
TC Liew wrote:
Richard,
Is there a purpose that you used DTIMER 3 but not 1 or 2? FYI: DTIMER3 is currently used for system time, DTIMER0 is currently used for udelay() in u-boot.
You can change the u-boot 5271's system timer in include/asm-m68k/immap.h. #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR1) #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT20)
Regards, TsiChung
Hi TC,
Sorry for the long-delay on this issue, I got tasked with other stuff, but thanks to your hint from the last e-mail, I think I might have found the root-cause to the problem.
In include/asm-m68k/immap.h.
#ifdef CONFIG_M5271 #include <asm/immap_5271.h> #include <asm/m5271.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
/* Timer */ #ifdef CONFIG_MCFTMR #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (0) /* Level must include inorder to work */ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif
According to MCF5271 RefMan Rev 2 (07/2006) page 13-12, I think this means that the interrupt, although unmasked, have a level 0, priority 0, which essentially disables it.
What should be the proper value? (0x09) will make it level 1, priority 1, is this ok? Or am I chasing the wrong rabbit?
Thanks for your time
- Richard
Richard,
I used 6 for most platforms. 1 is lowest priority - 7 - is the highest.
Regards, TsiChung
On Thu, Mar 19, 2009 at 4:15 PM, Richard Retanubun RichardRetanubun@ruggedcom.com wrote:
Richard Retanubun wrote:
Hi TC,
TC Liew wrote:
Richard, Is there a purpose that you used DTIMER 3 but not 1 or 2? FYI: DTIMER3 is currently used for system time, DTIMER0 is currently used for udelay() in u-boot. You can change the u-boot 5271's system timer in include/asm-m68k/immap.h. #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR1) #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT20) Regards, TsiChung
Hi TC,
Sorry for the long-delay on this issue, I got tasked with other stuff, but thanks to your hint from the last e-mail, I think I might have found the root-cause to the problem.
In include/asm-m68k/immap.h.
#ifdef CONFIG_M5271 #include <asm/immap_5271.h> #include <asm/m5271.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT
- 0x40))
/* Timer */ #ifdef CONFIG_MCFTMR #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (0) /* Level must include inorder to work */ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif
According to MCF5271 RefMan Rev 2 (07/2006) page 13-12, I think this means that the interrupt, although unmasked, have a level 0, priority 0, which essentially disables it.
What should be the proper value? (0x09) will make it level 1, priority 1, is this ok? Or am I chasing the wrong rabbit?
Thanks for your time
- Richard
TC Liew wrote:
Richard,
I used 6 for most platforms. 1 is lowest priority - 7 - is the highest.
Got it, thanks TC, I set it similar to the other platform (x1E):
A patch for the timer interrupt that fixes the sleep command is submitted on a separate thread.
I have also submitted a patch for the periodic HW watchdog reset-ing.
If you'd like to continue the discussion, let's do it on the respective patch threads.
Richard
participants (2)
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Richard Retanubun -
TC Liew