[PATCH v2 0/3] rockchip: sdram: Fix issues observed on RK3576
Most Rockchip AArch64 SoCs have start of DRAM at 0x0. However, the RK3576 instead has start of DRAM at 0x40000000 and can extend continuous beyond the 4 GiB mark.
This series fixes issues observed on a Rockchip RK3576 board testing Heiko's RK3576 series [1].
Changes in v2: - Drop duplicate patch - Add patch to limit gd->ram_top to max 4G - Add patch to assign gd->ram_base in SPL - Collect r-b tag
[1] https://patchwork.ozlabs.org/cover/2013854/
Jonas Karlman (3): rockchip: sdram: Allow the first bank to extend beyond 4 GiB rockchip: sdram: Limit usable ram_top to max 4G rockchip: sdram: Ensure ram_base is correct in SPL
arch/arm/mach-rockchip/sdram.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
Allow the first bank to extend beyond 4 GiB when the blob of space for peripheral is located before start of DRAM, e.g. when start of DRAM is 0x40000000 and continue beyond the 4 GiB mark.
Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com --- v2: Collect r-b tag --- arch/arm/mach-rockchip/sdram.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 7c21ae8efc44..3d3fc327234f 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -310,6 +310,8 @@ int dram_init_banksize(void) if (ram_top > SZ_4G && top < SZ_4G) { gd->bd->bi_dram[1].start = SZ_4G; gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start; + } else if (ram_top > SZ_4G && top == SZ_4G) { + gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start; } #else #ifdef CONFIG_SPL_OPTEE_IMAGE
U-Boot only works correctly when it uses RAM below the 4G address boundary on Rockchip SoCs. Limit usable gd->ram_top to max 4G.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- v2: New patch --- arch/arm/mach-rockchip/sdram.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 3d3fc327234f..08deebb765f0 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -488,7 +488,10 @@ int dram_init(void)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { - unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; + unsigned long top; + + /* Make sure U-Boot only uses the space below the 4G address boundary */ + top = min_t(ulong, CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE, (ulong)SZ_4G);
return (gd->ram_top > top) ? top : gd->ram_top; }
Most Rockchip SoCs use 0x0 as DRAM base address, however some SoCs use 0x60000000 and RK3576 use 0x40000000 as DRAM base address.
CFG_SYS_SDRAM_BASE is defined with correct address for each SoC and U-Boot proper use this to set correct gd->ram_base in setup_dest_addr().
SPL never assign any value to gd->ram_base and instead use the default, 0x0. Set correct gd->ram_base in dram_init() to ensure its correctness in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- v2: New patch --- arch/arm/mach-rockchip/sdram.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 08deebb765f0..2092821002a8 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -479,6 +479,7 @@ int dram_init(void) debug("Cannot get DRAM size: %d\n", ret); return ret; } + gd->ram_base = ram.base; gd->ram_size = ram.size; debug("SDRAM base=%lx, size=%lx\n", (unsigned long)ram.base, (unsigned long)ram.size);
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Jonas Karlman