[U-Boot] [PATCH] ColdFire: Implement SBF feature for M5445EVB
From: TsiChung Liew Tsi-Chung.Liew@freescale.com
Signed-off-by: TsiChung Liew Tsi-Chung.Liew@freescale.com --- Makefile | 16 ++- board/freescale/m54455evb/m54455evb.c | 14 ++- board/freescale/m54455evb/u-boot.stm | 136 +++++++++++++++++ cpu/mcf5445x/cpu_init.c | 2 + cpu/mcf5445x/speed.c | 67 ++++++--- cpu/mcf5445x/start.S | 258 ++++++++++++++++++++++++++++++++- include/configs/M54455EVB.h | 92 ++++++++++-- 7 files changed, 539 insertions(+), 46 deletions(-) create mode 100644 board/freescale/m54455evb/u-boot.stm
diff --git a/Makefile b/Makefile index 89746a2..4fa235e 100644 --- a/Makefile +++ b/Makefile @@ -1898,7 +1898,8 @@ M54455EVB_intel_config \ M54455EVB_a33_config \ M54455EVB_a66_config \ M54455EVB_i33_config \ -M54455EVB_i66_config : unconfig +M54455EVB_i66_config \ +M54455EVB_stm33_config : unconfig @case "$@" in \ M54455EVB_config) FLASH=ATMEL; FREQ=33333333;; \ M54455EVB_atmel_config) FLASH=ATMEL; FREQ=33333333;; \ @@ -1907,18 +1908,27 @@ M54455EVB_i66_config : unconfig M54455EVB_a66_config) FLASH=ATMEL; FREQ=66666666;; \ M54455EVB_i33_config) FLASH=INTEL; FREQ=33333333;; \ M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \ + M54455EVB_stm33_config) FLASH=STMICRO; FREQ=33333333;; \ esac; \ if [ "$${FLASH}" = "INTEL" ] ; then \ - echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ + echo "#define CFG_INTEL_BOOT" >> $(obj)include/config.h ; \ echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \ cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \ $(XECHO) "... with INTEL boot..." ; \ - else \ + fi; \ + if [ "$${FLASH}" = "ATMEL" ] ; then \ echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \ cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \ $(XECHO) "... with ATMEL boot..." ; \ fi; \ + if [ "$${FLASH}" = "STMICRO" ] ; then \ + echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \ + echo "#define CFG_STMICRO_BOOT" >> $(obj)include/config.h ; \ + echo "TEXT_BASE = 0x4FE00000" > $(obj)board/freescale/m54455evb/config.tmp ; \ + cp $(obj)board/freescale/m54455evb/u-boot.stm $(obj)board/freescale/m54455evb/u-boot.lds ; \ + $(XECHO) "... with ST Micro boot..." ; \ + fi; \ echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \ $(XECHO) "... with $${FREQ}Hz input clock" @$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index 3c7b350..4f02121 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -39,9 +39,17 @@ int checkboard(void)
phys_size_t initdram(int board_type) { + u32 dramsize; +#ifdef CONFIG_CF_SBF + /* + * Serial Boot: The dram is already initialized in start.S + * only require to return DRAM size + */ + dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1; +#else volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); - u32 dramsize, i; + u32 i;
dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1;
@@ -51,7 +59,7 @@ phys_size_t initdram(int board_type) } i--;
- gpio->mscr_sdram = 0xAA; + gpio->mscr_sdram = CFG_SDRAM_DRV_STRENGTH;
sdram->sdcs0 = (CFG_SDRAM_BASE | i); sdram->sdcs1 = (CFG_SDRAM_BASE1 | i); @@ -80,7 +88,7 @@ phys_size_t initdram(int board_type) sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
udelay(100); - +#endif return (dramsize << 1); };
diff --git a/board/freescale/m54455evb/u-boot.stm b/board/freescale/m54455evb/u-boot.stm new file mode 100644 index 0000000..3dd9a6b --- /dev/null +++ b/board/freescale/m54455evb/u-boot.stm @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf5445x/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c index e07748b..51a9e90 100644 --- a/cpu/mcf5445x/cpu_init.c +++ b/cpu/mcf5445x/cpu_init.c @@ -61,11 +61,13 @@ void cpu_init_f(void) GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS;
+#if !defined(CONFIG_CF_SBF) #if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) fbcs->csar0 = CFG_CS0_BASE; fbcs->cscr0 = CFG_CS0_CTRL; fbcs->csmr0 = CFG_CS0_MASK; #endif +#endif
#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) /* Latch chipselect */ diff --git a/cpu/mcf5445x/speed.c b/cpu/mcf5445x/speed.c index 967becf..f677f3c 100644 --- a/cpu/mcf5445x/speed.c +++ b/cpu/mcf5445x/speed.c @@ -84,26 +84,29 @@ void clock_exit_limp(void) */ int get_clocks(void) { + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; - volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3); - volatile u8 *fpga = (volatile u8 *)(CFG_CS3_BASE + 14); int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 }; int pllmult_pci[] = { 12, 6, 16, 8 }; - int vco, bPci, temp, fbtemp, pcrvalue; + int vco = 0, bPci, temp, fbtemp, pcrvalue; int *pPllmult = NULL; u16 fbpll_mask; - u8 cpldmode; + +#ifdef CONFIG_M54455EVB + volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3); +#endif + u8 bootmode;
/* To determine PCI is present or not */ if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) || ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { pPllmult = &pllmult_pci[0]; - fbpll_mask = 3; + fbpll_mask = 3; /* 11b */ bPci = 1; } else { pPllmult = &pllmult_nopci[0]; - fbpll_mask = 7; + fbpll_mask = 7; /* 111b */ #ifdef CONFIG_PCI gd->pci_clk = 0; #endif @@ -111,20 +114,36 @@ int get_clocks(void) }
#ifdef CONFIG_M54455EVB - /* Temporary place here, belongs in board/freescale/... */ - /* Temporary read from CCR- fixed fb issue, must be the same clock - as pci or input clock, causing cpld/fpga read inconsistancy */ - fbtemp = pPllmult[ccm->ccr & fbpll_mask]; + bootmode = (*cpld & 0x03);
- /* Break down into small pieces, code still in flex bus */ - pcrvalue = pll->pcr & 0xFFFFF0FF; - temp = fbtemp - 1; - pcrvalue |= PLL_PCR_OUTDIV3(temp); + if (bootmode != 3) { + /* Temporary read from CCR- fixed fb issue, must be the same clock + as pci or input clock, causing cpld/fpga read inconsistancy */ + fbtemp = pPllmult[ccm->ccr & fbpll_mask];
+ /* Break down into small pieces, code still in flex bus */ + pcrvalue = pll->pcr & 0xFFFFF0FF; + temp = fbtemp - 1; + pcrvalue |= PLL_PCR_OUTDIV3(temp); + + pll->pcr = pcrvalue; + } +#endif +#ifdef CONFIG_M54451EVB + /* No external logic to read the bootmode, hard coded from built */ +#ifdef CONFIG_CF_SBF + bootmode = 3; +#else + bootmode = 2; + + /* default value is 16 mul, set to 20 mul */ + pcrvalue = (pll->pcr & 0x00FFFFFF) | 0x14000000; pll->pcr = pcrvalue; + while ((pll->psr & PLL_PSR_LOCK) != PLL_PSR_LOCK); +#endif +#endif
- cpldmode = *cpld & 0x03; - if (cpldmode == 0) { + if (bootmode == 0) { /* RCON mode */ vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC;
@@ -151,14 +170,22 @@ int get_clocks(void) pll->pcr = pcrvalue; } gd->vco_clk = vco; /* Vco clock */ - } else if (cpldmode == 2) { + } else if (bootmode == 2) { /* Normal mode */ - vco = pPllmult[ccm->ccr & fbpll_mask] * CFG_INPUT_CLKSRC; + vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC; + if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { + /* Default value */ + pcrvalue = (pll->pcr & 0x00FFFFFF); + pcrvalue |= pPllmult[ccm->ccr & fbpll_mask] << 24; + pll->pcr = pcrvalue; + vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC; + } gd->vco_clk = vco; /* Vco clock */ - } else if (cpldmode == 3) { + } else if (bootmode == 3) { /* serial mode */ + vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC; + gd->vco_clk = vco; /* Vco clock */ } -#endif /* CONFIG_M54455EVB */
if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { /* Limp mode */ diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S index 89ec7bc..4bfc625 100644 --- a/cpu/mcf5445x/start.S +++ b/cpu/mcf5445x/start.S @@ -46,15 +46,30 @@ addl #60,%sp; /* space for 15 regs */ \ rte;
+#if defined(CONFIG_CF_SBF) +#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CFG_INIT_RAM_ADDR) +#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CFG_INIT_RAM_ADDR) +#endif + .text + /* * Vector table. This is used for initial platform startup. * These vectors are to catch any un-intended traps. */ _vectors: +#if defined(CONFIG_CF_SBF) + +INITSP: .long 0 /* Initial SP */ +INITPC: .long ASM_DRAMINIT /* Initial PC */ + +#else + +INITSP: .long 0 /* Initial SP */ +INITPC: .long _START /* Initial PC */ + +#endif
-INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ vector02: .long _FAULT /* Access Error */ vector03: .long _FAULT /* Address Error */ vector04: .long _FAULT /* Illegal Instruction */ @@ -83,6 +98,8 @@ vector1D: .long _FAULT /* Autovector Level 5 */ vector1E: .long _FAULT /* Autovector Level 6 */ vector1F: .long _FAULT /* Autovector Level 7 */
+#if !defined(CONFIG_CF_SBF) + /* TRAP #0 - #15 */ vector20_2F: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT @@ -122,9 +139,237 @@ vector192_255: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +#endif
- .text +#if defined(CONFIG_CF_SBF) + /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ +asm_sbf_img_hdr: + .long 0x00000000 /* checksum, not yet implemented */ + .long 0x00030000 /* image length */ + .long TEXT_BASE /* image to be relocated at */ + +asm_dram_init: + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 /* init Rambar */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + /* Must disable global address */ + move.l #0xFC008000, %a1 + move.l #(CFG_CS0_BASE), (%a1) + move.l #0xFC008008, %a1 + move.l #(CFG_CS0_CTRL), (%a1) + move.l #0xFC008004, %a1 + move.l #(CFG_CS0_MASK), (%a1) + + /* + * Dram Initialization + * a1, a2, and d0 + */ + /* mscr sdram */ + move.l #0xFC0A4074, %a1 + move.b #(CFG_SDRAM_DRV_STRENGTH), (%a1) + nop + + /* SDRAM Chip 0 and 1 */ + move.l #0xFC0B8110, %a1 + move.l #0xFC0B8114, %a2 + + /* calculate the size */ + move.l #0x13, %d1 + move.l #(CFG_SDRAM_SIZE), %d2 +#ifdef CFG_SDRAM_BASE1 + lsr.l #1, %d2 +#endif + +dramsz_loop: + lsr.l #1, %d2 + add.l #1, %d1 + cmp.l #1, %d2 + bne dramsz_loop + + /* SDRAM Chip 0 and 1 */ + move.l #(CFG_SDRAM_BASE), (%a1) + or.l %d1, (%a1) +#ifdef CFG_SDRAM_BASE1 + move.l #(CFG_SDRAM_BASE1), (%a2) + or.l %d1, (%a2) +#endif + nop + + /* dram cfg1 and cfg2 */ + move.l #0xFC0B8008, %a1 + move.l #(CFG_SDRAM_CFG1), (%a1) + nop + move.l #0xFC0B800C, %a2 + move.l #(CFG_SDRAM_CFG2), (%a2) + nop + + move.l #0xFC0B8000, %a1 /* Mode */ + move.l #0xFC0B8004, %a2 /* Ctrl */ + +#ifdef CONFIG_M54455EVB + /* Issue PALL */ + move.l #(CFG_SDRAM_CTRL + 2), (%a2) + nop + + /* Issue LEMR */ + move.l #(CFG_SDRAM_EMOD + 0x408), (%a1) + nop + move.l #(CFG_SDRAM_MODE + 0x300), (%a1) + nop + + move.l #1000, %d0 +wait1000: + nop + subq.l #1, %d0 + bne wait1000 +#endif + + /* Issue PALL */ + move.l #(CFG_SDRAM_CTRL + 2), (%a2) + nop + + /* Perform two refresh cycles */ + move.l #(CFG_SDRAM_CTRL + 4), %d0 + nop + move.l %d0, (%a2) + move.l %d0, (%a2) + nop
+#ifdef CONFIG_M54455EVB + move.l #(CFG_SDRAM_MODE + 0x200), (%a1) + nop +#elif defined(CONFIG_M54451EVB) + /* Issue LEMR */ + move.l #(CFG_SDRAM_MODE), (%a2) + nop + move.l #(CFG_SDRAM_EMOD), (%a2) + nop +#endif + + move.l #500, %d0 +wait500: + nop + subq.l #1, %d0 + bne wait500 + + move.l #(CFG_SDRAM_CTRL), %d0 + and.l #0x7FFFFFFF, %d0 +#ifdef CONFIG_M54455EVB + or.l #0x10000c00, %d0 +#elif defined(CONFIG_M54451EVB) + or.l #0x10000000, %d0 +#endif + move.l %d0, (%a2) + nop + + /* + * DSPI Initialization + * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h + * a1 - dspi status + * a2 - dtfr + * a3 - drfr + * a4 - Dst addr + */ + /* Enable pins for DSPI mode - chip-selects are enabled later */ + move.l #0xFC0A4063, %a0 + move.b #0x7F, (%a0) + + /* Configure DSPI module */ + move.l #0xFC05C000, %a0 + move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */ + + move.l #0xFC05C00C, %a0 + move.l #0x3E000011, (%a0) + + move.l #0xFC05C034, %a2 /* dtfr */ + move.l #0xFC05C03B, %a3 /* drfr */ + + move.l #(ASM_SBF_IMG_HDR + 4), %a1 + move.l (%a1)+, %d5 + move.l (%a1), %a4 + + move.l #(CFG_INIT_RAM_ADDR + CFG_SBFHDR_DATA_OFFSET), %a0 + move.l #(CFG_SBFHDR_SIZE), %d4 + + move.l #0xFC05C02C, %a1 /* dspi status */ + + /* Issue commands and address */ + move.l #0x8002000B, %d2 /* Fast Read Cmd */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Address byte 2 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Address byte 1 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Address byte 0 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Dummy Wr and Rd */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + /* Transfer serial boot header to sram */ +asm_dspi_rd_loop1: + move.l #0x80020000, %d2 + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.b %d1, (%a0) /* read, copy to dst */ + + add.l #1, %a0 /* inc dst by 1 */ + sub.l #1, %d4 /* dec cnt by 1 */ + bne asm_dspi_rd_loop1 + + /* Transfer u-boot from serial flash to memory */ +asm_dspi_rd_loop2: + move.l #0x80020000, %d2 + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.b %d1, (%a4) /* read, copy to dst */ + + add.l #1, %a4 /* inc dst by 1 */ + sub.l #1, %d5 /* dec cnt by 1 */ + bne asm_dspi_rd_loop2 + + move.l #0x00020000, %d2 /* Terminate */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + /* jump to memory and execute */ + move.l #(TEXT_BASE + 0x400), %a0 + jmp (%a0) + +asm_dspi_wr_status: + move.l (%a1), %d0 /* status */ + and.l #0x0000F000, %d0 + cmp.l #0x00003000, %d0 + bgt asm_dspi_wr_status + + move.l %d2, (%a2) + rts + +asm_dspi_rd_status: + move.l (%a1), %d0 /* status */ + and.l #0x000000F0, %d0 + lsr.l #4, %d0 + cmp.l #0, %d0 + beq asm_dspi_rd_status + + move.b (%a3), %d1 + rts +#endif /* CONFIG_CF_SBF */ + + .text + . = 0x400 .globl _start _start: nop @@ -132,11 +377,16 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */ +#if defined(CONFIG_CF_SBF) + move.l #TEXT_BASE, %d0 + movec %d0, %VBR +#else move.l #CFG_FLASH_BASE, %d0 movec %d0, %VBR
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 +#endif
/* initialize general use internal ram */ move.l #0, %d0 @@ -253,7 +503,7 @@ clear_bss: /* exception code */ .globl _fault _fault: - bra _fault + jmp _fault .globl _exc_handler
_exc_handler: diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 936766a..b7b5da0 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -121,18 +121,45 @@ #endif
#define CONFIG_HOSTNAME M54455EVB +#ifdef CFG_STMICRO_BOOT +/* ST Micro serial flash */ +#define CFG_LOAD_ADDR2 0x40010013 #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ - "loadaddr=40010000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ + "loadaddr=0x40010000\0" \ + "sbfhdr=sbfhdr.bin\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${sbfhdr};" \ + "tftp " MK_STR(CFG_LOAD_ADDR2) " ${uboot} \0" \ "upd=run load; run prog\0" \ - "prog=prot off 4000000 402ffff;" \ - "era 4000000 402ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ + "prog=sf probe 0:1 10000 1;" \ + "sf erase 0 30000;" \ + "sf write ${loadaddr} 0 0x30000;" \ "save\0" \ "" +#else +/* Atmel and Intel */ +#ifdef CFG_ATMEL_BOOT +# define CFG_UBOOT_END 0x0403FFFF +#elif defined(CFG_INTEL_BOOT) +# define CFG_UBOOT_END 0x3FFFF +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${uboot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off " MK_STR(CFG_FLASH_BASE) \ + " " MK_STR(CFG_UBOOT_END) ";" \ + "era " MK_STR(CFG_FLASH_BASE) " " \ + MK_STR(CFG_UBOOT_END) ";" \ + "cp.b ${loadaddr} " MK_STR(CFG_FLASH_BASE)\ + " ${filesize}; save\0" \ + "" +#endif
/* ATA configuration */ #define CONFIG_ISO_PARTITION @@ -175,6 +202,8 @@ /* DSPI and Serial Flash */ #define CONFIG_CF_DSPI #define CONFIG_HARD_SPI +#define CFG_SER_FLASH_BASE 0x01000000 +#define CFG_SBFHDR_SIZE 0x13 #ifdef CONFIG_CMD_SPI # define CFG_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ DSPI_DCTAR_CPOL | \ @@ -221,7 +250,7 @@ /* Input, PCI, Flexbus, and VCO */ #define CONFIG_EXTRA_CLOCK
-#define CONFIG_PRAM 512 /* 512 KB */ +#define CONFIG_PRAM 2048 /* 2048 KB */
#define CFG_PROMPT "-> " #define CFG_LONGHELP /* undef to save memory */ @@ -254,8 +283,9 @@ #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ #define CFG_INIT_RAM_CTRL 0x221 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16) +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 32) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_SBFHDR_DATA_OFFSET (CFG_INIT_RAM_END - 32)
/*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -270,11 +300,16 @@ #define CFG_SDRAM_CTRL 0xEA0B2000 #define CFG_SDRAM_EMOD 0x40010000 #define CFG_SDRAM_MODE 0x00010033 +#define CFG_SDRAM_DRV_STRENGTH 0xAA
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
-#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#ifdef CONFIG_CF_SBF +# define CFG_MONITOR_BASE (TEXT_BASE + 0x400) +#else +# define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#endif #define CFG_BOOTPARAMS_LEN 64*1024 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ @@ -287,27 +322,44 @@ /* Initial Memory map for Linux */ #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
-/* Configuration for environment +/* + * Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OVERWRITE 1 +#ifdef CONFIG_CF_SBF +# define CFG_ENV_IS_IN_SPI_FLASH +# define CFG_ENV_SPI_CS 1 +#else +# define CFG_ENV_IS_IN_FLASH 1 +#endif +#undef CONFIG_ENV_OVERWRITE #undef CFG_ENV_IS_EMBEDDED
/*----------------------------------------------------------------------- * FLASH organization */ +#ifdef CFG_STMICRO_BOOT +# define CFG_FLASH_BASE CFG_SER_FLASH_BASE +# define CFG_FLASH0_BASE CFG_SER_FLASH_BASE +# define CFG_FLASH1_BASE CFG_CS0_BASE +# define CFG_FLASH2_BASE CFG_CS1_BASE +# define CFG_ENV_OFFSET 0x30000 +# define CFG_ENV_SIZE 0x2000 +# define CFG_ENV_SECT_SIZE 0x10000 +#endif #ifdef CFG_ATMEL_BOOT # define CFG_FLASH_BASE CFG_CS0_BASE # define CFG_FLASH0_BASE CFG_CS0_BASE # define CFG_FLASH1_BASE CFG_CS1_BASE # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) # define CFG_ENV_SECT_SIZE 0x2000 -#else +#endif +#ifdef CFG_INTEL_BOOT # define CFG_FLASH_BASE CFG_CS0_BASE # define CFG_FLASH0_BASE CFG_CS0_BASE # define CFG_FLASH1_BASE CFG_CS1_BASE -# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) +# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) +# define CFG_ENV_SIZE 0x2000 # define CFG_ENV_SECT_SIZE 0x20000 #endif
@@ -339,15 +391,23 @@ * This is setting for JFFS2 support in u-boot. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. */ +#ifdef CONFIG_CMD_JFFS2 +#ifdef CF_STMICRO_BOOT +# define CONFIG_JFFS2_DEV "nor1" +# define CONFIG_JFFS2_PART_SIZE 0x01000000 +# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH2_BASE + 0x500000) +#endif #ifdef CFG_ATMEL_BOOT # define CONFIG_JFFS2_DEV "nor1" # define CONFIG_JFFS2_PART_SIZE 0x01000000 # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH1_BASE + 0x500000) -#else +#endif +#ifdef CFG_INTEL_BOOT # define CONFIG_JFFS2_DEV "nor0" # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) #endif +#endif
/*----------------------------------------------------------------------- * Cache Configuration @@ -366,7 +426,7 @@ * CS5 - Available */
-#ifdef CFG_ATMEL_BOOT +#if defined(CFG_ATMEL_BOOT) || defined(CFG_STMICRO_BOOT) /* Atmel Flash */ #define CFG_CS0_BASE 0x04000000 #define CFG_CS0_MASK 0x00070001
participants (1)
-
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