[U-Boot] [PATCH 1/3] arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width
Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board.
Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width.
Signed-off-by: Stefan Roese sr@denx.de Suggested-by: Adam Shobash adams@marvell.com Cc: Adam Shobash adams@marvell.com Cc: Nadav Haklai nadavh@marvell.com Cc: Konstantin Porotchkin kostap@marvell.com --- .../arm/mach-mvebu/serdes/axp/high_speed_env_lib.c | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+)
diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index afc0cefda3..5925bae69f 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -230,6 +230,20 @@ static int serdes_max_lines_get(void) return 0; }
+/* + * Tests have shown that on some boards the default width of the + * configuration pulse for the PEX link detection might lead to + * non-established PCIe links (link down). Especially under certain + * conditions (higher temperature) and with specific PCIe devices. + * To enable a board-specific detection pulse width this weak + * array "serdes_pex_pulse_width[4]" is introduced which can be + * overwritten if needed by a board-specific version. If the board + * code does not provide a non-weak version of this variable, the + * default value will be used. So nothing is changed from the + * current setup on the supported board. + */ +__weak u8 serdes_pex_pulse_width[4] = { 2, 2, 2, 2 }; + int serdes_phy_config(void) { int status = MV_OK; @@ -891,6 +905,23 @@ int serdes_phy_config(void) pex_unit = line_num >> 2; pex_line_num = line_num % 4; if (0 == pex_line_num) { + /* + * Configure the detection pulse with before + * the reset is deasserted + */ + + /* Read the old value (indirect access) */ + reg_write(PEX_PHY_ACCESS_REG(pex_unit), + (0x48 << 16) | (1 << 31) | + (pex_line_num << 24)); + tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit)); + tmp &= ~(1 << 31); /* Clear read */ + tmp &= ~(3 << 6); /* Mask width */ + /* Insert new detection pulse width */ + tmp |= serdes_pex_pulse_width[pex_unit] << 6; + /* Write value back */ + reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp); + reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x24); DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
Define a board-specific detection pulse-width array for the SerDes PCIe interfaces. If not defined in the board code, the default of currently 2 is used. Values from 0...3 are possible (2 bits).
In this case of the theadorable board, PEX interface 0 needs a value of 0 for the detection pulse width so that the PCIe device (Atheros WLAN PCIe device) is consistantly detected.
Signed-off-by: Stefan Roese sr@denx.de Cc: Adam Shobash adams@marvell.com Cc: Nadav Haklai nadavh@marvell.com Cc: Konstantin Porotchkin kostap@marvell.com --- board/theadorable/theadorable.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index 4be7b61cd2..ab282536ec 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -115,6 +115,13 @@ MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = { }, };
+/* + * Define a board-specific detection pulse-width array for the SerDes PCIe + * interfaces. If not defined in the board code, the default of currently 2 + * is used. Values from 0...3 are possible (2 bits). + */ +u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 }; + MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) { /* Only one mode supported for this board */
On 10.03.2017 15:40, Stefan Roese wrote:
Define a board-specific detection pulse-width array for the SerDes PCIe interfaces. If not defined in the board code, the default of currently 2 is used. Values from 0...3 are possible (2 bits).
In this case of the theadorable board, PEX interface 0 needs a value of 0 for the detection pulse width so that the PCIe device (Atheros WLAN PCIe device) is consistantly detected.
Signed-off-by: Stefan Roese sr@denx.de Cc: Adam Shobash adams@marvell.com Cc: Nadav Haklai nadavh@marvell.com Cc: Konstantin Porotchkin kostap@marvell.com
Applied to u-boot-marvell/master.
Thanks, Stefan
This board specific command tests for the presence of a specified PCIe device (via vendor-ID and device-ID). If the device is not detected, this will get printed. If the device is detected, the board will get resetted so that an easy loop test can be done. The board will reboot until the PCIe device is not detected.
Signed-off-by: Stefan Roese sr@denx.de --- board/theadorable/theadorable.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+)
diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index ab282536ec..6a24e1c8a6 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -298,3 +298,44 @@ int board_late_init(void) return 0; } #endif + +#ifndef CONFIG_SPL_BUILD +int do_pcie_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + pci_dev_t bdf; + u16 ven_id, dev_id; + + if (argc != 3) + return cmd_usage(cmdtp); + + ven_id = simple_strtoul(argv[1], NULL, 16); + dev_id = simple_strtoul(argv[2], NULL, 16); + + printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n", + ven_id, dev_id); + + /* + * Check if the PCIe device is detected (somtimes its not available + * on the PCIe bus) + */ + bdf = pci_find_device(ven_id, dev_id, 0); + if (bdf == -1) { + /* PCIe device not found! */ + printf("Failed to find PCIe device\n"); + } else { + /* PCIe device found! */ + printf("PCIe device found, resetting board...\n"); + + /* default handling: SOFT reset */ + do_reset(NULL, 0, 0, NULL); + } + + return 0; +} + +U_BOOT_CMD( + pcie, 3, 0, do_pcie_test, + "Test for presence of a PCIe device", + "<VendorID> <DeviceID>" +); +#endif
On 10.03.2017 15:40, Stefan Roese wrote:
This board specific command tests for the presence of a specified PCIe device (via vendor-ID and device-ID). If the device is not detected, this will get printed. If the device is detected, the board will get resetted so that an easy loop test can be done. The board will reboot until the PCIe device is not detected.
Signed-off-by: Stefan Roese sr@denx.de
Applied to u-boot-marvell/master.
Thanks, Stefan
On 10.03.2017 15:40, Stefan Roese wrote:
Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board.
Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width.
Signed-off-by: Stefan Roese sr@denx.de Suggested-by: Adam Shobash adams@marvell.com Cc: Adam Shobash adams@marvell.com Cc: Nadav Haklai nadavh@marvell.com Cc: Konstantin Porotchkin kostap@marvell.com
Applied to u-boot-marvell/master.
Thanks, Stefan
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Stefan Roese