The directory here is misspelled. Fix it.

Signed-off-by: Simon Glass sjg@chromium.org ---

board/solidrun/clearfog/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/solidrun/clearfog/MAINTAINERS b/board/solidrun/clearfog/MAINTAINERS index 298e5011c79..6d0c3ef58bd 100644 --- a/board/solidrun/clearfog/MAINTAINERS +++ b/board/solidrun/clearfog/MAINTAINERS @@ -1,6 +1,6 @@ CLEARFOG BOARD M: Stefan Roese sr@denx.de S: Maintained -F: board/soldrun/clearfog/ +F: board/solidrun/clearfog/ F: include/configs/clearfog.h F: configs/clearfog_defconfig

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/Kconfig | 1 - board/freescale/ls1043ardb/Kconfig | 41 --- board/freescale/ls1043ardb/MAINTAINERS | 16 - board/freescale/ls1043ardb/Makefile | 10 - board/freescale/ls1043ardb/README | 54 ---- board/freescale/ls1043ardb/cpld.c | 173 ----------- board/freescale/ls1043ardb/cpld.h | 45 --- board/freescale/ls1043ardb/ddr.c | 238 --------------- board/freescale/ls1043ardb/ddr.h | 116 ------- board/freescale/ls1043ardb/eth.c | 76 ----- board/freescale/ls1043ardb/ls1043ardb.c | 221 -------------- board/freescale/ls1043ardb/ls1043ardb_pbi.cfg | 14 - .../ls1043ardb/ls1043ardb_rcw_nand.cfg | 7 - .../ls1043ardb/ls1043ardb_rcw_sd.cfg | 7 - configs/ls1043ardb_SECURE_BOOT_defconfig | 51 ---- configs/ls1043ardb_defconfig | 49 --- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 68 ----- configs/ls1043ardb_nand_defconfig | 66 ---- .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 66 ---- configs/ls1043ardb_sdcard_defconfig | 64 ---- include/configs/ls1043ardb.h | 285 ------------------ 21 files changed, 1668 deletions(-) delete mode 100644 board/freescale/ls1043ardb/Kconfig delete mode 100644 board/freescale/ls1043ardb/MAINTAINERS delete mode 100644 board/freescale/ls1043ardb/Makefile delete mode 100644 board/freescale/ls1043ardb/README delete mode 100644 board/freescale/ls1043ardb/cpld.c delete mode 100644 board/freescale/ls1043ardb/cpld.h delete mode 100644 board/freescale/ls1043ardb/ddr.c delete mode 100644 board/freescale/ls1043ardb/ddr.h delete mode 100644 board/freescale/ls1043ardb/eth.c delete mode 100644 board/freescale/ls1043ardb/ls1043ardb.c delete mode 100644 board/freescale/ls1043ardb/ls1043ardb_pbi.cfg delete mode 100644 board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg delete mode 100644 board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg delete mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043ardb_defconfig delete mode 100644 configs/ls1043ardb_nand_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043ardb_nand_defconfig delete mode 100644 configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043ardb_sdcard_defconfig delete mode 100644 include/configs/ls1043ardb.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 11f2e0f826d..08d6db1cadf 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1513,7 +1513,6 @@ source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/ls1021aiot/Kconfig" source "board/freescale/ls1046aqds/Kconfig" -source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/ls1046ardb/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig deleted file mode 100644 index 3d9e295c4e7..00000000000 --- a/board/freescale/ls1043ardb/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ - -if TARGET_LS1043ARDB - -config SYS_BOARD - default "ls1043ardb" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1043ardb" - -config SYS_HAS_ARMV8_SECURE_BASE - bool "Enable secure address for PSCI image" - depends on ARMV8_PSCI - default n - help - PSCI image can be re-located to secure RAM. - If enabled, please also define the value for ARMV8_SECURE_BASE, - for LS1043ARDB, it could be some address in OCRAM. - -if FSL_LS_PPA -config SYS_LS_PPA_FW_ADDR - hex "PPA Firmware Addr" - default 0x60400000 if SYS_LS_PPA_FW_IN_XIP - default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND - -if CHAIN_OF_TRUST -config SYS_LS_PPA_ESBC_ADDR - hex "PPA Firmware HDR Addr" - default 0x60680000 if SYS_LS_PPA_FW_IN_XIP - default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND -endif -endif - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS deleted file mode 100644 index 88fe42e1e8a..00000000000 --- a/board/freescale/ls1043ardb/MAINTAINERS +++ /dev/null @@ -1,16 +0,0 @@ -LS1043A BOARD -M: Mingkai Hu mingkai.hu@nxp.com -S: Maintained -F: board/freescale/ls1043ardb/ -F: board/freescale/ls1043ardb/ls1043ardb.c -F: include/configs/ls1043ardb.h -F: configs/ls1043ardb_defconfig -F: configs/ls1043ardb_nand_defconfig -F: configs/ls1043ardb_sdcard_defconfig - -LS1043A_SECURE_BOOT BOARD -M: Ruchika Gupta ruchika.gupta@nxp.com -S: Maintained -F: configs/ls1043ardb_SECURE_BOOT_defconfig -F: configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig -F: configs/ls1043ardb_nand_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile deleted file mode 100644 index 5309576c688..00000000000 --- a/board/freescale/ls1043ardb/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2015 Freescale Semiconductor - -obj-y += ddr.o -obj-y += ls1043ardb.o -ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_NET) += eth.o -obj-y += cpld.o -endif diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README deleted file mode 100644 index 709ddbbef31..00000000000 --- a/board/freescale/ls1043ardb/README +++ /dev/null @@ -1,54 +0,0 @@ -Overview --------- -The LS1043A Reference Design Board (RDB) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS1043A -LayerScape Architecture processor. The LS1043ARDB provides SW development -platform for the Freescale LS1043A processor series, with a complete -debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. - -LS1043A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A -SoC overview. - - LS1043ARDB board Overview - ----------------------- - - SERDES Connections, 4 lanes supporting: - - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and - standard PCIe card - - QSGMII with x4 RJ45 connector - - XFI with x1 RJ45 connector - - DDR Controller - - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s - -IFC/Local Bus - - One 128MB NOR flash 16-bit data bus - - One 512 MB NAND flash with ECC support - - CPLD connection - - USB 3.0 - - Two super speed USB 3.0 Type A ports - - SDHC: connects directly to a full SD/MMC slot - - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) - - 4 I2C controllers - - UART - - Two 4-pin serial ports at up to 115.2 Kbit/s - - Two DB9 D-Type connectors supporting one Serial port each - - ARM JTAG support - -Memory map from core's view ----------------------------- -Start Address End Address Description Size -0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB -0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB -0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB -0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB -0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB -0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB -0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB - -Booting Options ---------------- -a) NOR boot -b) NAND boot -c) SD boot diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c deleted file mode 100644 index 00c70b1e49d..00000000000 --- a/board/freescale/ls1043ardb/cpld.c +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor - * - * Freescale LS1043ARDB board-specific CPLD controlling supports. - */ - -#include <common.h> -#include <command.h> -#include <asm/io.h> -#include "cpld.h" - -u8 cpld_read(unsigned int reg) -{ - void *p = (void *)CONFIG_SYS_CPLD_BASE; - - return in_8(p + reg); -} - -void cpld_write(unsigned int reg, u8 value) -{ - void *p = (void *)CONFIG_SYS_CPLD_BASE; - - out_8(p + reg, value); -} - -/* Set the boot bank to the alternate bank */ -void cpld_set_altbank(void) -{ - u16 reg = CPLD_CFG_RCW_SRC_NOR; - u8 reg4 = CPLD_READ(soft_mux_on); - u8 reg5 = (u8)(reg >> 1); - u8 reg6 = (u8)(reg & 1); - u8 reg7 = CPLD_READ(vbank); - - cpld_rev_bit(&reg5); - - CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); - - CPLD_WRITE(cfg_rcw_src1, reg5); - CPLD_WRITE(cfg_rcw_src2, reg6); - - reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; - CPLD_WRITE(vbank, reg7); - - CPLD_WRITE(system_rst, 1); -} - -/* Set the boot bank to the default bank */ -void cpld_set_defbank(void) -{ - u16 reg = CPLD_CFG_RCW_SRC_NOR; - u8 reg4 = CPLD_READ(soft_mux_on); - u8 reg5 = (u8)(reg >> 1); - u8 reg6 = (u8)(reg & 1); - - cpld_rev_bit(&reg5); - - CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); - - CPLD_WRITE(cfg_rcw_src1, reg5); - CPLD_WRITE(cfg_rcw_src2, reg6); - - CPLD_WRITE(vbank, 0); - - CPLD_WRITE(system_rst, 1); -} - -void cpld_set_nand(void) -{ - u16 reg = CPLD_CFG_RCW_SRC_NAND; - u8 reg5 = (u8)(reg >> 1); - u8 reg6 = (u8)(reg & 1); - - cpld_rev_bit(&reg5); - - CPLD_WRITE(soft_mux_on, 1); - - CPLD_WRITE(cfg_rcw_src1, reg5); - CPLD_WRITE(cfg_rcw_src2, reg6); - - CPLD_WRITE(system_rst, 1); -} - -void cpld_set_sd(void) -{ - u16 reg = CPLD_CFG_RCW_SRC_SD; - u8 reg5 = (u8)(reg >> 1); - u8 reg6 = (u8)(reg & 1); - - cpld_rev_bit(&reg5); - - CPLD_WRITE(soft_mux_on, 1); - - CPLD_WRITE(cfg_rcw_src1, reg5); - CPLD_WRITE(cfg_rcw_src2, reg6); - - CPLD_WRITE(system_rst, 1); -} -#ifdef DEBUG -static void cpld_dump_regs(void) -{ - printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); - printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub)); - printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); - printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); - printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1)); - printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2)); - printf("vbank = %x\n", CPLD_READ(vbank)); - printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); - printf("uart_sel = %x\n", CPLD_READ(uart_sel)); - printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel)); - printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel)); - printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel)); - printf("status_led = %x\n", CPLD_READ(status_led)); - putc('\n'); -} -#endif - -void cpld_rev_bit(unsigned char *value) -{ - u8 rev_val, val; - int i; - - val = *value; - rev_val = val & 1; - for (i = 1; i <= 7; i++) { - val >>= 1; - rev_val <<= 1; - rev_val |= val & 1; - } - - *value = rev_val; -} - -int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int rc = 0; - - if (argc <= 1) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "reset") == 0) { - if (strcmp(argv[2], "altbank") == 0) - cpld_set_altbank(); - else if (strcmp(argv[2], "nand") == 0) - cpld_set_nand(); - else if (strcmp(argv[2], "sd") == 0) - cpld_set_sd(); - else - cpld_set_defbank(); -#ifdef DEBUG - } else if (strcmp(argv[1], "dump") == 0) { - cpld_dump_regs(); -#endif - } else { - rc = cmd_usage(cmdtp); - } - - return rc; -} - -U_BOOT_CMD( - cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, - "Reset the board or alternate bank", - "reset: reset to default bank\n" - "cpld reset altbank: reset to alternate bank\n" - "cpld reset nand: reset to boot from NAND flash\n" - "cpld reset sd: reset to boot from SD card\n" -#ifdef DEBUG - "cpld dump - display the CPLD registers\n" -#endif -); diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h deleted file mode 100644 index 2e757b557f4..00000000000 --- a/board/freescale/ls1043ardb/cpld.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor - */ - -#ifndef __CPLD_H__ -#define __CPLD_H__ - -/* - * CPLD register set of LS1043ARDB board-specific. - */ -struct cpld_data { - u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ - u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ - u8 pcba_ver; /* 0x2 - PCBA Revision Register */ - u8 system_rst; /* 0x3 - system reset register */ - u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */ - u8 cfg_rcw_src1; /* 0x5 - Reset config word 1 */ - u8 cfg_rcw_src2; /* 0x6 - Reset config word 1 */ - u8 vbank; /* 0x7 - Flash bank selection Control */ - u8 sysclk_sel; /* 0x8 - */ - u8 uart_sel; /* 0x9 - */ - u8 sd1refclk_sel; /* 0xA - */ - u8 tdmclk_mux_sel; /* 0xB - */ - u8 sdhc_spics_sel; /* 0xC - */ - u8 status_led; /* 0xD - */ - u8 global_rst; /* 0xE - */ -}; - -u8 cpld_read(unsigned int reg); -void cpld_write(unsigned int reg, u8 value); -void cpld_rev_bit(unsigned char *value); - -#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) -#define CPLD_WRITE(reg, value) \ - cpld_write(offsetof(struct cpld_data, reg), value) - -/* CPLD on IFC */ -#define CPLD_SW_MUX_BANK_SEL 0x40 -#define CPLD_BANK_SEL_MASK 0x07 -#define CPLD_BANK_SEL_ALTBANK 0x04 -#define CPLD_CFG_RCW_SRC_NOR 0x025 -#define CPLD_CFG_RCW_SRC_NAND 0x106 -#define CPLD_CFG_RCW_SRC_SD 0x040 -#endif diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c deleted file mode 100644 index 7bc0f568ffb..00000000000 --- a/board/freescale/ls1043ardb/ddr.c +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include "ddr.h" -#ifdef CONFIG_FSL_DEEP_SLEEP -#include <fsl_sleep.h> -#endif -#include <asm/arch/clock.h> - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->cpo_override = pbsp->cpo_override; - popts->write_data_delay = - pbsp->write_data_delay; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for %lu MT/s\n", - ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); - - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 1; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x46; - - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ -} - -/* DDR model number: MT40A512M8HX-093E */ -#ifdef CONFIG_SYS_DDR_RAW_TIMING -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 2147483648u, - .capacity = 2147483648u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .bank_addr_bits = 0, - .bank_group_bits = 2, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 938, - .tckmax_ps = 1500, - .caslat_x = 0x000DFA00, - .taa_ps = 13500, - .trcd_ps = 13500, - .trp_ps = 13500, - .tras_ps = 33000, - .trc_ps = 46500, - .trfc1_ps = 260000, - .trfc2_ps = 160000, - .trfc4_ps = 110000, - .tfaw_ps = 21000, - .trrds_ps = 3700, - .trrdl_ps = 5300, - .tccdl_ps = 5355, - .refresh_rate_ps = 7800000, - .dq_mapping[0] = 0x0, - .dq_mapping[1] = 0x0, - .dq_mapping[2] = 0x0, - .dq_mapping[3] = 0x0, - .dq_mapping[4] = 0x0, - .dq_mapping[5] = 0x0, - .dq_mapping[6] = 0x0, - .dq_mapping[7] = 0x0, - .dq_mapping[8] = 0x0, - .dq_mapping[9] = 0x0, - .dq_mapping[10] = 0x0, - .dq_mapping[11] = 0x0, - .dq_mapping[12] = 0x0, - .dq_mapping[13] = 0x0, - .dq_mapping[14] = 0x0, - .dq_mapping[15] = 0x0, - .dq_mapping[16] = 0x0, - .dq_mapping[17] = 0x0, - .dq_mapping_ors = 0, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - static const char dimm_model[] = "Fixed DDR on board"; - - if (((controller_number == 0) && (dimm_number == 0)) || - ((controller_number == 1) && (dimm_number == 0))) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} -#else - -phys_size_t fixed_sdram(void) -{ - int i; - char buf[32]; - fsl_ddr_cfg_regs_t ddr_cfg_regs; - phys_size_t ddr_size; - ulong ddr_freq, ddr_freq_mhz; - - ddr_freq = get_ddr_freq(0); - ddr_freq_mhz = ddr_freq / 1000000; - - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { - if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && - (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { - memcpy(&ddr_cfg_regs, - fixed_ddr_parm_0[i].ddr_settings, - sizeof(ddr_cfg_regs)); - break; - } - } - - if (fixed_ddr_parm_0[i].max_freq == 0) - panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - ddr_size = (phys_size_t)2048 * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - - return ddr_size; -} -#endif - -int fsl_initdram(void) -{ - phys_size_t dram_size; - -#ifdef CONFIG_SYS_DDR_RAW_TIMING -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) - puts("Initializing DDR....\n"); - dram_size = fsl_ddr_sdram(); -#else - dram_size = fsl_ddr_sdram_size(); -#endif -#else -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) - puts("Initialzing DDR using fixed setting\n"); - dram_size = fixed_sdram(); -#else - gd->ram_size = 0x80000000; - - return 0; -#endif -#endif - erratum_a008850_post(); - -#ifdef CONFIG_FSL_DEEP_SLEEP - fsl_dp_ddr_restore(); -#endif - - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h deleted file mode 100644 index 85ed920ca6d..00000000000 --- a/board/freescale/ls1043ardb/ddr.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ - -extern void erratum_a008850_post(void); - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; - u32 cpo_override; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ -#ifdef CONFIG_SYS_FSL_DDR4 - {1, 1666, 0, 12, 7, 0x07090800, 0x00000000,}, - {1, 1900, 0, 12, 7, 0x07090800, 0x00000000,}, - {1, 2200, 0, 12, 7, 0x07090800, 0x00000000,}, -#endif - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -#ifndef CONFIG_SYS_DDR_RAW_TIMING -fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = { - .cs[0].bnds = 0x0000007F, - .cs[1].bnds = 0, - .cs[2].bnds = 0, - .cs[3].bnds = 0, - .cs[0].config = 0x80040322, - .cs[0].config_2 = 0, - .cs[1].config = 0, - .cs[1].config_2 = 0, - .cs[2].config = 0, - .cs[3].config = 0, - .timing_cfg_3 = 0x010C1000, - .timing_cfg_0 = 0x91550018, - .timing_cfg_1 = 0xBBB48C42, - .timing_cfg_2 = 0x0048C111, - .ddr_sdram_cfg = 0xC50C0008, - .ddr_sdram_cfg_2 = 0x00401100, - .ddr_sdram_cfg_3 = 0, - .ddr_sdram_mode = 0x03010210, - .ddr_sdram_mode_2 = 0, - .ddr_sdram_mode_3 = 0x00010210, - .ddr_sdram_mode_4 = 0, - .ddr_sdram_mode_5 = 0x00010210, - .ddr_sdram_mode_6 = 0, - .ddr_sdram_mode_7 = 0x00010210, - .ddr_sdram_mode_8 = 0, - .ddr_sdram_mode_9 = 0x00000500, - .ddr_sdram_mode_10 = 0x04000000, - .ddr_sdram_mode_11 = 0x00000400, - .ddr_sdram_mode_12 = 0x04000000, - .ddr_sdram_mode_13 = 0x00000400, - .ddr_sdram_mode_14 = 0x04000000, - .ddr_sdram_mode_15 = 0x00000400, - .ddr_sdram_mode_16 = 0x04000000, - .ddr_sdram_interval = 0x18600618, - .ddr_data_init = 0xDEADBEEF, - .ddr_sdram_clk_cntl = 0x03000000, - .ddr_init_addr = 0, - .ddr_init_ext_addr = 0, - .timing_cfg_4 = 0x00000002, - .timing_cfg_5 = 0x03401400, - .timing_cfg_6 = 0, - .timing_cfg_7 = 0x13300000, - .timing_cfg_8 = 0x02115600, - .timing_cfg_9 = 0, - .ddr_zq_cntl = 0x8A090705, - .ddr_wrlvl_cntl = 0x8675F607, - .ddr_wrlvl_cntl_2 = 0x07090800, - .ddr_wrlvl_cntl_3 = 0, - .ddr_sr_cntr = 0, - .ddr_sdram_rcw_1 = 0, - .ddr_sdram_rcw_2 = 0, - .ddr_cdr1 = 0x80040000, - .ddr_cdr2 = 0x0000A181, - .dq_map_0 = 0, - .dq_map_1 = 0, - .dq_map_2 = 0, - .dq_map_3 = 0, - .debug[28] = 0x00700046, - -}; - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {1550, 1650, &ddr_cfg_regs_1600}, - {0, 0, NULL} -}; - -#endif -#endif diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c deleted file mode 100644 index a8d0c1109b4..00000000000 --- a/board/freescale/ls1043ardb/eth.c +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ -#include <common.h> -#include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_dtsec.h> -#include <fsl_mdio.h> -#include <malloc.h> - -#include "../common/fman.h" - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_FMAN_ENET - int i; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR); - - switch (srds_s1) { - case 0x1455: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) - fm_info_set_mdio(i, dev); - - /* XFI on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(FM1_10GEC1, dev); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c deleted file mode 100644 index f31f0ec515d..00000000000 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ /dev/null @@ -1,221 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <i2c.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/fsl_serdes.h> -#include <asm/arch/soc.h> -#include <asm/arch-fsl-layerscape/fsl_icid.h> -#include <fdt_support.h> -#include <hwconfig.h> -#include <ahci.h> -#include <mmc.h> -#include <scsi.h> -#include <fm_eth.h> -#include <fsl_esdhc.h> -#include <fsl_ifc.h> -#include <fsl_sec.h> -#include "cpld.h" -#ifdef CONFIG_U_QE -#include <fsl_qe.h> -#endif -#include <asm/arch/ppa.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - fsl_lsch2_early_init_f(); - - return 0; -} - -#ifndef CONFIG_SPL_BUILD - -int checkboard(void) -{ - static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; -#ifndef CONFIG_SD_BOOT - u8 cfg_rcw_src1, cfg_rcw_src2; - u16 cfg_rcw_src; -#endif - u8 sd1refclk_sel; - - printf("Board: LS1043ARDB, boot from "); - -#ifdef CONFIG_SD_BOOT - puts("SD\n"); -#else - cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); - cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); - cpld_rev_bit(&cfg_rcw_src1); - cfg_rcw_src = cfg_rcw_src1; - cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; - - if (cfg_rcw_src == 0x25) - printf("vBank %d\n", CPLD_READ(vbank)); - else if (cfg_rcw_src == 0x106) - puts("NAND\n"); - else - printf("Invalid setting of SW4\n"); -#endif - - printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), - CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); - - puts("SERDES Reference Clocks:\n"); - sd1refclk_sel = CPLD_READ(sd1refclk_sel); - printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); - - return 0; -} - -int board_init(void) -{ - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - -#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 - erratum_a010315(); -#endif - -#ifdef CONFIG_FSL_IFC - init_final_memctl_regs(); -#endif - -#ifdef CONFIG_SECURE_BOOT - /* In case of Secure Boot, the IBR configures the SMMU - * to allow only Secure transactions. - * SMMU must be reset in bypass mode. - * Set the ClientPD bit and Clear the USFCFG Bit - */ - u32 val; - val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); - out_le32(SMMU_SCR0, val); - val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); - out_le32(SMMU_NSCR0, val); -#endif - -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - -#ifdef CONFIG_FSL_LS_PPA - ppa_init(); -#endif - -#ifdef CONFIG_U_QE - u_qe_init(); -#endif - /* invert AQR105 IRQ pins polarity */ - out_be32(&scfg->intpcr, AQR105_IRQ_MASK); - - return 0; -} - -int config_board_mux(void) -{ - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - u32 usb_pwrfault; - - if (hwconfig("qe-hdlc")) { - out_be32(&scfg->rcwpmuxcr0, - (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600); - printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n", - in_be32(&scfg->rcwpmuxcr0)); - } else { -#ifdef CONFIG_HAS_FSL_XHCI_USB - out_be32(&scfg->rcwpmuxcr0, 0x3333); - out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); - usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB3_SHIFT) | - (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB2_SHIFT) | - (SCFG_USBPWRFAULT_SHARED << - SCFG_USBPWRFAULT_USB1_SHIFT); - out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); -#endif - } - return 0; -} - -#if defined(CONFIG_MISC_INIT_R) -int misc_init_r(void) -{ - config_board_mux(); - return 0; -} -#endif - -void fdt_del_qe(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,qe")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - - /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - - fdt_fixup_memory_banks(blob, base, size, 2); - ft_cpu_setup(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN - fdt_fixup_fman_ethernet(blob); -#endif - - fdt_fixup_icid(blob); - - /* - * qe-hdlc and usb multi-use the pins, - * when set hwconfig to qe-hdlc, delete usb node. - */ - if (hwconfig("qe-hdlc")) -#ifdef CONFIG_HAS_FSL_XHCI_USB - fdt_del_node_and_alias(blob, "usb1"); -#endif - /* - * qe just support qe-uart and qe-hdlc, - * if qe-uart and qe-hdlc are not set in hwconfig, - * delete qe node. - */ - if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc")) - fdt_del_qe(blob); - - return 0; -} - -u8 flash_read8(void *addr) -{ - return __raw_readb(addr + 1); -} - -void flash_write16(u16 val, void *addr) -{ - u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); - - __raw_writew(shftval, addr); -} - -u16 flash_read16(void *addr) -{ - u16 val = __raw_readw(addr); - - return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); -} - -#endif diff --git a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg deleted file mode 100644 index f072274f474..00000000000 --- a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg +++ /dev/null @@ -1,14 +0,0 @@ -#Configure Scratch register -09570600 00000000 -09570604 10000000 -#Alt base register -09570158 00001000 -#Disable CCI barrier tranaction -09570178 0000e010 -09180000 00000008 -#USB PHY frequency sel -09570418 0000009e -0957041c 0000009e -09570420 0000009e -#flush PBI data -096100c0 000fffff diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg deleted file mode 100644 index d87058b7efe..00000000000 --- a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# serdes protocol -08100010 0a000000 00000000 00000000 -14550002 80004012 e0106000 c1002000 -00000000 00000000 00000000 00038800 -00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg deleted file mode 100644 index e2ee34b7dfc..00000000000 --- a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# RCW -08100010 0a000000 00000000 00000000 -14550002 80004012 60040000 c1002000 -00000000 00000000 00000000 00038800 -00000000 00001100 00000096 00000001 diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig deleted file mode 100644 index 41df0b9fbfa..00000000000 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ /dev/null @@ -1,51 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS1043ARDB=y -CONFIG_SYS_TEXT_BASE=0x60100000 -CONFIG_SECURE_BOOT=y -CONFIG_FSL_LS_PPA=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_MISC_INIT_R=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MP=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" -CONFIG_DM=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig deleted file mode 100644 index 7541fad3db4..00000000000 --- a/configs/ls1043ardb_defconfig +++ /dev/null @@ -1,49 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS1043ARDB=y -CONFIG_SYS_TEXT_BASE=0x60100000 -CONFIG_FSL_LS_PPA=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_MISC_INIT_R=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MP=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_E1000=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig deleted file mode 100644 index 2879f45d564..00000000000 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ /dev/null @@ -1,68 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS1043ARDB=y -CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SECURE_BOOT=y -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" -CONFIG_NAND_BOOT=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 -CONFIG_SPL_CRYPTO_SUPPORT=y -CONFIG_SPL_HASH_SUPPORT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MP=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" -CONFIG_DM=y -CONFIG_SPL_DM=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_E1000=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig deleted file mode 100644 index 5a23e3cfff5..00000000000 --- a/configs/ls1043ardb_nand_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS1043ARDB=y -CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" -CONFIG_NAND_BOOT=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_MISC_INIT_R=y -CONFIG_SPL_BOARD_INIT=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MP=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_E1000=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig deleted file mode 100644 index 3c196944568..00000000000 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS1043ARDB=y -CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SECURE_BOOT=y -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" -CONFIG_SD_BOOT=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 -CONFIG_SPL_CRYPTO_SUPPORT=y -CONFIG_SPL_HASH_SUPPORT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MP=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" -CONFIG_DM=y -CONFIG_SPL_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig deleted file mode 100644 index 144e48b885b..00000000000 --- a/configs/ls1043ardb_sdcard_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS1043ARDB=y -CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" -CONFIG_SD_BOOT=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_MISC_INIT_R=y -CONFIG_SPL_BOARD_INIT=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MP=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_E1000=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h deleted file mode 100644 index 54e6eef417b..00000000000 --- a/include/configs/ls1043ardb.h +++ /dev/null @@ -1,285 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor - */ - -#ifndef __LS1043ARDB_H__ -#define __LS1043ARDB_H__ - -#include "ls1043a_common.h" - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 - -#define CONFIG_LAYERSCAPE_NS_ACCESS - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -/* Physical Memory Map */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -#define CONFIG_SYS_SPD_BUS_NUM 0 - -#ifndef CONFIG_SPL -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ -#define CONFIG_FSL_DDR_BIST -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg -#endif - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg -#endif - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg -#define CONFIG_CMD_SPL -#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000 -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500 -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30 -#endif - -/* - * NOR Flash Definitions - */ -#define CONFIG_SYS_NOR_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) - -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ - FTIM0_NOR_TEADC(0x1) | \ - FTIM0_NOR_TAVDS(0x0) | \ - FTIM0_NOR_TEAHC(0xc)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ - FTIM1_NOR_TRAD_NOR(0xb) | \ - FTIM1_NOR_TSEQRAD_NOR(0x9)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x8) | \ - FTIM2_NOR_TWP(0x10)) -#define CONFIG_SYS_NOR_FTIM3 0 -#define CONFIG_SYS_IFC_CCR 0x01000000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } - -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_WRITE_SWAPPED_DATA - -/* - * NAND Flash Definitions - */ -#ifndef SPL_NO_IFC -#define CONFIG_NAND_FSL_IFC -#endif - -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_NAND \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x7) | \ - FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0xe) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ - FTIM2_NAND_TREH(0xa) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) -#endif - -/* - * CPLD - */ -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE - -#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) -#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ - CSPR_PORT_SIZE_8 | \ - CSPR_MSEL_GPCM | \ - CSPR_V) -#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_NOR_MODE_AVD_NOR | \ - CSOR_NOR_TRHZ_80) - -/* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ - FTIM0_GPCM_TEADC(0xf) | \ - FTIM0_GPCM_TEAHC(0xf)) -#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ - FTIM2_GPCM_TCH(0xf) | \ - FTIM2_GPCM_TWP(0xff)) -#define CONFIG_SYS_CPLD_FTIM3 0x0 - -/* IFC Timing Params */ -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 - -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 - -/* EEPROM */ -#ifndef SPL_NO_EEPROM -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#endif - -/* - * Environment - */ -#ifndef SPL_NO_ENV -#define CONFIG_ENV_OVERWRITE -#endif - -#if defined(CONFIG_NAND_BOOT) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x20000 -#endif - -/* FMan */ -#ifndef SPL_NO_FMAN -#define AQR105_IRQ_MASK 0x40000000 - -#ifdef CONFIG_NET -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#endif - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_FMAN_ENET - -#define RGMII_PHY1_ADDR 0x1 -#define RGMII_PHY2_ADDR 0x2 - -#define QSGMII_PORT1_PHY_ADDR 0x4 -#define QSGMII_PORT2_PHY_ADDR 0x5 -#define QSGMII_PORT3_PHY_ADDR 0x6 -#define QSGMII_PORT4_PHY_ADDR 0x7 - -#define FM1_10GEC1_PHY_ADDR 0x1 - -#define CONFIG_ETHPRIME "FM1@DTSEC3" -#endif -#endif - -/* SATA */ -#ifndef SPL_NO_SATA -#ifndef CONFIG_CMD_EXT2 -#define CONFIG_CMD_EXT2 -#endif -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 2 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#define SCSI_VEND_ID 0x1b4b -#define SCSI_DEV_ID 0x9170 -#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} -#endif - -#include <asm/fsl_secure_boot.h> - -#endif /* __LS1043ARDB_H__ */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-imx/mx6/Kconfig | 1 - .../toradex/colibri_imx6/800mhz_2x64mx16.cfg | 58 - .../toradex/colibri_imx6/800mhz_4x64mx16.cfg | 58 - board/toradex/colibri_imx6/Kconfig | 44 - board/toradex/colibri_imx6/MAINTAINERS | 8 - board/toradex/colibri_imx6/Makefile | 5 - board/toradex/colibri_imx6/clocks.cfg | 41 - board/toradex/colibri_imx6/colibri_imx6.c | 1121 ----------------- board/toradex/colibri_imx6/colibri_imx6.cfg | 37 - board/toradex/colibri_imx6/ddr-setup.cfg | 97 -- board/toradex/colibri_imx6/do_fuse.c | 97 -- board/toradex/colibri_imx6/pf0100.c | 212 ---- board/toradex/colibri_imx6/pf0100.h | 52 - board/toradex/colibri_imx6/pf0100_otp.inc | 188 --- configs/colibri_imx6_defconfig | 73 -- configs/colibri_imx6_nospl_defconfig | 61 - include/configs/colibri_imx6.h | 251 ---- 17 files changed, 2404 deletions(-) delete mode 100644 board/toradex/colibri_imx6/800mhz_2x64mx16.cfg delete mode 100644 board/toradex/colibri_imx6/800mhz_4x64mx16.cfg delete mode 100644 board/toradex/colibri_imx6/Kconfig delete mode 100644 board/toradex/colibri_imx6/MAINTAINERS delete mode 100644 board/toradex/colibri_imx6/Makefile delete mode 100644 board/toradex/colibri_imx6/clocks.cfg delete mode 100644 board/toradex/colibri_imx6/colibri_imx6.c delete mode 100644 board/toradex/colibri_imx6/colibri_imx6.cfg delete mode 100644 board/toradex/colibri_imx6/ddr-setup.cfg delete mode 100644 board/toradex/colibri_imx6/do_fuse.c delete mode 100644 board/toradex/colibri_imx6/pf0100.c delete mode 100644 board/toradex/colibri_imx6/pf0100.h delete mode 100644 board/toradex/colibri_imx6/pf0100_otp.inc delete mode 100644 configs/colibri_imx6_defconfig delete mode 100644 configs/colibri_imx6_nospl_defconfig delete mode 100644 include/configs/colibri_imx6.h

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 06c25bae362..fb25bc81e11 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -563,7 +563,6 @@ source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/toradex/apalis_imx6/Kconfig" -source "board/toradex/colibri_imx6/Kconfig" source "board/toradex/colibri-imx6ull/Kconfig" source "board/k+p/kp_imx6q_tpc/Kconfig" source "board/udoo/Kconfig" diff --git a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg deleted file mode 100644 index c9407143d23..00000000000 --- a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - */ - -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D -DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x00301023 -DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D -/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */ -DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 -/* DDR3 DATA BUS SIZE: 64BIT */ -/* DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 */ -/* DDR3 DATA BUS SIZE: 32BIT */ -DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 - -/* Write commands to DDR */ -/* Load Mode Registers */ -/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ -/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 -/* ZQ calibration */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 - -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 - -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 - -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218 - -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344 -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930 - -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039 -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D - -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg deleted file mode 100644 index c319d2a7296..00000000000 --- a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - */ - -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D -DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x00301023 -DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D -/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */ -DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 -/* DDR3 DATA BUS SIZE: 64BIT */ -DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 -/* DDR3 DATA BUS SIZE: 32BIT */ -/* DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 */ - -/* Write commands to DDR */ -/* Load Mode Registers */ -/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ -/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 -/* ZQ calibration */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 - -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 - -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 - -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218 - -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344 -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930 - -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039 -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D - -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/colibri_imx6/Kconfig b/board/toradex/colibri_imx6/Kconfig deleted file mode 100644 index d2ad1ce2a03..00000000000 --- a/board/toradex/colibri_imx6/Kconfig +++ /dev/null @@ -1,44 +0,0 @@ -if TARGET_COLIBRI_IMX6 - -config SYS_BOARD - default "colibri_imx6" - -config SYS_CONFIG_NAME - default "colibri_imx6" - -config SYS_CPU - default "armv7" - -config SYS_SOC - default "mx6" - -config SYS_VENDOR - default "toradex" - -config TDX_CFG_BLOCK - default y - -config TDX_HAVE_MMC - default y - -config TDX_CFG_BLOCK_DEV - default "0" - -config TDX_CFG_BLOCK_PART - default "1" - -# Toradex config block in eMMC, at the end of 1st "boot sector" -config TDX_CFG_BLOCK_OFFSET - default "-512" - -config TDX_CMD_IMX_MFGR - bool "Enable factory testing commands for Toradex iMX 6 modules" - help - This adds the commands - pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100 - If executed on already fused modules it doesn't change any fuse setting. - default y - -source "board/toradex/common/Kconfig" - -endif diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS deleted file mode 100644 index 1cc7ef2e71b..00000000000 --- a/board/toradex/colibri_imx6/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -Colibri iMX6 -M: Max Krummenacher max.krummenacher@toradex.com -W: http://developer.toradex.com/software/linux/linux-software -S: Maintained -F: board/toradex/colibri_imx6/ -F: include/configs/colibri_imx6.h -F: configs/colibri_imx6_defconfig -F: configs/colibri_imx6_nospl_defconfig diff --git a/board/toradex/colibri_imx6/Makefile b/board/toradex/colibri_imx6/Makefile deleted file mode 100644 index c81bc2d741c..00000000000 --- a/board/toradex/colibri_imx6/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2012-2014 Toradex, Inc. -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := colibri_imx6.o do_fuse.o -obj-$(CONFIG_TDX_CMD_IMX_MFGR) += pf0100.o diff --git a/board/toradex/colibri_imx6/clocks.cfg b/board/toradex/colibri_imx6/clocks.cfg deleted file mode 100644 index 1bcbc4fa380..00000000000 --- a/board/toradex/colibri_imx6/clocks.cfg +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0x00FFF300 -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ -DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c deleted file mode 100644 index 68c0c02a8ac..00000000000 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ /dev/null @@ -1,1121 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. - * Copyright (C) 2013, Boundary Devices info@boundarydevices.com - * Copyright (C) 2014-2016, Toradex AG - * copied from nitrogen6x - */ - -#include <common.h> -#include <dm.h> -#include <asm/arch/clock.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/mx6-ddr.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/arch/sys_proto.h> -#include <asm/bootm.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/sata.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/video.h> -#include <asm/io.h> -#include <dm/platform_data/serial_mxc.h> -#include <dm/platdata.h> -#include <fsl_esdhc.h> -#include <i2c.h> -#include <input.h> -#include <imx_thermal.h> -#include <linux/errno.h> -#include <malloc.h> -#include <micrel.h> -#include <miiphy.h> -#include <mmc.h> -#include <netdev.h> - -#include "../common/tdx-cfg-block.h" -#ifdef CONFIG_TDX_CMD_IMX_MFGR -#include "pf0100.h" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_SRE_SLOW) - -#define NO_PULLUP ( \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_SRE_SLOW) - -#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_HYS | PAD_CTL_SRE_SLOW) - -#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) - -#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST) - -int dram_init(void) -{ - /* use the DDR controllers configured size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - (ulong)imx_ddr_size()); - - return 0; -} - -/* Colibri UARTA */ -iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* Colibri I2C */ -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } -}; - -/* Colibri local, PMIC, SGTL5000, STMPE811 */ -struct i2c_pads_info i2c_pad_info_loc = { - .scl = { - .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, - .gp = IMX_GPIO_NR(2, 30) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, - .gp = IMX_GPIO_NR(3, 16) - } -}; - -/* Apalis MMC */ -iomux_v3_cfg_t const usdhc1_pads[] = { - MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -# define GPIO_MMC_CD IMX_GPIO_NR(2, 5) -}; - -/* eMMC */ -iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); -} - -/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */ -iomux_v3_cfg_t const gpio_pads[] = { - /* ADDRESS[17:18] [25] used as GPIO */ - MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP), - /* ADDRESS[19:24] used as GPIO */ - MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), - /* DATA[16:29] [31] used as GPIO */ - MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), - /* DQM[0:3] used as GPIO */ - MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), - /* RDY used as GPIO */ - MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), - /* ADDRESS[16] DATA[30] used as GPIO */ - MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN), - MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), - /* CSI pins used as GPIO */ - MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN), - MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), - /* GPIO */ - MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), - /* USBH_OC */ - MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP), - /* USBC_ID */ - MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), - /* USBC_DET */ - MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), -}; - -static void setup_iomux_gpio(void) -{ - imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); -} - -iomux_v3_cfg_t const usb_pads[] = { - /* USB_PE */ - MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), -# define GPIO_USBH_EN IMX_GPIO_NR(3, 31) -}; - -/* - * UARTs are used in DTE mode, switch the mode on all UARTs before - * any pinmuxing connects a (DCE) output to a transceiver output. - */ -#define UFCR 0x90 /* FIFO Control Register */ -#define UFCR_DCEDTE (1<<6) /* DCE=0 */ - -static void setup_dtemode_uart(void) -{ - setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE); - setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE); - setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE); -} - -static void setup_iomux_uart(void) -{ - setup_dtemode_uart(); - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -#ifdef CONFIG_USB_EHCI_MX6 -int board_ehci_hcd_init(int port) -{ - imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); - return 0; -} - -int board_ehci_power(int port, int on) -{ - switch (port) { - case 0: - /* control OTG power */ - /* No special PE for USBC, always on when ID pin signals - host mode */ - break; - case 1: - /* Control MXM USBH */ - /* Set MXM USBH power enable, '0' means on */ - gpio_direction_output(GPIO_USBH_EN, !on); - mdelay(100); - break; - default: - break; - } - return 0; -} -#endif - -#ifdef CONFIG_FSL_ESDHC -/* use the following sequence: eMMC, MMC */ -struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { - {USDHC3_BASE_ADDR}, - {USDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = true; /* default: assume inserted */ - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - gpio_direction_input(GPIO_MMC_CD); - ret = !gpio_get_value(GPIO_MMC_CD); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ -#ifndef CONFIG_SPL_BUILD - s32 status = 0; - u32 index = 0; - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - usdhc_cfg[0].max_bus_width = 8; - usdhc_cfg[1].max_bus_width = 4; - - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - break; - default: - printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; - } - - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - } - - return status; -#else - struct src *psrc = (struct src *)SRC_BASE_ADDR; - unsigned reg = readl(&psrc->sbmr1) >> 11; - /* - * Upon reading BOOT_CFG register the following map is done: - * Bit 11 and 12 of BOOT_CFG register can determine the current - * mmc port - * 0x1 SD1 - * 0x2 SD2 - * 0x3 SD4 - */ - - switch (reg & 0x3) { - case 0x0: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - break; - case 0x2: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - break; - default: - puts("MMC boot device not available"); - } - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -#endif -} -#endif - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - uint32_t base = IMX_FEC_BASE; - struct mii_dev *bus = NULL; - struct phy_device *phydev = NULL; - int ret; - - /* provide the PHY clock from the i.MX 6 */ - ret = enable_fec_anatop_clock(0, ENET_50MHZ); - if (ret) - return ret; - /* set gpr1[ENET_CLK_SEL] */ - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); - - setup_iomux_enet(); - -#ifdef CONFIG_FEC_MXC - bus = fec_get_miibus(base, -1); - if (!bus) - return 0; - /* scan PHY 1..7 */ - phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII); - if (!phydev) { - free(bus); - puts("no PHY found\n"); - return 0; - } - phy_reset(phydev); - printf("using PHY at %d\n", phydev->addr); - ret = fec_probe(bis, -1, base, bus, phydev); - if (ret) { - printf("FEC MXC: %s:failed\n", __func__); - free(phydev); - free(bus); - } -#endif - return 0; -} - -static iomux_v3_cfg_t const pwr_intb_pads[] = { - /* - * the bootrom sets the iomux to vselect, potentially connecting - * two outputs. Set this back to GPIO - */ - MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) -}; - -#if defined(CONFIG_VIDEO_IPUV3) - -static iomux_v3_cfg_t const backlight_pads[] = { - /* Backlight On */ - MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL), -#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26) - /* Backlight PWM, used as GPIO in U-Boot */ - MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP), - MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), -#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9) -}; - -static iomux_v3_cfg_t const rgb_pads[] = { - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB), - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB), -}; - -static void do_enable_hdmi(struct display_info_t const *dev) -{ - imx_enable_hdmi_phy(); -} - -static void enable_rgb(struct display_info_t const *dev) -{ - imx_iomux_v3_setup_multiple_pads( - rgb_pads, - ARRAY_SIZE(rgb_pads)); - gpio_direction_output(RGB_BACKLIGHT_GP, 1); - gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); -} - -static int detect_default(struct display_info_t const *dev) -{ - (void) dev; - return 1; -} - -struct display_info_t const displays[] = {{ - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = do_enable_hdmi, - .mode = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} }, { - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB666, - .detect = detect_default, - .enable = enable_rgb, - .mode = { - .name = "vga-rgb", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 33000, - .left_margin = 48, - .right_margin = 16, - .upper_margin = 31, - .lower_margin = 11, - .hsync_len = 96, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED -} }, { - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB666, - .enable = enable_rgb, - .mode = { - .name = "wvga-rgb", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 25000, - .left_margin = 40, - .right_margin = 88, - .upper_margin = 33, - .lower_margin = 10, - .hsync_len = 128, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED -} } }; -size_t display_count = ARRAY_SIZE(displays); - -static void setup_display(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - int reg; - - enable_ipu_clock(); - imx_setup_hdmi(); - /* Turn on LDB0,IPU,IPU DI0 clocks */ - reg = __raw_readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; - writel(reg, &mxc_ccm->CCGR3); - - /* set LDB0, LDB1 clk select to 011/011 */ - reg = readl(&mxc_ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK - |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) - |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); - writel(reg, &mxc_ccm->cs2cdr); - - reg = readl(&mxc_ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; - writel(reg, &mxc_ccm->cscmr2); - - reg = readl(&mxc_ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - writel(reg, &mxc_ccm->chsccdr); - - reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES - |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH - |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW - |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG - |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT - |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG - |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT - |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED - |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; - writel(reg, &iomux->gpr[2]); - - reg = readl(&iomux->gpr[3]); - reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK - |IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 - <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); - writel(reg, &iomux->gpr[3]); - - /* backlight unconditionally on for now */ - imx_iomux_v3_setup_multiple_pads(backlight_pads, - ARRAY_SIZE(backlight_pads)); - /* use 0 for EDT 7", use 1 for LG fullHD panel */ - gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); - gpio_direction_output(RGB_BACKLIGHT_GP, 1); -} -#endif /* defined(CONFIG_VIDEO_IPUV3) */ - -int board_early_init_f(void) -{ - imx_iomux_v3_setup_multiple_pads(pwr_intb_pads, - ARRAY_SIZE(pwr_intb_pads)); - setup_iomux_uart(); - - return 0; -} - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc); - -#if defined(CONFIG_VIDEO_IPUV3) - setup_display(); -#endif - -#ifdef CONFIG_TDX_CMD_IMX_MFGR - (void) pmic_init(); -#endif - -#ifdef CONFIG_SATA - setup_sata(); -#endif - - setup_iomux_gpio(); - - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ -#if defined(CONFIG_REVISION_TAG) && \ - defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) - char env_str[256]; - u32 rev; - - rev = get_board_rev(); - snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev); - env_set("board_rev", env_str); -#endif - - return 0; -} -#endif /* CONFIG_BOARD_LATE_INIT */ - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP) -int ft_system_setup(void *blob, bd_t *bd) -{ - return 0; -} -#endif - -int checkboard(void) -{ - char it[] = " IT"; - int minc, maxc; - - switch (get_cpu_temp_grade(&minc, &maxc)) { - case TEMP_AUTOMOTIVE: - case TEMP_INDUSTRIAL: - break; - case TEMP_EXTCOMMERCIAL: - default: - it[0] = 0; - }; - printf("Model: Toradex Colibri iMX6 %s %sMB%s\n", - is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo", - (gd->ram_size == 0x20000000) ? "512" : "256", it); - return 0; -} - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - return ft_common_board_setup(blob, bd); -} -#endif - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int misc_init_r(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - return 0; -} - -#ifdef CONFIG_LDO_BYPASS_CHECK -/* TODO, use external pmic, for now always ldo_enable */ -void ldo_mode_set(int ldo_bypass) -{ - return; -} -#endif - -#ifdef CONFIG_SPL_BUILD -#include <spl.h> -#include <linux/libfdt.h> -#include "asm/arch/mx6dl-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -static int mx6s_dcd_table[] = { -/* ddr-setup.cfg */ - -MX6_IOM_DRAM_SDQS0, 0x00000030, -MX6_IOM_DRAM_SDQS1, 0x00000030, -MX6_IOM_DRAM_SDQS2, 0x00000030, -MX6_IOM_DRAM_SDQS3, 0x00000030, -MX6_IOM_DRAM_SDQS4, 0x00000030, -MX6_IOM_DRAM_SDQS5, 0x00000030, -MX6_IOM_DRAM_SDQS6, 0x00000030, -MX6_IOM_DRAM_SDQS7, 0x00000030, - -MX6_IOM_GRP_B0DS, 0x00000030, -MX6_IOM_GRP_B1DS, 0x00000030, -MX6_IOM_GRP_B2DS, 0x00000030, -MX6_IOM_GRP_B3DS, 0x00000030, -MX6_IOM_GRP_B4DS, 0x00000030, -MX6_IOM_GRP_B5DS, 0x00000030, -MX6_IOM_GRP_B6DS, 0x00000030, -MX6_IOM_GRP_B7DS, 0x00000030, -MX6_IOM_GRP_ADDDS, 0x00000030, -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -MX6_IOM_GRP_CTLDS, 0x00000030, - -MX6_IOM_DRAM_DQM0, 0x00020030, -MX6_IOM_DRAM_DQM1, 0x00020030, -MX6_IOM_DRAM_DQM2, 0x00020030, -MX6_IOM_DRAM_DQM3, 0x00020030, -MX6_IOM_DRAM_DQM4, 0x00020030, -MX6_IOM_DRAM_DQM5, 0x00020030, -MX6_IOM_DRAM_DQM6, 0x00020030, -MX6_IOM_DRAM_DQM7, 0x00020030, - -MX6_IOM_DRAM_CAS, 0x00020030, -MX6_IOM_DRAM_RAS, 0x00020030, -MX6_IOM_DRAM_SDCLK_0, 0x00020030, -MX6_IOM_DRAM_SDCLK_1, 0x00020030, - -MX6_IOM_DRAM_RESET, 0x00020030, -MX6_IOM_DRAM_SDCKE0, 0x00003000, -MX6_IOM_DRAM_SDCKE1, 0x00003000, - -MX6_IOM_DRAM_SDODT0, 0x00003030, -MX6_IOM_DRAM_SDODT1, 0x00003030, - -/* (differential input) */ -MX6_IOM_DDRMODE_CTL, 0x00020000, -/* (differential input) */ -MX6_IOM_GRP_DDRMODE, 0x00020000, -/* disable ddr pullups */ -MX6_IOM_GRP_DDRPKE, 0x00000000, -MX6_IOM_DRAM_SDBA2, 0x00000000, -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -MX6_IOM_GRP_DDR_TYPE, 0x000C0000, - -/* Read data DQ Byte0-3 delay */ -MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333, -MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333, -MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333, -MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, - -/* - * MDMISC mirroring interleaved (row/bank/col) - */ -/* TODO: check what the RALAT field does */ -MX6_MMDC_P0_MDMISC, 0x00081740, - -/* - * MDSCR con_req - */ -MX6_MMDC_P0_MDSCR, 0x00008000, - - -/* 800mhz_2x64mx16.cfg */ - -MX6_MMDC_P0_MDPDC, 0x0002002D, -MX6_MMDC_P0_MDCFG0, 0x2C305503, -MX6_MMDC_P0_MDCFG1, 0xB66D8D63, -MX6_MMDC_P0_MDCFG2, 0x01FF00DB, -MX6_MMDC_P0_MDRWD, 0x000026D2, -MX6_MMDC_P0_MDOR, 0x00301023, -MX6_MMDC_P0_MDOTC, 0x00333030, -MX6_MMDC_P0_MDPDC, 0x0002556D, -/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */ -MX6_MMDC_P0_MDASP, 0x00000017, -/* DDR3 DATA BUS SIZE: 64BIT */ -/* MX6_MMDC_P0_MDCTL, 0x821A0000, */ -/* DDR3 DATA BUS SIZE: 32BIT */ -MX6_MMDC_P0_MDCTL, 0x82190000, - -/* Write commands to DDR */ -/* Load Mode Registers */ -/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ -/* MX6_MMDC_P0_MDSCR, 0x04408032, */ -MX6_MMDC_P0_MDSCR, 0x04008032, -MX6_MMDC_P0_MDSCR, 0x00008033, -MX6_MMDC_P0_MDSCR, 0x00048031, -MX6_MMDC_P0_MDSCR, 0x13208030, -/* ZQ calibration */ -MX6_MMDC_P0_MDSCR, 0x04008040, - -MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003, -MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003, -MX6_MMDC_P0_MDREF, 0x00005800, - -MX6_MMDC_P0_MPODTCTRL, 0x00000000, -MX6_MMDC_P1_MPODTCTRL, 0x00000000, - -MX6_MMDC_P0_MPDGCTRL0, 0x42360232, -MX6_MMDC_P0_MPDGCTRL1, 0x021F022A, -MX6_MMDC_P1_MPDGCTRL0, 0x421E0224, -MX6_MMDC_P1_MPDGCTRL1, 0x02110218, - -MX6_MMDC_P0_MPRDDLCTL, 0x41434344, -MX6_MMDC_P1_MPRDDLCTL, 0x4345423E, -MX6_MMDC_P0_MPWRDLCTL, 0x39383339, -MX6_MMDC_P1_MPWRDLCTL, 0x3E363930, - -MX6_MMDC_P0_MPWLDECTRL0, 0x00340039, -MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D, -MX6_MMDC_P1_MPWLDECTRL0, 0x00120019, -MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D, - -MX6_MMDC_P0_MPMUR0, 0x00000800, -MX6_MMDC_P1_MPMUR0, 0x00000800, -MX6_MMDC_P0_MDSCR, 0x00000000, -MX6_MMDC_P0_MAPSR, 0x00011006, -}; - -static int mx6dl_dcd_table[] = { -/* ddr-setup.cfg */ - -MX6_IOM_DRAM_SDQS0, 0x00000030, -MX6_IOM_DRAM_SDQS1, 0x00000030, -MX6_IOM_DRAM_SDQS2, 0x00000030, -MX6_IOM_DRAM_SDQS3, 0x00000030, -MX6_IOM_DRAM_SDQS4, 0x00000030, -MX6_IOM_DRAM_SDQS5, 0x00000030, -MX6_IOM_DRAM_SDQS6, 0x00000030, -MX6_IOM_DRAM_SDQS7, 0x00000030, - -MX6_IOM_GRP_B0DS, 0x00000030, -MX6_IOM_GRP_B1DS, 0x00000030, -MX6_IOM_GRP_B2DS, 0x00000030, -MX6_IOM_GRP_B3DS, 0x00000030, -MX6_IOM_GRP_B4DS, 0x00000030, -MX6_IOM_GRP_B5DS, 0x00000030, -MX6_IOM_GRP_B6DS, 0x00000030, -MX6_IOM_GRP_B7DS, 0x00000030, -MX6_IOM_GRP_ADDDS, 0x00000030, -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -MX6_IOM_GRP_CTLDS, 0x00000030, - -MX6_IOM_DRAM_DQM0, 0x00020030, -MX6_IOM_DRAM_DQM1, 0x00020030, -MX6_IOM_DRAM_DQM2, 0x00020030, -MX6_IOM_DRAM_DQM3, 0x00020030, -MX6_IOM_DRAM_DQM4, 0x00020030, -MX6_IOM_DRAM_DQM5, 0x00020030, -MX6_IOM_DRAM_DQM6, 0x00020030, -MX6_IOM_DRAM_DQM7, 0x00020030, - -MX6_IOM_DRAM_CAS, 0x00020030, -MX6_IOM_DRAM_RAS, 0x00020030, -MX6_IOM_DRAM_SDCLK_0, 0x00020030, -MX6_IOM_DRAM_SDCLK_1, 0x00020030, - -MX6_IOM_DRAM_RESET, 0x00020030, -MX6_IOM_DRAM_SDCKE0, 0x00003000, -MX6_IOM_DRAM_SDCKE1, 0x00003000, - -MX6_IOM_DRAM_SDODT0, 0x00003030, -MX6_IOM_DRAM_SDODT1, 0x00003030, - -/* (differential input) */ -MX6_IOM_DDRMODE_CTL, 0x00020000, -/* (differential input) */ -MX6_IOM_GRP_DDRMODE, 0x00020000, -/* disable ddr pullups */ -MX6_IOM_GRP_DDRPKE, 0x00000000, -MX6_IOM_DRAM_SDBA2, 0x00000000, -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -MX6_IOM_GRP_DDR_TYPE, 0x000C0000, - -/* Read data DQ Byte0-3 delay */ -MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333, -MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333, -MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333, -MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, - -/* - * MDMISC mirroring interleaved (row/bank/col) - */ -/* TODO: check what the RALAT field does */ -MX6_MMDC_P0_MDMISC, 0x00081740, - -/* - * MDSCR con_req - */ -MX6_MMDC_P0_MDSCR, 0x00008000, - - -/* 800mhz_2x64mx16.cfg */ - -MX6_MMDC_P0_MDPDC, 0x0002002D, -MX6_MMDC_P0_MDCFG0, 0x2C305503, -MX6_MMDC_P0_MDCFG1, 0xB66D8D63, -MX6_MMDC_P0_MDCFG2, 0x01FF00DB, -MX6_MMDC_P0_MDRWD, 0x000026D2, -MX6_MMDC_P0_MDOR, 0x00301023, -MX6_MMDC_P0_MDOTC, 0x00333030, -MX6_MMDC_P0_MDPDC, 0x0002556D, -/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */ -MX6_MMDC_P0_MDASP, 0x00000017, -/* DDR3 DATA BUS SIZE: 64BIT */ -MX6_MMDC_P0_MDCTL, 0x821A0000, -/* DDR3 DATA BUS SIZE: 32BIT */ -/* MX6_MMDC_P0_MDCTL, 0x82190000, */ - -/* Write commands to DDR */ -/* Load Mode Registers */ -/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ -/* MX6_MMDC_P0_MDSCR, 0x04408032, */ -MX6_MMDC_P0_MDSCR, 0x04008032, -MX6_MMDC_P0_MDSCR, 0x00008033, -MX6_MMDC_P0_MDSCR, 0x00048031, -MX6_MMDC_P0_MDSCR, 0x13208030, -/* ZQ calibration */ -MX6_MMDC_P0_MDSCR, 0x04008040, - -MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003, -MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003, -MX6_MMDC_P0_MDREF, 0x00005800, - -MX6_MMDC_P0_MPODTCTRL, 0x00000000, -MX6_MMDC_P1_MPODTCTRL, 0x00000000, - -MX6_MMDC_P0_MPDGCTRL0, 0x42360232, -MX6_MMDC_P0_MPDGCTRL1, 0x021F022A, -MX6_MMDC_P1_MPDGCTRL0, 0x421E0224, -MX6_MMDC_P1_MPDGCTRL1, 0x02110218, - -MX6_MMDC_P0_MPRDDLCTL, 0x41434344, -MX6_MMDC_P1_MPRDDLCTL, 0x4345423E, -MX6_MMDC_P0_MPWRDLCTL, 0x39383339, -MX6_MMDC_P1_MPWRDLCTL, 0x3E363930, - -MX6_MMDC_P0_MPWLDECTRL0, 0x00340039, -MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D, -MX6_MMDC_P1_MPWLDECTRL0, 0x00120019, -MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D, - -MX6_MMDC_P0_MPMUR0, 0x00000800, -MX6_MMDC_P1_MPMUR0, 0x00000800, -MX6_MMDC_P0_MDSCR, 0x00000000, -MX6_MMDC_P0_MAPSR, 0x00011006, -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC03, &ccm->CCGR1); - writel(0x0FFFFFF3, &ccm->CCGR2); - writel(0x3FF0300F, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); - writel(0x0F0000F3, &ccm->CCGR5); - writel(0x000003FF, &ccm->CCGR6); - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ - writel(0x000000FB, &ccm->ccosr); -} - -static void ddr_init(int *table, int size) -{ - int i; - - for (i = 0; i < size / 2 ; i++) - writel(table[2 * i + 1], table[2 * i]); -} - -static void spl_dram_init(void) -{ - int minc, maxc; - - switch (get_cpu_temp_grade(&minc, &maxc)) { - case TEMP_COMMERCIAL: - case TEMP_EXTCOMMERCIAL: - if (is_cpu_type(MXC_CPU_MX6DL)) { - puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n"); - ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); - } else { - puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n"); - ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); - } - break; - case TEMP_INDUSTRIAL: - case TEMP_AUTOMOTIVE: - default: - if (is_cpu_type(MXC_CPU_MX6DL)) { - ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); - } else { - puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n"); - ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); - } - break; - }; - udelay(100); -} - -void board_init_f(ulong dummy) -{ - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - gpr_init(); - - /* iomux and setup of i2c */ - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* Make sure we use dte mode */ - setup_dtemode_uart(); - - /* DDR initialization */ - spl_dram_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} - -void reset_cpu(ulong addr) -{ -} - -#endif - -static struct mxc_serial_platdata mxc_serial_plat = { - .reg = (struct mxc_uart *)UART1_BASE, - .use_dte = true, -}; - -U_BOOT_DEVICE(mxc_serial) = { - .name = "serial_mxc", - .platdata = &mxc_serial_plat, -}; diff --git a/board/toradex/colibri_imx6/colibri_imx6.cfg b/board/toradex/colibri_imx6/colibri_imx6.cfg deleted file mode 100644 index 517c5eb1072..00000000000 --- a/board/toradex/colibri_imx6/colibri_imx6.cfg +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014 Toradex AG - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -#include "ddr-setup.cfg" - -#if CONFIG_DDR_MB == 256 -#include "800mhz_2x64mx16.cfg" -#elif CONFIG_DDR_MB == 512 -#include "800mhz_4x64mx16.cfg" -#else -#error "unknown DDR size" -#endif - -#include "clocks.cfg" diff --git a/board/toradex/colibri_imx6/ddr-setup.cfg b/board/toradex/colibri_imx6/ddr-setup.cfg deleted file mode 100644 index a943fd228c4..00000000000 --- a/board/toradex/colibri_imx6/ddr-setup.cfg +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* - * DDR3 settings - * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), - * memory bus width: 64 bits x16/x32/x64 - * MX6DL ddr is limited to 800 MHz(400 MHz clock) - * memory bus width: 64 bits x16/x32/x64 - * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) - * memory bus width: 32 bits x16/x32 - */ -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 - -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 - -DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 - -DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 - -DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 - -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 - -/* (differential input) */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -/* (differential input) */ -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -/* disable ddr pullups */ -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 - -/* Read data DQ Byte0-3 delay */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 - -/* - * MDMISC mirroring interleaved (row/bank/col) - */ -/* TODO: check what the RALAT field does */ -DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 - -/* - * MDSCR con_req - */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c deleted file mode 100644 index e6793e366a3..00000000000 --- a/board/toradex/colibri_imx6/do_fuse.c +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014-2016, Toradex AG - */ - -/* - * Helpers for i.MX OTP fusing during module production -*/ - -#include <common.h> -#ifndef CONFIG_SPL_BUILD -#include <console.h> -#include <fuse.h> - -static int mfgr_fuse(void) -{ - unsigned val, val6; - - fuse_sense(0, 5, &val); - printf("Fuse 0, 5: %8x\n", val); - fuse_sense(0, 6, &val6); - printf("Fuse 0, 6: %8x\n", val6); - fuse_sense(4, 3, &val); - printf("Fuse 4, 3: %8x\n", val); - fuse_sense(4, 2, &val); - printf("Fuse 4, 2: %8x\n", val); - if (val6 & 0x10) { - puts("BT_FUSE_SEL already fused, will do nothing\n"); - return CMD_RET_FAILURE; - } - /* boot cfg */ - fuse_prog(0, 5, 0x00005072); - /* BT_FUSE_SEL */ - fuse_prog(0, 6, 0x00000010); - return CMD_RET_SUCCESS; -} - -int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - int ret; - puts("Fusing...\n"); - ret = mfgr_fuse(); - if (ret == CMD_RET_SUCCESS) - puts("done.\n"); - else - puts("failed.\n"); - return ret; -} - -int do_updt_fuse(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - unsigned val; - int ret; - int confirmed = argc >= 1 && !strcmp(argv[1], "-y"); - - /* can be used in scripts for command availability check */ - if (argc >= 1 && !strcmp(argv[1], "-n")) - return CMD_RET_SUCCESS; - - /* boot cfg */ - fuse_sense(0, 5, &val); - printf("Fuse 0, 5: %8x\n", val); - if (val & 0x10) { - puts("Fast boot mode already fused, no need to fuse\n"); - return CMD_RET_SUCCESS; - } - if (!confirmed) { - puts("Warning: Programming fuses is an irreversible operation!\n" - " Updating to fast boot mode prevents easy\n" - " downgrading to previous BSP versions.\n" - "\nReally perform this fuse programming? <y/N>\n"); - if (!confirm_yesno()) - return CMD_RET_FAILURE; - } - puts("Fusing fast boot mode...\n"); - ret = fuse_prog(0, 5, 0x00005072); - if (ret == CMD_RET_SUCCESS) - puts("done.\n"); - else - puts("failed.\n"); - return ret; -} - -U_BOOT_CMD( - mfgr_fuse, 1, 0, do_mfgr_fuse, - "OTP fusing during module production", - "" -); - -U_BOOT_CMD( - updt_fuse, 2, 0, do_updt_fuse, - "OTP fusing during module update", - "updt_fuse [-n] [-y] - boot cfg fast boot mode fusing" -); -#endif /* CONFIG_SPL_BUILD */ diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c deleted file mode 100644 index fa63865670f..00000000000 --- a/board/toradex/colibri_imx6/pf0100.c +++ /dev/null @@ -1,212 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014-2016, Toradex AG - */ - -/* - * Helpers for Freescale PMIC PF0100 -*/ - -#include <common.h> -#include <i2c.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> - -#include "pf0100_otp.inc" -#include "pf0100.h" - -/* define for PMIC register dump */ -/*#define DEBUG */ - -/* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */ -static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = { - MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL), -# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 3) -}; - -unsigned pmic_init(void) -{ - unsigned programmed = 0; - uchar bus = 1; - uchar devid, revid, val; - - puts("PMIC: "); - if (!((0 == i2c_set_bus_num(bus)) && - (0 == i2c_probe(PFUZE100_I2C_ADDR)))) { - puts("i2c bus failed\n"); - return 0; - } - /* get device ident */ - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) { - puts("i2c pmic devid read failed\n"); - return 0; - } - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) { - puts("i2c pmic revid read failed\n"); - return 0; - } - printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid); - -#ifdef DEBUG - { - unsigned i, j; - - for (i = 0; i < 16; i++) - printf("\t%x", i); - for (j = 0; j < 0x80; ) { - printf("\n%2x", j); - for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); - printf("\t%2x", val); - } - j += 0x10; - } - printf("\nEXT Page 1"); - - val = PFUZE100_PAGE_REGISTER_PAGE1; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, - &val, 1)) { - puts("i2c write failed\n"); - return 0; - } - - for (j = 0x80; j < 0x100; ) { - printf("\n%2x", j); - for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); - printf("\t%2x", val); - } - j += 0x10; - } - printf("\nEXT Page 2"); - - val = PFUZE100_PAGE_REGISTER_PAGE2; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, - &val, 1)) { - puts("i2c write failed\n"); - return 0; - } - - for (j = 0x80; j < 0x100; ) { - printf("\n%2x", j); - for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); - printf("\t%2x", val); - } - j += 0x10; - } - printf("\n"); - } -#endif - /* get device programmed state */ - val = PFUZE100_PAGE_REGISTER_PAGE1; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) { - puts("i2c write failed\n"); - return 0; - } - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) { - puts("i2c fuse_por read failed\n"); - return 0; - } - if (val & PFUZE100_FUSE_POR_M) - programmed++; - - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) { - puts("i2c fuse_por read failed\n"); - return programmed; - } - if (val & PFUZE100_FUSE_POR_M) - programmed++; - - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) { - puts("i2c fuse_por read failed\n"); - return programmed; - } - if (val & PFUZE100_FUSE_POR_M) - programmed++; - - switch (programmed) { - case 0: - printf("PMIC: not programmed\n"); - break; - case 3: - printf("PMIC: programmed\n"); - break; - default: - printf("PMIC: undefined programming state\n"); - break; - } - - return programmed; -} - -#ifndef CONFIG_SPL_BUILD -static int pf0100_prog(void) -{ - unsigned char bus = 1; - unsigned char val; - unsigned int i; - - if (pmic_init() == 3) { - puts("PMIC already programmed, exiting\n"); - return CMD_RET_FAILURE; - } - /* set up gpio to manipulate vprog, initially off */ - imx_iomux_v3_setup_multiple_pads(pmic_prog_pads, - ARRAY_SIZE(pmic_prog_pads)); - gpio_direction_output(PMIC_PROG_VOLTAGE, 0); - - if (!((0 == i2c_set_bus_num(bus)) && - (0 == i2c_probe(PFUZE100_I2C_ADDR)))) { - puts("i2c bus failed\n"); - return CMD_RET_FAILURE; - } - - for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) { - switch (pmic_otp_prog[i].cmd) { - case pmic_i2c: - val = (unsigned char) (pmic_otp_prog[i].value & 0xff); - if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg, - 1, &val, 1)) { - printf("i2c write failed, reg 0x%2x, value 0x%2x\n", - pmic_otp_prog[i].reg, val); - return CMD_RET_FAILURE; - } - break; - case pmic_delay: - udelay(pmic_otp_prog[i].value * 1000); - break; - case pmic_vpgm: - gpio_direction_output(PMIC_PROG_VOLTAGE, - pmic_otp_prog[i].value); - break; - case pmic_pwr: - /* TODO */ - break; - } - } - return CMD_RET_SUCCESS; -} - -static int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - int ret; - puts("Programming PMIC OTP..."); - ret = pf0100_prog(); - if (ret == CMD_RET_SUCCESS) - puts("done.\n"); - else - puts("failed.\n"); - return ret; -} - -U_BOOT_CMD( - pf0100_otp_prog, 1, 0, do_pf0100_prog, - "Program the OTP fuses on the PMIC PF0100", - "" -); -#endif diff --git a/board/toradex/colibri_imx6/pf0100.h b/board/toradex/colibri_imx6/pf0100.h deleted file mode 100644 index c0efb79bbc9..00000000000 --- a/board/toradex/colibri_imx6/pf0100.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014-2016, Toradex AG - */ - -/* - * Helpers for Freescale PMIC PF0100 -*/ - -#ifndef PF0100_H_ -#define PF0100_H_ - -/* 7-bit I2C bus slave address */ -#define PFUZE100_I2C_ADDR (0x08) -/* Register Addresses */ -#define PFUZE100_DEVICEID (0x0) -#define PFUZE100_REVID (0x3) -#define PFUZE100_SW1AMODE (0x23) -#define PFUZE100_SW1ACON 36 -#define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */ -#define PFUZE100_SW1ACON_SPEED_M (0x3<<6) -#define PFUZE100_SW1CCON 49 -#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */ -#define PFUZE100_SW1CCON_SPEED_M (0x3<<6) -#define PFUZE100_SW1AVOL 32 -#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0) -#define PFUZE100_SW1CVOL 46 -#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0) -#define PFUZE100_VGEN1CTL (0x6c) -#define PFUZE100_VGEN1_VAL (0x30 + 0x08) /* Always ON, 1.2V */ -#define PFUZE100_SWBSTCTL (0x66) -/* Always ON, Auto Switching Mode, 5.0V */ -#define PFUZE100_SWBST_VAL (0x40 + 0x08 + 0x00) - -/* chooses the extended page (registers 0x80..0xff) */ -#define PFUZE100_PAGE_REGISTER 0x7f -#define PFUZE100_PAGE_REGISTER_PAGE_M (0x1f << 0) -#define PFUZE100_PAGE_REGISTER_PAGE1 (0x01 & PFUZE100_PAGE_REGISTER_PAGE_M) -#define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M) - -/* extended page 1 */ -#define PFUZE100_FUSE_POR1 0xe4 -#define PFUZE100_FUSE_POR2 0xe5 -#define PFUZE100_FUSE_POR3 0xe6 -#define PFUZE100_FUSE_POR_M (0x1 << 1) - - -/* output some informational messages, return the number FUSE_POR=1 */ -/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */ -unsigned pmic_init(void); - -#endif /* PF0100_H_ */ diff --git a/board/toradex/colibri_imx6/pf0100_otp.inc b/board/toradex/colibri_imx6/pf0100_otp.inc deleted file mode 100644 index ce29b95ae2a..00000000000 --- a/board/toradex/colibri_imx6/pf0100_otp.inc +++ /dev/null @@ -1,188 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014-2016, Toradex AG - */ - -// Register Output for PF0100 programmer -// Customer: Toradex AG -// Program: Colibri iMX6 -// Sample marking: -// Date: 24.07.2015 -// Time: 10:52:58 -// Generated from Spreadsheet Revision: P1.8 - -/* sed commands to get from programmer script to struct */ -/* sed -e 's/^WRITE_I2C:(..):(..)/{pmic_i2c, 0x\1, 0x\2},/g' -e 's/^DELAY:([0-9]*)/{pmic_delay, 0, \1},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc - sed -i -e 's/^VPGM:ON/{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/{pmic_vpgm, 0, 0},/g' pf0100_otp.inc - sed -i -e 's/^PWRON: HIGH/{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/{pmic_pwr, 0, 0},/g' pf0100_otp.inc */ - -enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr }; -struct pmic_otp_prog_t{ - unsigned char cmd; - unsigned char reg; - unsigned short value; -}; - -struct pmic_otp_prog_t pmic_otp_prog[] = { -{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1 -{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94 -{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95 -{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96 -{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102 -{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103 -{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104 -{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106 -{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108 -{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110 -{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111 -{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112 -{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114 -{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115 -{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116 -{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118 -{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120 -{pmic_i2c, 0xBD, 0x0E}, // Auto gen from Row123 -{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126 -{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130 -{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134 -{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138 -{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139 -{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142 -{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147 -{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150 -{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151 -{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154 -{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155 -{pmic_i2c, 0xE0, 0x05}, // Auto gen from Row158 - -#if 0 /* TBB mode */ -{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1 -{pmic_delay, 0, 10}, -#else -// Write OTP -{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1 -{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1 -{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1 -{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register -{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register -{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2 -{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register -{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register -//----------------------------------------------------------------------------------- -{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -//----------------------------------------------------------------------------------- -{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST -//VPGM:DOWN:n -//VPGM:UP:n -{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up -//----------------------------------------------------------------------------------- -// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10) -//----------------------------------------------------------------------------------- -// BANK 1 -//----------------------------------------------------------------------------------- -{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN -{pmic_delay, 0, 10}, // Allow time for bank programming to complete -{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN -{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -//----------------------------------------------------------------------------------- -// BANK 2 -//----------------------------------------------------------------------------------- -{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN -{pmic_delay, 0, 10}, // Allow time for bank programming to complete -{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN -{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -//----------------------------------------------------------------------------------- -// BANK 3 -//----------------------------------------------------------------------------------- -{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN -{pmic_delay, 0, 10}, // Allow time for bank programming to complete -{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN -{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -//----------------------------------------------------------------------------------- -// BANK 4 -//----------------------------------------------------------------------------------- -{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN -{pmic_delay, 0, 10}, // Allow time for bank programming to complete -{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN -{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -//----------------------------------------------------------------------------------- -// BANK 5 -//----------------------------------------------------------------------------------- -{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN -{pmic_delay, 0, 10}, // Allow time for bank programming to complete -{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN -{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -//----------------------------------------------------------------------------------- -// BANK 6 -//----------------------------------------------------------------------------------- -{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN -{pmic_delay, 0, 10}, // Allow time for bank programming to complete -{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN -{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -//----------------------------------------------------------------------------------- -// BANK 7 -//----------------------------------------------------------------------------------- -{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN -{pmic_delay, 0, 10}, // Allow time for bank programming to complete -{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN -{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -//----------------------------------------------------------------------------------- -// BANK 8 -//----------------------------------------------------------------------------------- -{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN -{pmic_delay, 0, 10}, // Allow time for bank programming to complete -{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN -{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -//----------------------------------------------------------------------------------- -// BANK 9 -//----------------------------------------------------------------------------------- -{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN -{pmic_delay, 0, 10}, // Allow time for bank programming to complete -{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN -{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -//----------------------------------------------------------------------------------- -// BANK 10 -//----------------------------------------------------------------------------------- -{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN -{pmic_delay, 0, 10}, // Allow time for bank programming to complete -{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN -{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits -//----------------------------------------------------------------------------------- -{pmic_vpgm, 0, 0}, // Turn off 8V SWBST -{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off -{pmic_i2c, 0xD0, 0x00}, // Clear -{pmic_i2c, 0xD1, 0x00}, // Clear -{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data -{pmic_delay, 0, 500}, -{pmic_pwr, 0, 1}, -#endif -}; \ No newline at end of file diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig deleted file mode 100644 index d86c0872b4f..00000000000 --- a/configs/colibri_imx6_defconfig +++ /dev/null @@ -1,73 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_COLIBRI_IMX6=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_CMD_HDMIDETECT=y -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL" -CONFIG_BOOTDELAY=1 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_MISC_INIT_R=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_DMA_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_USB_HOST_SUPPORT=y -CONFIG_SPL_USB_GADGET_SUPPORT=y -CONFIG_SPL_USB_SDP_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Colibri iMX6 # " -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -CONFIG_CMD_ASKENV=y -CONFIG_CRC32_VERIFY=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_SDP=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_FSL_ESDHC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_MII=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Toradex" -CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 -CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_HOST_ETHER=y -CONFIG_VIDEO=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y -CONFIG_OF_LIBFDT_OVERLAY=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/colibri_imx6_nospl_defconfig b/configs/colibri_imx6_nospl_defconfig deleted file mode 100644 index 2ed42b54cc2..00000000000 --- a/configs/colibri_imx6_nospl_defconfig +++ /dev/null @@ -1,61 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_TARGET_COLIBRI_IMX6=y -CONFIG_CMD_HDMIDETECT=y -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,MX6DL,DDR_MB=256" -CONFIG_BOOTDELAY=1 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_MISC_INIT_R=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Colibri iMX6 # " -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -CONFIG_CMD_ASKENV=y -CONFIG_CRC32_VERIFY=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_FSL_ESDHC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_MII=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Toradex" -CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 -CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_HOST_ETHER=y -CONFIG_VIDEO=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y -# CONFIG_EFI_LOADER is not set diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h deleted file mode 100644 index 7eb87cada6f..00000000000 --- a/include/configs/colibri_imx6.h +++ /dev/null @@ -1,251 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2015 Toradex, Inc. - * - * Configuration settings for the Toradex Colibri iMX6 - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#undef CONFIG_DISPLAY_BOARDINFO - -#include <asm/arch/imx-regs.h> -#include <asm/mach-imx/gpio.h> - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* OCOTP Configs */ -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif - -/* MMC Configs */ -#define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - -/* Network */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 1 -#define CONFIG_IP_DEFRAG -#define CONFIG_TFTP_BLOCKSIZE 16352 -#define CONFIG_TFTP_TSIZE - -/* USB Configs */ -/* Host */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -/* Client */ -#define CONFIG_USBD_HS - -#define CONFIG_USB_GADGET_MASS_STORAGE -/* USB DFU */ -#define CONFIG_DFU_MMC - -/* Miscellaneous commands */ - -/* Framebuffer and LCD */ -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CONSOLE_MUX -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition */ -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_FLASH - -#undef CONFIG_IPADDR -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#undef CONFIG_SERVERIP -#define CONFIG_SERVERIP 192.168.10.1 - -#define CONFIG_LOADADDR 0x12000000 - -#ifdef CONFIG_CMD_MMC -#define CONFIG_DRIVE_MMC "mmc " -#else -#define CONFIG_DRIVE_MMC -#endif - -#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_MMC - -#define DFU_ALT_EMMC_INFO \ - "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \ - "boot part 0 1;" \ - "rootfs part 0 2;" \ - "uImage fat 0 1;" \ - "imx6q-colibri-eval-v3.dtb fat 0 1;" \ - "imx6q-colibri-cam-eval-v3.dtb fat 0 1" - -#define EMMC_BOOTCMD \ - "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \ - "rootwait\0" \ - "emmcboot=run setup; " \ - "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ - "${vidargs}; echo Booting from internal eMMC chip...; " \ - "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \ - "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ - "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \ - "${fdt_file} && setenv dtbparam " - ${fdt_addr_r}" && true\0" - -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "fdt_addr_r=0x12000000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "kernel_addr_r=0x11000000\0" \ - "ramdisk_addr_r=0x12100000\0" - -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ - "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ - "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \ - "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ - "&& setenv dtbparam " - ${fdt_addr_r}" && true\0" - -#define SD_BOOTCMD \ - "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \ - "rootwait\0" \ - "sdboot=run setup; " \ - "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \ - "${vidargs}; echo Booting from SD card; " \ - "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \ - "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ - "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \ - "${fdt_file} && setenv dtbparam " - ${fdt_addr_r}" && true\0" - -#define USB_BOOTCMD \ - "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \ - "rootwait\0" \ - "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \ - "${usbargs} ${vidargs}; echo Booting from USB stick...; " \ - "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \ - "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ - "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \ - "${fdt_file} && setenv dtbparam " - ${fdt_addr_r}" && true\0" - -#define FDT_FILE "imx6dl-colibri-eval-v3.dtb" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \ - "run nfsboot ; echo ; echo nfsboot failed ; " \ - "usb start ;" \ - "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \ - "boot_file=uImage\0" \ - "console=ttymxc0\0" \ - "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \ - "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ - EMMC_BOOTCMD \ - "fdt_file=" FDT_FILE "\0" \ - "fdt_fixup=;\0" \ - MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ - SD_BOOTCMD \ - "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ - "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ - "flash_eth.img && source ${loadaddr}\0" \ - "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \ - "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ - "setup=setenv setupargs fec_mac=${ethaddr} " \ - "consoleblank=0 no_console_suspend=1 console=tty1 " \ - "console=${console},${baudrate}n8\0 " \ - "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ - "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ - "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ - "splashpos=m,m\0" \ - "vidargs=video=mxcfb0:dev=lcd,640x480M@60,if=RGB666 " \ - "video=mxcfb1:off fbmem=8M\0 " - -/* Miscellaneous configurable options */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 48 - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#define CONFIG_ENV_SIZE (8 * 1024) - -#if defined(CONFIG_ENV_IS_IN_MMC) -/* Environment in eMMC, before config block at the end of 1st "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ - CONFIG_TDX_CFG_BLOCK_OFFSET) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 1 -#endif - -#define CONFIG_OF_SYSTEM_SETUP - -#define CONFIG_CMD_TIME - -#endif /* __CONFIG_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-kirkwood/Kconfig | 1 - board/Marvell/guruplug/Kconfig | 12 --- board/Marvell/guruplug/MAINTAINERS | 6 -- board/Marvell/guruplug/Makefile | 7 -- board/Marvell/guruplug/guruplug.c | 138 -------------------------- board/Marvell/guruplug/guruplug.h | 22 ----- board/Marvell/guruplug/kwbimage.cfg | 144 ---------------------------- configs/guruplug_defconfig | 43 --------- include/configs/guruplug.h | 82 ---------------- 9 files changed, 455 deletions(-) delete mode 100644 board/Marvell/guruplug/Kconfig delete mode 100644 board/Marvell/guruplug/MAINTAINERS delete mode 100644 board/Marvell/guruplug/Makefile delete mode 100644 board/Marvell/guruplug/guruplug.c delete mode 100644 board/Marvell/guruplug/guruplug.h delete mode 100644 board/Marvell/guruplug/kwbimage.cfg delete mode 100644 configs/guruplug_defconfig delete mode 100644 include/configs/guruplug.h

diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 3b860c4f55f..00ed62591ea 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -73,7 +73,6 @@ config SYS_SOC source "board/Marvell/openrd/Kconfig" source "board/Marvell/dreamplug/Kconfig" source "board/Synology/ds109/Kconfig" -source "board/Marvell/guruplug/Kconfig" source "board/Marvell/sheevaplug/Kconfig" source "board/buffalo/lsxl/Kconfig" source "board/cloudengines/pogo_e02/Kconfig" diff --git a/board/Marvell/guruplug/Kconfig b/board/Marvell/guruplug/Kconfig deleted file mode 100644 index 529e6e3b4ba..00000000000 --- a/board/Marvell/guruplug/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_GURUPLUG - -config SYS_BOARD - default "guruplug" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "guruplug" - -endif diff --git a/board/Marvell/guruplug/MAINTAINERS b/board/Marvell/guruplug/MAINTAINERS deleted file mode 100644 index b5d07348316..00000000000 --- a/board/Marvell/guruplug/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -GURUPLUG BOARD -M: Siddarth Gore gores@marvell.com -S: Maintained -F: board/Marvell/guruplug/ -F: include/configs/guruplug.h -F: configs/guruplug_defconfig diff --git a/board/Marvell/guruplug/Makefile b/board/Marvell/guruplug/Makefile deleted file mode 100644 index b0dfc0cd6d9..00000000000 --- a/board/Marvell/guruplug/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Siddarth Gore gores@marvell.com - -obj-y := guruplug.o diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c deleted file mode 100644 index 466f85eb081..00000000000 --- a/board/Marvell/guruplug/guruplug.c +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Siddarth Gore gores@marvell.com - */ - -#include <common.h> -#include <miiphy.h> -#include <asm/mach-types.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> -#include <asm/arch/mpp.h> -#include "guruplug.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* - * default gpio configuration - * There are maximum 64 gpios controlled through 2 sets of registers - * the below configuration configures mainly initial LED status - */ - mvebu_config_gpio(GURUPLUG_OE_VAL_LOW, - GURUPLUG_OE_VAL_HIGH, - GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, /* GPIO_RST */ - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, - MPP13_SD_CMD, - MPP14_SD_D0, - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_GE1_0, - MPP21_GE1_1, - MPP22_GE1_2, - MPP23_GE1_3, - MPP24_GE1_4, - MPP25_GE1_5, - MPP26_GE1_6, - MPP27_GE1_7, - MPP28_GE1_8, - MPP29_GE1_9, - MPP30_GE1_10, - MPP31_GE1_11, - MPP32_GE1_12, - MPP33_GE1_13, - MPP34_GE1_14, - MPP35_GE1_15, - MPP36_GPIO, - MPP37_GPIO, - MPP38_GPIO, - MPP39_GPIO, - MPP40_TDM_SPI_SCK, - MPP41_TDM_SPI_MISO, - MPP42_TDM_SPI_MOSI, - MPP43_GPIO, - MPP44_GPIO, - MPP45_GPIO, - MPP46_GPIO, /* M_RLED */ - MPP47_GPIO, /* M_GLED */ - MPP48_GPIO, /* B_RLED */ - MPP49_GPIO, /* B_GLED */ - 0 - }; - kirkwood_mpp_conf(kwmpp_config, NULL); - return 0; -} - -int board_init(void) -{ - /* - * arch number of board - */ - gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -void mv_phy_88e1121_init(char *name) -{ - u16 reg; - u16 devadr; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..%s could not read PHY dev address\n", - __FUNCTION__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, &reg); - reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg); - miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); - - printf("88E1121 Initialized on %s\n", name); -} - -void reset_phy(void) -{ - /* configure and initialize both PHY's */ - mv_phy_88e1121_init("egiga0"); - mv_phy_88e1121_init("egiga1"); -} -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/guruplug/guruplug.h b/board/Marvell/guruplug/guruplug.h deleted file mode 100644 index a7023668132..00000000000 --- a/board/Marvell/guruplug/guruplug.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Siddarth Gore gores@marvell.com - */ - -#ifndef __GURUPLUG_H -#define __GURUPLUG_H - -#define GURUPLUG_OE_LOW (~(0)) -#define GURUPLUG_OE_HIGH (~(0)) -#define GURUPLUG_OE_VAL_LOW 0 -#define GURUPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */ - -/* PHY related */ -#define MV88E1121_MAC_CTRL2_REG 21 -#define MV88E1121_PGADR_REG 22 -#define MV88E1121_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1121_RGMII_RXTM_CTRL (1 << 5) - -#endif /* __GURUPLUG_H */ diff --git a/board/Marvell/guruplug/kwbimage.cfg b/board/Marvell/guruplug/kwbimage.cfg deleted file mode 100644 index 8a0d752c91c..00000000000 --- a/board/Marvell/guruplug/kwbimage.cfg +++ /dev/null @@ -1,144 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Siddarth Gore gores@marvell.com -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM nand -NAND_ECC_MODE default -NAND_PAGE_SIZE 0x0800 - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0/1 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b9b9b - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register -# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x37543000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x000000cc # DDR Address Control -# bit1-0: 01, Cs0width=x8 -# bit3-2: 10, Cs0size=1Gb -# bit5-4: 01, Cs1width=x8 -# bit7-6: 10, Cs1size=1Gb -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000C52 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000040 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 0, DDR drive strenght normal -# bit2: 0, DDR ODT control lsd (disabled) -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, (disabled) -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB) - -DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb -DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 - -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 01, ODT1 active NEVER! -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000E803 # CPU ODT Control -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig deleted file mode 100644 index 9998e48ab9c..00000000000 --- a/configs/guruplug_defconfig +++ /dev/null @@ -1,43 +0,0 @@ -CONFIG_ARM=y -CONFIG_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_TARGET_GURUPLUG=y -CONFIG_IDENT_STRING="\nMarvell-GuruPlug" -CONFIG_NR_DRAM_BANKS=2 -# CONFIG_SYS_MALLOC_F is not set -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896K(uboot),128K(uboot_env),-@1M(root)" -CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-guruplug-server-plus" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_DM=y -CONFIG_MVSATA_IDE=y -# CONFIG_MMC is not set -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_DM_RTC=y -CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_LZMA=y diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h deleted file mode 100644 index 739ab320f63..00000000000 --- a/include/configs/guruplug.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009-2014 - * Gerald Kerma dreagle@doukki.net - * Marvell Semiconductor <www.marvell.com> - * Written-by: Siddarth Gore gores@marvell.com - */ - -#ifndef _CONFIG_GURUPLUG_H -#define _CONFIG_GURUPLUG_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ - -/* - * Standard filesystems - */ -#define CONFIG_BZIP2 - -/* - * mv-plug-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-plug-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ -#endif -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_OFFSET 0xE0000 /* env starts here */ -/* - * Environment is right behind U-Boot in flash. Make sure U-Boot - * doesn't grow into the environment area. - */ -#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ - "ubi part root; " \ - "ubifsmount ubi:rootfs; " \ - "ubifsload 0x800000 ${kernel}; " \ - "ubifsload 0x700000 ${fdt}; " \ - "ubifsumount; " \ - "fdt addr 0x700000; fdt resize; fdt chosen; " \ - "bootz 0x800000 - 0x700000" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ - "kernel=/boot/zImage\0" \ - "fdt=/boot/guruplug-server-plus.dtb\0" \ - "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -#define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#endif /* _CONFIG_GURUPLUG_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-omap2/omap3/Kconfig | 1 - board/logicpd/zoom1/Kconfig | 12 --- board/logicpd/zoom1/MAINTAINERS | 6 -- board/logicpd/zoom1/Makefile | 6 -- board/logicpd/zoom1/config.mk | 14 --- board/logicpd/zoom1/zoom1.c | 146 ------------------------------ board/logicpd/zoom1/zoom1.h | 122 ------------------------- configs/omap3_zoom1_defconfig | 39 -------- include/configs/omap3_zoom1.h | 138 ---------------------------- 9 files changed, 484 deletions(-) delete mode 100644 board/logicpd/zoom1/Kconfig delete mode 100644 board/logicpd/zoom1/MAINTAINERS delete mode 100644 board/logicpd/zoom1/Makefile delete mode 100644 board/logicpd/zoom1/config.mk delete mode 100644 board/logicpd/zoom1/zoom1.c delete mode 100644 board/logicpd/zoom1/zoom1.h delete mode 100644 configs/omap3_zoom1_defconfig delete mode 100644 include/configs/omap3_zoom1.h

diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index b5f6061a17a..04b6ffe574a 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -202,7 +202,6 @@ source "board/timll/devkit8000/Kconfig" source "board/ti/evm/Kconfig" source "board/isee/igep00x0/Kconfig" source "board/overo/Kconfig" -source "board/logicpd/zoom1/Kconfig" source "board/ti/am3517crane/Kconfig" source "board/pandora/Kconfig" source "board/8dtech/eco5pk/Kconfig" diff --git a/board/logicpd/zoom1/Kconfig b/board/logicpd/zoom1/Kconfig deleted file mode 100644 index d76cb663f72..00000000000 --- a/board/logicpd/zoom1/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_OMAP3_ZOOM1 - -config SYS_BOARD - default "zoom1" - -config SYS_VENDOR - default "logicpd" - -config SYS_CONFIG_NAME - default "omap3_zoom1" - -endif diff --git a/board/logicpd/zoom1/MAINTAINERS b/board/logicpd/zoom1/MAINTAINERS deleted file mode 100644 index 338b965debd..00000000000 --- a/board/logicpd/zoom1/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ZOOM1 BOARD -M: Nishanth Menon nm@ti.com -S: Maintained -F: board/logicpd/zoom1/ -F: include/configs/omap3_zoom1.h -F: configs/omap3_zoom1_defconfig diff --git a/board/logicpd/zoom1/Makefile b/board/logicpd/zoom1/Makefile deleted file mode 100644 index e73b42e7027..00000000000 --- a/board/logicpd/zoom1/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y := zoom1.o diff --git a/board/logicpd/zoom1/config.mk b/board/logicpd/zoom1/config.mk deleted file mode 100644 index a8e4f52e7bf..00000000000 --- a/board/logicpd/zoom1/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006-2008 -# Texas Instruments, <www.ti.com> -# -# Zoom MDK uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c deleted file mode 100644 index 5e32077d649..00000000000 --- a/board/logicpd/zoom1/zoom1.c +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2004-2008 - * Texas Instruments, <www.ti.com> - * - * Author : - * Nishanth Menon nm@ti.com - * - * Derived from Beagle Board and 3430 SDP code by - * Sunil Kumar sunilsaini05@gmail.com - * Shashi Ranjan shashiranjanmca05@gmail.com - * Richard Woodruff r-woodruff2@ti.com - * Syed Mohammed Khasim khasim@ti.com - * - */ -#include <common.h> -#include <dm.h> -#include <environment.h> -#include <ns16550.h> -#include <netdev.h> -#include <twl4030.h> -#include <linux/mtd/omap_gpmc.h> -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-types.h> -#include "zoom1.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * gpmc_cfg is initialized by gpmc_init and we use it here. - * GPMC definitions for Ethenet Controller LAN9211 - */ -static const u32 gpmc_lab_enet[] = { - ZOOM1_ENET_GPMC_CONF1, - ZOOM1_ENET_GPMC_CONF2, - ZOOM1_ENET_GPMC_CONF3, - ZOOM1_ENET_GPMC_CONF4, - ZOOM1_ENET_GPMC_CONF5, - ZOOM1_ENET_GPMC_CONF6, - /*CONF7- computed as params */ -}; - -static const struct ns16550_platdata zoom1_serial = { - .base = OMAP34XX_UART3, - .reg_shift = 2, - .clock = V_NS16550_CLK, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DEVICE(zoom1_uart) = { - "ns16550_serial", - &zoom1_serial -}; - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* CS1 is Ethernet LAN9211 */ - enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1], - DEBUG_BASE, GPMC_SIZE_16M); - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP; - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -/* - * Routine: misc_init_r - * Description: Configure zoom board specific configurations - */ -int misc_init_r(void) -{ - twl4030_power_init(); - twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); - omap_die_id_display(); - - /* - * Board Reset - * The board is reset by holding the red button on the - * top right front face for eight seconds. - */ - twl4030_power_reset_init(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - /* platform specific muxes */ - MUX_ZOOM1_MDK(); -} - -#ifdef CONFIG_MMC -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} - -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; - -#ifdef CONFIG_SMC911X -#define STR_ENV_ETHADDR "ethaddr" - - struct eth_device *dev; - uchar eth_addr[6]; - - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); - if (!eth_env_get_enetaddr(STR_ENV_ETHADDR, eth_addr)) { - dev = eth_get_dev_by_index(0); - if (dev) { - eth_env_set_enetaddr(STR_ENV_ETHADDR, dev->enetaddr); - } else { - printf("zoom1: Couldn't get eth device\n"); - rc = -1; - } - } -#endif - - return rc; -} -#endif diff --git a/board/logicpd/zoom1/zoom1.h b/board/logicpd/zoom1/zoom1.h deleted file mode 100644 index 63847616cfd..00000000000 --- a/board/logicpd/zoom1/zoom1.h +++ /dev/null @@ -1,122 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 - * Texas Instruments - * Nishanth Menon nm@ti.com - * - * Derived from: board/omap3/beagle/beagle.h - * Dirk Behme dirk.behme@gmail.com - */ -#ifndef _BOARD_ZOOM1_H_ -#define _BOARD_ZOOM1_H_ - -const omap3_sysinfo sysinfo = { - DDR_STACKED, - "OMAP3 Zoom MDK Rev 1", - "NAND", -}; - -#define ZOOM1_ENET_GPMC_CONF1 0x00611000 -#define ZOOM1_ENET_GPMC_CONF2 0x001F1F01 -#define ZOOM1_ENET_GPMC_CONF3 0x00080803 -#define ZOOM1_ENET_GPMC_CONF4 0x1D091D09 -#define ZOOM1_ENET_GPMC_CONF5 0x041D1F1F -#define ZOOM1_ENET_GPMC_CONF6 0x1D0904C4 - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_ZOOM1_MDK() \ - /*SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - /*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | DIS | M7)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | DIS | M4)) /*GPMC_nCS3 -> GPIO54*/\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M4)) /*GPMC_nCS4 -> GPIO 55*/\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4)) /*GPMC_nCS5 -> GPIO 56*/\ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7 -> GPMC_IO_DIR*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/ - -#endif /* _BOARD_ZOOM_H_ */ diff --git a/configs/omap3_zoom1_defconfig b/configs/omap3_zoom1_defconfig deleted file mode 100644 index 325c0020cab..00000000000 --- a/configs/omap3_zoom1_defconfig +++ /dev/null @@ -1,39 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_TARGET_OMAP3_ZOOM1=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_CMD_IMI is not set -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_LOCK_UNLOCK=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_TWL4030_LED=y -CONFIG_MMC_OMAP_HS=y -CONFIG_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x08000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_MUSB_UDC=y -CONFIG_USB_OMAP3=y -CONFIG_TWL4030_USB=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h deleted file mode 100644 index 0a02ecdc149..00000000000 --- a/include/configs/omap3_zoom1.h +++ /dev/null @@ -1,138 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments. - * Richard Woodruff r-woodruff2@ti.com - * Syed Mohammed Khasim x0khasim@ti.com - * Nishanth Menon nm@ti.com - * - * Configuration settings for the TI OMAP3430 Zoom MDK board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> -#include <configs/ti_omap3_common.h> - -/* Remove SPL boot option - we do not support that on LDP yet */ - -/* Generic NAND definition conflicts with debug_base */ -#undef CONFIG_SYS_NAND_BASE - -#define CONFIG_REVISION_TAG 1 - -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - -/* - * Hardware drivers - */ - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "Zoom1" - -#if defined(CONFIG_CMD_NAND) -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#endif -#endif - -/* - * TWL4030 - */ - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ - -/* Environment information */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "fdtaddr=0x80f80000\0" \ - "bootfile=uImage\0" \ - "fdtfile=omap3-ldp.dtb\0" \ - "bootdir=/\0" \ - "bootpart=0:1\0" \ - "usbtty=cdc_acm\0" \ - "console=ttyO2,115200n8\0" \ - "mmcdev=0\0" \ - "videomode=1024x768@60,vxres=1024,vyres=768\0" \ - "videospec=omapfb:vram:2M,vram:4M\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ - "nandargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mtdblock4 rw " \ - "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "loadzimage=setenv bootfile zImage; if run loadimage; then run loadfdt;fi\0"\ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "mmczboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else if run loadzimage; then " \ - "run mmczboot; " \ - "else run nandboot; " \ - "fi; fi;" \ - "fi; " \ - "else run nandboot; fi" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1) /* memtest */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_2 + \ - 0x01F00000) /* 31MB */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET 0x260000 -#define CONFIG_ENV_ADDR 0x260000 - -#endif /* __CONFIG_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-imx/mx6/Kconfig | 1 - board/tbs/tbs2910/Kconfig | 18 -- board/tbs/tbs2910/MAINTAINERS | 6 - board/tbs/tbs2910/Makefile | 5 - board/tbs/tbs2910/tbs2910.c | 454 ---------------------------------- board/tbs/tbs2910/tbs2910.cfg | 114 --------- configs/tbs2910_defconfig | 58 ----- include/configs/tbs2910.h | 158 ------------ 8 files changed, 814 deletions(-) delete mode 100644 board/tbs/tbs2910/Kconfig delete mode 100644 board/tbs/tbs2910/MAINTAINERS delete mode 100644 board/tbs/tbs2910/Makefile delete mode 100644 board/tbs/tbs2910/tbs2910.c delete mode 100644 board/tbs/tbs2910/tbs2910.cfg delete mode 100644 configs/tbs2910_defconfig delete mode 100644 include/configs/tbs2910.h

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 9ed827067b1..2b96c55b61b 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -559,7 +559,6 @@ source "board/logicpd/imx6/Kconfig" source "board/seco/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" -source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/toradex/apalis_imx6/Kconfig" source "board/toradex/colibri-imx6ull/Kconfig" diff --git a/board/tbs/tbs2910/Kconfig b/board/tbs/tbs2910/Kconfig deleted file mode 100644 index 2e5e1d492a5..00000000000 --- a/board/tbs/tbs2910/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if TARGET_TBS2910 - -config SYS_BOARD - default "tbs2910" - -config SYS_VENDOR - default "tbs" - -config SYS_CONFIG_NAME - default "tbs2910" - -config MX6Q - default y - -config IMX_CONFIG - default "board/tbs/tbs2910/tbs2910.cfg" - -endif diff --git a/board/tbs/tbs2910/MAINTAINERS b/board/tbs/tbs2910/MAINTAINERS deleted file mode 100644 index bf176553d24..00000000000 --- a/board/tbs/tbs2910/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TBS2910 BOARD -M: Soeren Moch smoch@web.de -S: Maintained -F: board/tbs/tbs2910/ -F: configs/tbs2910_defconfig -F: include/configs/tbs2910.h diff --git a/board/tbs/tbs2910/Makefile b/board/tbs/tbs2910/Makefile deleted file mode 100644 index 78f4a3eecd4..00000000000 --- a/board/tbs/tbs2910/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2014 Soeren Moch smoch@web.de - -obj-y := tbs2910.o diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c deleted file mode 100644 index ecb45f208d0..00000000000 --- a/board/tbs/tbs2910/tbs2910.c +++ /dev/null @@ -1,454 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014 Soeren Moch smoch@web.de - */ - -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/sata.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/video.h> -#include <mmc.h> -#include <fsl_esdhc.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/arch/crm_regs.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <i2c.h> -DECLARE_GLOBAL_DATA_PTR; - -#define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_SRE_SLOW) - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) - -#ifdef CONFIG_SYS_I2C -/* I2C1, SGTL5000 */ -static struct i2c_pads_info i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD, - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD, - .gp = IMX_GPIO_NR(5, 26) - } -}; - -/* I2C2 HDMI */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -/* I2C3, CON11, DS1307, PCIe_SMB */ -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD, - .gp = IMX_GPIO_NR(1, 6) - } -}; -#endif /* CONFIG_SYS_I2C */ - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - /* AR8035 PHY Reset */ - MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const pcie_pads[] = { - /* W_DISABLE# */ - MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), - /* PERST# */ - MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -int dram_init(void) -{ - gd->ram_size = 2048ul * 1024 * 1024; - return 0; -} - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); - - /* Reset AR8035 PHY */ - gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); - udelay(500); - gpio_set_value(IMX_GPIO_NR(1, 25), 1); -} - -static void setup_pcie(void) -{ - imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); -} - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); -} - -#ifdef CONFIG_FSL_ESDHC -static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC2_BASE_ADDR}, - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) -#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = !gpio_get_value(USDHC3_CD_GPIO); - break; - case USDHC4_BASE_ADDR: - ret = 1; /* eMMC/uSDHC4 is always present */ - break; - } - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - /* - * (U-Boot device node) (Physical Port) - * mmc0 SD2 - * mmc1 SD3 - * mmc2 eMMC - */ - int i, ret; - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - gpio_direction_input(USDHC3_CD_GPIO); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - return 0; -} - -/* set environment device to boot device when booting from SD */ -int board_mmc_get_env_dev(int devno) -{ - return devno - 1; -} - -int board_mmc_get_env_part(int devno) -{ - return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */ -} -#endif /* CONFIG_FSL_ESDHC */ - -#ifdef CONFIG_VIDEO_IPUV3 -static void do_enable_hdmi(struct display_info_t const *dev) -{ - imx_enable_hdmi_phy(); -} - -struct display_info_t const displays[] = {{ - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = do_enable_hdmi, - .mode = { - .name = "HDMI", - /* 1024x768@60Hz (VESA)*/ - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15384, - .left_margin = 160, - .right_margin = 24, - .upper_margin = 29, - .lower_margin = 3, - .hsync_len = 136, - .vsync_len = 6, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} } }; -size_t display_count = ARRAY_SIZE(displays); - -static void setup_display(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int reg; - s32 timeout = 100000; - - enable_ipu_clock(); - imx_setup_hdmi(); - - /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */ - reg = readl(&ccm->analog_pll_video); - reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN; - writel(reg, &ccm->analog_pll_video); - - reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; - reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37); - reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; - reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1); - writel(reg, &ccm->analog_pll_video); - - writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); - writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); - - reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; - writel(reg, &ccm->analog_pll_video); - - while (timeout--) - if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) - break; - if (timeout < 0) - printf("Warning: video pll lock timeout!\n"); - - reg = readl(&ccm->analog_pll_video); - reg |= BM_ANADIG_PLL_VIDEO_ENABLE; - reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; - writel(reg, &ccm->analog_pll_video); - - /* gate ipu1_di0_clk */ - reg = readl(&ccm->CCGR3); - reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK; - writel(reg, &ccm->CCGR3); - - /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */ - reg = readl(&ccm->chsccdr); - reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | - MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK | - MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); - reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) | - (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) | - (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - writel(reg, &ccm->chsccdr); - - /* enable ipu1_di0_clk */ - reg = readl(&ccm->CCGR3); - reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; - writel(reg, &ccm->CCGR3); -} -#endif /* CONFIG_VIDEO_IPUV3 */ - -static int ar8035_phy_fixup(struct phy_device *phydev) -{ - unsigned short val; - - /* To enable AR8035 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - ar8035_phy_fixup(phydev); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - setup_iomux_enet(); - setup_pcie(); - return cpu_eth_init(bis); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - return 0; -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, - {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, - /* 8 bit bus width */ - {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -#ifdef CONFIG_USB_EHCI_MX6 -static iomux_v3_cfg_t const usb_otg_pads[] = { - MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), -}; -#endif - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - -#ifdef CONFIG_VIDEO_IPUV3 - setup_display(); -#endif -#ifdef CONFIG_SYS_I2C - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); -#endif -#ifdef CONFIG_DWC_AHSATA - setup_sata(); -#endif -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif -#ifdef CONFIG_USB_EHCI_MX6 - imx_iomux_v3_setup_multiple_pads( - usb_otg_pads, ARRAY_SIZE(usb_otg_pads)); -#endif - return 0; -} - -int checkboard(void) -{ - puts("Board: TBS2910 Matrix ARM mini PC\n"); - return 0; -} diff --git a/board/tbs/tbs2910/tbs2910.cfg b/board/tbs/tbs2910/tbs2910.cfg deleted file mode 100644 index 3ca807b3157..00000000000 --- a/board/tbs/tbs2910/tbs2910.cfg +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Soeren Moch smoch@web.de - */ - -#define __ASSEMBLY__ -#include "asm/arch/crm_regs.h" -#include "asm/arch/iomux.h" -#include "asm/arch/mx6-ddr.h" - -/* image version 2 for imx6 */ -IMAGE_VERSION 2 -BOOT_FROM sd - -/* set the default clock gates to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0x00FFF300 -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF -/* set CKO1 (used as AUDIO_MCLK) to ahb_clk_root/8 = 16.5 MHz */ -DATA 4, CCM_CCOSR, 0x000000fb - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x77177717 -DATA 4, MX6_IOMUXC_GPR7, 0x77177717 - - -/* - * DDR3/DDR3L settings - * use default 40 Ohm pad drive strength, no odt - * 4x256Mx16 DDR3L-1066 7-7-7 - */ - -/* disable dq pullup */ -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -/* disable dqs pullup */ -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 -/* set ddr input mode for dq signals */ -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -/* set ddr input mode for dqs signals */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -/* set pad calibration type to DDR3 */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 -/* ZQ calibration */ -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -/* dqs write delay */ -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001f001f -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001f001f -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f001f -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001f001f -/* dqs read delay */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 -/* dqs read gating control */ -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43000300 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03000300 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43000300 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03000300 -/* start delay line calibration */ -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -/* tRFC=0x89+1,tXS=0x8e+1,tXP=3+1,tXPDLL=0xc+1,tFAW=0x17+1,tCL=0x4+3 */ -DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974 -/* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */ -DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 -/* tDLLK=0x1ff+1,tRTP=3+1,tWTR=3+1,tRRD=3+1 */ -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -/* RTW_SAME=2,WTR_DIFF=3,WTW_DIFF=3,RTW_DIFF=2,RTR_DIFF=2 */ -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -/* tXPR=0x8e+1,SDE2RST=0x10-2,RST2CKE=0x23-2 */ -DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 -/* ODT timing */ -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 -/* read odt settings, 120 Ohm */ -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 -/* cs0, 15-bit row, 10-bit column, BL 8, 64-bit bus */ -DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 -/* interleaved bank access (row/bank/col), 5 cycles additional read delay */ -DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 -/* 2GiByte RAM at cs0 */ -DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 -/* load mode registers of external ddr chips */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -/* externel chip ZQ calibration */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -/* configure and start refreshes, 8 refresh commands at 32 kHz */ -DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 -/* tCKE=2+1,tCKSRX=6,tCKSE=6, active power down after 256 cycles (setting 5) */ -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 -/* set automatic self refresh */ -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 -/* controller configuration finished */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig deleted file mode 100644 index 55cd9bd998f..00000000000 --- a/configs/tbs2910_defconfig +++ /dev/null @@ -1,58 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_TARGET_TBS2910=y -CONFIG_CMD_HDMIDETECT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_BOOTDELAY=3 -CONFIG_PRE_CONSOLE_BUFFER=y -CONFIG_PRE_CON_BUF_ADDR=0x7c000000 -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Matrix U-Boot> " -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MEMTEST=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_EFI_PARTITION=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_DM=y -CONFIG_DWC_AHSATA=y -CONFIG_FSL_ESDHC=y -CONFIG_PHYLIB=y -CONFIG_MII=y -CONFIG_PCI=y -CONFIG_DM_THERMAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="TBS" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h deleted file mode 100644 index a60223c6235..00000000000 --- a/include/configs/tbs2910.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Soeren Moch smoch@web.de - * - * Configuration settings for the TBS2910 MatrixARM board. - */ - -#ifndef __TBS2910_CONFIG_H -#define __TBS2910_CONFIG_H - -#include "mx6_common.h" - -/* General configuration */ - -#define CONFIG_MACH_TYPE 3980 - -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_IMX_THERMAL - -/* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024) - -#define CONFIG_SYS_BOOTMAPSZ 0x10000000 - -/* Serial console */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ - -/* Filesystems / image support */ - -/* MMC */ -#define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 4 -#define CONFIG_PHY_ATHEROS - -/* Framebuffer */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP -#endif - -/* PCI */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) -#endif - -/* SATA */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#ifdef CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USBD_HS -#endif /* CONFIG_CMD_USB_MASS_STORAGE */ -#ifdef CONFIG_USB_KEYBOARD -#define CONFIG_PREBOOT \ - "usb start; " \ - "if hdmidet; then " \ - "run set_con_hdmi; " \ - "else " \ - "run set_con_serial; " \ - "fi;" -#endif /* CONFIG_USB_KEYBOARD */ -#endif /* CONFIG_CMD_USB */ - -/* RTC */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1307 -#define CONFIG_SYS_RTC_BUS_NUM 2 -#endif - -/* I2C */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_I2C_EDID -#endif - -/* Environment organization */ -#define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */ -#define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */ -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_OFFSET (384 * 1024) -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ - "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \ - "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \ - "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \ - "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \ - "${bootargs_mmc3}\0" \ - "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \ - "rdinit=/sbin/init enable_wait_mode=off\0" \ - "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \ - "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \ - "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \ - "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \ - "run bootargs_upd; " \ - "bootm 0x10800000 0x10d00000\0" \ - "console=ttymxc0\0" \ - "fan=gpio set 92\0" \ - "set_con_serial=setenv stdout serial; " \ - "setenv stderr serial;\0" \ - "set_con_hdmi=setenv stdout serial,vga; " \ - "setenv stderr serial,vga;\0" \ - "stderr=serial,vga;\0" \ - "stdin=serial,usbkbd;\0" \ - "stdout=serial,vga;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan; " \ - "if run bootcmd_up1; then " \ - "run bootcmd_up2; " \ - "else " \ - "run bootcmd_mmc; " \ - "fi" - -#endif /* __TBS2910_CONFIG_H * */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/cpu/arm926ejs/lpc32xx/Kconfig | 1 - board/timll/devkit3250/Kconfig | 12 -- board/timll/devkit3250/MAINTAINERS | 6 - board/timll/devkit3250/Makefile | 7 - board/timll/devkit3250/devkit3250.c | 80 ---------- board/timll/devkit3250/devkit3250_spl.c | 67 -------- configs/devkit3250_defconfig | 48 ------ include/configs/devkit3250.h | 194 ------------------------ 8 files changed, 415 deletions(-) delete mode 100644 board/timll/devkit3250/Kconfig delete mode 100644 board/timll/devkit3250/MAINTAINERS delete mode 100644 board/timll/devkit3250/Makefile delete mode 100644 board/timll/devkit3250/devkit3250.c delete mode 100644 board/timll/devkit3250/devkit3250_spl.c delete mode 100644 configs/devkit3250_defconfig delete mode 100644 include/configs/devkit3250.h

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig b/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig index 986ad738ac1..407252c8c30 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig +++ b/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig @@ -14,7 +14,6 @@ config TARGET_WORK_92105

endchoice

-source "board/timll/devkit3250/Kconfig" source "board/work-microwave/work_92105/Kconfig"

endif diff --git a/board/timll/devkit3250/Kconfig b/board/timll/devkit3250/Kconfig deleted file mode 100644 index 5129c2dcae5..00000000000 --- a/board/timll/devkit3250/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DEVKIT3250 - -config SYS_BOARD - default "devkit3250" - -config SYS_VENDOR - default "timll" - -config SYS_CONFIG_NAME - default "devkit3250" - -endif diff --git a/board/timll/devkit3250/MAINTAINERS b/board/timll/devkit3250/MAINTAINERS deleted file mode 100644 index cb93563feda..00000000000 --- a/board/timll/devkit3250/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -DEVKIT3250 BOARD -M: Vladimir Zapolskiy vz@mleia.com -S: Maintained -F: board/timll/devkit3250/ -F: include/configs/devkit3250.h -F: configs/devkit3250_defconfig diff --git a/board/timll/devkit3250/Makefile b/board/timll/devkit3250/Makefile deleted file mode 100644 index 056813995eb..00000000000 --- a/board/timll/devkit3250/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 by Vladimir Zapolskiy vz@mleia.com -# Copyright (C) 2008, Guennadi Liakhovetski lg@denx.de - -obj-y := devkit3250.o -obj-$(CONFIG_SPL_BUILD) += devkit3250_spl.o diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c deleted file mode 100644 index a4b963d463a..00000000000 --- a/board/timll/devkit3250/devkit3250.c +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Embest/Timll DevKit3250 board support - * - * Copyright (C) 2011-2015 Vladimir Zapolskiy vz@mleia.com - */ - -#include <common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/clk.h> -#include <asm/arch/cpu.h> -#include <asm/arch/emc.h> -#include <asm/arch/wdt.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; -static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; -static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE; - -void reset_periph(void) -{ - /* This function resets peripherals by triggering RESOUT_N */ - setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); - writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl); - udelay(300); - - writel(0, &wdt->mctrl); - clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); - - /* Such a long delay is needed to initialize SMSC phy */ - udelay(10000); -} - -int board_early_init_f(void) -{ - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); - lpc32xx_i2c_init(1); - lpc32xx_i2c_init(2); - lpc32xx_ssp_init(); - lpc32xx_mac_init(); - - /* - * nWP may be controlled by GPO19, but unpopulated by default R23 - * makes no sense to configure this GPIO level, nWP is always high - */ - lpc32xx_slc_nand_init(); - - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - -#ifdef CONFIG_SYS_FLASH_CFI - /* Use 16-bit memory interface for NOR Flash */ - emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT; - - /* Change the NOR timings to optimum value to get maximum bandwidth */ - emc->stat[0].waitwen = EMC_STAT_WAITWEN(1); - emc->stat[0].waitoen = EMC_STAT_WAITOEN(0); - emc->stat[0].waitrd = EMC_STAT_WAITRD(12); - emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12); - emc->stat[0].waitwr = EMC_STAT_WAITWR(5); - emc->stat[0].waitturn = EMC_STAT_WAITTURN(2); -#endif - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - - return 0; -} diff --git a/board/timll/devkit3250/devkit3250_spl.c b/board/timll/devkit3250/devkit3250_spl.c deleted file mode 100644 index 47af78ae0b1..00000000000 --- a/board/timll/devkit3250/devkit3250_spl.c +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Timll DevKit3250 board support, SPL board configuration - * - * (C) Copyright 2015 Vladimir Zapolskiy vz@mleia.com - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/cpu.h> -#include <asm/arch/emc.h> -#include <asm/arch-lpc32xx/gpio.h> -#include <spl.h> - -static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; - -/* - * SDRAM K4S561632N-LC60 settings are selected in assumption that - * SDRAM clock may be set up to 166 MHz, however at the moment - * it is 104 MHz. Most delay values are converted to be a multiple of - * base clock, and precise pinned values are not needed here. - */ -struct emc_dram_settings dram_64mb = { - .cmddelay = 0x0001C000, - .config0 = 0x00005682, - .rascas0 = 0x00000302, - .rdconfig = 0x00000011, /* undocumented but crucial value */ - - .trp = 83333333, - .tras = 23809524, - .tsrex = 12500000, - .twr = 83000000, /* tWR = tRDL = 2 CLK */ - .trc = 15384616, - .trfc = 15384616, - .txsr = 12500000, - .trrd = 1, - .tmrd = 1, - .tcdlr = 0, - - .refresh = 130000, /* 800 clock cycles */ - - .mode = 0x00018000, - .emode = 0x02000000, -}; - -void spl_board_init(void) -{ - /* First of all silence buzzer controlled by GPO_20 */ - writel((1 << 20), &gpio->p3_outp_clr); - - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); - preloader_console_init(); - - ddr_init(&dram_64mb); - - /* - * NAND initialization is done by nand_init(), - * here just enable NAND SLC clocks - */ - lpc32xx_slc_nand_init(); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_NAND; -} diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig deleted file mode 100644 index b739f27803b..00000000000 --- a/configs/devkit3250_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_LPC32XX=y -CONFIG_SYS_TEXT_BASE=0x83F00000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_BOOTDELAY=1 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200n8" -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_ENV_IS_IN_NAND=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_NAND=y -CONFIG_NAND_LPC32XX_SLC=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_PHYLIB=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_PHY_ADDR=31 -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_LPC32XX_SSP=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h deleted file mode 100644 index 2f8c655b2cc..00000000000 --- a/include/configs/devkit3250.h +++ /dev/null @@ -1,194 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Embest/Timll DevKit3250 board configuration file - * - * Copyright (C) 2011-2015 Vladimir Zapolskiy vz@mleia.com - */ - -#ifndef __CONFIG_DEVKIT3250_H__ -#define __CONFIG_DEVKIT3250_H__ - -/* SoC and board defines */ -#include <linux/sizes.h> -#include <asm/arch/cpu.h> - -#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250 - -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* - * Memory configurations - */ -#define CONFIG_SYS_MALLOC_LEN SZ_1M -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_64M -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ - - GENERATED_GBL_DATA_SIZE) - -/* - * Serial Driver - */ -#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */ - -/* - * DMA - */ -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_DMA_LPC32XX -#endif - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_LPC32XX -#define CONFIG_SYS_I2C_SPEED 100000 - -/* - * GPIO - */ -#define CONFIG_LPC32XX_GPIO - -/* - * SSP/SPI - */ -#define CONFIG_LPC32XX_SSP_TIMEOUT 100000 - -/* - * Ethernet - */ -#define CONFIG_RMII -#define CONFIG_PHY_SMSC -#define CONFIG_LPC32XX_ETH -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -/* - * NOR Flash - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 -#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE -#define CONFIG_SYS_FLASH_SIZE SZ_4M - -/* - * NAND controller - */ -#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } - -/* - * NAND chip timings - */ -#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14 -#define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 -#define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 -#define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 -#define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14 -#define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 -#define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 -#define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 - -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE -#define CONFIG_SYS_NAND_USE_FLASH_BBT - -/* - * USB - */ -#define CONFIG_USB_OHCI_LPC32XX -#define CONFIG_USB_ISP1301_I2C_ADDR 0x2d - -/* - * U-Boot General Configurations - */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * Pass open firmware flat tree - */ - -/* - * Environment - */ -#define CONFIG_ENV_SIZE SZ_128K -#define CONFIG_ENV_OFFSET 0x000A0000 - -#define CONFIG_BOOTCOMMAND \ - "dhcp; " \ - "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \ - "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \ - "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \ - "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \ - "bootm ${loadaddr} - ${dtbaddr}" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ - "ethaddr=00:01:90:00:C0:81\0" \ - "dtbaddr=0x81000000\0" \ - "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ - "tftpdir=vladimir/oe/devkit3250\0" \ - "userargs=oops=panic\0" - -/* - * U-Boot Commands - */ - -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x80008000 - -/* - * SPL specific defines - */ -/* SPL will be executed at offset 0 */ -#define CONFIG_SPL_TEXT_BASE 0x00000000 - -/* SPL will use SRAM as stack */ -#define CONFIG_SPL_STACK 0x0000FFF8 - -/* Use the framework and generic lib */ - -/* SPL will use serial */ - -/* SPL loads an image from NAND */ -#define CONFIG_SPL_NAND_RAW_ONLY -#define CONFIG_SPL_NAND_DRIVERS - -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_NAND_SOFTECC - -#define CONFIG_SPL_MAX_SIZE 0x20000 -#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE - -/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE - -/* See common/spl/spl.c spl_set_header_raw_uboot() */ -#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE - -/* - * Include SoC specific configuration - */ -#include <asm/arch/config.h> - -#endif /* __CONFIG_DEVKIT3250_H__*/

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-kirkwood/Kconfig | 1 - board/Synology/ds109/Kconfig | 12 -- board/Synology/ds109/MAINTAINERS | 6 - board/Synology/ds109/Makefile | 7 -- board/Synology/ds109/ds109.c | 176 ------------------------------ board/Synology/ds109/ds109.h | 43 -------- board/Synology/ds109/kwbimage.cfg | 150 ------------------------- board/Synology/ds109/openocd.cfg | 115 ------------------- configs/ds109_defconfig | 38 ------- include/configs/ds109.h | 86 --------------- 10 files changed, 634 deletions(-) delete mode 100644 board/Synology/ds109/Kconfig delete mode 100644 board/Synology/ds109/MAINTAINERS delete mode 100644 board/Synology/ds109/Makefile delete mode 100644 board/Synology/ds109/ds109.c delete mode 100644 board/Synology/ds109/ds109.h delete mode 100644 board/Synology/ds109/kwbimage.cfg delete mode 100644 board/Synology/ds109/openocd.cfg delete mode 100644 configs/ds109_defconfig delete mode 100644 include/configs/ds109.h

diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 00ed62591ea..11491f61b8a 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -72,7 +72,6 @@ config SYS_SOC

source "board/Marvell/openrd/Kconfig" source "board/Marvell/dreamplug/Kconfig" -source "board/Synology/ds109/Kconfig" source "board/Marvell/sheevaplug/Kconfig" source "board/buffalo/lsxl/Kconfig" source "board/cloudengines/pogo_e02/Kconfig" diff --git a/board/Synology/ds109/Kconfig b/board/Synology/ds109/Kconfig deleted file mode 100644 index a7c75ae368f..00000000000 --- a/board/Synology/ds109/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DS109 - -config SYS_BOARD - default "ds109" - -config SYS_VENDOR - default "Synology" - -config SYS_CONFIG_NAME - default "ds109" - -endif diff --git a/board/Synology/ds109/MAINTAINERS b/board/Synology/ds109/MAINTAINERS deleted file mode 100644 index 8783fdb1f20..00000000000 --- a/board/Synology/ds109/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -DS109 BOARD -M: Walter Schweizer swwa@users.sourceforge.net -S: Maintained -F: board/Synology/ds109 -F: configs/ds109_defconfig -F: include/configs/ds109.h diff --git a/board/Synology/ds109/Makefile b/board/Synology/ds109/Makefile deleted file mode 100644 index 9d103a61bcd..00000000000 --- a/board/Synology/ds109/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com - -obj-y := ds109.o diff --git a/board/Synology/ds109/ds109.c b/board/Synology/ds109/ds109.c deleted file mode 100644 index 1f2fce989c9..00000000000 --- a/board/Synology/ds109/ds109.c +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2009-2012 - * Wojciech Dubowik wojciech.dubowik@neratec.com - * Luka Perkov luka@openwrt.org - */ - -#include <common.h> -#include <miiphy.h> -#include <asm/setup.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> -#include <asm/arch/mpp.h> -#include "ds109.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* - * default gpio configuration - * There are maximum 64 gpios controlled through 2 sets of registers - * the below configuration configures mainly initial LED status - */ - mvebu_config_gpio(DS109_OE_VAL_LOW, - DS109_OE_VAL_HIGH, - DS109_OE_LOW, DS109_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { - MPP0_SPI_SCn, /* SPI Flash */ - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, - MPP4_GPIO, - MPP5_GPO, - MPP6_SYSRST_OUTn, /* Reset signal */ - MPP7_GPO, - MPP8_TW_SDA, /* I2C */ - MPP9_TW_SCK, /* I2C */ - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_GPO, - MPP13_UART1_TXD, - MPP14_UART1_RXD, - MPP15_GPIO, - MPP16_GPIO, - MPP17_GPIO, - MPP18_GPO, - MPP19_GPO, - MPP20_SATA1_ACTn, - MPP21_SATA0_ACTn, - MPP22_GPIO, /* HDD2 FAIL LED */ - MPP23_GPIO, /* HDD1 FAIL LED */ - MPP24_GPIO, - MPP25_GPIO, - MPP26_GPIO, - MPP27_GPIO, - MPP28_GPIO, - MPP29_GPIO, - MPP30_GPIO, - MPP31_GPIO, /* HDD2 */ - MPP32_GPIO, /* FAN A */ - MPP33_GPIO, /* FAN B */ - MPP34_GPIO, /* FAN C */ - MPP35_GPIO, /* FAN SENSE */ - MPP36_GPIO, - MPP37_GPIO, - MPP38_GPIO, - MPP39_GPIO, - MPP40_GPIO, - MPP41_GPIO, - MPP42_GPIO, - MPP43_GPIO, - MPP44_GPIO, - MPP45_GPIO, - MPP46_GPIO, - MPP47_GPIO, - MPP48_GPIO, - MPP49_GPIO, - 0 - }; - kirkwood_mpp_conf(kwmpp_config, NULL); - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - - return 0; -} - -/* Synology reset uses UART */ -#include <ns16550.h> -#define SOFTWARE_SHUTDOWN 0x31 -#define SOFTWARE_REBOOT 0x43 -#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE -void reset_misc(void) -{ - int b_d; - printf("Synology reset..."); - udelay(50000); - - b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2, - CONFIG_SYS_NS16550_CLK, 9600); - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d); - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT); -} - -/* Support old kernels */ -void setup_board_tags(struct tag **in_params) -{ - unsigned int boardId; - struct tag *params; - struct tag_mv_uboot *t; - int i; - - printf("Synology board tags..."); - params = *in_params; - t = (struct tag_mv_uboot *)&params->u; - - t->uboot_version = VER_NUM; - - boardId = SYNO_DS109_ID; - t->uboot_version |= boardId; - - t->tclk = CONFIG_SYS_TCLK; - t->sysclk = CONFIG_SYS_TCLK*2; - - t->isusbhost = 1; - for (i = 0; i < 4; i++) { - memset(t->macaddr[i], 0, sizeof(t->macaddr[i])); - t->mtu[i] = 0; - } - - params->hdr.tag = ATAG_MV_UBOOT; - params->hdr.size = tag_size(tag_mv_uboot); - params = tag_next(params); - *in_params = params; -} - -#ifdef CONFIG_RESET_PHY_R -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) -{ - u16 reg; - u16 devadr; - char *name = "egiga0"; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { - printf("Error: 88E1116 could not read PHY dev address\n"); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); - - printf("88E1116 Initialized on %s\n", name); -} -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Synology/ds109/ds109.h b/board/Synology/ds109/ds109.h deleted file mode 100644 index cc6ef991f39..00000000000 --- a/board/Synology/ds109/ds109.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009-2012 - * Wojciech Dubowik wojciech.dubowik@neratec.com - * Luka Perkov luka@openwrt.org - */ - -#ifndef __DS109_H -#define __DS109_H - -#define DS109_OE_LOW (0) -#define DS109_OE_HIGH (0) -#define DS109_OE_VAL_LOW ((1 << 22)|(1 << 23)) -#define DS109_OE_VAL_HIGH ((1 << 1)|1) - -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_MAC_CTRL2_REG 21 - -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -/* Marvell uboot parameters */ -#define ATAG_MV_UBOOT 0x41000403 -#define VER_NUM 0x03040400 /* 3.4.4 */ -#define BOARD_ID_BASE 0x0 -#define SYNO_DS109_ID (BOARD_ID_BASE+0x15) - -struct tag_mv_uboot { - u32 uboot_version; - u32 tclk; - u32 sysclk; - u32 isusbhost; - char macaddr[4][6]; - u16 mtu[4]; - u32 fw_image_base; - u32 fw_image_size; -}; - -#endif /* __DS109_H */ diff --git a/board/Synology/ds109/kwbimage.cfg b/board/Synology/ds109/kwbimage.cfg deleted file mode 100644 index 8f6e7051379..00000000000 --- a/board/Synology/ds109/kwbimage.cfg +++ /dev/null @@ -1,150 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2011 -# Jason Cooper u-boot@lakedaemon.net -# -# Based on work by: -# Marvell Semiconductor <www.marvell.com> -# Written-by: Siddarth Gore gores@marvell.com -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0/1 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b1b9b - -DATA 0xFFD20134 0xbbbbbbbb -DATA 0xFFD20138 0x00bbbbbb - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register -# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x39543000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000833 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x0000000d # DDR Address Control -# bit1-0: 01, Cs0width=x8 -# bit3-2: 10, Cs0size=1Gb -# bit5-4: 01, Cs1width=x8 -# bit7-6: 10, Cs1size=1Gb -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000C52 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000042 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 0, DDR drive strenght normal -# bit2: 0, DDR ODT control lsd (disabled) -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, (disabled) -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x07, Size (i.e. 128MB) - -DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled - -DATA 0xFFD01510 0x20000000 # CS[2]n Base address to 256Mb -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD01518 0x30000000 # CS[3]n Base address to 256Mb -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low) -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 01, ODT1 active NEVER! -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000F80F # CPU ODT Control -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/Synology/ds109/openocd.cfg b/board/Synology/ds109/openocd.cfg deleted file mode 100644 index baa512aef24..00000000000 --- a/board/Synology/ds109/openocd.cfg +++ /dev/null @@ -1,115 +0,0 @@ -# Synology DS109 - -interface ftdi -ftdi_vid_pid 0x0403 0x6010 - -ftdi_layout_init 0x0008 0x000b -ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010 -ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040 - -adapter_khz 2000 - -# length of reset signal: [ms] -adapter_nsrst_assert_width 1000 - -# don't talk to JTAG after reset for: [ms] -adapter_nsrst_delay 200 - -source [find target/feroceon.cfg] - -reset_config trst_and_srst srst_nogate - -proc ds109_init { } { - - # We need to assert DBGRQ while holding nSRST down. - # However DBGACK will be set only when nSRST is released. - # Furthermore, the JTAG interface doesn't respond at all when - # the CPU is in the WFI (wait for interrupts) state, so it is - # possible that initial tap examination failed. So let's - # re-examine the target again here when nSRST is asserted which - # should then succeed. - jtag_reset 0 1 - feroceon.cpu arp_examine - halt 0 - jtag_reset 0 0 - wait_halt - #reset run - #soft_reset_halt - - arm mcr 15 0 0 1 0 0x00052078 - - mww 0xD00100e0 0x1b1b1b9b ;# - mww 0xD0020134 0xbbbbbbbb ;# - mww 0xD0020138 0x00bbbbbb ;# - mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register - mww 0xD0001404 0x39743000 ;# Dunit Control Low Register - mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register - mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register - mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register - mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register - mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register - mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register - mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register - mww 0xD0001424 0x0000F1FF ;# Dunit Control High Register - mww 0xD0001428 0x00085520 ;# Dunit Control High Register - mww 0xD000147c 0x00008552 ;# Dunit Control High Register - mww 0xD0001500 0x00000000 ;# - mww 0xD0001504 0x07FFFFF1 ;# CS0n Size Register - mww 0xD0001508 0x10000000 ;# CS1n Base Register - mww 0xD000150C 0x00000000 ;# CS1n Size Register - mww 0xD0001510 0x20000000 ;# - mww 0xD0001514 0x00000000 ;# CS2n Size Register - mww 0xD000151C 0x00000000 ;# CS3n Size Register - mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register - mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister - mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register - mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register - mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - mww 0xD0020204 0x00000000 ;# " - - mww 0xD0010000 0x01111111 ;# MPP 0 to 7 - mww 0xD0010004 0x11113322 ;# MPP 8 to 15 - mww 0xD0010008 0x00001111 ;# MPP 16 to 23 -} - -proc ds109_load { } { - # load u-Boot into RAM and execute it - ds109_init - load_image u-boot.bin 0x00600000 bin - resume 0x00600000 -} diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig deleted file mode 100644 index 23f1886a249..00000000000 --- a/configs/ds109_defconfig +++ /dev/null @@ -1,38 +0,0 @@ -CONFIG_ARM=y -CONFIG_KIRKWOOD=y -CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_TARGET_DS109=y -CONFIG_NR_DRAM_BANKS=2 -# CONFIG_SYS_MALLOC_F is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_ISO_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ds109" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_DM=y -CONFIG_MVSATA_IDE=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MVTWSI=y -# CONFIG_MMC is not set -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_DM_RTC=y -CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_FS_EXT4=y diff --git a/include/configs/ds109.h b/include/configs/ds109.h deleted file mode 100644 index c06f0058deb..00000000000 --- a/include/configs/ds109.h +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Jason Cooper u-boot@lakedaemon.net - * - * Based on work by: - * Marvell Semiconductor <www.marvell.com> - * Written-by: Siddarth Gore gores@marvell.com - */ - -#ifndef _CONFIG_DS109_H -#define _CONFIG_DS109_H - -/* Provide the MACH_TYPE value that the vendor kernel requires. */ -#define CONFIG_MACH_TYPE 527 - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ - -/* - * Commands configuration - */ -#define CONFIG_CMD_EXT2 - -/* - * mv-plug-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-plug-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_SPI_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64k */ -#endif - -#ifdef CONFIG_CMD_SF -#define CONFIG_HARD_SPI 1 -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */ -#endif - -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_ADDR 0x3d0000 -#define CONFIG_ENV_OFFSET 0x3d0000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \ - "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "bootm 0x6400000;" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "x_bootcmd_ethernet=ping 192.168.1.2\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \ - "x_bootargs=console=ttyS0,115200\0" \ - "x_bootargs_root=root=/dev/sda2 rootdelay=10\0" \ - "ipaddr=192.168.1.5\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable one port */ -#define CONFIG_PHY_BASE_ADR 8 -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#endif /* _CONFIG_DS109_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/Kconfig | 1 - board/bosch/shc/Kconfig | 87 --- board/bosch/shc/MAINTAINERS | 11 - board/bosch/shc/Makefile | 8 - board/bosch/shc/README | 114 ---- board/bosch/shc/board.c | 647 --------------------- board/bosch/shc/board.h | 186 ------ board/bosch/shc/mux.c | 260 --------- configs/am335x_shc_defconfig | 46 -- configs/am335x_shc_ict_defconfig | 47 -- configs/am335x_shc_netboot_defconfig | 48 -- configs/am335x_shc_prompt_defconfig | 45 -- configs/am335x_shc_sdboot_defconfig | 47 -- configs/am335x_shc_sdboot_prompt_defconfig | 47 -- include/configs/am335x_shc.h | 263 --------- 15 files changed, 1857 deletions(-) delete mode 100644 board/bosch/shc/Kconfig delete mode 100644 board/bosch/shc/MAINTAINERS delete mode 100644 board/bosch/shc/Makefile delete mode 100644 board/bosch/shc/README delete mode 100644 board/bosch/shc/board.c delete mode 100644 board/bosch/shc/board.h delete mode 100644 board/bosch/shc/mux.c delete mode 100644 configs/am335x_shc_defconfig delete mode 100644 configs/am335x_shc_ict_defconfig delete mode 100644 configs/am335x_shc_netboot_defconfig delete mode 100644 configs/am335x_shc_prompt_defconfig delete mode 100644 configs/am335x_shc_sdboot_defconfig delete mode 100644 configs/am335x_shc_sdboot_prompt_defconfig delete mode 100644 include/configs/am335x_shc.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c111d42a38f..42e3fcb5e1a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1487,7 +1487,6 @@ source "arch/arm/cpu/armv8/Kconfig"

source "arch/arm/mach-imx/Kconfig"

-source "board/bosch/shc/Kconfig" source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" source "board/Marvell/gplugd/Kconfig" diff --git a/board/bosch/shc/Kconfig b/board/bosch/shc/Kconfig deleted file mode 100644 index e0e56e6bfdc..00000000000 --- a/board/bosch/shc/Kconfig +++ /dev/null @@ -1,87 +0,0 @@ -if TARGET_AM335X_SHC - -config SYS_BOARD - default "shc" - -config SYS_VENDOR - default "bosch" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "am335x_shc" - -choice - prompt "enable different boot versions for the shc board" - default SHC_EMMC - help - Select the boot version of the shc board. - -config SHC_EMMC - bool "enable eMMC" - help - enable here the eMMC functionality on the bosch shc board. - -config SHC_ICT - bool "enable ICT" - help - enable here the ICT functionality on the bosch shc board - -config SHC_NETBOOT - bool "enable NETBOOT" - help - enable here the NETBOOT functionality on the bosch shc board - -config SHC_SDBOOT - bool "enable SDBOOT" - help - enable here the SDBOOT functionality on the bosch shc board - -endchoice - -choice - prompt "enable different board versions for the shc board" - default C3_SAMPLE - help - Select the board version of the shc board. - -config B_SAMPLE - bool "B Sample board version" - help - activate, if you want to build for the B sample version - of the bosch shc board - -config B2_SAMPLE - bool "B2 Sample board version" - help - activate, if you want to build for the B2 sample version - of the bosch shc board - -config C_SAMPLE - bool "C Sample board version" - help - activate, if you want to build for the C sample version - of the bosch shc board - -config C2_SAMPLE - bool "C2 Sample board version" - help - activate, if you want to build for the C2 sample version - of the bosch shc board - -config C3_SAMPLE - bool "C3 Sample board version" - help - activate, if you want to build for the C3 sample version - of the bosch shc board - -config SERIES - bool "Series board version" - help - activate, if you want to build for the Series version - of the bosch shc board - -endchoice - -endif diff --git a/board/bosch/shc/MAINTAINERS b/board/bosch/shc/MAINTAINERS deleted file mode 100644 index ae3c0355c07..00000000000 --- a/board/bosch/shc/MAINTAINERS +++ /dev/null @@ -1,11 +0,0 @@ -SHC BOARD -M: Heiko Schocher hs@denx.de -S: Maintained -F: board/bosch/shc -F: include/configs/am335x_shc.h -F: configs/am335x_shc_defconfig -F: configs/am335x_shc_ict_defconfig -F: configs/am335x_shc_netboot_defconfig -F: configs/am335x_shc_prompt_defconfig -F: configs/am335x_shc_sdboot_defconfig -F: configs/am335x_shc_sdboot_prompt_defconfig diff --git a/board/bosch/shc/Makefile b/board/bosch/shc/Makefile deleted file mode 100644 index 93f2df3773e..00000000000 --- a/board/bosch/shc/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Makefile -# -# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - -obj-y := mux.o -obj-y += board.o diff --git a/board/bosch/shc/README b/board/bosch/shc/README deleted file mode 100644 index 2f206e0d551..00000000000 --- a/board/bosch/shc/README +++ /dev/null @@ -1,114 +0,0 @@ -Summary -======= - -This document covers various features of the 'am335x_shc' build. - -Hardware -======== - -AM335X based board: - -I2C: ready -DRAM: 512 MiB -Enabling the D-Cache -MMC: OMAP SD/MMC: 0 @ 26 MHz, OMAP SD/MMC: 1 @ 26 MHz -Net: cpsw - -Following boot options are possible: - -2 Jumpers: - -Jumper 1 Jumper 2 Bootmode -off off eMMC boot -on off SD boot -off on Net boot - -Compiling -========= - -$ make am335x_shc_defconfig - HOSTCC scripts/basic/fixdep - HOSTCC scripts/kconfig/conf.o - SHIPPED scripts/kconfig/zconf.tab.c - SHIPPED scripts/kconfig/zconf.lex.c - SHIPPED scripts/kconfig/zconf.hash.c - HOSTCC scripts/kconfig/zconf.tab.o - HOSTLD scripts/kconfig/conf -# -# configuration written to .config -# -$ make -s all - --> now you have the MLO and the u-boot.img file, you can put -on your SD card or eMMC. - -Configuring -=========== - -There are a lot of board versions and boot configurations, which -can be selected through "make menuconfig" - -ARM architecture ---> - enable different boot versions for the shc board (enable eMMC) ---> - (X) enable eMMC - ( ) enable ICT - ( ) enable NETBOOT - ( ) enable SDBOOT - - enable different board versions for the shc board (C3 Sample board version) ---> - ( ) B Sample board version - ( ) B2 Sample board version - ( ) C Sample board version - ( ) C2 Sample board version - (X) C3 Sample board version - ( ) Series board version - -Netboot -======= -- see also doc/SPL/README.am335x-network - -- set the jumper into netboot mode -- compile the U-boot sources with: - make am335x_shc_netboot_defconfig - make all -- copy the images into your tftp boot directory - cp spl/u-boot-spl.bin /tftpboot/.../u-boot-spl-restore.bin - cp u-boot.img /tftpboot/.../u-boot-restore.img -- power on the board, and you should get something like this: - -U-Boot SPL 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18) -#### NETBOOT #### -SHC -MPU reference clock runs at 6 MHz -Setting MPU clock to 594 MHz -Enabling Spread Spectrum of 18 permille for MPU -Trying to boot from net -Using default environment - -<ethaddr> not set. Validating first E-fuse MAC -cpsw -cpsw Waiting for PHY auto negotiation to complete... done -link up on port 0, speed 100, full duplex -BOOTP broadcast 1 -BOOTP broadcast 2 -DHCP client bound to address 192.168.20.91 (258 ms) -Using cpsw device -TFTP from server 192.168.1.1; our IP address is 192.168.20.91 -Filename 'shc/u-boot-restore.img'. -Load address: 0x807fffc0 -Loading: ################## - 1.2 MiB/s -done -Bytes transferred = 262480 (40150 hex) - - -U-Boot 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18 +0200) - - Watchdog enabled -I2C: ready -DRAM: 512 MiB -MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 -*** Warning - bad CRC, using default environment - -Net: cpsw -switch to partitions #0, OK diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c deleted file mode 100644 index 1ec9a3f5ffc..00000000000 --- a/board/bosch/shc/board.c +++ /dev/null @@ -1,647 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * board.c - * - * (C) Copyright 2016 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Board functions for TI AM335X based boards - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#include <common.h> -#include <errno.h> -#include <spl.h> -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> -#include <asm/arch/omap.h> -#include <asm/arch/ddr_defs.h> -#include <asm/arch/clock.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mem.h> -#include <asm/io.h> -#include <asm/emif.h> -#include <asm/gpio.h> -#include <i2c.h> -#include <miiphy.h> -#include <cpsw.h> -#include <power/tps65217.h> -#include <environment.h> -#include <watchdog.h> -#include <environment.h> -#include "mmc.h" -#include "board.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_SPL_BUILD) || \ - (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH)) -static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; -#endif -static struct shc_eeprom __attribute__((section(".data"))) header; -static int shc_eeprom_valid; - -/* - * Read header information from EEPROM into global structure. - */ -static int read_eeprom(void) -{ - /* Check if baseboard eeprom is available */ - if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { - puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); - return -ENODEV; - } - - /* read the eeprom using i2c */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, - sizeof(header))) { - puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n"); - return -EIO; - } - - if (header.magic != HDR_MAGIC) { - printf("Incorrect magic number (0x%x) in EEPROM\n", - header.magic); - return -EIO; - } - - shc_eeprom_valid = 1; - - return 0; -} - -static void shc_request_gpio(void) -{ - gpio_request(LED_PWR_BL_GPIO, "LED PWR BL"); - gpio_request(LED_PWR_RD_GPIO, "LED PWR RD"); - gpio_request(RESET_GPIO, "reset"); - gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN"); - gpio_request(WIFI_RST_GPIO, "WIFI rst"); - gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst"); - gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst"); - gpio_request(ENOC_RST_GPIO, "ENOC rst"); -#if defined CONFIG_B_SAMPLE - gpio_request(LED_PWR_GN_GPIO, "LED PWR GN"); - gpio_request(LED_CONN_BL_GPIO, "LED CONN BL"); - gpio_request(LED_CONN_RD_GPIO, "LED CONN RD"); - gpio_request(LED_CONN_GN_GPIO, "LED CONN GN"); -#else - gpio_request(LED_LAN_BL_GPIO, "LED LAN BL"); - gpio_request(LED_LAN_RD_GPIO, "LED LAN RD"); - gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL"); - gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD"); - gpio_request(LED_PWM_GPIO, "LED PWM"); - gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst"); -#endif - gpio_request(BACK_BUTTON_GPIO, "Back button"); - gpio_request(FRONT_BUTTON_GPIO, "Front button"); -} - -/* - * Function which forces all installed modules into running state for ICT - * testing. Called by SPL. - */ -static void __maybe_unused force_modules_running(void) -{ - /* Wi-Fi power regulator enable - high = enabled */ - gpio_direction_output(WIFI_REGEN_GPIO, 1); - /* - * Wait for Wi-Fi power regulator to reach a stable voltage - * (soft-start time, max. 350 µs) - */ - __udelay(350); - - /* Wi-Fi module reset - high = running */ - gpio_direction_output(WIFI_RST_GPIO, 1); - - /* ZigBee reset - high = running */ - gpio_direction_output(ZIGBEE_RST_GPIO, 1); - - /* BidCos reset - high = running */ - gpio_direction_output(BIDCOS_RST_GPIO, 1); - -#if !defined(CONFIG_B_SAMPLE) - /* Z-Wave reset - high = running */ - gpio_direction_output(Z_WAVE_RST_GPIO, 1); -#endif - - /* EnOcean reset - low = running */ - gpio_direction_output(ENOC_RST_GPIO, 0); -} - -/* - * Function which forces all installed modules into reset - to be released by - * the OS, called by SPL - */ -static void __maybe_unused force_modules_reset(void) -{ - /* Wi-Fi module reset - low = reset */ - gpio_direction_output(WIFI_RST_GPIO, 0); - - /* Wi-Fi power regulator enable - low = disabled */ - gpio_direction_output(WIFI_REGEN_GPIO, 0); - - /* ZigBee reset - low = reset */ - gpio_direction_output(ZIGBEE_RST_GPIO, 0); - - /* BidCos reset - low = reset */ - /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/ - -#if !defined(CONFIG_B_SAMPLE) - /* Z-Wave reset - low = reset */ - gpio_direction_output(Z_WAVE_RST_GPIO, 0); -#endif - - /* EnOcean reset - high = reset*/ - gpio_direction_output(ENOC_RST_GPIO, 1); -} - -/* - * Function to set the LEDs in the state "Bootloader booting" - */ -static void __maybe_unused leds_set_booting(void) -{ -#if defined(CONFIG_B_SAMPLE) - - /* Turn all red LEDs on */ - gpio_direction_output(LED_PWR_RD_GPIO, 1); - gpio_direction_output(LED_CONN_RD_GPIO, 1); - -#else /* All other SHCs starting with B2-Sample */ - /* Set the PWM GPIO */ - gpio_direction_output(LED_PWM_GPIO, 1); - /* Turn all red LEDs on */ - gpio_direction_output(LED_PWR_RD_GPIO, 1); - gpio_direction_output(LED_LAN_RD_GPIO, 1); - gpio_direction_output(LED_CLOUD_RD_GPIO, 1); - -#endif -} - -/* - * Function to set the LEDs in the state "Bootloader error" - */ -static void leds_set_failure(int state) -{ -#if defined(CONFIG_B_SAMPLE) - /* Turn all blue and green LEDs off */ - gpio_set_value(LED_PWR_BL_GPIO, 0); - gpio_set_value(LED_PWR_GN_GPIO, 0); - gpio_set_value(LED_CONN_BL_GPIO, 0); - gpio_set_value(LED_CONN_GN_GPIO, 0); - - /* Turn all red LEDs to 'state' */ - gpio_set_value(LED_PWR_RD_GPIO, state); - gpio_set_value(LED_CONN_RD_GPIO, state); - -#else /* All other SHCs starting with B2-Sample */ - /* Set the PWM GPIO */ - gpio_direction_output(LED_PWM_GPIO, 1); - - /* Turn all blue LEDs off */ - gpio_set_value(LED_PWR_BL_GPIO, 0); - gpio_set_value(LED_LAN_BL_GPIO, 0); - gpio_set_value(LED_CLOUD_BL_GPIO, 0); - - /* Turn all red LEDs to 'state' */ - gpio_set_value(LED_PWR_RD_GPIO, state); - gpio_set_value(LED_LAN_RD_GPIO, state); - gpio_set_value(LED_CLOUD_RD_GPIO, state); -#endif -} - -/* - * Function to set the LEDs in the state "Bootloader finished" - */ -static void leds_set_finish(void) -{ -#if defined(CONFIG_B_SAMPLE) - /* Turn all LEDs off */ - gpio_set_value(LED_PWR_BL_GPIO, 0); - gpio_set_value(LED_PWR_RD_GPIO, 0); - gpio_set_value(LED_PWR_GN_GPIO, 0); - gpio_set_value(LED_CONN_BL_GPIO, 0); - gpio_set_value(LED_CONN_RD_GPIO, 0); - gpio_set_value(LED_CONN_GN_GPIO, 0); -#else /* All other SHCs starting with B2-Sample */ - /* Turn all LEDs off */ - gpio_set_value(LED_PWR_BL_GPIO, 0); - gpio_set_value(LED_PWR_RD_GPIO, 0); - gpio_set_value(LED_LAN_BL_GPIO, 0); - gpio_set_value(LED_LAN_RD_GPIO, 0); - gpio_set_value(LED_CLOUD_BL_GPIO, 0); - gpio_set_value(LED_CLOUD_RD_GPIO, 0); - - /* Turn off the PWM GPIO and mux it to EHRPWM */ - gpio_set_value(LED_PWM_GPIO, 0); - enable_shc_board_pwm_pin_mux(); -#endif -} - -static void check_button_status(void) -{ - ulong value; - gpio_direction_input(FRONT_BUTTON_GPIO); - value = gpio_get_value(FRONT_BUTTON_GPIO); - - if (value == 0) { - printf("front button activated !\n"); - env_set("harakiri", "1"); - } -} - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - return 1; -} -#endif - -static void shc_board_early_init(void) -{ - shc_request_gpio(); -# ifdef CONFIG_SHC_ICT - /* Force all modules into enabled state for ICT testing */ - force_modules_running(); -# else - /* Force all modules to enter Reset state until released by the OS */ - force_modules_reset(); -# endif - leds_set_booting(); -} - -#define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */ -#define OSC (V_OSCK/1000000) -/* Bosch: Predivider must be fixed to 4, so N = 4-1 */ -#define MPUPLL_N (4-1) -/* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */ -#define MPUPLL_FREF (OSC / (MPUPLL_N + 1)) - -const struct dpll_params dpll_ddr_shc = { - 400, OSC-1, 1, -1, -1, -1, -1}; - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr_shc; -} - -/* - * As we enabled downspread SSC with 1.8%, the values needed to be corrected - * such that the 20% overshoot will not lead to too high frequencies. - * In all cases, this is achieved by subtracting one from M (6 MHz less). - * Example: 600 MHz CPU - * Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz - * 600 MHz - 6 MHz (1x Fref) = 594 MHz - * SSC: 594 MHz * 1.8% = 10.7 MHz SSC - * Overshoot: 10.7 MHz * 20 % = 2.2 MHz - * --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK! - */ -const struct dpll_params dpll_mpu_shc_opp100 = { - 99, MPUPLL_N, 1, -1, -1, -1, -1}; - -void am33xx_spl_board_init(void) -{ - int sil_rev; - int mpu_vdd; - - puts(BOARD_ID_STR); - - /* - * Set CORE Frequency to OPP100 - * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100) - */ - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); - - sil_rev = readl(&cdev->deviceid) >> 28; - if (sil_rev < 2) { - puts("We do not support Silicon Revisions below 2.0!\n"); - return; - } - - dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); - if (i2c_probe(TPS65217_CHIP_PM)) - return; - - /* - * Retrieve the CPU max frequency by reading the efuse - * SHC-Default: 600 MHz - */ - switch (dpll_mpu_opp100.m) { - case MPUPLL_M_1000: - mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; - break; - case MPUPLL_M_800: - mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; - break; - case MPUPLL_M_720: - mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV; - break; - case MPUPLL_M_600: - mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV; - break; - case MPUPLL_M_300: - mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV; - break; - default: - puts("Cannot determine the frequency, failing!\n"); - return; - } - - if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { - puts("tps65217_voltage_update failure\n"); - return; - } - - /* Set MPU Frequency to what we detected */ - printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF); - printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF * - dpll_mpu_shc_opp100.m); - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100); - - /* Enable Spread Spectrum for this freq to be clean on EMI side */ - set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE); - - /* - * Using the default voltages for the PMIC (TPS65217D) - * LS1 = 1.8V (VDD_1V8) - * LS2 = 3.3V (VDD_3V3A) - * LDO1 = 1.8V (VIO and VRTC) - * LDO2 = 3.3V (VDD_3V3AUX) - */ - shc_board_early_init(); -} - -void set_uart_mux_conf(void) -{ - enable_uart0_pin_mux(); -} - -void set_mux_conf_regs(void) -{ - enable_shc_board_pin_mux(); -} - -const struct ctrl_ioregs ioregs_evmsk = { - .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, -}; - -static const struct ddr_data ddr3_shc_data = { - .datardsratio0 = MT41K256M16HA125E_RD_DQS, - .datawdsratio0 = MT41K256M16HA125E_WR_DQS, - .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, - .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, -}; - -static const struct cmd_control ddr3_shc_cmd_ctrl_data = { - .cmd0csratio = MT41K256M16HA125E_RATIO, - .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, - - .cmd1csratio = MT41K256M16HA125E_RATIO, - .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, - - .cmd2csratio = MT41K256M16HA125E_RATIO, - .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, -}; - -static struct emif_regs ddr3_shc_emif_reg_data = { - .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, - .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, - .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, - .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, - .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, - .zq_config = MT41K256M16HA125E_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY | - PHY_EN_DYN_PWRDN, -}; - -void sdram_init(void) -{ - /* Configure the DDR3 RAM */ - config_ddr(400, &ioregs_evmsk, &ddr3_shc_data, - &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0); -} -#endif - -/* - * Basic board specific setup. Pinmux has been handled already. - */ -int board_init(void) -{ -#if defined(CONFIG_HW_WATCHDOG) - hw_watchdog_init(); -#endif - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - if (read_eeprom() < 0) - puts("EEPROM Content Invalid.\n"); - - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -#if defined(CONFIG_NOR) || defined(CONFIG_NAND) - gpmc_init(); -#endif - shc_request_gpio(); - - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - check_button_status(); -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - if (shc_eeprom_valid) - if (is_valid_ethaddr(header.mac_addr)) - eth_env_set_enetaddr("ethaddr", header.mac_addr); -#endif - - return 0; -} -#endif - -#ifndef CONFIG_DM_ETH -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ - - return; -} - -static struct cpsw_slave_data cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - }, - { - .slave_reg_ofs = 0x308, - .sliver_reg_ofs = 0xdc0, - .phy_addr = 1, - }, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 1, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; -#endif - -/* - * This function will: - * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr - * in the environment - * Perform fixups to the PHY present on certain boards. We only need this - * function in: - * - SPL with either CPSW or USB ethernet support - * - Full U-Boot, with either CPSW or USB ethernet - * Build in only these cases to avoid warnings about unused variables - * when we build an SPL that has neither option but full U-Boot will. - */ -#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \ - defined(CONFIG_SPL_USB_ETHER)) && \ - defined(CONFIG_SPL_BUILD)) || \ - ((defined(CONFIG_DRIVER_TI_CPSW) || \ - defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \ - !defined(CONFIG_SPL_BUILD)) -int board_eth_init(bd_t *bis) -{ - int rv, n = 0; - uint8_t mac_addr[6]; - uint32_t mac_hi, mac_lo; - - /* try reading mac address from efuse */ - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - mac_addr[0] = mac_hi & 0xFF; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - mac_addr[4] = mac_lo & 0xFF; - mac_addr[5] = (mac_lo & 0xFF00) >> 8; - -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) - if (!env_get("ethaddr")) { - printf("<ethaddr> not set. Validating first E-fuse MAC\n"); - - if (is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("ethaddr", mac_addr); - } - - writel(MII_MODE_ENABLE, &cdev->miisel); - cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII; - cpsw_slaves[1].phy_if = cpsw_slaves[0].phy_if; - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - else - n += rv; -#endif - -#if defined(CONFIG_USB_ETHER) && \ - (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) - if (is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("usbnet_devaddr", mac_addr); - - rv = usb_eth_initialize(bis); - if (rv < 0) - printf("Error %d registering USB_ETHER\n", rv); - else - n += rv; -#endif - return n; -} -#endif - -#endif /* CONFIG_DM_ETH */ - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -static void bosch_check_reset_pin(void) -{ - if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) { - printf("Resetting ...\n"); - writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0); - disable_interrupts(); - reset_cpu(0); - /*NOTREACHED*/ - } -} - -static void hang_bosch(const char *cause, int code) -{ - int lv; - - gpio_direction_input(RESET_GPIO); - - /* Enable reset pin interrupt on falling edge */ - writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0); - writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT); - enable_interrupts(); - - puts(cause); - for (;;) { - for (lv = 0; lv < code; lv++) { - bosch_check_reset_pin(); - leds_set_failure(1); - __udelay(150 * 1000); - leds_set_failure(0); - __udelay(150 * 1000); - } -#if defined(BLINK_CODE) - __udelay(300 * 1000); -#endif - } -} - -void show_boot_progress(int val) -{ - switch (val) { - case BOOTSTAGE_ID_NEED_RESET: - hang_bosch("need reset", 4); - break; - } -} -#endif - -void arch_preboot_os(void) -{ - leds_set_finish(); -} - -#if defined(CONFIG_MMC) -int board_mmc_init(bd_t *bis) -{ - int ret; - - /* Bosch: Do not enable 52MHz for eMMC device to avoid EMI */ - ret = omap_mmc_init(0, MMC_MODE_HS_52MHz, 26000000, -1, -1); - if (ret) - return ret; - - ret = omap_mmc_init(1, MMC_MODE_HS_52MHz, 26000000, -1, -1); - return ret; -} -#endif diff --git a/board/bosch/shc/board.h b/board/bosch/shc/board.h deleted file mode 100644 index 997595bf42b..00000000000 --- a/board/bosch/shc/board.h +++ /dev/null @@ -1,186 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * board.h - * - * (C) Copyright 2016 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * TI AM335x boards information header - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* Definition to control the GPIOs (for LEDs and Reset) */ -#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) - -static inline int board_is_b_sample(void) -{ -#if defined CONFIG_B_SAMPLE - return 1; -#else - return 0; -#endif -} - -static inline int board_is_c_sample(void) -{ -#if defined CONFIG_C_SAMPLE - return 1; -#else - return 0; -#endif -} - -static inline int board_is_c3_sample(void) -{ -#if defined CONFIG_C3_SAMPLE - return 1; -#else - return 0; -#endif -} - -static inline int board_is_series(void) -{ -#if defined CONFIG_SERIES - return 1; -#else - return 0; -#endif -} - -/* - * Definitions for pinmuxing header and Board ID strings - */ -#if defined CONFIG_B_SAMPLE -# define BOARD_ID_STR "SHC B-Sample\n" -#elif defined CONFIG_B2_SAMPLE -# define BOARD_ID_STR "SHC B2-Sample\n" -#elif defined CONFIG_C_SAMPLE -# if defined(CONFIG_SHC_NETBOOT) -# define BOARD_ID_STR "#### NETBOOT ####\nSHC C-Sample\n" -# elif defined(CONFIG_SHC_SDBOOT) -# define BOARD_ID_STR "#### SDBOOT ####\nSHC C-Sample\n" -# else -# define BOARD_ID_STR "SHC C-Sample\n" -# endif -#elif defined CONFIG_C2_SAMPLE -# if defined(CONFIG_SHC_ICT) -# define BOARD_ID_STR "#### ICT ####\nSHC C2-Sample\n" -# elif defined(CONFIG_SHC_NETBOOT) -# define BOARD_ID_STR "#### NETBOOT ####\nSHC C2-Sample\n" -# elif defined(CONFIG_SHC_SDBOOT) -# define BOARD_ID_STR "#### SDBOOT ####\nSHC C2-Sample\n" -# else -# define BOARD_ID_STR "SHC C2-Sample\n" -# endif -#elif defined CONFIG_C3_SAMPLE -# if defined(CONFIG_SHC_ICT) -# define BOARD_ID_STR "#### ICT ####\nSHC C3-Sample\n" -# elif defined(CONFIG_SHC_NETBOOT) -# define BOARD_ID_STR "#### NETBOOT ####\nSHC C3-Sample\n" -# elif defined(CONFIG_SHC_SDBOOT) -# define BOARD_ID_STR "#### SDBOOT ####\nSHC C3-Sample\n" -# else -# define BOARD_ID_STR "SHC C3-Sample\n" -# endif -#elif defined CONFIG_SERIES -# if defined(CONFIG_SHC_ICT) -# define BOARD_ID_STR "#### ICT ####\nSHC\n" -# elif defined(CONFIG_SHC_NETBOOT) -# define BOARD_ID_STR "#### NETBOOT ####\nSHC\n" -# elif defined(CONFIG_SHC_SDBOOT) -# define BOARD_ID_STR "#### SDBOOT ####\nSHC\n" -# else -# define BOARD_ID_STR "SHC\n" -# endif -#else -# define BOARD_ID_STR "Unknown device!\n" -#endif - -/* - * Definitions for GPIO pin assignments - */ -#if defined CONFIG_B_SAMPLE - -# define LED_PWR_BL_GPIO GPIO_TO_PIN(1, 17) -# define LED_PWR_RD_GPIO GPIO_TO_PIN(1, 18) -# define LED_PWR_GN_GPIO GPIO_TO_PIN(1, 19) -# define LED_CONN_BL_GPIO GPIO_TO_PIN(0, 26) -# define LED_CONN_RD_GPIO GPIO_TO_PIN(0, 22) -# define LED_CONN_GN_GPIO GPIO_TO_PIN(0, 23) -# define RESET_GPIO GPIO_TO_PIN(1, 29) -# define WIFI_REGEN_GPIO GPIO_TO_PIN(1, 16) -# define WIFI_RST_GPIO GPIO_TO_PIN(0, 27) -# define ZIGBEE_RST_GPIO GPIO_TO_PIN(3, 18) -# define BIDCOS_RST_GPIO GPIO_TO_PIN(0, 12) -# define ENOC_RST_GPIO GPIO_TO_PIN(1, 22) - -#else - -# define LED_PWR_BL_GPIO GPIO_TO_PIN(0, 22) -# define LED_PWR_RD_GPIO GPIO_TO_PIN(0, 23) -# define LED_LAN_BL_GPIO GPIO_TO_PIN(1, 17) -# define LED_LAN_RD_GPIO GPIO_TO_PIN(0, 26) -# define LED_CLOUD_BL_GPIO GPIO_TO_PIN(1, 18) -# define LED_CLOUD_RD_GPIO GPIO_TO_PIN(2, 2) -# define LED_PWM_GPIO GPIO_TO_PIN(1, 19) -# define RESET_GPIO GPIO_TO_PIN(1, 29) -# define WIFI_REGEN_GPIO GPIO_TO_PIN(1, 16) -# define WIFI_RST_GPIO GPIO_TO_PIN(0, 27) -# define ZIGBEE_RST_GPIO GPIO_TO_PIN(3, 18) -# define BIDCOS_RST_GPIO GPIO_TO_PIN(1, 24) -# define Z_WAVE_RST_GPIO GPIO_TO_PIN(1, 21) -# define ENOC_RST_GPIO GPIO_TO_PIN(1, 22) - -#endif - -#define BACK_BUTTON_GPIO GPIO_TO_PIN(1, 29) -#define FRONT_BUTTON_GPIO GPIO_TO_PIN(1, 25) - -/* Reset is on GPIO pin 29 of GPIO bank 1 */ -#define RESET_MASK (0x1 << 29) - -#define HDR_MAGIC 0x43485342 -#define HDR_ETH_ALEN 6 -#define HDR_NAME_LEN 8 -#define HDR_REV_LEN 8 -#define HDR_SER_LEN 16 -#define HDR_ROOT_LEN 12 -#define HDR_FATC_LEN 12 - -/* -* SHC parameters held in On-Board I²C EEPROM device. -* -* Header Format -* -* Name Size Contents -*------------------------------------------------------------- -* Magic 4 0x42 0x53 0x48 0x43 [BSHC] -* -* Version 2 0x0100 for v1.0 -* -* Lenght 2 The length of the complete structure, not only this header -* -* Eth-MAC 6 Ethernet MAC Address -* SHC Pool: 7C:AC:B2:00:10:01 - TBD -* -* --- Further values follow, not important for Bootloader --- -*/ - -struct shc_eeprom { - u32 magic; - u16 version; - u16 lenght; - uint8_t mac_addr[HDR_ETH_ALEN]; -}; - -void enable_uart0_pin_mux(void); -void enable_shc_board_pin_mux(void); -void enable_shc_board_pwm_pin_mux(void); - -#endif diff --git a/board/bosch/shc/mux.c b/board/bosch/shc/mux.c deleted file mode 100644 index b04c5914f0d..00000000000 --- a/board/bosch/shc/mux.c +++ /dev/null @@ -1,260 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * mux.c - * - * (C) Copyright 2016 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include <common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/hardware.h> -#include <asm/arch/mux.h> -#include <asm/io.h> -#include <i2c.h> -#include "board.h" - -static struct module_pin_mux uart0_pin_mux[] = { - {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_RXD */ - {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */ - {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_CTS */ - {OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)}, /* UART0_RTS */ - {-1}, -}; - -static struct module_pin_mux uart1_pin_mux[] = { - {OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART1_RXD */ - {OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)}, /* UART1_TXD */ - {OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART1_CTS */ - {OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)}, /* UART1_RTS */ - {-1}, -}; - -static struct module_pin_mux uart2_pin_mux[] = { - {OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)}, /* UART2_RXD */ - {OFFSET(spi0_d0), (MODE(1) | PULLUDDIS)}, /* UART2_TXD */ - {-1}, -}; - -static struct module_pin_mux spi1_pin_mux[] = { - {OFFSET(mcasp0_aclkx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_SCLK */ - {OFFSET(mcasp0_fsx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D0 */ - {OFFSET(mcasp0_axr0), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D1 */ - {OFFSET(mcasp0_ahclkr), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_CS0 */ - {-1}, -}; - -static struct module_pin_mux uart4_pin_mux[] = { - {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ - {OFFSET(gpmc_wpn), (MODE(6) | PULLUP_EN)}, /* UART4_TXD */ - {-1}, -}; - -static struct module_pin_mux mmc0_pin_mux[] = { - {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT3 */ - {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT2 */ - {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT1 */ - {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT0 */ - {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ - {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_CMD */ - {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDDIS)}, /* MMC0_CD */ - {-1}, -}; - -static struct module_pin_mux mmc1_pin_mux[] = { - {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ - {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ - {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ - {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ - {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ - {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ - {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ - {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ - {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUDDIS)}, /* MMC1_CLK */ - {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ - {-1}, -}; - -static struct module_pin_mux mmc2_pin_mux[] = { - {OFFSET(gpmc_ad12), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT0 */ - {OFFSET(gpmc_ad13), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT1 */ - {OFFSET(gpmc_ad14), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT2 */ - {OFFSET(gpmc_ad15), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT3 */ - {OFFSET(gpmc_csn3), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CMD */ - {OFFSET(gpmc_clk), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CLK */ - {-1}, -}; -static struct module_pin_mux i2c0_pin_mux[] = { - {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_DATA */ - {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_SCLK */ - {-1}, -}; - -static struct module_pin_mux gpio0_7_pin_mux[] = { - {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUP_EN)}, /* GPIO0_7 */ - {-1}, -}; - -static struct module_pin_mux jtag_pin_mux[] = { - {OFFSET(xdma_event_intr0), (MODE(6) | RXACTIVE | PULLUDDIS)}, - {OFFSET(xdma_event_intr1), (MODE(6) | RXACTIVE | PULLUDDIS)}, - {OFFSET(nresetin_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, - {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)}, - {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(tdo), (MODE(0) | PULLUP_EN)}, - {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(ntrst), (MODE(0) | RXACTIVE)}, - {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)}, - {OFFSET(rsvd2), (MODE(0) | PULLUP_EN)}, - {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, - {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)}, - {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)}, - {OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN)}, - {OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS)}, - {-1}, -}; - -static struct module_pin_mux gpio_pin_mux[] = { - {OFFSET(gpmc_ad8), (MODE(7) | PULLUDDIS)}, /* gpio0[22] - LED_PWR_BL (external pull-down) */ - {OFFSET(gpmc_ad9), (MODE(7) | PULLUDDIS)}, /* gpio0[23] - LED_PWR_RD (external pull-down) */ - {OFFSET(gpmc_ad10), (MODE(7) | PULLUDDIS)}, /* gpio0[26] - LED_LAN_RD (external pull-down) */ - {OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)}, /* gpio0[27] - #WIFI_RST (external pull-down) */ - {OFFSET(gpmc_a0), (MODE(7) | PULLUDDIS)}, /* gpio1[16] - WIFI_REGEN */ - {OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS)}, /* gpio1[17] - LED_LAN_BL */ - {OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS)}, /* gpio1[18] - LED_Cloud_BL */ - {OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS)}, /* gpio1[19] - LED_PWM as GPIO */ - {OFFSET(gpmc_a4), (MODE(7))}, /* gpio1[20] - #eMMC_RST */ - {OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)}, /* gpio1[21] - #Z-Wave_RST */ - {OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)}, /* gpio1[22] - ENOC_RST */ - {OFFSET(gpmc_a7), (MODE(7) | PULLUP_EN)}, /* gpio1[23] - WIFI_MODE */ - {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[24] - #BIDCOS_RST */ - {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[25] - USR_BUTTON */ - {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[26] - #USB1_OC */ - {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[27] - BIDCOS_PROG */ - {OFFSET(gpmc_be1n), (MODE(7) | PULLUP_EN)}, /* gpio1[28] - ZIGBEE_PC7 */ - {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[29] - RESET_BUTTON */ - {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS)}, /* gpio2[2] - LED_Cloud_RD */ - {OFFSET(gpmc_oen_ren), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* gpio2[3] - #WIFI_POR */ - {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, /* gpio2[4] - N/C */ - {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)}, /* gpio2[5] - EEPROM_WP */ - {OFFSET(lcd_data0), (MODE(7) | PULLUDDIS)}, /* gpio2[6] */ - {OFFSET(lcd_data1), (MODE(7) | PULLUDDIS)}, /* gpio2[7] */ - {OFFSET(lcd_data2), (MODE(7) | PULLUDDIS)}, /* gpio2[8] */ - {OFFSET(lcd_data3), (MODE(7) | PULLUDDIS)}, /* gpio2[9] */ - {OFFSET(lcd_data4), (MODE(7) | PULLUDDIS)}, /* gpio2[10] */ - {OFFSET(lcd_data5), (MODE(7) | PULLUDDIS)}, /* gpio2[11] */ - {OFFSET(lcd_data6), (MODE(7) | PULLUDDIS)}, /* gpio2[12] */ - {OFFSET(lcd_data7), (MODE(7) | PULLUDDIS)}, /* gpio2[13] */ - {OFFSET(lcd_data8), (MODE(7) | PULLUDDIS)}, /* gpio2[14] */ - {OFFSET(lcd_data9), (MODE(7) | PULLUDDIS)}, /* gpio2[15] */ - {OFFSET(lcd_data10), (MODE(7) | PULLUDDIS)}, /* gpio2[16] */ - {OFFSET(lcd_data11), (MODE(7) | PULLUDDIS)}, /* gpio2[17] */ - {OFFSET(lcd_data12), (MODE(7) | PULLUDDIS)}, /* gpio0[8] */ - {OFFSET(lcd_data13), (MODE(7) | PULLUDDIS)}, /* gpio0[9] */ - {OFFSET(lcd_data14), (MODE(7) | PULLUDDIS)}, /* gpio0[10] */ - {OFFSET(lcd_data15), (MODE(7) | PULLUDDIS)}, /* gpio0[11] */ - {OFFSET(lcd_vsync), (MODE(7) | PULLUDDIS)}, /* gpio2[22] */ - {OFFSET(lcd_hsync), (MODE(7) | PULLUDDIS)}, /* gpio2[23] */ - {OFFSET(lcd_pclk), (MODE(7) | PULLUDDIS)}, /* gpio2[24] */ - {OFFSET(lcd_ac_bias_en), (MODE(7) | PULLUDDIS)},/* gpio2[25] */ - {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS)}, /* gpio0[4] */ - {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)}, /* gpio0[5] */ - {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS)}, /* gpio3[18] - #ZIGBEE_RST */ - {OFFSET(mcasp0_fsr), (MODE(7)) | PULLUDDIS}, /* gpio3[19] - ZIGBEE_BOOT */ - {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)}, /* gpio3[19] - ZIGBEE_BOOT */ - {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE | PULLUP_EN)},/* gpio3[21] - ZIGBEE_PC5 */ - {-1}, -}; - -static struct module_pin_mux mii1_pin_mux[] = { - {OFFSET(mii1_col), MODE(0) | RXACTIVE}, - {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, - {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, - {OFFSET(mii1_txen), MODE(0)}, - {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, - {OFFSET(mii1_txd3), MODE(0)}, - {OFFSET(mii1_txd2), MODE(0)}, - {OFFSET(mii1_txd1), MODE(0) | RXACTIVE}, - {OFFSET(mii1_txd0), MODE(0) | RXACTIVE}, - {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, - {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, - {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, - {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, - {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, - {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, - {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, - {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, - {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, - {-1}, -}; - -static struct module_pin_mux pwm_pin_mux[] = { - {OFFSET(gpmc_a3), (MODE(6) | PULLUDDIS)}, - {-1}, -}; - -void enable_uart0_pin_mux(void) -{ - configure_module_pin_mux(uart0_pin_mux); -} - -void enable_uart1_pin_mux(void) -{ - configure_module_pin_mux(uart1_pin_mux); -} - -void enable_uart2_pin_mux(void) -{ - configure_module_pin_mux(uart2_pin_mux); -} - -void enable_uart3_pin_mux(void) -{ -} - -void enable_uart4_pin_mux(void) -{ - configure_module_pin_mux(uart4_pin_mux); -} - -void enable_uart5_pin_mux(void) -{ -} - -void enable_i2c0_pin_mux(void) -{ - configure_module_pin_mux(i2c0_pin_mux); -} - -void enable_shc_board_pwm_pin_mux(void) -{ - configure_module_pin_mux(pwm_pin_mux); -} - -void enable_shc_board_pin_mux(void) -{ - /* Do board-specific muxes. */ - if (board_is_c3_sample() || board_is_series()) { - configure_module_pin_mux(mii1_pin_mux); - configure_module_pin_mux(mmc0_pin_mux); - configure_module_pin_mux(mmc1_pin_mux); - configure_module_pin_mux(mmc2_pin_mux); - configure_module_pin_mux(i2c0_pin_mux); - configure_module_pin_mux(gpio0_7_pin_mux); - configure_module_pin_mux(gpio_pin_mux); - configure_module_pin_mux(uart1_pin_mux); - configure_module_pin_mux(uart2_pin_mux); - configure_module_pin_mux(uart4_pin_mux); - configure_module_pin_mux(spi1_pin_mux); - configure_module_pin_mux(jtag_pin_mux); - } else { - puts("Unknown board, cannot configure pinmux."); - hang(); - } -} diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig deleted file mode 100644 index 25e1a4f9437..00000000000 --- a/configs/am335x_shc_defconfig +++ /dev/null @@ -1,46 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_AM33XX=y -CONFIG_TARGET_AM335X_SHC=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SERIES=y -CONFIG_DISTRO_DEFAULTS=y -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_YMODEM_SUPPORT=y -# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set -CONFIG_SYS_PROMPT="U-Boot# " -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n" -CONFIG_AUTOBOOT_DELAY_STR="shc" -CONFIG_AUTOBOOT_STOP_STR="noautoboot" -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_MMC_OMAP_HS=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_FAT_WRITE=y -CONFIG_LZO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig deleted file mode 100644 index 9ebfe5e7f59..00000000000 --- a/configs/am335x_shc_ict_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_AM33XX=y -CONFIG_TARGET_AM335X_SHC=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SHC_ICT=y -CONFIG_SERIES=y -CONFIG_DISTRO_DEFAULTS=y -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_YMODEM_SUPPORT=y -# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set -CONFIG_SYS_PROMPT="U-Boot# " -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n" -CONFIG_AUTOBOOT_DELAY_STR="shc" -CONFIG_AUTOBOOT_STOP_STR="noautoboot" -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_MMC_OMAP_HS=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_FAT_WRITE=y -CONFIG_LZO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig deleted file mode 100644 index 064b3c355c5..00000000000 --- a/configs/am335x_shc_netboot_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_AM33XX=y -CONFIG_TARGET_AM335X_SHC=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SHC_NETBOOT=y -CONFIG_SERIES=y -CONFIG_DISTRO_DEFAULTS=y -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_YMODEM_SUPPORT=y -# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set -CONFIG_SYS_PROMPT="U-Boot# " -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n" -CONFIG_AUTOBOOT_DELAY_STR="shc" -CONFIG_AUTOBOOT_STOP_STR="noautoboot" -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_MMC_OMAP_HS=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_FAT_WRITE=y -CONFIG_LZO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_shc_prompt_defconfig b/configs/am335x_shc_prompt_defconfig deleted file mode 100644 index dce83347322..00000000000 --- a/configs/am335x_shc_prompt_defconfig +++ /dev/null @@ -1,45 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_AM33XX=y -CONFIG_TARGET_AM335X_SHC=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SERIES=y -CONFIG_DISTRO_DEFAULTS=y -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_YMODEM_SUPPORT=y -# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n" -CONFIG_AUTOBOOT_DELAY_STR="shc" -CONFIG_AUTOBOOT_STOP_STR="noautoboot" -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_MMC_OMAP_HS=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_FAT_WRITE=y -CONFIG_LZO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig deleted file mode 100644 index e4e6adef194..00000000000 --- a/configs/am335x_shc_sdboot_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_AM33XX=y -CONFIG_TARGET_AM335X_SHC=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SHC_SDBOOT=y -CONFIG_SERIES=y -CONFIG_DISTRO_DEFAULTS=y -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_YMODEM_SUPPORT=y -# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set -CONFIG_SYS_PROMPT="U-Boot# " -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n" -CONFIG_AUTOBOOT_DELAY_STR="shc" -CONFIG_AUTOBOOT_STOP_STR="noautoboot" -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_MMC_OMAP_HS=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_FAT_WRITE=y -CONFIG_LZO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_shc_sdboot_prompt_defconfig b/configs/am335x_shc_sdboot_prompt_defconfig deleted file mode 100644 index e4e6adef194..00000000000 --- a/configs/am335x_shc_sdboot_prompt_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_AM33XX=y -CONFIG_TARGET_AM335X_SHC=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SHC_SDBOOT=y -CONFIG_SERIES=y -CONFIG_DISTRO_DEFAULTS=y -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_YMODEM_SUPPORT=y -# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set -CONFIG_SYS_PROMPT="U-Boot# " -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n" -CONFIG_AUTOBOOT_DELAY_STR="shc" -CONFIG_AUTOBOOT_STOP_STR="noautoboot" -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_MMC_OMAP_HS=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_FAT_WRITE=y -CONFIG_LZO=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h deleted file mode 100644 index 6368872e5b5..00000000000 --- a/include/configs/am335x_shc.h +++ /dev/null @@ -1,263 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * am335x_evm.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef __CONFIG_AM335X_SHC_H -#define __CONFIG_AM335X_SHC_H - -#include <configs/ti_am335x_common.h> - -/* settings we don;t want on this board */ -#undef CONFIG_CMD_SPI - -#define CONFIG_CMD_CACHE - -#ifndef CONFIG_SPL_BUILD -# define CONFIG_TIMESTAMP -#endif - -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -/* - * in case of SD Card or Network boot we want to have a possibility to - * debrick the shc, therefore do not read environment from eMMC - */ -#if defined(CONFIG_SHC_SDBOOT) || defined(CONFIG_SHC_NETBOOT) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#else -#define CONFIG_SYS_MMC_ENV_DEV 1 -#endif - -/* - * Info when using boot partitions: As environment resides within first - * 128 kB, MLO must start at 128 kB == 0x20000 - * ENV at MMC Boot0 Partition - 0/Undefined=user, 1=boot0, 2=boot1, - * 4..7=general0..3 - */ -#define CONFIG_ENV_SIZE 0x1000 /* 4 KB */ -#define CONFIG_ENV_OFFSET 0x7000 /* 28 kB */ - -#define CONFIG_HSMMC2_8BIT - -#define CONFIG_ENV_OFFSET_REDUND 0x9000 /* 36 kB */ -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#ifndef CONFIG_SHC_ICT -/* - * In builds other than ICT, reset to retry after timeout - * Define a timeout after which a stopped bootloader continues autoboot - * (only works with CONFIG_RESET_TO_RETRY) - */ -# define CONFIG_BOOT_RETRY_TIME 30 -# define CONFIG_RESET_TO_RETRY -#endif - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "kloadaddr=0x84000000\0" \ - "fdtaddr=0x85000000\0" \ - "fdt_high=0xffffffff\0" \ - "rdaddr=0x81000000\0" \ - "bootfile=uImage\0" \ - "fdtfile=am335x-shc.dtb\0" \ - "verify=no\0" \ - "serverip=10.55.152.184\0" \ - "rootpath=/srv/nfs/shc-rootfs\0" \ - "console=ttyO0,115200n8\0" \ - "optargs=quiet\0" \ - "mmcdev=1\0" \ - "harakiri=0\0" \ - "mmcpart=2\0" \ - "active_root=root1\0" \ - "inactive_root=root2\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "nfsopts=nolock\0" \ - "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ - "::off\0" \ - "ip_method=none\0" \ - "bootargs_defaults=setenv bootargs " \ - "console=${console} " \ - "${optargs}\0" \ - "mmcargs=run bootargs_defaults;" \ - "setenv bootargs ${bootargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype} ip=${ip_method}\0" \ - "netargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=/dev/nfs " \ - "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ - "ip=dhcp\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootenv=if fatload mmc ${mmcdev} ${loadaddr} ${bootenv}; then " \ - "echo Loaded environment from ${bootenv}; " \ - "run importbootenv; " \ - "fi;\0" \ - "importbootenv=echo Importing environment variables from uEnv.txt ...; " \ - "env import -t $loadaddr $filesize\0" \ - "loaduimagefat=fatload mmc ${mmcdev} ${kloadaddr} ${bootfile}\0" \ - "loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${kloadaddr} /boot/${bootfile}\0" \ - "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdtaddr} /boot/${fdtfile}\0" \ - "netloaduimage=tftp ${loadaddr} ${bootfile}\0" \ - "netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \ - "mmcboot=echo Booting Linux from ${mmcdevice} ...; " \ - "run mmcargs; " \ - "if run loadfdt; then " \ - "echo device tree detected; " \ - "bootm ${kloadaddr} - ${fdtaddr}; " \ - "else " \ - "bootm ${kloadaddr}; " \ - "fi; \0" \ - "netboot=echo Booting from network ...; " \ - "setenv autoload no; " \ - "dhcp; " \ - "run netloaduimage; " \ - "run netargs; " \ - "echo NFS path: ${serverip}:${rootpath};" \ - "if run netloadfdt; then " \ - "echo device tree detected; " \ - "bootm ${loadaddr} - ${fdtaddr}; " \ - "else " \ - "bootm ${loadaddr}; " \ - "fi; \0" \ - "emmc_erase=if test ${harakiri} = 1 ; then echo erase emmc ...; setenv mmcdev 1; mmc erase 0 200; reset; fi; \0" \ - "mmcpart_gp=mmcpart gp 1 40; \0" \ - "mmcpart_enhance=mmcpart enhance 0 64; \0" \ - "mmcpart_rel_write=mmcpart rel_write 1f; \0" \ - "mmcpart_commit=mmcpart commit 1; \0" \ - "mmc_hw_part=run mmcpart_gp; run mmcpart_enhance; run mmcpart_rel_write; run mmcpart_commit; \0" \ - "led_success=gpio set 22; \0" \ - "fusecmd=mmc dev 1; if mmcpart iscommitted; then echo HW Partitioning already committed; mmcpart list; else run mmc_hw_part; fi; run led_success; \0" \ - "uenv_exec=if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...; " \ - "run uenvcmd; " \ - "fi;\0" \ - "sd_setup=echo SD/MMC-Card detected on device 0; " \ - "setenv mmcdevice SD; " \ - "setenv mmcdev 0; " \ - "setenv mmcpart 2; " \ - "setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0" \ - "emmc_setup=echo eMMC detected on device 1; " \ - "setenv mmcdevice eMMC; " \ - "setenv mmcdev 1; " \ - "run emmc_erase; " \ - "if test ${active_root} = root2; then " \ - "echo Active root is partition 6 (root2); " \ - "setenv mmcpart 6; " \ - "else " \ - "echo Active root is partition 5 (root1); " \ - "setenv mmcpart 5; " \ - "fi; " \ - "setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0" -#endif /* #ifndef CONFIG_SPL_BUILD */ - -#if defined CONFIG_SHC_NETBOOT -/* Network Boot */ -# define CONFIG_BOOTCOMMAND \ - "run fusecmd; " \ - "if run netboot; then " \ - "echo Booting from network; " \ - "else " \ - "echo ERROR: Cannot boot from network!; " \ - "panic; " \ - "fi; " - -#elif defined CONFIG_SHC_SDBOOT /* !defined CONFIG_SHC_NETBOOT */ -/* SD-Card Boot */ -# define CONFIG_BOOTCOMMAND \ - "if mmc dev 0; mmc rescan; then " \ - "run sd_setup; " \ - "else " \ - "echo ERROR: SD/MMC-Card not detected!; " \ - "panic; " \ - "fi; " \ - "if run loaduimage; then " \ - "echo Bootable SD/MMC-Card inserted, booting from it!; " \ - "run mmcboot; " \ - "else " \ - "echo ERROR: Unable to load uImage from SD/MMC-Card!; " \ - "panic; " \ - "fi; " - -#elif defined CONFIG_SHC_ICT -/* ICT adapter boots only u-boot and does HW partitioning */ -# define CONFIG_BOOTCOMMAND \ - "if mmc dev 0; mmc rescan; then " \ - "run sd_setup; " \ - "else " \ - "echo ERROR: SD/MMC-Card not detected!; " \ - "panic; " \ - "fi; " \ - "run fusecmd; " - -#else /* !defined CONFIG_SHC_NETBOOT, !defined CONFIG_SHC_SDBOOT */ -/* Regular Boot from internal eMMC */ -# define CONFIG_BOOTCOMMAND \ - "if mmc dev 1; mmc rescan; then " \ - "run emmc_setup; " \ - "else " \ - "echo ERROR: eMMC device not detected!; " \ - "panic; " \ - "fi; " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else " \ - "echo ERROR Unable to load uImage from eMMC!; " \ - "echo Performing Rollback!; " \ - "setenv _active_ ${active_root}; " \ - "setenv _inactive_ ${inactive_root}; " \ - "setenv active_root ${_inactive_}; " \ - "setenv inactive_root ${_active_}; " \ - "saveenv; " \ - "reset; " \ - "fi; " - -#endif /* Regular Boot */ - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ - -/* PMIC support */ -#define CONFIG_POWER_TPS65217 - -/* SPL */ - -/* - * Disable MMC DM for SPL build and can be re-enabled after adding - * DM support in SPL - */ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_MMC -#undef CONFIG_TIMER -#endif - -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_PHY_SMSC - -/* I2C configuration */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 1 - -#define CONFIG_SHOW_BOOT_PROGRESS -#endif /* ! __CONFIG_AM335X_SHC_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-omap2/Kconfig | 1 - board/compulab/cm_t43/Kconfig | 15 --- board/compulab/cm_t43/MAINTAINERS | 6 -- board/compulab/cm_t43/Makefile | 11 -- board/compulab/cm_t43/board.h | 11 -- board/compulab/cm_t43/cm_t43.c | 164 ------------------------------ board/compulab/cm_t43/mux.c | 142 -------------------------- board/compulab/cm_t43/spl.c | 134 ------------------------ configs/cm_t43_defconfig | 72 ------------- include/configs/cm_t43.h | 140 ------------------------- 10 files changed, 696 deletions(-) delete mode 100644 board/compulab/cm_t43/Kconfig delete mode 100644 board/compulab/cm_t43/MAINTAINERS delete mode 100644 board/compulab/cm_t43/Makefile delete mode 100644 board/compulab/cm_t43/board.h delete mode 100644 board/compulab/cm_t43/cm_t43.c delete mode 100644 board/compulab/cm_t43/mux.c delete mode 100644 board/compulab/cm_t43/spl.c delete mode 100644 configs/cm_t43_defconfig delete mode 100644 include/configs/cm_t43.h

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 58e545a45b4..438cbb30419 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -185,7 +185,6 @@ source "board/ti/ti816x/Kconfig" source "board/ti/am43xx/Kconfig" source "board/ti/am335x/Kconfig" source "board/compulab/cm_t335/Kconfig" -source "board/compulab/cm_t43/Kconfig"

config SPL_LDSCRIPT default "arch/arm/mach-omap2/u-boot-spl.lds" diff --git a/board/compulab/cm_t43/Kconfig b/board/compulab/cm_t43/Kconfig deleted file mode 100644 index a19188975ec..00000000000 --- a/board/compulab/cm_t43/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_CM_T43 - -config SYS_BOARD - default "cm_t43" - -config SYS_VENDOR - default "compulab" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "cm_t43" - -endif diff --git a/board/compulab/cm_t43/MAINTAINERS b/board/compulab/cm_t43/MAINTAINERS deleted file mode 100644 index 951c370dd71..00000000000 --- a/board/compulab/cm_t43/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CM_T43 BOARD -M: Nikita Kiryanov nikita@compulab.co.il -S: Maintained -F: board/compulab/cm_t43/ -F: include/configs/cm_t43.h -F: configs/cm_t43_defconfig diff --git a/board/compulab/cm_t43/Makefile b/board/compulab/cm_t43/Makefile deleted file mode 100644 index 6fa231a045e..00000000000 --- a/board/compulab/cm_t43/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Makefile -# -# Copyright (C) 2015 Compulab, Ltd. - -ifdef CONFIG_SPL_BUILD -obj-y += spl.o mux.o -else -obj-y += cm_t43.o mux.o -endif diff --git a/board/compulab/cm_t43/board.h b/board/compulab/cm_t43/board.h deleted file mode 100644 index fcacd2bc0f8..00000000000 --- a/board/compulab/cm_t43/board.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Compulab, Ltd. - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ -void set_i2c_pin_mux(void); -void set_mdio_pin_mux(void); -void set_rgmii_pin_mux(void); -#endif diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c deleted file mode 100644 index 2aa453471d9..00000000000 --- a/board/compulab/cm_t43/cm_t43.c +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Compulab, Ltd. - */ - -#include <common.h> -#include <i2c.h> -#include <miiphy.h> -#include <cpsw.h> -#include <asm/gpio.h> -#include <asm/arch/sys_proto.h> -#include <asm/emif.h> -#include <power/pmic.h> -#include <power/tps65218.h> -#include "board.h" -#include <usb.h> -#include <asm/omap_common.h> - -DECLARE_GLOBAL_DATA_PTR; - -static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - -/* setup board specific PMIC */ -int power_init_board(void) -{ - struct pmic *p; - uchar tps_status = 0; - - power_tps65218_init(I2C_PMIC); - p = pmic_get("TPS65218_PMIC"); - if (p && !pmic_probe(p)) { - puts("PMIC: TPS65218\n"); - /* We don't care if fseal is locked, but we do need it set */ - tps65218_lock_fseal(); - tps65218_reg_read(TPS65218_STATUS, &tps_status); - if (!(tps_status & TPS65218_FSEAL)) - printf("WARNING: RTC not backed by battery!\n"); - } - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - gpmc_init(); - set_i2c_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - i2c_probe(TPS65218_CHIP_PM); - - return 0; -} - -int board_usb_init(int index, enum usb_init_type init) -{ - enable_usb_clocks(index); - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - disable_usb_clocks(index); - return 0; -} - -#ifdef CONFIG_DRIVER_TI_CPSW - -static void cpsw_control(int enabled) -{ - return; -} - -static struct cpsw_slave_data cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - .phy_if = PHY_INTERFACE_MODE_RGMII, - }, - { - .slave_reg_ofs = 0x308, - .sliver_reg_ofs = 0xdc0, - .phy_addr = 1, - .phy_if = PHY_INTERFACE_MODE_RGMII, - }, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 2, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; - -#define GPIO_PHY1_RST 170 -#define GPIO_PHY2_RST 168 - -int board_phy_config(struct phy_device *phydev) -{ - unsigned short val; - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} - -static void board_phy_init(void) -{ - set_mdio_pin_mux(); - writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */ - writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */ - writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */ - - /* For revision A */ - writel(0x2000009, 0x44df2e6c); - writel(0x38a, 0x44df2e70); - - mdelay(10); - - gpio_request(GPIO_PHY1_RST, "phy1_rst"); - gpio_request(GPIO_PHY2_RST, "phy2_rst"); - gpio_direction_output(GPIO_PHY1_RST, 0); - gpio_direction_output(GPIO_PHY2_RST, 0); - mdelay(2); - - gpio_set_value(GPIO_PHY1_RST, 1); - gpio_set_value(GPIO_PHY2_RST, 1); - mdelay(2); -} - -int board_eth_init(bd_t *bis) -{ - int rv; - - set_rgmii_pin_mux(); - writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); - board_phy_init(); - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - - return rv; -} -#endif diff --git a/board/compulab/cm_t43/mux.c b/board/compulab/cm_t43/mux.c deleted file mode 100644 index 778ea05e84c..00000000000 --- a/board/compulab/cm_t43/mux.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Compulab, Ltd. - */ - -#include <common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mux.h> -#include "board.h" - -static struct module_pin_mux rgmii1_pin_mux[] = { - {OFFSET(mii1_txen), MODE(2)}, - {OFFSET(mii1_txd3), MODE(2)}, - {OFFSET(mii1_txd2), MODE(2)}, - {OFFSET(mii1_txd1), MODE(2)}, - {OFFSET(mii1_txd0), MODE(2)}, - {OFFSET(mii1_txclk), MODE(2)}, - {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE | PULLDOWN_EN}, - {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE | PULLDOWN_EN}, - {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE | PULLDOWN_EN}, - {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE | PULLDOWN_EN}, - {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE | PULLDOWN_EN}, - {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE | PULLDOWN_EN}, - {-1}, -}; - -static struct module_pin_mux rgmii2_pin_mux[] = { - {OFFSET(gpmc_a0), MODE(2)}, /* txen */ - {OFFSET(gpmc_a2), MODE(2)}, /* txd3 */ - {OFFSET(gpmc_a3), MODE(2)}, /* txd2 */ - {OFFSET(gpmc_a4), MODE(2)}, /* txd1 */ - {OFFSET(gpmc_a5), MODE(2)}, /* txd0 */ - {OFFSET(gpmc_a6), MODE(2)}, /* txclk */ - {OFFSET(gpmc_a1), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxvd */ - {OFFSET(gpmc_a7), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxclk */ - {OFFSET(gpmc_a8), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd3 */ - {OFFSET(gpmc_a9), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd2 */ - {OFFSET(gpmc_a10), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd1 */ - {OFFSET(gpmc_a11), MODE(2) | RXACTIVE | PULLUP_EN}, /* rxd0 */ - {-1}, -}; - -static struct module_pin_mux mdio_pin_mux[] = { - {OFFSET(mdio_data), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, - {-1}, -}; - -static struct module_pin_mux uart0_pin_mux[] = { - {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, - {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, - {-1}, -}; - -static struct module_pin_mux mmc0_pin_mux[] = { - {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, - {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {-1}, -}; - -static struct module_pin_mux i2c_pin_mux[] = { - {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, - {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, - {OFFSET(spi2_sclk), (MODE(1) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, - {OFFSET(spi2_cs0), (MODE(1) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, - {-1}, -}; - -static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, - {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, - {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, - {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, - {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, - {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, - {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, - {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, - {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(gpmc_wpn), (MODE(0) | PULLUP_EN)}, - {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, - {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, - {-1}, -}; - -static struct module_pin_mux emmc_pin_mux[] = { - {OFFSET(gpmc_csn1), (MODE(2) | PULLUDDIS | RXACTIVE)}, /* EMMC_CLK */ - {OFFSET(gpmc_csn2), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_CMD */ - {OFFSET(gpmc_ad8), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT0 */ - {OFFSET(gpmc_ad9), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT1 */ - {OFFSET(gpmc_ad10), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT2 */ - {OFFSET(gpmc_ad11), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT3 */ - {OFFSET(gpmc_ad12), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT4 */ - {OFFSET(gpmc_ad13), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT5 */ - {OFFSET(gpmc_ad14), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT6 */ - {OFFSET(gpmc_ad15), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT7 */ - {-1}, -}; - -static struct module_pin_mux spi_flash_pin_mux[] = { - {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN)}, - {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, - {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN)}, - {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, - {-1}, -}; - -void set_uart_mux_conf(void) -{ - configure_module_pin_mux(uart0_pin_mux); -} - -void set_mdio_pin_mux(void) -{ - configure_module_pin_mux(mdio_pin_mux); -} - -void set_rgmii_pin_mux(void) -{ - configure_module_pin_mux(rgmii1_pin_mux); - configure_module_pin_mux(rgmii2_pin_mux); -} - -void set_mux_conf_regs(void) -{ - configure_module_pin_mux(mmc0_pin_mux); - configure_module_pin_mux(emmc_pin_mux); - configure_module_pin_mux(i2c_pin_mux); - configure_module_pin_mux(spi_flash_pin_mux); - configure_module_pin_mux(nand_pin_mux); -} - -void set_i2c_pin_mux(void) -{ - configure_module_pin_mux(i2c_pin_mux); -} diff --git a/board/compulab/cm_t43/spl.c b/board/compulab/cm_t43/spl.c deleted file mode 100644 index 7da9a9ad86b..00000000000 --- a/board/compulab/cm_t43/spl.c +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Compulab, Ltd. - */ - -#include <common.h> -#include <spl.h> -#include <i2c.h> -#include <asm/arch/clock.h> -#include <asm/arch/ddr_defs.h> -#include <asm/gpio.h> -#include <power/pmic.h> -#include <power/tps65218.h> -#include "board.h" - -const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 }; -const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 }; -const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 }; -const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 }; - -const struct ctrl_ioregs ioregs_ddr3 = { - .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, - .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, - .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, - .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, - .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, - .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, - .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, - .emif_sdram_config_ext = 0x0143, -}; - -/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ -struct emif_regs ddr3_emif_regs = { - .sdram_config = 0x638413B2, - .ref_ctrl = 0x00000C30, - .sdram_tim1 = 0xEAAAD4DB, - .sdram_tim2 = 0x266B7FDA, - .sdram_tim3 = 0x107F8678, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x50074BE4, - .temp_alert_config = 0x0, - .emif_ddr_phy_ctlr_1 = 0x0E004008, - .emif_ddr_ext_phy_ctrl_1 = 0x08020080, - .emif_ddr_ext_phy_ctrl_2 = 0x00000066, - .emif_ddr_ext_phy_ctrl_3 = 0x00000091, - .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, - .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, - .emif_rd_wr_exec_thresh = 0x80000405, - .emif_prio_class_serv_map = 0x80000001, - .emif_connect_id_serv_1_map = 0x80000094, - .emif_connect_id_serv_2_map = 0x00000000, - .emif_cos_config = 0x000FFFFF -}; - -const u32 ext_phy_ctrl_const_base_ddr3[] = { - 0x00000000, - 0x00000044, - 0x00000044, - 0x00000046, - 0x00000046, - 0x00000000, - 0x00000059, - 0x00000077, - 0x00000093, - 0x000000A8, - 0x00000000, - 0x00000019, - 0x00000037, - 0x00000053, - 0x00000068, - 0x00000000, - 0x0, - 0x0, - 0x40000000, - 0x08102040 -}; - -void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) -{ - *regs = ext_phy_ctrl_const_base_ddr3; - *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); -} - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr; -} - -const struct dpll_params *get_dpll_mpu_params(void) -{ - return &dpll_mpu; -} - -const struct dpll_params *get_dpll_core_params(void) -{ - return &dpll_core; -} - -const struct dpll_params *get_dpll_per_params(void) -{ - return &dpll_per; -} - -void scale_vcores(void) -{ - set_i2c_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - if (i2c_probe(TPS65218_CHIP_PM)) - return; - - tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV); - tps65218_voltage_update(TPS65218_DCDC2, TPS65218_DCDC_VOLT_SEL_1100MV); -} - -void sdram_init(void) -{ - unsigned long ram_size; - - config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); - ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (ram_size == 0x80000000 || - ram_size == 0x40000000 || - ram_size == 0x20000000) - return; - - ddr3_emif_regs.sdram_config = 0x638453B2; - config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); - ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (ram_size == 0x08000000) - return; - - hang(); -} - diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig deleted file mode 100644 index eb4a8f5a330..00000000000 --- a/configs/cm_t43_defconfig +++ /dev/null @@ -1,72 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_AM43XX=y -CONFIG_TARGET_CM_T43=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_MISC_INIT_R is not set -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480 -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MTD_SUPPORT=y -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_PROMPT="CM-T43 # " -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_EEPROM_LAYOUT=y -CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_NFS is not set -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_DM=y -CONFIG_DM_GPIO=y -CONFIG_MMC_OMAP_HS=y -CONFIG_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_MII=y -CONFIG_DM_SERIAL=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_OMAP_USB_PHY=y -CONFIG_USB_STORAGE=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h deleted file mode 100644 index 79eb865bf9c..00000000000 --- a/include/configs/cm_t43.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * cm_t43.h - * - * Copyright (C) 2015 Compulab, Ltd. - */ - -#ifndef __CONFIG_CM_T43_H -#define __CONFIG_CM_T43_H - -#define CONFIG_CM_T43 -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ - -#include <asm/arch/omap.h> - -/* Serial support */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 48000000 -#define CONFIG_SYS_NS16550_COM1 0x44e09000 -#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif - -/* NAND support */ -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -/* CPSW Ethernet support */ -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_PHY_ATHEROS -#define CONFIG_SYS_RX_ETH_BUFFER 64 - -/* USB support */ -#define CONFIG_USB_XHCI_OMAP -#define CONFIG_AM437X_USB2PHY2_HOST - -/* SPI Flash support */ -#define CONFIG_TI_SPI_MMAP -#define CONFIG_SF_DEFAULT_SPEED 48000000 -#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 - -/* Power */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_TPS65218 - -/* Enabling L2 Cache */ -#define CONFIG_SYS_L2_PL310 -#define CONFIG_SYS_PL310_BASE 0x48242000 - -/* - * Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -#define CONFIG_HSMMC2_8BIT - -#include <configs/ti_armv7_omap.h> -#undef CONFIG_SYS_MONITOR_LEN - -#define CONFIG_ENV_SIZE (16 * 1024) - -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_OFFSET (768 * 1024) -#define CONFIG_ENV_SPI_MAX_HZ 48000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "fdtaddr=0x81200000\0" \ - "bootm_size=0x8000000\0" \ - "autoload=no\0" \ - "console=ttyO0,115200n8\0" \ - "fdtfile=am437x-sb-som-t43.dtb\0" \ - "kernel=zImage-cm-t43\0" \ - "bootscr=bootscr.img\0" \ - "emmcroot=/dev/mmcblk0p2 rw\0" \ - "emmcrootfstype=ext4 rootwait\0" \ - "emmcargs=setenv bootargs console=${console} " \ - "root=${emmcroot} " \ - "rootfstype=${emmcrootfstype}\0" \ - "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "emmcboot=echo Booting from emmc ... && " \ - "run emmcargs && " \ - "load mmc 1 ${loadaddr} ${kernel} && " \ - "load mmc 1 ${fdtaddr} ${fdtfile} && " \ - "bootz ${loadaddr} - ${fdtaddr}\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev 0; " \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "fi; " \ - "fi; " \ - "mmc dev 1; " \ - "if mmc rescan; then " \ - "run emmcboot; " \ - "fi;" - -/* SPL defines. */ -#define CONFIG_SPL_TEXT_BASE 0x40300350 -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) -#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -/* EEPROM */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 - -#endif /* __CONFIG_CM_T43_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-omap2/omap3/Kconfig | 1 - board/isee/igep00x0/Kconfig | 12 -- board/isee/igep00x0/MAINTAINERS | 7 - board/isee/igep00x0/Makefile | 10 -- board/isee/igep00x0/common.c | 67 -------- board/isee/igep00x0/igep00x0.c | 258 ------------------------------ board/isee/igep00x0/igep00x0.h | 127 --------------- board/isee/igep00x0/spl.c | 63 -------- configs/igep0032_defconfig | 52 ------ configs/igep00x0_defconfig | 53 ------ include/configs/omap3_igep00x0.h | 135 ---------------- 11 files changed, 785 deletions(-) delete mode 100644 board/isee/igep00x0/Kconfig delete mode 100644 board/isee/igep00x0/MAINTAINERS delete mode 100644 board/isee/igep00x0/Makefile delete mode 100644 board/isee/igep00x0/common.c delete mode 100644 board/isee/igep00x0/igep00x0.c delete mode 100644 board/isee/igep00x0/igep00x0.h delete mode 100644 board/isee/igep00x0/spl.c delete mode 100644 configs/igep0032_defconfig delete mode 100644 configs/igep00x0_defconfig delete mode 100644 include/configs/omap3_igep00x0.h

diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index 04b6ffe574a..9bd07dd8c55 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -200,7 +200,6 @@ source "board/compulab/cm_t35/Kconfig" source "board/compulab/cm_t3517/Kconfig" source "board/timll/devkit8000/Kconfig" source "board/ti/evm/Kconfig" -source "board/isee/igep00x0/Kconfig" source "board/overo/Kconfig" source "board/ti/am3517crane/Kconfig" source "board/pandora/Kconfig" diff --git a/board/isee/igep00x0/Kconfig b/board/isee/igep00x0/Kconfig deleted file mode 100644 index aa46882b051..00000000000 --- a/board/isee/igep00x0/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_OMAP3_IGEP00X0 - -config SYS_BOARD - default "igep00x0" - -config SYS_VENDOR - default "isee" - -config SYS_CONFIG_NAME - default "omap3_igep00x0" - -endif diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS deleted file mode 100644 index d75d400eed0..00000000000 --- a/board/isee/igep00x0/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -IGEP00X0 BOARD -M: Enric Balletbo i Serra eballetbo@gmail.com -S: Maintained -F: board/isee/igep00x0/ -F: include/configs/omap3_igep00x0.h -F: configs/igep00x0_defconfig -F: configs/igep0032_defconfig diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile deleted file mode 100644 index e095bcada29..00000000000 --- a/board/isee/igep00x0/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifdef CONFIG_SPL_BUILD -obj-y := spl.o common.o -else -obj-y := igep00x0.o common.o -endif diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c deleted file mode 100644 index f5d62ffc2e5..00000000000 --- a/board/isee/igep00x0/common.c +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include <common.h> -#include <twl4030.h> -#include <asm/io.h> -#include <asm/omap_mmc.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <jffs2/load_kernel.h> -#include <linux/mtd/rawnand.h> -#include "igep00x0.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -} - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - int loops = 100; - - /* find out flash memory type, assume NAND first */ - gpmc_cs0_flash = MTD_DEV_TYPE_NAND; - gpmc_init(); - - /* Issue a RESET and then READID */ - writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); - writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); - while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) - != NAND_STATUS_READY) { - udelay(1); - if (--loops == 0) { - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; - gpmc_init(); /* reinitialize for OneNAND */ - break; - } - } - - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -#if defined(CONFIG_MMC) -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} - -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c deleted file mode 100644 index 367af82d4a1..00000000000 --- a/board/isee/igep00x0/igep00x0.c +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * ISEE 2007 SL, <www.iseebcn.com> - */ -#include <common.h> -#include <status_led.h> -#include <dm.h> -#include <ns16550.h> -#include <twl4030.h> -#include <netdev.h> -#include <spl.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/rawnand.h> -#include <linux/mtd/onenand.h> -#include <jffs2/load_kernel.h> -#include <mtd_node.h> -#include <fdt_support.h> -#include "igep00x0.h" - -static const struct ns16550_platdata igep_serial = { - .base = OMAP34XX_UART3, - .reg_shift = 2, - .clock = V_NS16550_CLK, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DEVICE(igep_uart) = { - "ns16550_serial", - &igep_serial -}; - -/* - * Routine: get_board_revision - * Description: GPIO_28 and GPIO_129 are used to read board and revision from - * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from - * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because - * this functionality is shared by USB HOST. - * Once USB reset is applied, U-boot configures these pins as input pullup to - * detect board and revision: - * IGEP0020-RF = 0b00 - * IGEP0020-RC = 0b01 - * IGEP0030-RG = 0b10 - * IGEP0030-RE = 0b11 - */ -static int get_board_revision(void) -{ - int revision; - - gpio_request(IGEP0030_USB_TRANSCEIVER_RESET, - "igep0030_usb_transceiver_reset"); - gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0); - - gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection"); - gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION); - revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION); - gpio_free(GPIO_IGEP00X0_BOARD_DETECTION); - - gpio_request(GPIO_IGEP00X0_REVISION_DETECTION, - "igep00x0_revision_detection"); - gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION); - revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION); - gpio_free(GPIO_IGEP00X0_REVISION_DETECTION); - - gpio_free(IGEP0030_USB_TRANSCEIVER_RESET); - - return revision; -} - -int onenand_board_init(struct mtd_info *mtd) -{ - if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) { - struct onenand_chip *this = mtd->priv; - this->base = (void *)CONFIG_SYS_ONENAND_BASE; - return 0; - } - return 1; -} - -#if defined(CONFIG_CMD_NET) -static void reset_net_chip(int gpio) -{ - if (!gpio_request(gpio, "eth nrst")) { - gpio_direction_output(gpio, 1); - udelay(1); - gpio_set_value(gpio, 0); - udelay(40); - gpio_set_value(gpio, 1); - mdelay(10); - } -} - -/* - * Routine: setup_net_chip - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -static void setup_net_chip(void) -{ - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - static const u32 gpmc_lan_config[] = { - NET_LAN9221_GPMC_CONFIG1, - NET_LAN9221_GPMC_CONFIG2, - NET_LAN9221_GPMC_CONFIG3, - NET_LAN9221_GPMC_CONFIG4, - NET_LAN9221_GPMC_CONFIG5, - NET_LAN9221_GPMC_CONFIG6, - }; - - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], - CONFIG_SMC911X_BASE, GPMC_SIZE_16M); - - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ - writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, - &ctrl_base->gpmc_nadv_ale); - - reset_net_chip(64); -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_SMC911X - return smc911x_initialize(0, CONFIG_SMC911X_BASE); -#else - return 0; -#endif -} -#else -static inline void setup_net_chip(void) {} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -static int ft_enable_by_compatible(void *blob, char *compat, int enable) -{ - int off = fdt_node_offset_by_compatible(blob, -1, compat); - if (off < 0) - return off; - - if (enable) - fdt_status_okay(blob, off); - else - fdt_status_disabled(blob, off); - - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ -#ifdef CONFIG_FDT_FIXUP_PARTITIONS - static const struct node_info nodes[] = { - { "ti,omap2-nand", MTD_DEV_TYPE_NAND, }, - { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, }, - }; - - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); -#endif - ft_enable_by_compatible(blob, "ti,omap2-nand", - gpmc_cs0_flash == MTD_DEV_TYPE_NAND); - ft_enable_by_compatible(blob, "ti,omap2-onenand", - gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND); - - return 0; -} -#endif - -void set_led(void) -{ - switch (get_board_revision()) { - case 0: - case 1: - gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led"); - gpio_direction_output(IGEP0020_GPIO_LED, 1); - break; - case 2: - case 3: - gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led"); - gpio_direction_output(IGEP0030_GPIO_LED, 0); - break; - default: - /* Should not happen... */ - break; - } -} - -void set_boardname(void) -{ - char rev[5] = { 'F','C','G','E', }; - int i = get_board_revision(); - - rev[i+1] = 0; - env_set("board_rev", rev + i); - env_set("board_name", i < 2 ? "igep0020" : "igep0030"); -} - -/* - * Routine: misc_init_r - * Description: Configure board specific parts - */ -int misc_init_r(void) -{ - t2_t *t2_base = (t2_t *)T2_BASE; - u32 pbias_lite; - - twl4030_power_init(); - - /* set VSIM to 1.8V */ - twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED, - TWL4030_PM_RECEIVER_VSIM_VSEL_18, - TWL4030_PM_RECEIVER_VSIM_DEV_GRP, - TWL4030_PM_RECEIVER_DEV_GRP_P1); - - /* set up dual-voltage GPIOs to 1.8V */ - pbias_lite = readl(&t2_base->pbias_lite); - pbias_lite &= ~PBIASLITEVMODE1; - pbias_lite |= PBIASLITEPWRDNZ1; - writel(pbias_lite, &t2_base->pbias_lite); - if (get_cpu_family() == CPU_OMAP36XX) - writel(readl(OMAP34XX_CTRL_WKUP_CTRL) | - OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, - OMAP34XX_CTRL_WKUP_CTRL); - - setup_net_chip(); - - omap_die_id_display(); - - set_led(); - - set_boardname(); - - return 0; -} - -void board_mtdparts_default(const char **mtdids, const char **mtdparts) -{ - struct mtd_info *mtd = get_mtd_device(NULL, 0); - if (mtd) { - static char ids[24]; - static char parts[48]; - const char *linux_name = "omap2-nand"; - if (strncmp(mtd->name, "onenand0", 8) == 0) - linux_name = "omap2-onenand"; - snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name); - snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)", - linux_name, 4 * mtd->erasesize >> 10); - *mtdids = ids; - *mtdparts = parts; - } -} diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h deleted file mode 100644 index aa532acad95..00000000000 --- a/board/isee/igep00x0/igep00x0.h +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * ISEE 2007 SL, <www.iseebcn.com> - */ -#ifndef _IGEP00X0_H_ -#define _IGEP00X0_H_ - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\ - MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54 */\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\ - MUX_VAL(CP(GPIO129), (IEN | PTU | EN | M4)) /* GPIO_129 */\ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */ -#endif diff --git a/board/isee/igep00x0/spl.c b/board/isee/igep00x0/spl.c deleted file mode 100644 index e092e1a418b..00000000000 --- a/board/isee/igep00x0/spl.c +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/sys_proto.h> -#include <jffs2/load_kernel.h> -#include <linux/mtd/rawnand.h> -#include "igep00x0.h" - -/* - * Routine: get_board_mem_timings - * Description: If we use SPL then there is no x-loader nor config header - * so we have to setup the DDR timings ourself on both banks. - */ -void get_board_mem_timings(struct board_sdrc_timings *timings) -{ - int mfr, id, err = identify_nand_chip(&mfr, &id); - - timings->mr = MICRON_V_MR_165; - if (!err) { - switch (mfr) { - case NAND_MFR_HYNIX: - timings->mcfg = HYNIX_V_MCFG_200(256 << 20); - timings->ctrla = HYNIX_V_ACTIMA_200; - timings->ctrlb = HYNIX_V_ACTIMB_200; - break; - case NAND_MFR_MICRON: - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - break; - default: - /* Should not happen... */ - break; - } - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - gpmc_cs0_flash = MTD_DEV_TYPE_NAND; - } else { - if (get_cpu_family() == CPU_OMAP34XX) { - timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_165; - timings->ctrlb = NUMONYX_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - } else { - timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_200; - timings->ctrlb = NUMONYX_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - } - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; - } -} - -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - /* break into full u-boot on 'c' */ - if (serial_tstc() && serial_getc() == 'c') - return 1; - - return 0; -} -#endif diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig deleted file mode 100644 index 383648789c5..00000000000 --- a/configs/igep0032_defconfig +++ /dev/null @@ -1,52 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_TARGET_OMAP3_IGEP00X0=y -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=3 -CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_SPL_EXT_SUPPORT is not set -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_ONENAND_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_CMD_SPL=y -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_ONENAND=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_MMC_OMAP_HS=y -CONFIG_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x2C000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_CONS_INDEX=3 -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_MUSB_UDC=y -CONFIG_USB_OMAP3=y -CONFIG_TWL4030_USB=y -CONFIG_FAT_WRITE=y -CONFIG_UBIFS_SILENCE_MSG=y -CONFIG_BCH=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig deleted file mode 100644 index f2989e34e12..00000000000 --- a/configs/igep00x0_defconfig +++ /dev/null @@ -1,53 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_TARGET_OMAP3_IGEP00X0=y -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=3 -CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_SPL_EXT_SUPPORT is not set -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_ONENAND_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_CMD_SPL=y -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_ONENAND=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_MMC_OMAP_HS=y -CONFIG_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x2C000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_CONS_INDEX=3 -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_MUSB_UDC=y -CONFIG_USB_OMAP3=y -CONFIG_TWL4030_USB=y -CONFIG_FAT_WRITE=y -CONFIG_UBIFS_SILENCE_MSG=y -CONFIG_BCH=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h deleted file mode 100644 index b9d65697521..00000000000 --- a/include/configs/omap3_igep00x0.h +++ /dev/null @@ -1,135 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Common configuration settings for IGEP technology based boards - * - * (C) Copyright 2012 - * ISEE 2007 SL, <www.iseebcn.com> - */ - -#ifndef __IGEP00X0_H -#define __IGEP00X0_H - -#include <configs/ti_omap3_common.h> - -/* - * We are only ever GP parts and will utilize all of the "downloaded image" - * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). - */ -#undef CONFIG_SPL_TEXT_BASE -#define CONFIG_SPL_TEXT_BASE 0x40200000 - -#define CONFIG_REVISION_TAG 1 - -/* GPIO banks */ -#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */ -#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */ - -/* TPS65950 */ -#define PBIASLITEVMODE1 (1 << 8) - -/* LED */ -#define IGEP0020_GPIO_LED 27 -#define IGEP0030_GPIO_LED 16 - -/* Board and revision detection GPIOs */ -#define IGEP0030_USB_TRANSCEIVER_RESET 54 -#define GPIO_IGEP00X0_BOARD_DETECTION 28 -#define GPIO_IGEP00X0_REVISION_DETECTION 129 - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 - -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "IGEP" - -#ifndef CONFIG_SPL_BUILD - -/* Environment */ -#define ENV_DEVICE_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define MEM_LAYOUT_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "scriptaddr=0x87E00000\0" \ - "pxefile_addr_r=0x87F00000\0" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) - -#include <config_distro_bootcmd.h> - -#define ENV_FINDFDT \ - "findfdt="\ - "if test ${board_name} = igep0020; then " \ - "if test ${board_rev} = F; then " \ - "setenv fdtfile omap3-igep0020-rev-f.dtb; " \ - "else " \ - "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \ - "if test ${board_name} = igep0030; then " \ - "if test ${board_rev} = G; then " \ - "setenv fdtfile omap3-igep0030-rev-g.dtb; " \ - "else " \ - "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \ - "if test ${fdtfile} = ''; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - ENV_FINDFDT \ - ENV_DEVICE_SETTINGS \ - MEM_LAYOUT_SETTINGS \ - BOOTENV - -#endif - -#define CONFIG_SYS_MTDPARTS_RUNTIME - -/* OneNAND config */ -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) - -/* NAND config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW - -/* UBI configuration */ -#define CONFIG_SPL_UBI 1 -#define CONFIG_SPL_UBI_MAX_VOL_LEBS 256 -#define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024) -#define CONFIG_SPL_UBI_MAX_PEBS 4096 -#define CONFIG_SPL_UBI_VOL_IDS 8 -#define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0 -#define CONFIG_SPL_UBI_LOAD_KERNEL_ID 3 -#define CONFIG_SPL_UBI_LOAD_ARGS_ID 4 -#define CONFIG_SPL_UBI_PEB_OFFSET 4 -#define CONFIG_SPL_UBI_VID_OFFSET 512 -#define CONFIG_SPL_UBI_LEB_START 2048 -#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000 - -/* environment organization */ -#define CONFIG_ENV_UBI_PART "UBI" -#define CONFIG_ENV_UBI_VOLUME "config" -#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r" -#define CONFIG_ENV_SIZE (32*1024) - -#endif /* __IGEP00X0_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-omap2/omap3/Kconfig | 1 - board/overo/Kconfig | 9 - board/overo/MAINTAINERS | 6 - board/overo/Makefile | 10 - board/overo/common.c | 341 ------------------------ board/overo/overo.c | 420 ------------------------------ board/overo/overo.h | 169 ------------ board/overo/spl.c | 59 ----- configs/omap3_overo_defconfig | 51 ---- include/configs/omap3_overo.h | 192 -------------- 10 files changed, 1258 deletions(-) delete mode 100644 board/overo/Kconfig delete mode 100644 board/overo/MAINTAINERS delete mode 100644 board/overo/Makefile delete mode 100644 board/overo/common.c delete mode 100644 board/overo/overo.c delete mode 100644 board/overo/overo.h delete mode 100644 board/overo/spl.c delete mode 100644 configs/omap3_overo_defconfig delete mode 100644 include/configs/omap3_overo.h

diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index 9bd07dd8c55..4e8be5f9d04 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -200,7 +200,6 @@ source "board/compulab/cm_t35/Kconfig" source "board/compulab/cm_t3517/Kconfig" source "board/timll/devkit8000/Kconfig" source "board/ti/evm/Kconfig" -source "board/overo/Kconfig" source "board/ti/am3517crane/Kconfig" source "board/pandora/Kconfig" source "board/8dtech/eco5pk/Kconfig" diff --git a/board/overo/Kconfig b/board/overo/Kconfig deleted file mode 100644 index 74572a62be6..00000000000 --- a/board/overo/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_OMAP3_OVERO - -config SYS_BOARD - default "overo" - -config SYS_CONFIG_NAME - default "omap3_overo" - -endif diff --git a/board/overo/MAINTAINERS b/board/overo/MAINTAINERS deleted file mode 100644 index 8f089e87f8b..00000000000 --- a/board/overo/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -OVERO BOARD -M: Steve Sakoman sakoman@gmail.com -S: Maintained -F: board/overo/ -F: include/configs/omap3_overo.h -F: configs/omap3_overo_defconfig diff --git a/board/overo/Makefile b/board/overo/Makefile deleted file mode 100644 index b62bab9fe4f..00000000000 --- a/board/overo/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifdef CONFIG_SPL_BUILD -obj-y := spl.o common.o -else -obj-y := overo.o common.o -endif diff --git a/board/overo/common.c b/board/overo/common.c deleted file mode 100644 index fc02d66d531..00000000000 --- a/board/overo/common.c +++ /dev/null @@ -1,341 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Maintainer : Steve Sakoman steve@sakoman.com - * - * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by - * Richard Woodruff r-woodruff2@ti.com - * Syed Mohammed Khasim khasim@ti.com - * Sunil Kumar sunilsaini05@gmail.com - * Shashi Ranjan shashiranjanmca05@gmail.com - * - * (C) Copyright 2004-2008 - * Texas Instruments, <www.ti.com> - */ -#include <twl4030.h> -#include <common.h> -#include <asm/io.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/mach-types.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define TWL4030_I2C_BUS 0 - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_OVERO; - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -#define MUX_OVERO() \ - /*SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - /*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\ - /* - MMC1_WP*/\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - /*CAMERA*/\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M0)) /*CAM_HS */\ - MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M0)) /*CAM_VS */\ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M0)) /*CAM_PCLK*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\ - /*Audio Interface */\ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ - /*Expansion card */\ - MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) /*MMC1_CLK*/\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ - /*Wireless LAN */\ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ - MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\ - MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ - /*Bluetooth*/\ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\ - MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\ - MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\ - MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\ - MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\ - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*McBSP1_CLKR*/\ - MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /*McBSP1_FSR*/\ - MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M0)) /*McBSP1_DX*/\ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*McBSP1_DR*/\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\ - /*Serial Interface*/\ - MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\ - /* BT_NRESET*/\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\ - /* - USBH_CPEN*/\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\ - /* - USBH_RESET*/\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA5*/\ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA6*/\ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA3*/\ - /*Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\ - /* - W2W_NRESET*/\ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/\ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/\ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/\ - /* die to die */\ - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ - -/* - * Routine: get_board_revision - * Description: Returns the board revision - */ -int get_board_revision(void) -{ - int revision; - - if (!gpio_request(112, "") && - !gpio_request(113, "") && - !gpio_request(115, "")) { - - gpio_direction_input(112); - gpio_direction_input(113); - gpio_direction_input(115); - - revision = gpio_get_value(115) << 2 | - gpio_get_value(113) << 1 | - gpio_get_value(112); - } else { - puts("Error: unable to acquire board revision GPIOs\n"); - revision = -1; - } - - return revision; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_OVERO(); -} diff --git a/board/overo/overo.c b/board/overo/overo.c deleted file mode 100644 index 8fa41f81550..00000000000 --- a/board/overo/overo.c +++ /dev/null @@ -1,420 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Maintainer : Steve Sakoman steve@sakoman.com - * - * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by - * Richard Woodruff r-woodruff2@ti.com - * Syed Mohammed Khasim khasim@ti.com - * Sunil Kumar sunilsaini05@gmail.com - * Shashi Ranjan shashiranjanmca05@gmail.com - * - * (C) Copyright 2004-2008 - * Texas Instruments, <www.ti.com> - */ -#include <common.h> -#include <dm.h> -#include <ns16550.h> -#include <netdev.h> -#include <twl4030.h> -#include <linux/mtd/rawnand.h> -#include <asm/io.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/mux.h> -#include <asm/arch/mem.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/mach-types.h> -#include "overo.h" - -#ifdef CONFIG_USB_EHCI_HCD -#include <usb.h> -#include <asm/ehci-omap.h> -#endif - -#define TWL4030_I2C_BUS 0 -#define EXPANSION_EEPROM_I2C_BUS 2 -#define EXPANSION_EEPROM_I2C_ADDRESS 0x51 - -#define GUMSTIX_EMPTY_EEPROM 0x0 - -#define GUMSTIX_SUMMIT 0x01000200 -#define GUMSTIX_TOBI 0x02000200 -#define GUMSTIX_TOBI_DUO 0x03000200 -#define GUMSTIX_PALO35 0x04000200 -#define GUMSTIX_PALO43 0x05000200 -#define GUMSTIX_CHESTNUT43 0x06000200 -#define GUMSTIX_PINTO 0x07000200 -#define GUMSTIX_GALLOP43 0x08000200 -#define GUMSTIX_ALTO35 0x09000200 -#define GUMSTIX_STAGECOACH 0x0A000200 -#define GUMSTIX_THUMBO 0x0B000200 -#define GUMSTIX_TURTLECORE 0x0C000200 -#define GUMSTIX_ARBOR43C 0x0D000200 - -#define ETTUS_USRP_E 0x01000300 - -#define GUMSTIX_NO_EEPROM 0xffffffff - -static struct { - unsigned int device_vendor; - unsigned char revision; - unsigned char content; - char fab_revision[8]; - char env_var[16]; - char env_setting[64]; -} expansion_config = {0x0}; - -static const struct ns16550_platdata overo_serial = { - .base = OMAP34XX_UART3, - .reg_shift = 2, - .clock = V_NS16550_CLK, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DEVICE(overo_uart) = { - "ns16550_serial", - &overo_serial -}; - -/* - * Routine: get_sdio2_config - * Description: Return information about the wifi module connection - * Returns 0 if the module connects though a level translator - * Returns 1 if the module connects directly - */ -int get_sdio2_config(void) -{ - int sdio_direct; - - if (!gpio_request(130, "") && !gpio_request(139, "")) { - - gpio_direction_output(130, 0); - gpio_direction_input(139); - - sdio_direct = 1; - gpio_set_value(130, 0); - if (gpio_get_value(139) == 0) { - gpio_set_value(130, 1); - if (gpio_get_value(139) == 1) - sdio_direct = 0; - } - - gpio_direction_input(130); - } else { - puts("Error: unable to acquire sdio2 clk GPIOs\n"); - sdio_direct = -1; - } - - return sdio_direct; -} - -/* - * Routine: get_expansion_id - * Description: This function checks for expansion board by checking I2C - * bus 2 for the availability of an AT24C01B serial EEPROM. - * returns the device_vendor field from the EEPROM - */ -unsigned int get_expansion_id(void) -{ - if (expansion_config.device_vendor != 0x0) - return expansion_config.device_vendor; - - i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS); - - /* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */ - if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) { - i2c_set_bus_num(TWL4030_I2C_BUS); - return GUMSTIX_NO_EEPROM; - } - - /* read configuration data */ - i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config, - sizeof(expansion_config)); - - i2c_set_bus_num(TWL4030_I2C_BUS); - - return expansion_config.device_vendor; -} - -/* - * Routine: misc_init_r - * Description: Configure board specific parts - */ -int misc_init_r(void) -{ - unsigned int expansion_id; - - twl4030_power_init(); - twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); - - printf("Board revision: %d\n", get_board_revision()); - - switch (get_sdio2_config()) { - case 0: - puts("Tranceiver detected on mmc2\n"); - MUX_OVERO_SDIO2_TRANSCEIVER(); - break; - case 1: - puts("Direct connection on mmc2\n"); - MUX_OVERO_SDIO2_DIRECT(); - break; - default: - puts("Unable to detect mmc2 connection type\n"); - } - - expansion_id = get_expansion_id(); - switch (expansion_id) { - case GUMSTIX_SUMMIT: - printf("Recognized Summit expansion board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_GUMSTIX(); - env_set("defaultdisplay", "dvi"); - env_set("expansionname", "summit"); - break; - case GUMSTIX_TOBI: - printf("Recognized Tobi expansion board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_GUMSTIX(); - env_set("defaultdisplay", "dvi"); - env_set("expansionname", "tobi"); - break; - case GUMSTIX_TOBI_DUO: - printf("Recognized Tobi Duo expansion board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_GUMSTIX(); - env_set("expansionname", "tobiduo"); - break; - case GUMSTIX_PALO35: - printf("Recognized Palo35 expansion board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_GUMSTIX(); - env_set("defaultdisplay", "lcd35"); - env_set("expansionname", "palo35"); - break; - case GUMSTIX_PALO43: - printf("Recognized Palo43 expansion board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_GUMSTIX(); - env_set("defaultdisplay", "lcd43"); - env_set("expansionname", "palo43"); - break; - case GUMSTIX_CHESTNUT43: - printf("Recognized Chestnut43 expansion board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_GUMSTIX(); - env_set("defaultdisplay", "lcd43"); - env_set("expansionname", "chestnut43"); - break; - case GUMSTIX_PINTO: - printf("Recognized Pinto expansion board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_GUMSTIX(); - break; - case GUMSTIX_GALLOP43: - printf("Recognized Gallop43 expansion board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_GUMSTIX(); - env_set("defaultdisplay", "lcd43"); - env_set("expansionname", "gallop43"); - break; - case GUMSTIX_ALTO35: - printf("Recognized Alto35 expansion board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_GUMSTIX(); - MUX_ALTO35(); - env_set("defaultdisplay", "lcd35"); - env_set("expansionname", "alto35"); - break; - case GUMSTIX_STAGECOACH: - printf("Recognized Stagecoach expansion board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_GUMSTIX(); - break; - case GUMSTIX_THUMBO: - printf("Recognized Thumbo expansion board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_GUMSTIX(); - break; - case GUMSTIX_TURTLECORE: - printf("Recognized Turtlecore expansion board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_GUMSTIX(); - break; - case GUMSTIX_ARBOR43C: - printf("Recognized Arbor43C expansion board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_GUMSTIX(); - MUX_ARBOR43C(); - env_set("defaultdisplay", "lcd43"); - env_set("expansionname", "arbor43c"); - break; - case ETTUS_USRP_E: - printf("Recognized Ettus Research USRP-E (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_GUMSTIX(); - MUX_USRP_E(); - env_set("defaultdisplay", "dvi"); - break; - case GUMSTIX_NO_EEPROM: - case GUMSTIX_EMPTY_EEPROM: - puts("No or empty EEPROM on expansion board\n"); - MUX_GUMSTIX(); - env_set("expansionname", "tobi"); - break; - default: - printf("Unrecognized expansion board 0x%08x\n", expansion_id); - break; - } - - if (expansion_config.content == 1) - env_set(expansion_config.env_var, expansion_config.env_setting); - - omap_die_id_display(); - - if (get_cpu_family() == CPU_OMAP34XX) - env_set("boardname", "overo"); - else - env_set("boardname", "overo-storm"); - - return 0; -} - -#if defined(CONFIG_CMD_NET) -/* GPMC definitions for LAN9221 chips on Tobi expansion boards */ -static const u32 gpmc_lan_config[] = { - NET_LAN9221_GPMC_CONFIG1, - NET_LAN9221_GPMC_CONFIG2, - NET_LAN9221_GPMC_CONFIG3, - NET_LAN9221_GPMC_CONFIG4, - NET_LAN9221_GPMC_CONFIG5, - NET_LAN9221_GPMC_CONFIG6, - /*CONFIG7- computed as params */ -}; - -/* - * Routine: setup_net_chip - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -static void setup_net_chip(void) -{ - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ - writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, - &ctrl_base->gpmc_nadv_ale); -} - -/* - * Routine: reset_net_chip - * Description: Reset the Ethernet hardware. - */ -static void reset_net_chip(void) -{ - /* Make GPIO 64 as output pin and send a magic pulse through it */ - if (!gpio_request(64, "")) { - gpio_direction_output(64, 0); - gpio_set_value(64, 1); - udelay(1); - gpio_set_value(64, 0); - udelay(1); - gpio_set_value(64, 1); - } -} - -int board_eth_init(bd_t *bis) -{ - unsigned int expansion_id; - int rc = 0; - -#ifdef CONFIG_SMC911X - expansion_id = get_expansion_id(); - switch (expansion_id) { - case GUMSTIX_TOBI_DUO: - /* second lan chip */ - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], - 0x2B000000, GPMC_SIZE_16M); - /* no break */ - case GUMSTIX_TOBI: - case GUMSTIX_CHESTNUT43: - case GUMSTIX_STAGECOACH: - case GUMSTIX_NO_EEPROM: - case GUMSTIX_EMPTY_EEPROM: - /* first lan chip */ - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], - 0x2C000000, GPMC_SIZE_16M); - - setup_net_chip(); - reset_net_chip(); - - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); - break; - default: - break; - } -#endif - - return rc; -} -#endif - -#if defined(CONFIG_MMC) -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#if defined(CONFIG_MMC) -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif - -#if defined(CONFIG_USB_EHCI_HCD) -static struct omap_usbhs_board_data usbhs_bdata = { - .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED -}; - -#define GUMSTIX_GPIO_USBH_CPEN 168 -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - /* Enable USB power */ - if (!gpio_request(GUMSTIX_GPIO_USBH_CPEN, "usbh_cpen")) - gpio_direction_output(GUMSTIX_GPIO_USBH_CPEN, 1); - - return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); -} - -int ehci_hcd_stop(void) -{ - /* Disable USB power */ - gpio_set_value(GUMSTIX_GPIO_USBH_CPEN, 0); - gpio_free(GUMSTIX_GPIO_USBH_CPEN); - - return omap_ehci_hcd_stop(); -} - -#endif /* CONFIG_USB_EHCI_HCD */ diff --git a/board/overo/overo.h b/board/overo/overo.h deleted file mode 100644 index 513a3e3d632..00000000000 --- a/board/overo/overo.h +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 - * Steve Sakoman steve@sakoman.com - */ -#ifndef _OVERO_H_ -#define _OVERO_H_ - -const omap3_sysinfo sysinfo = { - DDR_STACKED, - "Gumstix Overo board", -#if defined(CONFIG_ENV_IS_IN_ONENAND) - "OneNAND", -#else - "NAND", -#endif -}; - -int get_board_revision(void); - -/* overo revisions */ -#define REVISION_0 0x0 -#define REVISION_1 0x1 -#define REVISION_2 0x2 -#define REVISION_3 0x3 -#define REVISION_4 0x4 - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_GUMSTIX() \ - /*GPMC*/\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) /*GPIO_63*/\ - /* - CAM_IRQ*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ - /* - SMSC911X_NRES*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\ - /*DSS*/\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ - /*CAMERA*/\ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\ - /* - PEN_DOWN*/\ - /*Bluetooth*/\ - MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\ - MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\ - MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - /*Serial Interface*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ - MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ - MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\ - /* - LAN_INTR */\ - /*Control and debug */\ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\ - MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\ - -#define MUX_OVERO_SDIO2_DIRECT() \ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ - MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M0)) /*MMC2_DAT4*/\ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M0)) /*MMC2_DAT5*/\ - MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M0)) /*MMC2_DAT6*/\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/ - -#define MUX_OVERO_SDIO2_TRANSCEIVER() \ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ - MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\ - MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) /*GPIO_126*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/ - -#define MUX_USRP_E() \ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M4)) /*GPIO_173 */\ - MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175 */\ - -#define MUX_ALTO35() \ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-BTN*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M4)) /*GPIO_148-RED LED*/\ - MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\ - MUX_VAL(CP(UART1_RX), (IDIS | PTD | DIS | M4)) /*GPIO_151-BLUE LED*/\ - MUX_VAL(CP(HDQ_SIO), (IDIS | PTD | DIS | M4)) /*GPIO_170-GREEN LED*/\ - MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175*/\ - -#define MUX_ARBOR43C() \ - MUX_VAL(CP(CSI2_DX1), (IDIS | PTD | DIS | M4)) /*GPIO_114-RED LED*/\ - MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\ - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) /*GPIO_170-BUTTON */\ - MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)) /*GPIO_186-BLUE LED*/\ - MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | DIS | M4)) /*GPIO_31-CAP WAKE*/\ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-CAP IRQ*/\ - -#endif diff --git a/board/overo/spl.c b/board/overo/spl.c deleted file mode 100644 index d577e00fbca..00000000000 --- a/board/overo/spl.c +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Maintainer : Steve Sakoman steve@sakoman.com - * - * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by - * Richard Woodruff r-woodruff2@ti.com - * Syed Mohammed Khasim khasim@ti.com - * Sunil Kumar sunilsaini05@gmail.com - * Shashi Ranjan shashiranjanmca05@gmail.com - * - * (C) Copyright 2004-2008 - * Texas Instruments, <www.ti.com> - */ -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/sys_proto.h> -#include "overo.h" - -/* - * Routine: get_board_mem_timings - * Description: If we use SPL then there is no x-loader nor config header - * so we have to setup the DDR timings ourself on both banks. - */ -void get_board_mem_timings(struct board_sdrc_timings *timings) -{ - timings->mr = MICRON_V_MR_165; - switch (get_board_revision()) { - case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ - timings->mcfg = MICRON_V_MCFG_165(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - break; - case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - case REVISION_4: - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - break; - case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - timings->mcfg = HYNIX_V_MCFG_200(256 << 20); - timings->ctrla = HYNIX_V_ACTIMA_200; - timings->ctrlb = HYNIX_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - break; - case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ - timings->mcfg = MCFG(512 << 20, 15); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - break; - default: - timings->mcfg = MICRON_V_MCFG_165(128 << 20); - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - } -} diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig deleted file mode 100644 index 1e7e5f7d835..00000000000 --- a/configs/omap3_overo_defconfig +++ /dev/null @@ -1,51 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_OMAP3_OVERO=y -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_PROMPT="Overo # " -# CONFIG_CMD_IMI is not set -CONFIG_CMD_SPL=y -CONFIG_CMD_SPL_NAND_OFS=0x240000 -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader),1792k(u-boot),256k(environ),8m(linux),-(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_TWL4030_LED=y -CONFIG_MMC_OMAP_HS=y -CONFIG_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x2C000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_CONS_INDEX=3 -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_FAT_WRITE=y -CONFIG_BCH=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h deleted file mode 100644 index 35f3af4ae9a..00000000000 --- a/include/configs/omap3_overo.h +++ /dev/null @@ -1,192 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the Gumstix Overo board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <configs/ti_omap3_common.h> -/* - * We are only ever GP parts and will utilize all of the "downloaded image" - * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). - */ -#undef CONFIG_SPL_TEXT_BASE -#define CONFIG_SPL_TEXT_BASE 0x40200000 - -/* call misc_init_r */ - -/* pass the revision tag */ -#define CONFIG_REVISION_TAG - -/* override size of malloc() pool */ -#undef CONFIG_SYS_MALLOC_LEN -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ -/* Shift 128 << 15 provides 4 MiB heap to support UBI commands. - * Shift 128 << 10 provides 128 KiB heap for limited-memory devices. */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 15)) - -/* I2C Support */ - -/* TWL4030 LED */ - -/* USB EHCI */ -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 183 - -/* commands to include */ - -#ifdef CONFIG_NAND -/* NAND block size is 128 KiB. Synchronize these values with - * overo_nand_partitions in mach-omap2/board-overo.c in Linux: - * xloader 4 * NAND_BLOCK_SIZE = 512 KiB - * uboot 14 * NAND_BLOCK_SIZE = 1792 KiB - * uboot environtment 2 * NAND_BLOCK_SIZE = 256 KiB - * linux 64 * NAND_BLOCK_SIZE = 8 MiB - * rootfs remainder - */ -#endif /* CONFIG_NAND */ - -/* Board NAND Info. */ -/* Environment information */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "usbtty=cdc_acm\0" \ - "console=ttyO2,115200n8\0" \ - "mpurate=auto\0" \ - "optargs=\0" \ - "vram=12M\0" \ - "dvimode=1024x768MR-16@60\0" \ - "defaultdisplay=dvi\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "nandroot=ubi0:rootfs ubi.mtd=4\0" \ - "nandrootfstype=ubifs\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running boot script from mmc ...; " \ - "source ${loadaddr}\0" \ - "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadfdt=load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "loadubizimage=ubifsload ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadubifdt=ubifsload ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "mmcbootfdt=echo Booting with DT from mmc ...; " \ - "run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "if nand read ${loadaddr} linux; then " \ - "bootm ${loadaddr};" \ - "fi;\0" \ - "nanddtsboot=echo Booting from nand with DTS...; " \ - "run nandargs; " \ - "ubi part rootfs; "\ - "ubifsmount ubi0:rootfs; "\ - "run loadubifdt; "\ - "run loadubizimage; "\ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "fi;" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loaduimage; then " \ - "run mmcboot;" \ - "fi;" \ - "if run loadzimage; then " \ - "if test -z "${fdtfile}"; then " \ - "setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \ - "fi;" \ - "if run loadfdt; then " \ - "run mmcbootfdt;" \ - "fi;" \ - "fi;" \ - "fi;" \ - "run nandboot; " \ - "if test -z "${fdtfile}"; then "\ - "setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \ - "fi;" \ - "run nanddtsboot; " \ - -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -/* FLASH and environment organization */ -#if defined(CONFIG_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET 0x240000 -#define CONFIG_ENV_ADDR 0x240000 - -/* Initial RAM setup */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 - -/* NAND boot config */ -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ - 13, 14, 16, 17, 18, 19, 20, 21, 22, \ - 23, 24, 25, 26, 27, 28, 30, 31, 32, \ - 33, 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 44, 45, 46, 47, 48, 49, 50, 51, \ - 52, 53, 54, 55, 56} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 13 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#endif - -#endif /* __CONFIG_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-imx/mx7/Kconfig | 1 - board/warp7/Kconfig | 23 ---- board/warp7/MAINTAINERS | 7 - board/warp7/Makefile | 4 - board/warp7/README | 63 --------- board/warp7/imximage.cfg | 98 -------------- board/warp7/warp7.c | 237 ---------------------------------- configs/warp7_bl33_defconfig | 41 ------ configs/warp7_defconfig | 52 -------- include/configs/warp7.h | 169 ------------------------ 10 files changed, 695 deletions(-) delete mode 100644 board/warp7/Kconfig delete mode 100644 board/warp7/MAINTAINERS delete mode 100644 board/warp7/Makefile delete mode 100644 board/warp7/README delete mode 100644 board/warp7/imximage.cfg delete mode 100644 board/warp7/warp7.c delete mode 100644 configs/warp7_bl33_defconfig delete mode 100644 configs/warp7_defconfig delete mode 100644 include/configs/warp7.h

diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 232f33285d4..329a4acaebb 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -69,6 +69,5 @@ source "board/compulab/cl-som-imx7/Kconfig" source "board/freescale/mx7dsabresd/Kconfig" source "board/technexion/pico-imx7d/Kconfig" source "board/toradex/colibri_imx7/Kconfig" -source "board/warp7/Kconfig"

endif diff --git a/board/warp7/Kconfig b/board/warp7/Kconfig deleted file mode 100644 index c089bca2baf..00000000000 --- a/board/warp7/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -if TARGET_WARP7 - -config SYS_BOARD - default "warp7" - -config SYS_CONFIG_NAME - default "warp7" - -config WARP7_ROOT_PART - int "Partition number to use for root filesystem" - default 2 - help - The partition number to use for root filesystem this is the - partition that is typically specified with root=/dev/sdaX or - which gets converted into a root=PARTUUID=some_uuid. - -config SYS_FDT_ADDR - hex "FDT load address" - default 0x83000000 - help - The address the FDT file should be loaded to. - -endif diff --git a/board/warp7/MAINTAINERS b/board/warp7/MAINTAINERS deleted file mode 100644 index 55f8c815d46..00000000000 --- a/board/warp7/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -WARP7 BOARD -M: Fabio Estevam fabio.estevam@nxp.com -S: Maintained -F: board/warp7/ -F: include/configs/warp7.h -F: configs/warp7_defconfig -F: configs/warp7_bl33_defconfig diff --git a/board/warp7/Makefile b/board/warp7/Makefile deleted file mode 100644 index 92b0ca9060f..00000000000 --- a/board/warp7/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# (C) Copyright 2016 NXP Semiconductors - -obj-y := warp7.o diff --git a/board/warp7/README b/board/warp7/README deleted file mode 100644 index 60339da5437..00000000000 --- a/board/warp7/README +++ /dev/null @@ -1,63 +0,0 @@ -How to Update U-Boot on Warp7 board ----------------------------------- - -Required software on the host PC: - -- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader - -- dfu-util: http://dfu-util.sourceforge.net/releases/ (if you are in a -Debian distribution then you can get it via libdfu-dev package) - -- libusb: http://libusb.org/ (if you are in a Debian distribution -then you can get it via libusb-dev and libusb-1.0-0-dev) - -In U-Boot folder, build U-Boot for Warp7: - -$ make mrproper -$ make warp7_config -$ make - -This will generate the U-Boot binary called u-boot.imx. - -Put warp7 board in USB download mode: - -Remove the CPU board from the base board then put switch 2 in the upper -position - -Connect a USB to serial adapter between the host PC and warp7 - -Connect a USB cable between the OTG warp7 port and the host PC - -Copy u-boot.imx to the imx_usb_loader folder. - -Load u-boot.imx via USB: - -$ sudo ./imx_usb u-boot.imx - -Then U-Boot should start and its messages will appear in the console program. - -Open a terminal program such as minicom - -Use the default environment variables: - -=> env default -f -a -=> saveenv - -Run the DFU command: -=> dfu 0 mmc 0 - -Transfer u-boot.imx that will be flashed into the eMMC: - -$ sudo dfu-util -D u-boot.imx -a boot - -Then on the U-Boot prompt the following message should be seen after a -successful upgrade: - -#DOWNLOAD ... OK -Ctrl+C to exit ... - -Remove power from the warp7 board. - -Put warp7 board into normal boot mode (put the switch 2 in the lower position) - -Power up the board and the new updated U-Boot should boot from eMMC diff --git a/board/warp7/imximage.cfg b/board/warp7/imximage.cfg deleted file mode 100644 index a6edfdacef3..00000000000 --- a/board/warp7/imximage.cfg +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 NXP Semiconductors - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -#define __ASSEMBLY__ -#include <config.h> - -IMAGE_VERSION 2 -#ifdef CONFIG_SECURE_BOOT -CSF CONFIG_CSF_SIZE -#endif - -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -DATA 4 0x30340004 0x4F400005 - -DATA 4 0x30391000 0x00000002 -DATA 4 0x307a0000 0x03040008 -DATA 4 0x307a0064 0x00200038 -DATA 4 0x307a0490 0x00000001 -DATA 4 0x307a00d0 0x00350001 -DATA 4 0x307a00dc 0x00c3000a -DATA 4 0x307a00e0 0x00010000 -DATA 4 0x307a00e4 0x00110006 -DATA 4 0x307a00f4 0x0000033f -DATA 4 0x307a0100 0x0a0e110b -DATA 4 0x307a0104 0x00020211 -DATA 4 0x307a0108 0x03060708 -DATA 4 0x307a010c 0x00a0500c -DATA 4 0x307a0110 0x05020307 -DATA 4 0x307a0114 0x02020404 -DATA 4 0x307a0118 0x02020003 -DATA 4 0x307a011c 0x00000202 -DATA 4 0x307a0120 0x00000202 - -DATA 4 0x307a0180 0x00600018 -DATA 4 0x307a0184 0x00e00100 -DATA 4 0x307a0190 0x02098205 -DATA 4 0x307a0194 0x00060303 -DATA 4 0x307a01a0 0x80400003 -DATA 4 0x307a01a4 0x00100020 -DATA 4 0x307a01a8 0x80100004 - -DATA 4 0x307a0200 0x00000015 -DATA 4 0x307a0204 0x00161616 -DATA 4 0x307a0210 0x00000f0f -DATA 4 0x307a0214 0x04040404 -DATA 4 0x307a0218 0x0f0f0404 - -DATA 4 0x307a0240 0x06000600 -DATA 4 0x307a0244 0x00000000 -DATA 4 0x30391000 0x00000000 -DATA 4 0x30790000 0x17421e40 -DATA 4 0x30790004 0x10210100 -DATA 4 0x30790008 0x00010000 -DATA 4 0x30790010 0x0007080c -DATA 4 0x307900b0 0x1010007e - -DATA 4 0x3079001C 0x01010000 -DATA 4 0x3079009c 0x00000d6e - -DATA 4 0x30790030 0x06060606 -DATA 4 0x30790020 0x0a0a0a0a -DATA 4 0x30790050 0x01000008 -DATA 4 0x30790050 0x00000008 -DATA 4 0x30790018 0x0000000f -DATA 4 0x307900c0 0x0e487304 -DATA 4 0x307900c0 0x0e4c7304 -DATA 4 0x307900c0 0x0e4c7306 -DATA 4 0x307900c0 0x0e4c7304 - -CHECK_BITS_SET 4 0x307900c4 0x1 - -DATA 4 0x307900c0 0x0e487304 - -DATA 4 0x30384130 0x00000000 -DATA 4 0x30340020 0x00000178 -DATA 4 0x30384130 0x00000002 - -CHECK_BITS_SET 4 0x307a0004 0x1 diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c deleted file mode 100644 index 3d32b3eb52b..00000000000 --- a/board/warp7/warp7.c +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 NXP Semiconductors - * Author: Fabio Estevam fabio.estevam@nxp.com - */ - -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx7-pins.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/mach-imx/hab.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/io.h> -#include <common.h> -#include <fsl_esdhc.h> -#include <i2c.h> -#include <mmc.h> -#include <asm/arch/crm_regs.h> -#include <usb.h> -#include <netdev.h> -#include <power/pmic.h> -#include <power/pfuze3000_pmic.h> -#include "../freescale/common/pfuze.h" -#include <asm/setup.h> -#include <asm/bootm.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \ - PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) - -#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) - -#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, - .gp = IMX_GPIO_NR(4, 8), - }, - .sda = { - .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, - .gp = IMX_GPIO_NR(4, 9), - }, -}; -#endif - -int dram_init(void) -{ - gd->ram_size = PHYS_SDRAM_SIZE; - - /* Subtract the defined OPTEE runtime firmware length */ -#ifdef CONFIG_OPTEE_TZDRAM_SIZE - gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE; -#endif - - return 0; -} - -static iomux_v3_cfg_t const wdog_pads[] = { - MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart1_pads[] = { - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -}; - -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC3_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - /* Assume uSDHC3 emmc is always present */ - return 1; -} - -int board_mmc_init(bd_t *bis) -{ - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -#ifdef CONFIG_POWER -#define I2C_PMIC 0 -static struct pmic *pfuze; -int power_init_board(void) -{ - int ret; - unsigned int reg, rev_id; - - ret = power_pfuze3000_init(I2C_PMIC); - if (ret) - return ret; - - pfuze = pmic_get("PFUZE3000"); - ret = pmic_probe(pfuze); - if (ret) - return ret; - - pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg); - pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); - printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); - - /* disable Low Power Mode during standby mode */ - pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1); - - return 0; -} -#endif - -int board_eth_init(bd_t *bis) -{ - int ret = 0; - -#ifdef CONFIG_USB_ETHER - ret = usb_eth_initialize(bis); - if (ret < 0) - printf("Error %d registering USB ether.\n", ret); -#endif - - return ret; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - #ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - #endif - - return 0; -} - -int checkboard(void) -{ - char *mode; - - if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) - mode = "secure"; - else - mode = "non-secure"; - -#ifdef CONFIG_OPTEE_TZDRAM_SIZE - unsigned long optee_start, optee_end; - - optee_end = PHYS_SDRAM + PHYS_SDRAM_SIZE; - optee_start = optee_end - CONFIG_OPTEE_TZDRAM_SIZE; - - printf("Board: WARP7 in %s mode OPTEE DRAM 0x%08lx-0x%08lx\n", - mode, optee_start, optee_end); -#else - printf("Board: WARP7 in %s mode\n", mode); -#endif - - return 0; -} - -int board_usb_phy_mode(int port) -{ - return USB_INIT_DEVICE; -} - -int board_late_init(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; -#ifdef CONFIG_SERIAL_TAG - struct tag_serialnr serialnr; - char serial_string[0x20]; -#endif - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - /* - * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), - * since we use PMIC_PWRON to reset the board. - */ - clrsetbits_le16(&wdog->wcr, 0, 0x10); - -#ifdef CONFIG_SECURE_BOOT - /* Determine HAB state */ - env_set_ulong(HAB_ENABLED_ENVNAME, imx_hab_is_enabled()); -#else - env_set_ulong(HAB_ENABLED_ENVNAME, 0); -#endif - -#ifdef CONFIG_SERIAL_TAG - /* Set serial# standard environment variable based on OTP settings */ - get_board_serial(&serialnr); - snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x", - serialnr.low, serialnr.high); - env_set("serial#", serial_string); -#endif - - return 0; -} diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig deleted file mode 100644 index a568c6d10e0..00000000000 --- a/configs/warp7_bl33_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SECURE_BOOT=y -CONFIG_TARGET_WARP7=y -CONFIG_ARMV7_BOOT_SEC_DEFAULT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg" -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_DFU_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_MXC_USB_OTG_HACTIVE=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="FSL" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_ETHER=y -CONFIG_USB_ETH_CDC=y -CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" -CONFIG_OF_LIBFDT=y -CONFIG_OPTEE_TZDRAM_SIZE=0x2000000 diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig deleted file mode 100644 index 955c7af42af..00000000000 --- a/configs/warp7_defconfig +++ /dev/null @@ -1,52 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SECURE_BOOT=y -CONFIG_TARGET_WARP7=y -CONFIG_ARMV7_BOOT_SEC_DEFAULT=y -# CONFIG_ARMV7_VIRT is not set -CONFIG_IMX_RDC=y -CONFIG_IMX_BOOTAUX=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg" -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_BOOTD is not set -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_DFU_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_OPTEE=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_MXC_USB_OTG_HACTIVE=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="FSL" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_ETHER=y -CONFIG_USB_ETH_CDC=y -CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" -CONFIG_OF_LIBFDT=y -CONFIG_OPTEE_LOAD_ADDR=0x84000000 -CONFIG_OPTEE_TZDRAM_SIZE=0x3000000 -CONFIG_OPTEE_TZDRAM_BASE=0x9d000000 -CONFIG_BOOTM_OPTEE=y diff --git a/include/configs/warp7.h b/include/configs/warp7.h deleted file mode 100644 index a391dfb5c10..00000000000 --- a/include/configs/warp7.h +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 NXP Semiconductors - * - * Configuration settings for the i.MX7S Warp board. - */ - -#ifndef __WARP7_CONFIG_H -#define __WARP7_CONFIG_H - -#include "mx7_common.h" -#include <imximage.h> - -#define PHYS_SDRAM_SIZE SZ_512M - -/* - * If we have defined the OPTEE ram size and not OPTEE it means that we were - * launched by OPTEE, because of that we shall skip all the low level - * initialization since it was already done by ATF or OPTEE - */ -#ifdef CONFIG_OPTEE_TZDRAM_SIZE -#ifndef CONFIG_OPTEE -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif -#endif - -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) - -/* MMC Config*/ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -/* Switch on SERIAL_TAG */ -#define CONFIG_SERIAL_TAG - -#define CONFIG_DFU_ENV_SETTINGS \ - "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_DFU_ENV_SETTINGS \ - "script=boot.scr\0" \ - "script_signed=boot.scr.imx-signed\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "ethact=usb_ether\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx7s-warp.dtb\0" \ - "fdt_addr=" __stringify(CONFIG_SYS_FDT_ADDR)"\0" \ - "optee_addr=" __stringify(CONFIG_OPTEE_LOAD_ADDR)"\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "rootpart=" __stringify(CONFIG_WARP7_ROOT_PART) "\0" \ - "finduuid=part uuid mmc 0:${rootpart} uuid\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ - "ivt_offset=" __stringify(BOOTROM_IVT_HDR_OFFSET)"\0"\ - "warp7_auth_or_fail=hab_auth_img_or_fail ${hab_ivt_addr} ${filesize} 0;\0" \ - "do_bootscript_hab=" \ - "if test ${hab_enabled} -eq 1; then " \ - "setexpr hab_ivt_addr ${loadaddr} - ${ivt_offset}; " \ - "setenv script ${script_signed}; " \ - "load mmc ${mmcdev}:${mmcpart} ${hab_ivt_addr} ${script}; " \ - "run warp7_auth_or_fail; " \ - "run bootscript; "\ - "fi;\0" \ - "loadbootscript=" \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "run do_bootscript_hab;" \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "fi; " \ - "fi; " \ - "fi" - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* I2C configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE3000 -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 - -/* environment organization */ -#define CONFIG_ENV_SIZE SZ_8K - -#define CONFIG_ENV_OFFSET (8 * SZ_64K) -#define CONFIG_SYS_FSL_USDHC_NUM 1 - -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 0 - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */ - -#define CONFIG_IMX_THERMAL - -#define CONFIG_USBD_HS - -/* USB Device Firmware Update support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -#define CONFIG_USBNET_DEV_ADDR "de:ad:be:af:00:01" - -/* Environment variable name to represent HAB enable state */ -#define HAB_ENABLED_ENVNAME "hab_enabled" - -#endif

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-omap2/omap3/Kconfig | 1 - board/quipos/cairo/Kconfig | 12 -- board/quipos/cairo/MAINTAINERS | 6 - board/quipos/cairo/Makefile | 6 - board/quipos/cairo/cairo.c | 98 --------- board/quipos/cairo/cairo.h | 318 ------------------------------ configs/cairo_defconfig | 39 ---- include/configs/omap3_cairo.h | 231 ---------------------- 8 files changed, 711 deletions(-) delete mode 100644 board/quipos/cairo/Kconfig delete mode 100644 board/quipos/cairo/MAINTAINERS delete mode 100644 board/quipos/cairo/Makefile delete mode 100644 board/quipos/cairo/cairo.c delete mode 100644 board/quipos/cairo/cairo.h delete mode 100644 configs/cairo_defconfig delete mode 100644 include/configs/omap3_cairo.h

diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index 4e8be5f9d04..8970a8023cb 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -209,6 +209,5 @@ source "board/logicpd/omap3som/Kconfig" source "board/nokia/rx51/Kconfig" source "board/technexion/tao3530/Kconfig" source "board/technexion/twister/Kconfig" -source "board/quipos/cairo/Kconfig"

endif diff --git a/board/quipos/cairo/Kconfig b/board/quipos/cairo/Kconfig deleted file mode 100644 index 8df9421b574..00000000000 --- a/board/quipos/cairo/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_OMAP3_CAIRO - -config SYS_BOARD - default "cairo" - -config SYS_VENDOR - default "quipos" - -config SYS_CONFIG_NAME - default "omap3_cairo" - -endif diff --git a/board/quipos/cairo/MAINTAINERS b/board/quipos/cairo/MAINTAINERS deleted file mode 100644 index 01332da5ab3..00000000000 --- a/board/quipos/cairo/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CAIRO BOARD -M: Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr -S: Maintained -F: board/quipos/cairo/ -F: include/configs/omap3_cairo.h -F: configs/cairo_defconfig diff --git a/board/quipos/cairo/Makefile b/board/quipos/cairo/Makefile deleted file mode 100644 index ec2c83cc890..00000000000 --- a/board/quipos/cairo/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2014 DENX Software Engineering -# Written-By: Albert ARIBAUD albert.aribaud@3adev.fr - -obj-y := cairo.o diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c deleted file mode 100644 index 8999542a7dd..00000000000 --- a/board/quipos/cairo/cairo.c +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2014 DENX - * Written-by: Albert ARIBAUD albert.aribaud@3adev.fr - * - * Derived from code written by Robert Aigner (ra@spiid.net) - * - * Itself derived from Beagle Board and 3430 SDP code by - * Richard Woodruff r-woodruff2@ti.com - * Syed Mohammed Khasim khasim@ti.com - */ -#include <common.h> -#include <dm.h> -#include <netdev.h> -#include <ns16550.h> -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <i2c.h> -#include <asm/mach-types.h> -#include <asm/omap_mmc.h> -#include "cairo.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* board id for Linux */ - gd->bd->bi_arch_number = CONFIG_MACH_TYPE; - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_CAIRO(); -} - -#if defined(CONFIG_MMC) -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#ifdef CONFIG_SPL_BUILD -/* - * Routine: get_board_mem_timings - * Description: If we use SPL then there is no x-loader nor config header - * so we have to setup the DDR timings ourself on the first bank. This - * provides the timing values back to the function that configures - * the memory. - * - * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6 - */ -void get_board_mem_timings(struct board_sdrc_timings *timings) -{ - timings->sharing = SAMSUNG_SHARING; - timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20); - timings->ctrla = SAMSUNG_V_ACTIMA_165; - timings->ctrlb = SAMSUNG_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - timings->mr = SAMSUNG_V_MR_165; -} -#endif - -static const struct ns16550_platdata cairo_serial = { - .base = OMAP34XX_UART2, - .reg_shift = 2, - .clock = V_NS16550_CLK, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DEVICE(cairo_uart) = { - "ns16550_serial", - &cairo_serial -}; - -/* force SPL booting into U-Boot, not Linux */ -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - return 1; -} -#endif diff --git a/board/quipos/cairo/cairo.h b/board/quipos/cairo/cairo.h deleted file mode 100644 index f57a6081d82..00000000000 --- a/board/quipos/cairo/cairo.h +++ /dev/null @@ -1,318 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) DENX - * Written-by: Albert ARIBAUD albert.aribaud@3adev.fr - * - * Original code (C) Copyright 2010 - * Robert Aigner (ra@spiid.net) - */ -#ifndef _EVM_H_ -#define _EVM_H_ - - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "OMAP3 Cairo board", - "NAND", -}; - -/* - * OMAP3 Cairo handheld hardware revision - */ -enum { - OMAP3_CAIRO_BOARD_GEN_1 = 0, /* Cairo handheld V01 */ - OMAP3_CAIRO_BOARD_GEN_2, -}; - -#define MUX_CAIRO() \ -MUX_VAL(CONTROL_PADCONF_GPIO112, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPIO113, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPIO114, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPIO115, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPIO126, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPIO127, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPIO128, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPIO129, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_CAM_D0, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ -MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | DIS | SB_HIZ | M4)) \ -MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | DIS | SB_HIZ | M7)) \ -MUX_VAL(CONTROL_PADCONF_CAM_D3, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ -MUX_VAL(CONTROL_PADCONF_CAM_D4, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ -MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PTD | EN | SB_HIZ | SB_PD | M7)) \ -MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | DIS | SB_HIZ | M7)) \ -MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | DIS | SB_HIZ | M4)) \ -MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \ -MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | DIS | SB_HIZ | M4)) \ -MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \ -MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ -MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \ -MUX_VAL(CONTROL_PADCONF_CAM_VS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ -MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ -MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ -MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | DIS | SB_HIZ | SB_PD | M7)) \ -MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IDIS | PTD | EN | SB_HIZ | SB_PD | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA1, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA2, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA3, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA4, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA5, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA6, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA7, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA8, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA9, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA10, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA11, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA12, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA13, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA14, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA15, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA16, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA17, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IDIS | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IDIS | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IDIS | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IDIS | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PTU | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IDIS | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IDIS | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IEN | DIS | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | DIS | SB_HIZ | SB_PD | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IEN | DIS | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | DIS | SB_HIZ | M0)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | DIS | SB_HIZ | M4)) \ -MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IDIS | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_I2C1_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_I2C1_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_I2C2_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_I2C2_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_I2C3_SCL, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ -MUX_VAL(CONTROL_PADCONF_I2C3_SDA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ -MUX_VAL(CONTROL_PADCONF_I2C4_SCL, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_I2C4_SDA, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_JTAG_EMU0, (IEN | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_JTAG_EMU1, (IEN | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_JTAG_NTRST, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_JTAG_RTCK, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_JTAG_TCK, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_JTAG_TDI, (IEN | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_JTAG_TDO, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_JTAG_TMS, (IEN | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | DIS | SB_HIZ | M4)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | DIS | SB_HIZ | M4)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | DIS | SB_HIZ | SB_PD | M7)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | DIS | SB_HIZ | M4)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP2_CLKX, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP2_DR, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP2_DX, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP2_FSX, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP3_CLKX, (IDIS | DIS | SB_HIZ | SB_PU | M1)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP3_DR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP3_FSX, (IEN | PTU | EN | SB_HIZ | SB_PU | M1)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP4_CLKX, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP4_DR, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP4_DX, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_MCBSP4_FSX, (IEN | PTD | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PTU | EN | SB_HIZ | SB_PD | M0)) \ -MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PTU | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PTU | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IEN | PTD | EN | M3)) \ -MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IDIS | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PTD | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC2_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC2_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IDIS | DIS | SB_HIZ | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC2_DAT5, (IDIS | DIS | SB_HIZ | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IDIS | DIS | SB_HIZ | M0)) \ -MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A3, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A4, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A5, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A6, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A7, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A8, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A9, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A10, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A11, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A12, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A13, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_A14, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_BA0, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_BA1, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_CKE0, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_CKE1, (IDIS | DIS | M7)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_CLK, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D0, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D1, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D2, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D3, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D4, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D5, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D6, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D7, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D8, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D9, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D10, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D11, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D12, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D13, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D14, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D15, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D16, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D17, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D18, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D19, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D20, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D21, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D22, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D23, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D24, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D25, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D26, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D27, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D28, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D29, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D30, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_D31, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_DM0, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_DM1, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_DM2, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_DM3, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_DQS0, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_DQS1, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_DQS2, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_DQS3, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_NCAS, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_NCLK, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_NCS0, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_NCS1, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_NRAS, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SDRC_NWE, (IDIS | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SYS_32K, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SYS_BOOT0, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SYS_BOOT1, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SYS_BOOT2, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SYS_BOOT3, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SYS_BOOT4, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SYS_BOOT5, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SYS_BOOT6, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | DIS | M0)) \ -MUX_VAL(CONTROL_PADCONF_SYS_NIRQ, (IEN | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_SYS_NRESWARM, (IEN | PTU | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_SYS_OFF_MODE, (IDIS | PTD | EN | M0)) \ -MUX_VAL(CONTROL_PADCONF_UART1_CTS, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_UART1_RTS, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_UART1_RX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_UART1_TX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_UART2_CTS, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_UART2_RTS, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_UART2_RX, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PTU | EN | M7)) \ -MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, \ - (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ -MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ - -#endif diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig deleted file mode 100644 index dc1245f1bfb..00000000000 --- a/configs/cairo_defconfig +++ /dev/null @@ -1,39 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80100000 -CONFIG_TARGET_OMAP3_CAIRO=y -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_BOOTDELAY=-2 -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_PROMPT="Cairo # " -# CONFIG_CMD_IMI is not set -CONFIG_CMD_SPL=y -CONFIG_CMD_SPL_NAND_OFS=0x240000 -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_LOCK_UNLOCK=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_NET is not set -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_TWL4030_LED=y -CONFIG_MMC_OMAP_HS=y -CONFIG_NAND=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_CONS_INDEX=2 -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_FAT_WRITE=y -# CONFIG_REGEX is not set -CONFIG_OF_LIBFDT=y diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h deleted file mode 100644 index 04bce2f8b46..00000000000 --- a/include/configs/omap3_cairo.h +++ /dev/null @@ -1,231 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the QUIPOS Cairo board. - * - * Copyright (C) DENX GmbH - * - * Author : - * Albert ARIBAUD albert.aribaud@3adev.fr - * - * Derived from EVM code by - * Manikandan Pillai mani.pillai@ti.com - * Itself derived from Beagle Board and 3430 SDP code by - * Richard Woodruff r-woodruff2@ti.com - * Syed Mohammed Khasim khasim@ti.com - * - * Also derived from include/configs/omap3_beagle.h - */ - -#ifndef __OMAP3_CAIRO_CONFIG_H -#define __OMAP3_CAIRO_CONFIG_H - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. We use this rather than the inherited defines from - * ti_armv7_common.h for backwards compatibility. - */ -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -#include <configs/ti_omap3_common.h> - -#define CONFIG_REVISION_TAG 1 -#define CONFIG_ENV_OVERWRITE - -/* Enable Multi Bus support for I2C */ -#define CONFIG_I2C_MULTI_BUS 1 - -/* Probe all devices */ -#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} } - -/* - * TWL4030 - */ - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "machid=ffffffff\0" \ - "fdt_high=0x87000000\0" \ - "baudrate=115200\0" \ - "fec_addr=00:50:C2:7E:90:F0\0" \ - "netmask=255.255.255.0\0" \ - "ipaddr=192.168.2.9\0" \ - "gateway=192.168.2.1\0" \ - "serverip=192.168.2.10\0" \ - "nfshost=192.168.2.10\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "bootargs_mmc_ramdisk=mem=128M " \ - "console=ttyO1,115200n8 " \ - "root=/dev/ram0 rw " \ - "initrd=0x81600000,16M " \ - "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \ - "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \ - "mmcboot=mmc init; " \ - "fatload mmc 0 0x80000000 uImage; " \ - "fatload mmc 0 0x81600000 ramdisk.gz; " \ - "setenv bootargs ${bootargs_mmc_ramdisk}; " \ - "bootm 0x80000000\0" \ - "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \ - "root=/dev/nfs " \ - "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \ - "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \ - "omap_vout.vid1_static_vrfb_alloc=y\0" \ - "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \ - "bootm 0x80000000\0" \ - "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \ - "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \ - "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \ - "omapfb.rotate_type=1\0" \ - "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \ - "bootargs ${bootargs_nand}; bootm 0x80000000\0" \ - "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ - "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ - "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \ - "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ - "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \ - "mw 60 09 00 1; i2c mw 60 06 10 1\0" \ - "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ - "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ - "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \ - "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ - "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ - "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \ - "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \ - "nand erase 0 20000; " \ - "fatload mmc 0 0x81600000 MLO; " \ - "nandecc hw; " \ - "nand write.i 0x81600000 0 20000;\0" \ - "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \ - "nand erase 80000 40000; " \ - "fatload mmc 0 0x81600000 u-boot.bin; " \ - "nandecc sw; " \ - "nand write.i 0x81600000 80000 40000;\0" \ - "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \ - "nand erase 280000 300000; " \ - "fatload mmc 0 0x81600000 uImage; " \ - "nandecc sw; " \ - "nand write.i 0x81600000 280000 300000;\0" \ - "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \ - "nandecc sw; " \ - "nand write.jffs2 0x680000 0xFF ${filesize}; " \ - "nand erase 680000 ${filesize}; " \ - "nand write.jffs2 81600000 680000 ${filesize};\0" \ - "flash_scrub=nand scrub; " \ - "run flash_xloader; " \ - "run flash_uboot; " \ - "run flash_kernel; " \ - "run flash_rootfs;\0" \ - "flash_all=run ledred; " \ - "nand erase.chip; " \ - "run ledorange; " \ - "run flash_xloader; " \ - "run flash_uboot; " \ - "run flash_kernel; " \ - "run flash_rootfs; " \ - "run ledgreen; " \ - "run boot_nand; \0" \ - -#define CONFIG_BOOTCOMMAND \ - "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \ - "else run boot_nand; fi" - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET 0x260000 -#define CONFIG_ENV_ADDR 0x260000 - -/* Defines for SPL */ - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#endif - -/* env defaults */ -#define CONFIG_BOOTFILE "uImage" - -/* Override OMAP3 common serial console configuration from UART3 - * to UART2. - * - * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3) - * are needed and peripheral clocks for UART2 must be enabled in - * function per_clocks_enable(). - */ -#ifdef CONFIG_SPL_BUILD -#endif - -/* Provide the MACH_TYPE value the vendor kernel requires */ -#define CONFIG_MACH_TYPE 3063 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ - -#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ - /* on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) - -/* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ - CONFIG_SYS_MAX_NAND_DEVICE) -#define CONFIG_SYS_JFFS2_MEM_NAND -/* use flash_info[2] */ -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#endif /* __OMAP3_CAIRO_CONFIG_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-imx/mx6/Kconfig | 1 - board/liebherr/mccmon6/Kconfig | 12 - board/liebherr/mccmon6/MAINTAINERS | 7 - board/liebherr/mccmon6/Makefile | 6 - board/liebherr/mccmon6/mccmon6.c | 489 ------------------- board/liebherr/mccmon6/mon6_imximage_nor.cfg | 8 - board/liebherr/mccmon6/mon6_imximage_sd.cfg | 8 - board/liebherr/mccmon6/spl.c | 298 ----------- configs/mccmon6_nor_defconfig | 50 -- configs/mccmon6_sd_defconfig | 51 -- include/configs/mccmon6.h | 293 ----------- 11 files changed, 1223 deletions(-) delete mode 100644 board/liebherr/mccmon6/Kconfig delete mode 100644 board/liebherr/mccmon6/MAINTAINERS delete mode 100644 board/liebherr/mccmon6/Makefile delete mode 100644 board/liebherr/mccmon6/mccmon6.c delete mode 100644 board/liebherr/mccmon6/mon6_imximage_nor.cfg delete mode 100644 board/liebherr/mccmon6/mon6_imximage_sd.cfg delete mode 100644 board/liebherr/mccmon6/spl.c delete mode 100644 configs/mccmon6_nor_defconfig delete mode 100644 configs/mccmon6_sd_defconfig delete mode 100644 include/configs/mccmon6.h

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 7c7435b6d89..de9bf156ce2 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -551,7 +551,6 @@ source "board/grinn/liteboard/Kconfig" source "board/phytec/pfla02/Kconfig" source "board/kosagi/novena/Kconfig" source "board/liebherr/display5/Kconfig" -source "board/liebherr/mccmon6/Kconfig" source "board/logicpd/imx6/Kconfig" source "board/seco/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" diff --git a/board/liebherr/mccmon6/Kconfig b/board/liebherr/mccmon6/Kconfig deleted file mode 100644 index 4cc7fc2ba2c..00000000000 --- a/board/liebherr/mccmon6/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MCCMON6 - -config SYS_BOARD - default "mccmon6" - -config SYS_VENDOR - default "liebherr" - -config SYS_CONFIG_NAME - default "mccmon6" - -endif diff --git a/board/liebherr/mccmon6/MAINTAINERS b/board/liebherr/mccmon6/MAINTAINERS deleted file mode 100644 index c9c718305f3..00000000000 --- a/board/liebherr/mccmon6/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MCCMON6 BOARD -M: Lukasz Majewski lukma@denx.de -S: Maintained -F: board/liebherr/mccmon6/ -F: include/configs/mccmon6.h -F: configs/mccmon6_nor_defconfig -F: configs/mccmon6_sd_defconfig diff --git a/board/liebherr/mccmon6/Makefile b/board/liebherr/mccmon6/Makefile deleted file mode 100644 index ead6750ebf9..00000000000 --- a/board/liebherr/mccmon6/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2016-2017 -# Lukasz Majewski, DENX Software Engineering, lukma@denx.de - -obj-y := mccmon6.o spl.o diff --git a/board/liebherr/mccmon6/mccmon6.c b/board/liebherr/mccmon6/mccmon6.c deleted file mode 100644 index 946b91f3a1c..00000000000 --- a/board/liebherr/mccmon6/mccmon6.c +++ /dev/null @@ -1,489 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016-2017 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -#include <common.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/spi.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/io.h> -#include <fsl_esdhc.h> -#include <mmc.h> -#include <netdev.h> -#include <micrel.h> -#include <phy.h> -#include <input.h> -#include <i2c.h> -#include <spl.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) -#define ETH_PHY_RESET IMX_GPIO_NR(1, 27) -#define ECSPI3_CS0 IMX_GPIO_NR(4, 24) -#define ECSPI3_FLWP IMX_GPIO_NR(4, 27) -#define NOR_WP IMX_GPIO_NR(1, 1) -#define DISPLAY_EN IMX_GPIO_NR(1, 2) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static iomux_v3_cfg_t const uart1_pads[] = { - IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - /* Carrier MicroSD Card Detect */ - IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const enet_pads[] = { - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL - | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK - | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL - | MUX_PAD_CTRL(ENET_PAD_CTRL)), - /* KSZ9031 PHY Reset */ - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static void setup_iomux_uart(void) -{ - SETUP_IOMUX_PADS(uart1_pads); -} - -static void setup_iomux_enet(void) -{ - SETUP_IOMUX_PADS(enet_pads); - - /* Reset KSZ9031 PHY */ - gpio_direction_output(ETH_PHY_RESET, 0); - mdelay(10); - gpio_set_value(ETH_PHY_RESET, 1); - udelay(100); -} - -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC2_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - /* - * eMMC don't have card detect pin - since it is soldered to the - * PCB board - */ - ret = 1; - break; - } - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - u32 index = 0; - - /* - * MMC MAP - * (U-Boot device node) (Physical Port) - * mmc0 Soldered on board eMMC device - * mmc1 MicroSD card - */ - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[0].max_bus_width = 8; - break; - case 1: - SETUP_IOMUX_PADS(usdhc2_pads); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - usdhc_cfg[1].max_bus_width = 4; - gpio_direction_input(USDHC2_CD_GPIO); - break; - default: - printf("Warning: More USDHC controllers (%d) than supported (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} - -static iomux_v3_cfg_t const eimnor_pads[] = { - IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static void eimnor_cs_setup(void) -{ - struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; - - - /* NOR configuration */ - writel(0x00620181, &weim_regs->cs0gcr1); - writel(0x00000001, &weim_regs->cs0gcr2); - writel(0x0b020000, &weim_regs->cs0rcr1); - writel(0x0000b000, &weim_regs->cs0rcr2); - writel(0x0804a240, &weim_regs->cs0wcr1); - writel(0x00000000, &weim_regs->cs0wcr2); - - writel(0x00000120, &weim_regs->wcr); - writel(0x00000010, &weim_regs->wiar); - writel(0x00000000, &weim_regs->ear); - - set_chipselect_size(CS0_128); -} - -static void setup_eimnor(void) -{ - SETUP_IOMUX_PADS(eimnor_pads); - gpio_direction_output(NOR_WP, 1); - - enable_eim_clk(1); - eimnor_cs_setup(); -} - -/* mccmon6 board has SPI Flash is connected to SPI3 */ -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 2 && cs == 0) ? ECSPI3_CS0 : -1; -} - -static iomux_v3_cfg_t const ecspi3_pads[] = { - /* SPI3 */ - IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), -}; - -void setup_spi(void) -{ - SETUP_IOMUX_PADS(ecspi3_pads); - - enable_spi_clk(true, 2); - - /* set cs0 to high */ - gpio_direction_output(ECSPI3_CS0, 1); - - /* set flwp to high */ - gpio_direction_output(ECSPI3_FLWP, 1); -} - -struct i2c_pads_info mx6q_i2c1_pad_info = { - .scl = { - .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gp = IMX_GPIO_NR(5, 26) - } -}; - -struct i2c_pads_info mx6q_i2c2_pad_info = { - .scl = { - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 - | MUX_PAD_CTRL(I2C_PAD_CTRL), - .gp = IMX_GPIO_NR(4, 13) - } -}; - -int board_eth_init(bd_t *bis) -{ - setup_iomux_enet(); - - return cpu_eth_init(bis); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - gpio_direction_output(DISPLAY_EN, 1); - - setup_eimnor(); - setup_spi(); - - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info); - - return 0; -} - -int board_late_init(void) -{ - env_set("board_name", "mccmon6"); - - return 0; -} - -int checkboard(void) -{ - puts("Board: MCCMON6\n"); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - /* - * Default setting for GMII Clock Pad Skew Register 0x1EF: - * MMD Address 0x2h, Register 0x8h - * - * GTX_CLK Pad Skew 0xF -> 0.9 nsec skew - * RX_CLK Pad Skew 0xF -> 0.9 nsec skew - * - * Adjustment -> write 0x3FF: - * GTX_CLK Pad Skew 0x1F -> 1.8 nsec skew - * RX_CLK Pad Skew 0x1F -> 1.8 nsec skew - * - */ - ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x3FF); - - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x00FF); - - ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - 0x3333); - - ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - 0x2052); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -#ifdef CONFIG_SPL_BOARD_INIT -void spl_board_init(void) -{ - setup_eimnor(); - - gpio_direction_output(DISPLAY_EN, 1); -} -#endif /* CONFIG_SPL_BOARD_INIT */ - -#ifdef CONFIG_SPL_BUILD -void board_boot_order(u32 *spl_boot_list) -{ - switch (spl_boot_device()) { - case BOOT_DEVICE_MMC2: - case BOOT_DEVICE_MMC1: - spl_boot_list[0] = BOOT_DEVICE_MMC2; - spl_boot_list[1] = BOOT_DEVICE_MMC1; - break; - - case BOOT_DEVICE_NOR: - spl_boot_list[0] = BOOT_DEVICE_NOR; - break; - } -} -#endif /* CONFIG_SPL_BUILD */ - -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - char s[16]; - int ret; - /* - * We use BOOT_DEVICE_MMC1, but SD card is connected - * to MMC2 - * - * Correct "mapping" is delivered in board defined - * board_boot_order() function. - * - * SD card boot is regarded as a "development" one, - * hence we _always_ go through the u-boot. - * - */ - if (spl_boot_device() == BOOT_DEVICE_MMC1) - return 1; - - /* break into full u-boot on 'c' */ - if (serial_tstc() && serial_getc() == 'c') - return 1; - - env_init(); - ret = env_get_f("boot_os", s, sizeof(s)); - if ((ret != -1) && (strcmp(s, "no") == 0)) - return 1; - - /* - * Check if SWUpdate recovery needs to be started - * - * recovery_status = NULL (not set - ret == -1) -> normal operation - * - * recovery_status = progress or - * recovery_status = failed or - * recovery_status = <any value> -> start SWUpdate - * - */ - ret = env_get_f("recovery_status", s, sizeof(s)); - if (ret != -1) - return 1; - - return 0; -} -#endif /* CONFIG_SPL_OS_BOOT */ diff --git a/board/liebherr/mccmon6/mon6_imximage_nor.cfg b/board/liebherr/mccmon6/mon6_imximage_nor.cfg deleted file mode 100644 index 6f966a7dd75..00000000000 --- a/board/liebherr/mccmon6/mon6_imximage_nor.cfg +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016-2017 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -IMAGE_VERSION 2 -BOOT_FROM nor diff --git a/board/liebherr/mccmon6/mon6_imximage_sd.cfg b/board/liebherr/mccmon6/mon6_imximage_sd.cfg deleted file mode 100644 index 5a65e0f54ca..00000000000 --- a/board/liebherr/mccmon6/mon6_imximage_sd.cfg +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016-2017 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -IMAGE_VERSION 2 -BOOT_FROM sd diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c deleted file mode 100644 index acfc4902c11..00000000000 --- a/board/liebherr/mccmon6/spl.c +++ /dev/null @@ -1,298 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014 Wandboard - * Author: Tungyi Lin tungyilin1127@gmail.com - * Richard Hu hakahu@gmail.com - */ - -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/video.h> -#include <mmc.h> -#include <fsl_esdhc.h> -#include <asm/arch/crm_regs.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <spl.h> - -#if defined(CONFIG_SPL_BUILD) -#include <asm/arch/mx6-ddr.h> -/* - * Driving strength: - * 0x30 == 40 Ohm - * 0x28 == 48 Ohm - */ - -#define IMX6DQ_DRIVE_STRENGTH 0x30 -#define IMX6SDL_DRIVE_STRENGTH 0x28 - -/* configure MX6Q/DUAL mmdc DDR io registers */ -static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { - .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, - .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, - .dram_cas = IMX6DQ_DRIVE_STRENGTH, - .dram_ras = IMX6DQ_DRIVE_STRENGTH, - .dram_reset = IMX6DQ_DRIVE_STRENGTH, - .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, - .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, - .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, - .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, - .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, - .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, - .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, - .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, - .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, - .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, - .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, - .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, - .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, - .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, - .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, - .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, - .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, - .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, - .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, -}; - -/* configure MX6Q/DUAL mmdc GRP io registers */ -static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { - .grp_ddr_type = 0x000c0000, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_addds = IMX6DQ_DRIVE_STRENGTH, - .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, - .grp_ddrmode = 0x00020000, - .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, - .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, - .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, - .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, - .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, - .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, - .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, - .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, -}; - -/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ -struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { - .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, - .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, - .dram_cas = IMX6SDL_DRIVE_STRENGTH, - .dram_ras = IMX6SDL_DRIVE_STRENGTH, - .dram_reset = IMX6SDL_DRIVE_STRENGTH, - .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, - .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, - .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, - .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, - .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, - .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, - .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, - .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, - .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, - .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, - .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, - .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, - .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, - .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, - .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, - .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, - .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, - .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, - .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, -}; - -/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ -struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { - .grp_ddr_type = 0x000c0000, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_addds = IMX6SDL_DRIVE_STRENGTH, - .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, - .grp_ddrmode = 0x00020000, - .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, - .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, - .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, - .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, - .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, - .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, - .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, - .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, -}; - -/* H5T04G63AFR-PB */ -static struct mx6_ddr3_cfg h5t04g63afr = { - .mem_speed = 1600, - .density = 4, - .width = 16, - .banks = 8, - .rowaddr = 15, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -/* H5TQ2G63DFR-H9 */ -static struct mx6_ddr3_cfg h5tq2g63dfr = { - .mem_speed = 1333, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1350, - .trcmin = 4950, - .trasmin = 3600, -}; - -static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = { - .p0_mpwldectrl0 = 0x001f001f, - .p0_mpwldectrl1 = 0x001f001f, - .p1_mpwldectrl0 = 0x001f001f, - .p1_mpwldectrl1 = 0x001f001f, - .p0_mpdgctrl0 = 0x4301030d, - .p0_mpdgctrl1 = 0x03020277, - .p1_mpdgctrl0 = 0x4300030a, - .p1_mpdgctrl1 = 0x02780248, - .p0_mprddlctl = 0x4536393b, - .p1_mprddlctl = 0x36353441, - .p0_mpwrdlctl = 0x41414743, - .p1_mpwrdlctl = 0x462f453f, -}; - -/* DDR 64bit 2GB */ -static struct mx6_ddr_sysinfo mem_q = { - .dsize = 2, - .cs1_mirror = 0, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, - .ncs = 1, - .bi_on = 1, - .rtt_nom = 1, - .rtt_wr = 0, - .ralat = 5, - .walat = 0, - .mif3_mode = 3, - .rst_to_cke = 0x23, - .sde_to_rst = 0x10, -}; - -static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = { - .p0_mpwldectrl0 = 0x001f001f, - .p0_mpwldectrl1 = 0x001f001f, - .p1_mpwldectrl0 = 0x001f001f, - .p1_mpwldectrl1 = 0x001f001f, - .p0_mpdgctrl0 = 0x420e020e, - .p0_mpdgctrl1 = 0x02000200, - .p1_mpdgctrl0 = 0x42020202, - .p1_mpdgctrl1 = 0x01720172, - .p0_mprddlctl = 0x494c4f4c, - .p1_mprddlctl = 0x4a4c4c49, - .p0_mpwrdlctl = 0x3f3f3133, - .p1_mpwrdlctl = 0x39373f2e, -}; - -static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = { - .p0_mpwldectrl0 = 0x0040003c, - .p0_mpwldectrl1 = 0x0032003e, - .p0_mpdgctrl0 = 0x42350231, - .p0_mpdgctrl1 = 0x021a0218, - .p0_mprddlctl = 0x4b4b4e49, - .p0_mpwrdlctl = 0x3f3f3035, -}; - -/* DDR 64bit 1GB */ -static struct mx6_ddr_sysinfo mem_dl = { - .dsize = 2, - .cs1_mirror = 0, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, - .ncs = 1, - .bi_on = 1, - .rtt_nom = 1, - .rtt_wr = 0, - .ralat = 5, - .walat = 0, - .mif3_mode = 3, - .rst_to_cke = 0x23, - .sde_to_rst = 0x10, -}; - -/* DDR 32bit 512MB */ -static struct mx6_ddr_sysinfo mem_s = { - .dsize = 1, - .cs1_mirror = 0, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, - .ncs = 1, - .bi_on = 1, - .rtt_nom = 1, - .rtt_wr = 0, - .ralat = 5, - .walat = 0, - .mif3_mode = 3, - .rst_to_cke = 0x23, - .sde_to_rst = 0x10, -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC03, &ccm->CCGR1); - writel(0x0FFFC000, &ccm->CCGR2); - writel(0x3FF00000, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003FF, &ccm->CCGR6); -} - -static void spl_dram_init(void) -{ - if (is_cpu_type(MXC_CPU_MX6SOLO)) { - mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); - mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr); - } else if (is_cpu_type(MXC_CPU_MX6DL)) { - mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); - mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr); - } else if (is_cpu_type(MXC_CPU_MX6Q)) { - mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); - mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr); - } - - udelay(100); -} - -void board_init_f(ulong dummy) -{ - ccgr_init(); - - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - gpr_init(); - - /* iomux */ - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* DDR initialization */ - spl_dram_init(); -} -#endif diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig deleted file mode 100644 index 69fab7c7794..00000000000 --- a/configs/mccmon6_nor_defconfig +++ /dev/null @@ -1,50 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_MCCMON6=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -# CONFIG_CMD_BMODE is not set -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x40000(u-boot-env.nor),1m@0x80000(u-boot.nor),8m@0x180000(kernel.nor),8m@0x980000(swupdate-kernel.nor),8m@0x1180000(swupdate-rootfs.nor),128k@0x1980000(kernel-dtb.nor),128k@0x19C0000(swupdate-kernel-dtb.nor)" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_MTD_DEVICE=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_DM_THERMAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig deleted file mode 100644 index 05c6572beb3..00000000000 --- a/configs/mccmon6_sd_defconfig +++ /dev/null @@ -1,51 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_MCCMON6=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -# CONFIG_CMD_BMODE is not set -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x40000(u-boot-env.nor),1m@0x80000(u-boot.nor),8m@0x180000(kernel.nor),8m@0x980000(swupdate-kernel.nor),8m@0x1180000(swupdate-rootfs.nor),128k@0x1980000(kernel-dtb.nor),128k@0x19C0000(swupdate-kernel-dtb.nor)" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_MTD_DEVICE=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_DM_THERMAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h deleted file mode 100644 index 644f3399938..00000000000 --- a/include/configs/mccmon6.h +++ /dev/null @@ -1,293 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016-2017 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#include "imx6_spl.h" - -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) -#define CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + 0x180000) -#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + 0x1980000) -#define CONFIG_SYS_FDT_SIZE (48 * SZ_1K) -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - -/* - * Below defines are set but NOT really used since we by - * design force U-Boot run when we boot in development - * mode from SD card (SD2) - */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800) -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80) -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000) -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6q-mccmon.dtb" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) - -#define CONFIG_SF_DEFAULT_BUS 2 -#define CONFIG_SF_DEFAULT_CS 0 -#define CONFIG_SF_DEFAULT_SPEED 25000000 -#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* MMC Configuration */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* NOR 16-bit mode */ -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_FLASH_VERIFY - -/* NOR Flash MTD */ -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } -#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } - -/* MTD support */ - -/* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -/* Ethernet Configuration */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc0,115200 quiet\0" \ - "fdtfile=imx6q-mccmon6.dtb\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "boot_os=yes\0" \ - "download_kernel=" \ - "tftpboot ${kernel_addr} ${kernel_file};" \ - "tftpboot ${fdt_addr} ${fdtfile};\0" \ - "get_boot_medium=" \ - "setenv boot_medium nor;" \ - "setexpr.l _src_sbmr1 *0x020d8004;" \ - "setexpr _b_medium ${_src_sbmr1} '&' 0x00000040;" \ - "if test ${_b_medium} = 40; then " \ - "setenv boot_medium sdcard;" \ - "fi\0" \ - "kernel_file=uImage\0" \ - "load_kernel=" \ - "load mmc ${bootdev}:${bootpart} ${kernel_addr} uImage;" \ - "load mmc ${bootdev}:${bootpart} ${fdt_addr} ${fdtfile};\0" \ - "boot_sd=" \ - "echo '#######################';" \ - "echo '# Factory SDcard Boot #';" \ - "echo '#######################';" \ - "setenv mmcdev 1;" \ - "setenv mmcfactorydev 0;" \ - "setenv mmcfactorypart 1;" \ - "run factory_flash_img;\0" \ - "boot_nor=" \ - "setenv kernelnor 0x08180000;" \ - "setenv dtbnor 0x09980000;" \ - "setenv bootargs console=${console} " \ - CONFIG_MTDPARTS_DEFAULT " " \ - "root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \ - "cp.l ${dtbnor} ${dtbloadaddr} 0x8000;" \ - "bootm ${kernelnor} - ${dtbloadaddr};\0" \ - "boot_recovery=" \ - "echo '#######################';" \ - "echo '# RECOVERY SWU Boot #';" \ - "echo '#######################';" \ - "setenv rootfsloadaddr 0x13000000;" \ - "setenv swukernelnor 0x08980000;" \ - "setenv swurootfsnor 0x09180000;" \ - "setenv swudtbnor 0x099A0000;" \ - "setenv bootargs console=${console} " \ - CONFIG_MTDPARTS_DEFAULT " " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}::off root=/dev/ram rw;" \ - "cp.l ${swurootfsnor} ${rootfsloadaddr} 0x200000;" \ - "cp.l ${swudtbnor} ${dtbloadaddr} 0x8000;" \ - "bootm ${swukernelnor} ${rootfsloadaddr} ${dtbloadaddr};\0" \ - "boot_tftp=" \ - "echo '#######################';" \ - "echo '# TFTP Boot #';" \ - "echo '#######################';" \ - "if run download_kernel; then " \ - "setenv bootargs console=${console} " \ - "root=/dev/mmcblk0p2 rootwait;" \ - "bootm ${kernel_addr} - ${fdt_addr};" \ - "fi\0" \ - "bootcmd=" \ - "if test -n ${recovery_status}; then " \ - "run boot_recovery;" \ - "else " \ - "if test ! -n ${boot_medium}; then " \ - "run get_boot_medium;" \ - "if test ${boot_medium} = sdcard; then " \ - "run boot_sd;" \ - "else " \ - "run boot_nor;" \ - "fi;" \ - "else " \ - "if test ${boot_medium} = tftp; then " \ - "run boot_tftp;" \ - "fi;" \ - "fi;" \ - "fi\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "fdt_addr=0x18000000\0" \ - "bootdev=1\0" \ - "bootpart=1\0" \ - "kernel_addr=" __stringify(CONFIG_LOADADDR) "\0" \ - "netdev=eth0\0" \ - "load_addr=0x11000000\0" \ - "dtbloadaddr=0x12000000\0" \ - "uboot_file=u-boot.img\0" \ - "SPL_file=SPL\0" \ - "load_uboot=tftp ${load_addr} ${uboot_file}\0" \ - "nor_img_addr=0x11000000\0" \ - "nor_img_file=core-image-lwn-mccmon6.nor\0" \ - "emmc_img_file=core-image-lwn-mccmon6.ext4\0" \ - "nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ - "nor_img_size=0x02000000\0" \ - "factory_script_file=factory.scr\0" \ - "factory_load_script=" \ - "if test -e mmc ${mmcdev}:${mmcfactorypart} " \ - "${factory_script_file}; then " \ - "load mmc ${mmcdev}:${mmcfactorypart} " \ - "${loadaddr} ${factory_script_file};" \ - "fi\0" \ - "factory_script=echo Running factory script from mmc${mmcdev} ...; " \ - "source ${loadaddr}\0" \ - "factory_flash_img="\ - "echo 'Flash mccmon6 with factory images'; " \ - "if run factory_load_script; then " \ - "run factory_script;" \ - "else " \ - "echo No factory script: ${factory_script_file} found on " \ - "device ${mmcdev};" \ - "run factory_nor_img;" \ - "run factory_eMMC_img;" \ - "fi\0" \ - "factory_eMMC_img="\ - "echo 'Update mccmon6 eMMC image'; " \ - "if load mmc ${mmcdev}:${mmcfactorypart} " \ - "${loadaddr} ${emmc_img_file}; then " \ - "setexpr fw_sz ${filesize} / 0x200;" \ - "setexpr fw_sz ${fw_sz} + 1;" \ - "mmc dev ${mmcfactorydev};" \ - "mmc write ${loadaddr} 0x0 ${fw_sz};" \ - "fi\0" \ - "factory_nor_img="\ - "echo 'Update mccmon6 NOR image'; " \ - "if load mmc ${mmcdev}:${mmcfactorypart} " \ - "${nor_img_addr} ${nor_img_file}; then " \ - "run nor_update;" \ - "fi\0" \ - "nor_update=" \ - "protect off ${nor_bank_start} +${nor_img_size};" \ - "erase ${nor_bank_start} +${nor_img_size};" \ - "setexpr nor_img_size ${nor_img_size} / 4; " \ - "cp.l ${nor_img_addr} ${nor_bank_start} ${nor_img_size}\0" \ - "tftp_nor_uboot="\ - "echo 'Update mccmon6 NOR U-BOOT via TFTP'; " \ - "setenv nor_img_file u-boot.img; " \ - "setenv nor_img_size 0x80000; " \ - "setenv nor_bank_start 0x08080000; " \ - "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ - "run nor_update;" \ - "fi\0" \ - "tftp_nor_uImg="\ - "echo 'Update mccmon6 NOR uImage via TFTP'; " \ - "setenv nor_img_file uImage; " \ - "setenv nor_img_size 0x500000; " \ - "setenv nor_bank_start 0x08180000; " \ - "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ - "run nor_update;" \ - "fi\0" \ - "tftp_nor_dtb="\ - "echo 'Update mccmon6 NOR DTB via TFTP'; " \ - "setenv nor_img_file imx6q-mccmon6.dtb; " \ - "setenv nor_img_size 0x20000; " \ - "setenv nor_bank_start 0x09980000; " \ - "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ - "run nor_update;" \ - "fi\0" \ - "tftp_nor_img="\ - "echo 'Update mccmon6 NOR image via TFTP'; " \ - "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ - "run nor_update;" \ - "fi\0" \ - "tftp_nor_SPL="\ - "if tftp ${load_addr} SPL_padded; then " \ - "erase 0x08000000 +0x20000;" \ - "cp.b ${load_addr} 0x08000000 0x20000;" \ - "fi;\0" \ - "tftp_sd_SPL="\ - "if mmc dev 1; then " \ - "if tftp ${load_addr} ${SPL_file}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${load_addr} 0x2 ${fw_sz};" \ - "fi;" \ - "fi;\0" \ - "tftp_sd_uboot="\ - "if mmc dev 1; then " \ - "if run load_uboot; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${load_addr} 0x8A ${fw_sz};" \ - "fi;" \ - "fi;\0" - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE (SZ_128K) - -/* Envs are stored in NOR flash */ -#define CONFIG_ENV_SECT_SIZE (SZ_128K) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) - -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x60000) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#endif /* __CONFIG_H * */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-at91/Kconfig | 1 - board/bluewater/gurnard/Kconfig | 12 - board/bluewater/gurnard/MAINTAINERS | 6 - board/bluewater/gurnard/Makefile | 9 - board/bluewater/gurnard/gurnard.c | 423 ---- board/bluewater/gurnard/splash_logo.h | 2619 ------------------------- configs/gurnard_defconfig | 38 - include/configs/snapper9g45.h | 112 -- 8 files changed, 3220 deletions(-) delete mode 100644 board/bluewater/gurnard/Kconfig delete mode 100644 board/bluewater/gurnard/MAINTAINERS delete mode 100644 board/bluewater/gurnard/Makefile delete mode 100644 board/bluewater/gurnard/gurnard.c delete mode 100644 board/bluewater/gurnard/splash_logo.h delete mode 100644 configs/gurnard_defconfig delete mode 100644 include/configs/snapper9g45.h

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index a6329dc0220..0fe93263ba8 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -278,7 +278,6 @@ source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" source "board/atmel/sama5d4_xplained/Kconfig" source "board/atmel/sama5d4ek/Kconfig" -source "board/bluewater/gurnard/Kconfig" source "board/bluewater/snapper9260/Kconfig" source "board/calao/usb_a9263/Kconfig" source "board/egnite/ethernut5/Kconfig" diff --git a/board/bluewater/gurnard/Kconfig b/board/bluewater/gurnard/Kconfig deleted file mode 100644 index e2cd9f00df8..00000000000 --- a/board/bluewater/gurnard/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_GURNARD - -config SYS_BOARD - default "gurnard" - -config SYS_VENDOR - default "bluewater" - -config SYS_CONFIG_NAME - default "snapper9g45" - -endif diff --git a/board/bluewater/gurnard/MAINTAINERS b/board/bluewater/gurnard/MAINTAINERS deleted file mode 100644 index 5e546d43fb4..00000000000 --- a/board/bluewater/gurnard/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -GURNARD BOARD -M: Simon Glass sjg@chromium.org -S: Maintained -F: board/bluewater/gurnard/ -F: include/configs/snapper9g45.h -F: configs/gurnard_defconfig diff --git a/board/bluewater/gurnard/Makefile b/board/bluewater/gurnard/Makefile deleted file mode 100644 index 8218e2cd58b..00000000000 --- a/board/bluewater/gurnard/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2011 Bluewater Systems -# Ryan Mallon ryan@bluewatersys.com - -obj-y += gurnard.o diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c deleted file mode 100644 index 3cda2fafab2..00000000000 --- a/board/bluewater/gurnard/gurnard.c +++ /dev/null @@ -1,423 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Bluewater Systems Snapper 9260/9G20 modules - * - * (C) Copyright 2011 Bluewater Systems - * Author: Andre Renaud andre@bluewatersys.com - * Author: Ryan Mallon ryan@bluewatersys.com - */ - -#include <common.h> -#include <atmel_lcd.h> -#include <atmel_lcdc.h> -#include <atmel_mci.h> -#include <dm.h> -#include <lcd.h> -#include <net.h> -#ifndef CONFIG_DM_ETH -#include <netdev.h> -#endif -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/mach-types.h> -#include <asm/arch/at91sam9g45_matrix.h> -#include <asm/arch/at91sam9_smc.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_emac.h> -#include <asm/arch/at91_rstc.h> -#include <asm/arch/at91_rtc.h> -#include <asm/arch/at91_sck.h> -#include <asm/arch/atmel_serial.h> -#include <asm/arch/clk.h> -#include <asm/arch/gpio.h> -#include <dm/uclass-internal.h> - -#ifdef CONFIG_GURNARD_SPLASH -#include "splash_logo.h" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* IO Expander pins */ -#define IO_EXP_ETH_RESET (0 << 1) -#define IO_EXP_ETH_POWER (1 << 1) - -#ifdef CONFIG_MACB -static void gurnard_macb_hw_init(void) -{ - struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - - at91_periph_clk_enable(ATMEL_ID_EMAC); - - /* - * Enable pull-up on: - * RXDV (PA12) => MODE0 - PHY also has pull-up - * ERX0 (PA13) => MODE1 - PHY also has pull-up - * ERX1 (PA15) => MODE2 - PHY also has pull-up - */ - writel(pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA12) | - pin_to_mask(AT91_PIN_PA13), - &pioa->puer); - - at91_phy_reset(); - - at91_macb_hw_init(); -} -#endif - -#ifdef CONFIG_CMD_NAND -static int gurnard_nand_hw_init(void) -{ - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - ulong flags; - int ret; - - /* Enable CS3 as NAND/SmartMedia */ - setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | - AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), - &smc->cs[3].cycle); -#ifdef CONFIG_SYS_NAND_DBW_16 - flags = AT91_SMC_MODE_DBW_16; -#else - flags = AT91_SMC_MODE_DBW_8; -#endif - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - flags | - AT91_SMC_MODE_TDF_CYCLE(3), - &smc->cs[3].mode); - - ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy"); - if (ret) - return ret; - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); - - /* Enable NandFlash */ - ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce"); - if (ret) - return ret; - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); - - return 0; -} -#endif - -#ifdef CONFIG_GURNARD_SPLASH -static void lcd_splash(int width, int height) -{ - u16 colour; - int x, y; - u16 *base_addr = (u16 *)gd->video_bottom; - - memset(base_addr, 0xff, width * height * 2); - /* - * Blit the logo to the center of the screen - */ - for (y = 0; y < BMP_LOGO_HEIGHT; y++) { - for (x = 0; x < BMP_LOGO_WIDTH; x++) { - int posx, posy; - colour = bmp_logo_palette[bmp_logo_bitmap[ - y * BMP_LOGO_WIDTH + x]]; - posx = x + (width - BMP_LOGO_WIDTH) / 2; - posy = y; - base_addr[posy * width + posx] = colour; - } - } -} -#endif - -#ifdef CONFIG_DM_VIDEO -static void at91sam9g45_lcd_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ - at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ - at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ - at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ - at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ - - at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ - at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ - at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ - at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ - at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ - at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ - at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ - at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ - at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ - at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ - at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ - at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ - at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ - at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ - at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ - at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ - at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ - at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ - at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ - at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ - at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ - at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ - at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ - at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ - - at91_periph_clk_enable(ATMEL_ID_LCDC); -} -#endif - -#ifdef CONFIG_GURNARD_FPGA -/** - * Initialise the memory bus settings so that we can talk to the - * memory mapped FPGA - */ -static int fpga_hw_init(void) -{ - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - int i; - - setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS1A_SDRAMC); - - at91_set_a_periph(2, 4, 0); /* EBIA21 */ - at91_set_a_periph(2, 5, 0); /* EBIA22 */ - at91_set_a_periph(2, 6, 0); /* EBIA23 */ - at91_set_a_periph(2, 7, 0); /* EBIA24 */ - at91_set_a_periph(2, 12, 0); /* EBIA25 */ - for (i = 15; i <= 31; i++) /* EBINWAIT & EBID16 - 31 */ - at91_set_a_periph(2, i, 0); - - /* configure SMC cs0 for FPGA access timing */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(2) | - AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(2), - &smc->cs[0].setup); - writel(AT91_SMC_PULSE_NWE(5) | AT91_SMC_PULSE_NCS_WR(4) | - AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(4), - &smc->cs[0].pulse); - writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6), - &smc->cs[0].cycle); - writel(AT91_SMC_MODE_BAT | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_32 | - AT91_SMC_MODE_TDF | - AT91_SMC_MODE_TDF_CYCLE(2), - &smc->cs[0].mode); - - /* Do a write to within EBI_CS1 to enable the SDCK */ - writel(0, ATMEL_BASE_CS1); - - return 0; -} -#endif - -#ifdef CONFIG_CMD_USB - -#define USB0_ENABLE_PIN AT91_PIN_PB22 -#define USB1_ENABLE_PIN AT91_PIN_PB23 - -void gurnard_usb_init(void) -{ - at91_set_gpio_output(USB0_ENABLE_PIN, 1); - at91_set_gpio_value(USB0_ENABLE_PIN, 0); - at91_set_gpio_output(USB1_ENABLE_PIN, 1); - at91_set_gpio_value(USB1_ENABLE_PIN, 0); -} -#endif - -#ifdef CONFIG_GENERIC_ATMEL_MCI -int cpu_mmc_init(bd_t *bis) -{ - return atmel_mci_init((void *)ATMEL_BASE_MCI0); -} -#endif - -static void gurnard_enable_console(int enable) -{ - at91_set_gpio_output(AT91_PIN_PB14, 1); - at91_set_gpio_value(AT91_PIN_PB14, enable ? 0 : 1); -} - -void at91sam9g45_slowclock_init(void) -{ - /* - * On AT91SAM9G45 revC CPUs, the slow clock can be based on an - * internal impreciseRC oscillator or an external 32kHz oscillator. - * Switch to the latter. - */ - unsigned i, tmp; - ulong *reg = (ulong *)ATMEL_BASE_SCKCR; - - tmp = readl(reg); - if ((tmp & AT91SAM9G45_SCKCR_OSCSEL) == AT91SAM9G45_SCKCR_OSCSEL_RC) { - timer_init(); - tmp |= AT91SAM9G45_SCKCR_OSC32EN; - writel(tmp, reg); - for (i = 0; i < 1200; i++) - udelay(1000); - tmp |= AT91SAM9G45_SCKCR_OSCSEL_32; - writel(tmp, reg); - udelay(200); - tmp &= ~AT91SAM9G45_SCKCR_RCEN; - writel(tmp, reg); - } -} - -int board_early_init_f(void) -{ - at91_seriald_hw_init(); - gurnard_enable_console(1); - - return 0; -} - -int board_init(void) -{ - const char *rev_str; -#ifdef CONFIG_CMD_NAND - int ret; -#endif - - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - at91_periph_clk_enable(ATMEL_ID_PIODE); - - at91sam9g45_slowclock_init(); - - /* - * Clear the RTC IDR to disable all IRQs. Avoid issues when Linux - * boots with spurious IRQs. - */ - writel(0xffffffff, AT91_RTC_IDR); - - /* Make sure that the reset signal is attached properly */ - setbits_le32(AT91_ASM_RSTC_MR, AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN); - - gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260; - - /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - -#ifdef CONFIG_CMD_NAND - ret = gurnard_nand_hw_init(); - if (ret) - return ret; -#endif -#ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 4); -#endif - -#ifdef CONFIG_MACB - gurnard_macb_hw_init(); -#endif - -#ifdef CONFIG_GURNARD_FPGA - fpga_hw_init(); -#endif - -#ifdef CONFIG_CMD_USB - gurnard_usb_init(); -#endif - -#ifdef CONFIG_CMD_MMC - at91_set_A_periph(AT91_PIN_PA12, 0); - at91_set_gpio_output(AT91_PIN_PA8, 1); - at91_set_gpio_value(AT91_PIN_PA8, 0); - at91_mci_hw_init(); -#endif - -#ifdef CONFIG_DM_VIDEO - at91sam9g45_lcd_hw_init(); - at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ - - /* Select the second timing index for board rev 2 */ - rev_str = env_get("board_rev"); - if (rev_str && !strncmp(rev_str, "2", 1)) { - struct udevice *dev; - - uclass_find_first_device(UCLASS_VIDEO, &dev); - if (dev) { - struct atmel_lcd_platdata *plat = dev_get_platdata(dev); - - plat->timing_index = 1; - } - } -#endif - - return 0; -} - -int board_late_init(void) -{ - u_int8_t env_enetaddr[8]; - char *env_str; - char *end; - int i; - - /* - * Set MAC address so we do not need to init Ethernet before Linux - * boot - */ - env_str = env_get("ethaddr"); - if (env_str) { - struct at91_emac *emac = (struct at91_emac *)ATMEL_BASE_EMAC; - /* Parse MAC address */ - for (i = 0; i < 6; i++) { - env_enetaddr[i] = env_str ? - simple_strtoul(env_str, &end, 16) : 0; - if (env_str) - env_str = (*end) ? end+1 : end; - } - - /* Set hardware address */ - writel(env_enetaddr[0] | env_enetaddr[1] << 8 | - env_enetaddr[2] << 16 | env_enetaddr[3] << 24, - &emac->sa2l); - writel((env_enetaddr[4] | env_enetaddr[5] << 8), &emac->sa2h); - - printf("MAC: %s\n", env_get("ethaddr")); - } else { - /* Not set in environment */ - printf("MAC: not set\n"); - } -#ifdef CONFIG_GURNARD_SPLASH - lcd_splash(480, 272); -#endif - - return 0; -} - -#ifndef CONFIG_DM_ETH -int board_eth_init(bd_t *bis) -{ - return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0); -} -#endif - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -void reset_phy(void) -{ -} - -static struct atmel_serial_platdata at91sam9260_serial_plat = { - .base_addr = ATMEL_BASE_DBGU, -}; - -U_BOOT_DEVICE(at91sam9260_serial) = { - .name = "serial_atmel", - .platdata = &at91sam9260_serial_plat, -}; diff --git a/board/bluewater/gurnard/splash_logo.h b/board/bluewater/gurnard/splash_logo.h deleted file mode 100644 index fb87dea86cf..00000000000 --- a/board/bluewater/gurnard/splash_logo.h +++ /dev/null @@ -1,2619 +0,0 @@ -/* generated by ppm_logo (c) 2004 by Andre Renaud from logo_gurnard_small.ppm*/ -#ifndef __BMP_LOGO_H__ -#define __BMP_LOGO_H__ -#define BMP_LOGO_WIDTH 187 -#define BMP_LOGO_HEIGHT 139 -#define BMP_LOGO_COLORS 255 -#define BMP_LOGO_OFFSET 50 - -unsigned short bmp_logo_palette[] = { - 0xb61a, 0x9d78, 0xdefc, 0xffff, 0x7455, 0x32b1, 0xb5fa, 0xe75e, - 0xffdf, 0xc65b, 0x9538, 0xd6dc, 0xce9b, 0xf7df, 0xadb9, 0x84d7, - 0xffff, 0xffff, 0xffdf, 0x5bb4, 0x4b11, 0x3ad1, 0xf7bf, 0xf7bf, - 0xffff, 0xffff, 0xf79e, 0xef9e, 0x6c35, 0xef7e, 0xe75d, 0xdf1d, - 0xdf1c, 0xf7df, 0xde9a, 0xed96, 0xe6fb, 0xdb4d, 0xc945, 0xe410, - 0xffdf, 0xc965, 0xc986, 0xd2aa, 0xe451, 0xed14, 0xef5d, 0xffbe, - 0xffff, 0xef3c, }; - -unsigned char bmp_logo_bitmap[] = { - 0x0000, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, - 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, - 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, - 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, - 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, - 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, - 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0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, - 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, - 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, - 0x002d, 0x0022, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x001f, - 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, - 0x000e, 0x000e, 0x0009, }; -#endif diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig deleted file mode 100644 index 3c3537a77b5..00000000000 --- a/configs/gurnard_defconfig +++ /dev/null @@ -1,38 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_SYS_TEXT_BASE=0x73f00000 -CONFIG_TARGET_GURNARD=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45" -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_PART=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_NAND=y -CONFIG_NAND_ATMEL=y -CONFIG_PHYLIB=y -CONFIG_TIMER=y -CONFIG_ATMEL_PIT_TIMER=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_DM_VIDEO=y -CONFIG_CMD_DHRYSTONE=y -# CONFIG_EFI_LOADER is not set diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h deleted file mode 100644 index f2c47dabc5c..00000000000 --- a/include/configs/snapper9g45.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Bluewater Systems Snapper 9G45 module - * - * (C) Copyright 2011 Bluewater Systems - * Author: Andre Renaud andre@bluewatersys.com - * Author: Ryan Mallon ryan@bluewatersys.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* SoC type is defined in boards.cfg */ -#include <asm/hardware.h> -#include <linux/sizes.h> - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 - -/* CPU */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 -#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) - -/* Mem test settings */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) - -/* NAND Flash */ -#define CONFIG_ATMEL_NAND_HWECC -#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R -#define CONFIG_AT91_WANTS_COMMON_PHY -#define CONFIG_TFTP_PORT -#define CONFIG_TFTP_TSIZE - -/* MMC */ -#define CONFIG_GENERIC_ATMEL_MCI - -/* LCD */ -#define CONFIG_ATMEL_LCD -#define CONFIG_GURNARD_SPLASH - -/* GPIOs and IO expander */ -#define CONFIG_ATMEL_LEGACY -#define CONFIG_AT91_GPIO -#define CONFIG_AT91_GPIO_PULLUP 1 - -/* UARTs/Serial console */ -#define CONFIG_ATMEL_USART - -/* Boot options */ -#define CONFIG_SYS_LOAD_ADDR 0x23000000 - -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Environment settings */ -#define CONFIG_ENV_OFFSET (512 << 10) -#define CONFIG_ENV_SIZE (256 << 10) -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ethaddr=00:00:00:00:00:00\0" \ - "serial=0\0" \ - "stdout=serial_atmel\0" \ - "stderr=serial_atmel\0" \ - "stdin=serial_atmel\0" \ - "bootlimit=3\0" \ - "loadaddr=0x71000000\0" \ - "board_rev=2\0" \ - "bootfile=/tftpboot/uImage\0" \ - "bootargs_def=console=ttyS0,115200 panic=5 quiet lpj=997376\0" \ - "nfsroot=/export/root\0" \ - "boot_working=setenv bootargs $bootargs_def; nboot $loadaddr 0 0x20c0000 && bootm\0" \ - "boot_safe=setenv bootargs $bootargs_def; nboot $loadaddr 0 0xc0000 && bootm\0" \ - "boot_tftp=setenv bootargs $bootargs_def ip=any nfsroot=$nfsroot; setenv autoload y && bootp && bootm\0" \ - "boot_usb=setenv bootargs $bootargs_def; usb start && usb storage && fatload usb 0:1 $loadaddr dds-xm200.bin && bootm\0" \ - "boot_mmc=setenv bootargs $bootargs_def; mmc rescan && fatload mmc 0:1 $loadaddr dds-xm200.bin && bootm\0" \ - "bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" \ - "altbootcmd=run boot_mmc ; run boot_usb ; run boot_safe ; run boot_working\0" - -/* Console settings */ - -/* U-Boot memory settings */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) - -/* Command line configuration */ -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_CACHE - -#endif /* __CONFIG_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-imx/mx6/Kconfig | 1 - board/udoo/neo/Kconfig | 12 - board/udoo/neo/MAINTAINERS | 7 - board/udoo/neo/Makefile | 4 - board/udoo/neo/neo.c | 595 ---------------------------------- configs/udoo_neo_defconfig | 33 -- include/configs/udoo_neo.h | 106 ------ 7 files changed, 758 deletions(-) delete mode 100644 board/udoo/neo/Kconfig delete mode 100644 board/udoo/neo/MAINTAINERS delete mode 100644 board/udoo/neo/Makefile delete mode 100644 board/udoo/neo/neo.c delete mode 100644 configs/udoo_neo_defconfig delete mode 100644 include/configs/udoo_neo.h

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 3f0d27b76dd..8169bfb18e6 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -558,7 +558,6 @@ source "board/tqc/tqma6/Kconfig" source "board/toradex/colibri-imx6ull/Kconfig" source "board/k+p/kp_imx6q_tpc/Kconfig" source "board/udoo/Kconfig" -source "board/udoo/neo/Kconfig" source "board/warp/Kconfig"

endif diff --git a/board/udoo/neo/Kconfig b/board/udoo/neo/Kconfig deleted file mode 100644 index 8f474df2487..00000000000 --- a/board/udoo/neo/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_UDOO_NEO - -config SYS_VENDOR - default "udoo" - -config SYS_BOARD - default "neo" - -config SYS_CONFIG_NAME - default "udoo_neo" - -endif diff --git a/board/udoo/neo/MAINTAINERS b/board/udoo/neo/MAINTAINERS deleted file mode 100644 index 743fe33d059..00000000000 --- a/board/udoo/neo/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -UDOO NEO BOARD -M: Breno Lima breno.lima@nxp.com -M: Francesco Montefoschi francesco.montefoschi@udoo.org -S: Maintained -F: board/udoo/neo/ -F: include/configs/udoo_neo.h -F: configs/udoo_neo_defconfig diff --git a/board/udoo/neo/Makefile b/board/udoo/neo/Makefile deleted file mode 100644 index 831c084ce59..00000000000 --- a/board/udoo/neo/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# (C) Copyright 2015 UDOO Team - -obj-y := neo.o diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c deleted file mode 100644 index 828161360cb..00000000000 --- a/board/udoo/neo/neo.c +++ /dev/null @@ -1,595 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. - * Copyright (C) Jasbir Matharu - * Copyright (C) UDOO Team - * - * Author: Breno Lima breno.lima@nxp.com - * Author: Francesco Montefoschi francesco.monte@gmail.com - */ - -#include <asm/arch/clock.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <mmc.h> -#include <fsl_esdhc.h> -#include <asm/arch/crm_regs.h> -#include <asm/io.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/arch/sys_proto.h> -#include <spl.h> -#include <linux/sizes.h> -#include <common.h> -#include <i2c.h> -#include <miiphy.h> -#include <netdev.h> -#include <power/pmic.h> -#include <power/pfuze3000_pmic.h> -#include <malloc.h> - -DECLARE_GLOBAL_DATA_PTR; - -enum { - UDOO_NEO_TYPE_BASIC, - UDOO_NEO_TYPE_BASIC_KS, - UDOO_NEO_TYPE_FULL, - UDOO_NEO_TYPE_EXTENDED, -}; - -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) - -#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm) - -#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) -#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \ - MUX_MODE_SION) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - return 0; -} - -#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, - .gp = IMX_GPIO_NR(1, 0), - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, - .gp = IMX_GPIO_NR(1, 1), - }, -}; -#endif - -#ifdef CONFIG_POWER -int power_init_board(void) -{ - struct pmic *p; - int ret; - unsigned int reg, rev_id; - - ret = power_pfuze3000_init(PFUZE3000_I2C_BUS); - if (ret) - return ret; - - p = pmic_get("PFUZE3000"); - ret = pmic_probe(p); - if (ret) - return ret; - - pmic_reg_read(p, PFUZE3000_DEVICEID, &reg); - pmic_reg_read(p, PFUZE3000_REVID, &rev_id); - printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); - - /* disable Low Power Mode during standby mode */ - pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg); - reg |= 0x1; - ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); - if (ret) - return ret; - - ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc); - if (ret) - return ret; - - ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc); - if (ret) - return ret; - - ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc); - if (ret) - return ret; - - ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc); - if (ret) - return ret; - - /* set SW1A standby voltage 0.975V */ - pmic_reg_read(p, PFUZE3000_SW1ASTBY, &reg); - reg &= ~0x3f; - reg |= PFUZE3000_SW1AB_SETP(9750); - ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); - if (ret) - return ret; - - /* set SW1B standby voltage 0.975V */ - pmic_reg_read(p, PFUZE3000_SW1BSTBY, &reg); - reg &= ~0x3f; - reg |= PFUZE3000_SW1AB_SETP(9750); - ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); - if (ret) - return ret; - - /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE3000_SW1ACONF, &reg); - reg &= ~0xc0; - reg |= 0x40; - ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg); - if (ret) - return ret; - - /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE3000_SW1BCONF, &reg); - reg &= ~0xc0; - reg |= 0x40; - ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg); - if (ret) - return ret; - - /* set VDD_ARM_IN to 1.350V */ - pmic_reg_read(p, PFUZE3000_SW1AVOLT, &reg); - reg &= ~0x3f; - reg |= PFUZE3000_SW1AB_SETP(13500); - ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg); - if (ret) - return ret; - - /* set VDD_SOC_IN to 1.350V */ - pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg); - reg &= ~0x3f; - reg |= PFUZE3000_SW1AB_SETP(13500); - ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); - if (ret) - return ret; - - /* set DDR_1_5V to 1.350V */ - pmic_reg_read(p, PFUZE3000_SW3VOLT, &reg); - reg &= ~0x0f; - reg |= PFUZE3000_SW3_SETP(13500); - ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg); - if (ret) - return ret; - - /* set VGEN2_1V5 to 1.5V */ - pmic_reg_read(p, PFUZE3000_VLDO2CTL, &reg); - reg &= ~0x0f; - reg |= PFUZE3000_VLDO_SETP(15000); - /* enable */ - reg |= 0x10; - ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg); - if (ret) - return ret; - - return 0; -} -#endif - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - /* CD pin */ - MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* Power */ - MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const fec1_pads[] = { - MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static iomux_v3_cfg_t const phy_control_pads[] = { - /* 25MHz Ethernet PHY Clock */ - MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | - MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), -}; - -static iomux_v3_cfg_t const board_recognition_pads[] = { - /*Connected to R184*/ - MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG, - /*Connected to R185*/ - MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG, -}; - -static iomux_v3_cfg_t const wdog_b_pad = { - MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - -static iomux_v3_cfg_t const peri_3v3_pads[] = { - MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -static int setup_fec(int fec_id) -{ - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int reg; - - imx_iomux_v3_setup_multiple_pads(phy_control_pads, - ARRAY_SIZE(phy_control_pads)); - - /* Reset PHY */ - gpio_direction_output(IMX_GPIO_NR(2, 1) , 0); - udelay(10000); - gpio_set_value(IMX_GPIO_NR(2, 1), 1); - udelay(100); - - reg = readl(&anatop->pll_enet); - reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; - writel(reg, &anatop->pll_enet); - - return enable_fec_anatop_clock(fec_id, ENET_25MHZ); -} - -int board_eth_init(bd_t *bis) -{ - uint32_t base = IMX_FEC_BASE; - struct mii_dev *bus = NULL; - struct phy_device *phydev = NULL; - int ret; - - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - - setup_fec(CONFIG_FEC_ENET_DEV); - - bus = fec_get_miibus(base, CONFIG_FEC_ENET_DEV); - if (!bus) - return -EINVAL; - - phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR), - PHY_INTERFACE_MODE_RMII); - if (!phydev) { - free(bus); - return -EINVAL; - } - - ret = fec_probe(bis, CONFIG_FEC_ENET_DEV, base, bus, phydev); - if (ret) { - free(bus); - free(phydev); - return ret; - } - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_init(void) -{ - /* Address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - /* - * Because kernel set WDOG_B mux before pad with the commone pinctrl - * framwork now and wdog reset will be triggered once set WDOG_B mux - * with default pad setting, we set pad setting here to workaround this. - * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set - * as GPIO mux firstly here to workaround it. - */ - imx_iomux_v3_setup_pad(wdog_b_pad); - - /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ - imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, - ARRAY_SIZE(peri_3v3_pads)); - - /* Active high for ncp692 */ - gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); - -#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); -#endif - - return 0; -} - -static int get_board_value(void) -{ - int r184, r185; - - imx_iomux_v3_setup_multiple_pads(board_recognition_pads, - ARRAY_SIZE(board_recognition_pads)); - - gpio_direction_input(IMX_GPIO_NR(4, 13)); - gpio_direction_input(IMX_GPIO_NR(4, 0)); - - r184 = gpio_get_value(IMX_GPIO_NR(4, 13)); - r185 = gpio_get_value(IMX_GPIO_NR(4, 0)); - - /* - * Machine selection - - * Machine r184, r185 - * --------------------------------- - * Basic 0 0 - * Basic Ks 0 1 - * Full 1 0 - * Extended 1 1 - */ - - return (r184 << 1) + r185; -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC2_BASE_ADDR, 0, 4}, -}; - -#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1) -#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2) - -int board_mmc_getcd(struct mmc *mmc) -{ - return !gpio_get_value(USDHC2_CD_GPIO); -} - -int board_mmc_init(bd_t *bis) -{ - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; - gpio_direction_input(USDHC2_CD_GPIO); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - -static char *board_string(void) -{ - switch (get_board_value()) { - case UDOO_NEO_TYPE_BASIC: - return "BASIC"; - case UDOO_NEO_TYPE_BASIC_KS: - return "BASICKS"; - case UDOO_NEO_TYPE_FULL: - return "FULL"; - case UDOO_NEO_TYPE_EXTENDED: - return "EXTENDED"; - } - return "UNDEFINED"; -} - -int checkboard(void) -{ - printf("Board: UDOO Neo %s\n", board_string()); - return 0; -} - -int board_late_init(void) -{ -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", board_string()); -#endif - - return 0; -} - -#ifdef CONFIG_SPL_BUILD - -#include <linux/libfdt.h> -#include <asm/arch/mx6-ddr.h> - -static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_dqm0 = 0x00000028, - .dram_dqm1 = 0x00000028, - .dram_dqm2 = 0x00000028, - .dram_dqm3 = 0x00000028, - .dram_ras = 0x00000020, - .dram_cas = 0x00000020, - .dram_odt0 = 0x00000020, - .dram_odt1 = 0x00000020, - .dram_sdba2 = 0x00000000, - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - .dram_sdclk_0 = 0x00000030, - .dram_sdqs0 = 0x00000028, - .dram_sdqs1 = 0x00000028, - .dram_sdqs2 = 0x00000028, - .dram_sdqs3 = 0x00000028, - .dram_reset = 0x00000020, -}; - -static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { - .grp_addds = 0x00000020, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000028, - .grp_b1ds = 0x00000028, - .grp_ctlds = 0x00000020, - .grp_ddr_type = 0x000c0000, - .grp_b2ds = 0x00000028, - .grp_b3ds = 0x00000028, -}; - -static const struct mx6_mmdc_calibration neo_mmcd_calib = { - .p0_mpwldectrl0 = 0x000E000B, - .p0_mpwldectrl1 = 0x000E0010, - .p0_mpdgctrl0 = 0x41600158, - .p0_mpdgctrl1 = 0x01500140, - .p0_mprddlctl = 0x3A383E3E, - .p0_mpwrdlctl = 0x3A383C38, -}; - -static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = { - .p0_mpwldectrl0 = 0x001E0022, - .p0_mpwldectrl1 = 0x001C0019, - .p0_mpdgctrl0 = 0x41540150, - .p0_mpdgctrl1 = 0x01440138, - .p0_mprddlctl = 0x403E4644, - .p0_mpwrdlctl = 0x3C3A4038, -}; - -/* MT41K256M16 */ -static struct mx6_ddr3_cfg neo_mem_ddr = { - .mem_speed = 1600, - .density = 4, - .width = 16, - .banks = 8, - .rowaddr = 15, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -/* MT41K128M16 */ -static struct mx6_ddr3_cfg neo_basic_mem_ddr = { - .mem_speed = 1600, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0xFFFFFFFF, &ccm->CCGR0); - writel(0xFFFFFFFF, &ccm->CCGR1); - writel(0xFFFFFFFF, &ccm->CCGR2); - writel(0xFFFFFFFF, &ccm->CCGR3); - writel(0xFFFFFFFF, &ccm->CCGR4); - writel(0xFFFFFFFF, &ccm->CCGR5); - writel(0xFFFFFFFF, &ccm->CCGR6); - writel(0xFFFFFFFF, &ccm->CCGR7); -} - -static void spl_dram_init(void) -{ - int board = get_board_value(); - - struct mx6_ddr_sysinfo sysinfo = { - .dsize = 1, /* width of data bus: 1 = 32 bits */ - .cs_density = 24, - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 2, - .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - }; - - mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); - if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS) - mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib, - &neo_basic_mem_ddr); - else - mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr); -} - -void board_init_f(ulong dummy) -{ - ccgr_init(); - - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* DDR initialization */ - spl_dram_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} - -#endif diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig deleted file mode 100644 index de0e03726b8..00000000000 --- a/configs/udoo_neo_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_UDOO_NEO=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y -# CONFIG_CMD_BMODE is not set -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_FSL_ESDHC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_MII=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h deleted file mode 100644 index 6ba4270b72d..00000000000 --- a/include/configs/udoo_neo.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014-2015 Freescale Semiconductor, Inc. - * Copyright Jasbir Matharu - * Copyright 2015 UDOO Team - * - * Configuration settings for the UDOO NEO board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#include "imx6_spl.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) -#define CONFIG_MXC_UART - -/* MMC Configuration */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR - -/* Command definition */ -#define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC2*/ - -/* Linux only */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc0,115200\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdtfile=undefined\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_addr_r=0x83000000\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcrootfstype=ext4\0" \ - "findfdt="\ - "if test $board_name = BASIC; then " \ - "setenv fdtfile imx6sx-udoo-neo-basic.dtb; fi; " \ - "if test $board_name = BASICKS; then " \ - "setenv fdtfile imx6sx-udoo-neo-basic.dtb; fi; " \ - "if test $board_name = FULL; then " \ - "setenv fdtfile imx6sx-udoo-neo-full.dtb; fi; " \ - "if test $board_name = EXTENDED; then " \ - "setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \ - "if test $fdtfile = UNDEFINED; then " \ - "echo WARNING: Could not determine dtb to use; fi\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "ramdisk_addr_r=0x84000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) - -#include <config_distro_bootcmd.h> - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_OFFSET (8 * SZ_64K) -#define CONFIG_ENV_SIZE SZ_8K - -#define CONFIG_IMX_THERMAL - -/* I2C configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE3000 -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 -#define PFUZE3000_I2C_BUS 0 - -/* Network */ -#define CONFIG_FEC_MXC - -#define CONFIG_FEC_ENET_DEV 0 -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x0 - -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC0" - -#endif /* __CONFIG_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/Kconfig | 1 - board/eets/pdu001/Kconfig | 50 ------ board/eets/pdu001/MAINTAINERS | 6 - board/eets/pdu001/Makefile | 13 -- board/eets/pdu001/README | 35 ---- board/eets/pdu001/board.c | 275 -------------------------------- board/eets/pdu001/board.h | 37 ----- board/eets/pdu001/mux.c | 119 -------------- configs/am335x_pdu001_defconfig | 53 ------ include/configs/pdu001.h | 86 ---------- 10 files changed, 675 deletions(-) delete mode 100644 board/eets/pdu001/Kconfig delete mode 100644 board/eets/pdu001/MAINTAINERS delete mode 100644 board/eets/pdu001/Makefile delete mode 100644 board/eets/pdu001/README delete mode 100644 board/eets/pdu001/board.c delete mode 100644 board/eets/pdu001/board.h delete mode 100644 board/eets/pdu001/mux.c delete mode 100644 configs/am335x_pdu001_defconfig delete mode 100644 include/configs/pdu001.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7389b8db46d..76f9977eda9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1501,7 +1501,6 @@ source "board/broadcom/bcmnsp/Kconfig" source "board/broadcom/bcmns2/Kconfig" source "board/cavium/thunderx/Kconfig" source "board/cirrus/edb93xx/Kconfig" -source "board/eets/pdu001/Kconfig" source "board/emulation/qemu-arm/Kconfig" source "board/freescale/ls2080a/Kconfig" source "board/freescale/ls2080aqds/Kconfig" diff --git a/board/eets/pdu001/Kconfig b/board/eets/pdu001/Kconfig deleted file mode 100644 index e64ae28875b..00000000000 --- a/board/eets/pdu001/Kconfig +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -if TARGET_PDU001 - -config SYS_BOARD - default "pdu001" - -config SYS_VENDOR - default "eets" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "pdu001" - -choice - prompt "State of Run LED" - default RUN_LED_RED - help - The PDU001 has a bi-color (red/green) LED labeled 'Run' which - can be used to indicate the operating state of the board. By - default it will be lit red by U-Boot. Later in the start-up - process it can be changed to green (or heartbeat or anything else) - by the kernel or some other software. - -config RUN_LED_RED - bool - prompt "Red" - help - Lit Run LED red. - -config RUN_LED_GREEN - bool - prompt "Green" - help - Lit Run LED green. - -config RUN_LED_OFF - bool - prompt "Off" - help - Do not lit Run LED. - -endchoice - -endif diff --git a/board/eets/pdu001/MAINTAINERS b/board/eets/pdu001/MAINTAINERS deleted file mode 100644 index 95295ddea9a..00000000000 --- a/board/eets/pdu001/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PDU001 BOARD -M: Felix Brack fb@ltec.ch -S: Maintained -F: board/eets/pdu001/ -F: include/configs/pdu001.h -F: configs/am335x_pdu001_defconfig diff --git a/board/eets/pdu001/Makefile b/board/eets/pdu001/Makefile deleted file mode 100644 index 08c6d536d36..00000000000 --- a/board/eets/pdu001/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Makefile -# -# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) -obj-y := mux.o -endif - -obj-y += board.o diff --git a/board/eets/pdu001/README b/board/eets/pdu001/README deleted file mode 100644 index 50e715446b6..00000000000 --- a/board/eets/pdu001/README +++ /dev/null @@ -1,35 +0,0 @@ -# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -Summary -======= - -This document covers the PDU001 target. - -Hardware -======== - -The PDU-001 (Processor and Display Unit) is a plugin card for 19" racks. It is -manufactured by EETS GmbH (https://www.eets.ch). The core of the board is a m2 -SOM from bytes at work (https://www.bytesatwork.ch) which in turn is based on -AM3352 SOC from TI (http://www.ti.com). - -Customization -============= - -As usual the console serial interface is set by CONFIG_CONS_INDEX. Best choice -is 4 here since UART3 is wired to the connector K2. -The Run LED on the PDU-001 can be turned on red by setting CONFIG_RUN_LED_RED -or green by setting CONFIG_RUN_LED_GREEN. Setting CONFIG_RUN_LED_OFF will turn -off the Run LED. - -Booting -======= - -The system boots from either eMMC or SD card cage. It will first try to boot -from the SD card cage. If this fails (missing or unbootable SD card) it will -try to boot from the internal eMMC. The root file system is always expected to -be located in the second partition of the device (eMMC or SD card) that pro- -vided the boot loader. diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c deleted file mode 100644 index b4b8081c90a..00000000000 --- a/board/eets/pdu001/board.c +++ /dev/null @@ -1,275 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * board.c - * - * Board functions for EETS PDU001 board - * - * Copyright (C) 2018, EETS GmbH, http://www.eets.ch/ - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#include <common.h> -#include <errno.h> -#include <spl.h> -#include <i2c.h> -#include <environment.h> -#include <watchdog.h> -#include <debug_uart.h> -#include <dm/ofnode.h> -#include <power/pmic.h> -#include <power/regulator.h> -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> -#include <asm/arch/omap.h> -#include <asm/arch/ddr_defs.h> -#include <asm/arch/clock.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mem.h> -#include <asm/io.h> -#include <asm/emif.h> -#include <asm/gpio.h> -#include "board.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define I2C_ADDR_NODE_ID 0x50 -#define I2C_REG_NODE_ID_BASE 0xfa -#define NODE_ID_BYTE_COUNT 6 - -#define I2C_ADDR_LEDS 0x60 -#define I2C_REG_RUN_LED 0x06 -#define RUN_LED_OFF 0x0 -#define RUN_LED_RED 0x1 -#define RUN_LED_GREEN (0x1 << 2) - -#define VDD_MPU_REGULATOR "regulator@2" -#define VDD_CORE_REGULATOR "regulator@3" -#define DEFAULT_CORE_VOLTAGE 1137500 - -/* - * boot device save register - * ------------------------- - * The boot device can be quired by 'spl_boot_device()' in - * 'am33xx_spl_board_init'. However it can't be saved in the u-boot - * environment here. In turn 'spl_boot_device' can't be called in - * 'board_late_init' which allows writing to u-boot environment. - * To get the boot device from 'am33xx_spl_board_init' to - * 'board_late_init' we therefore use a scratch register from the RTC. - */ -#define CONFIG_SYS_RTC_SCRATCH0 0x60 -#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0) - -#ifdef CONFIG_SPL_BUILD -static void save_boot_device(void) -{ - *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device(); -} -#endif - -u32 boot_device(void) -{ - return *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)); -} - -/* Store the boot device in the environment variable 'boot_device' */ -static void env_set_boot_device(void) -{ - switch (boot_device()) { - case BOOT_DEVICE_MMC1: { - env_set("boot_device", "emmc"); - break; - } - case BOOT_DEVICE_MMC2: { - env_set("boot_device", "sdcard"); - break; - } - default: { - env_set("boot_device", "unknown"); - break; - } - } -} - -static void set_run_led(struct udevice *dev) -{ - int val = RUN_LED_OFF; - - if (IS_ENABLED(CONFIG_RUN_LED_RED)) - val = RUN_LED_RED; - else if (IS_ENABLED(CONFIG_RUN_LED_GREEN)) - val = RUN_LED_GREEN; - - dm_i2c_reg_write(dev, I2C_REG_RUN_LED, val); -} - -/* Set 'serial#' to the EUI-48 value of board node ID chip */ -static void env_set_serial(struct udevice *dev) -{ - int val; - char serial[2 * NODE_ID_BYTE_COUNT + 1]; - int n; - - for (n = 0; n < sizeof(serial); n += 2) { - val = dm_i2c_reg_read(dev, I2C_REG_NODE_ID_BASE + n / 2); - sprintf(serial + n, "%02X", val); - } - serial[2 * NODE_ID_BYTE_COUNT] = '\0'; - env_set("serial#", serial); -} - -static void set_mpu_and_core_voltage(void) -{ - int mpu_vdd; - int sil_rev; - struct udevice *dev; - struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - - /* - * The PDU001 (more precisely the computing module m2) uses a - * TPS65910 PMIC. For all MPU frequencies we support we use a CORE - * voltage of 1.1375V. For MPU voltage we need to switch based on - * the frequency we are running at. - */ - - /* - * Depending on MPU clock and PG we will need a different VDD - * to drive at that speed. - */ - sil_rev = readl(&cdev->deviceid) >> 28; - mpu_vdd = am335x_get_mpu_vdd(sil_rev, dpll_mpu_opp100.m); - - /* first update the MPU voltage */ - if (!regulator_get_by_devname(VDD_MPU_REGULATOR, &dev)) { - if (regulator_set_value(dev, mpu_vdd)) - debug("failed to set MPU voltage\n"); - } else { - debug("invalid MPU voltage ragulator %s\n", VDD_MPU_REGULATOR); - } - - /* second update the CORE voltage */ - if (!regulator_get_by_devname(VDD_CORE_REGULATOR, &dev)) { - if (regulator_set_value(dev, DEFAULT_CORE_VOLTAGE)) - debug("failed to set CORE voltage\n"); - } else { - debug("invalid CORE voltage ragulator %s\n", - VDD_CORE_REGULATOR); - } -} - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -static const struct ddr_data ddr2_data = { - .datardsratio0 = MT47H128M16RT25E_RD_DQS, - .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, - .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, -}; - -static const struct cmd_control ddr2_cmd_ctrl_data = { - .cmd0csratio = MT47H128M16RT25E_RATIO, - .cmd1csratio = MT47H128M16RT25E_RATIO, - .cmd2csratio = MT47H128M16RT25E_RATIO, -}; - -static const struct emif_regs ddr2_emif_reg_data = { - .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, - .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, - .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, - .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, - .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, - .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, -}; - -#define OSC (V_OSCK / 1000000) -const struct dpll_params dpll_ddr = { - 266, OSC - 1, 1, -1, -1, -1, -1}; -const struct dpll_params dpll_ddr_evm_sk = { - 303, OSC - 1, 1, -1, -1, -1, -1}; -const struct dpll_params dpll_ddr_bone_black = { - 400, OSC - 1, 1, -1, -1, -1, -1}; - -void am33xx_spl_board_init(void) -{ - struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - - /* Get the frequency */ - dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); - - /* Set CORE Frequencies to OPP100 */ - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); - - /* Set MPU Frequency to what we detected now that voltages are set */ - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); - - /* save boot device for later use by 'board_late_init' */ - save_boot_device(); -} - -const struct dpll_params *get_dpll_ddr_params(void) -{ - enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - - return &dpll_ddr; -} - -void set_mux_conf_regs(void) -{ - /* done first by the ROM and afterwards by the pin controller driver */ - enable_i2c0_pin_mux(); -} - -const struct ctrl_ioregs ioregs = { - .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, -}; - -void sdram_init(void) -{ - config_ddr(266, &ioregs, &ddr2_data, - &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); -} -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#ifdef CONFIG_DEBUG_UART -void board_debug_uart_init(void) -{ - /* done by pin controller driver if not debugging */ - enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE); -} -#endif - -/* - * Basic board specific setup. Pinmux has been handled already. - */ -int board_init(void) -{ -#ifdef CONFIG_HW_WATCHDOG - hw_watchdog_init(); -#endif - - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - struct udevice *dev; - - set_mpu_and_core_voltage(); - env_set_boot_device(); - - /* second I2C bus connects to node ID and front panel LED chip */ - if (!i2c_get_chip_for_busnum(1, I2C_ADDR_LEDS, 1, &dev)) - set_run_led(dev); - if (!i2c_get_chip_for_busnum(1, I2C_ADDR_NODE_ID, 1, &dev)) - env_set_serial(dev); - - return 0; -} -#endif diff --git a/board/eets/pdu001/board.h b/board/eets/pdu001/board.h deleted file mode 100644 index bfea96e5f02..00000000000 --- a/board/eets/pdu001/board.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * board.h - * - * EETS GmbH PDU001 board information header - * - * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * We have two pin mux functions that must exist. First we need I2C0 to - * access the TPS65910 PMIC located on the M2 computing module. - * Second, if we want low-level debugging or a early UART (ie. before the - * pin controller driver is running), we need one of the UART ports UART0 to - * UART5 (usually UART3 since it is wired to K2). - * In case of I2C0 access we explicitly don't rely on the the ROM but we could - * do so as we use the primary mode (mode 0) for I2C0. - * All other multiplexing and pin configuration is done by the DT once it - * gets parsed by the pin controller driver. - * However we relay on the ROM to configure the pins of MMC0 (eMMC) as well - * as MMC1 (microSD card-cage) since these are our boot devices. - */ -void enable_uart0_pin_mux(void); -void enable_uart1_pin_mux(void); -void enable_uart2_pin_mux(void); -void enable_uart3_pin_mux(void); -void enable_uart4_pin_mux(void); -void enable_uart5_pin_mux(void); -void enable_uart_pin_mux(u32 addr); -void enable_i2c0_pin_mux(void); - -#endif diff --git a/board/eets/pdu001/mux.c b/board/eets/pdu001/mux.c deleted file mode 100644 index f1d38e9b74d..00000000000 --- a/board/eets/pdu001/mux.c +++ /dev/null @@ -1,119 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * mux.c - * - * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include <common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/hardware.h> -#include <asm/arch/mux.h> -#include <asm/io.h> -#include <i2c.h> -#include "board.h" - -static struct module_pin_mux uart0_pin_mux[] = { - {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ - {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ - {-1}, -}; - -static struct module_pin_mux uart1_pin_mux[] = { - {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ - {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ - {-1}, -}; - -static struct module_pin_mux uart2_pin_mux[] = { - {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ - {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ - {-1}, -}; - -static struct module_pin_mux uart3_pin_mux[] = { - {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ - {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ - {-1}, -}; - -static struct module_pin_mux uart4_pin_mux[] = { - {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ - {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ - {-1}, -}; - -static struct module_pin_mux uart5_pin_mux[] = { - {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ - {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ - {-1}, -}; - -static struct module_pin_mux i2c0_pin_mux[] = { - {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | - PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ - {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | - PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ - {-1}, -}; - -void enable_uart0_pin_mux(void) -{ - configure_module_pin_mux(uart0_pin_mux); -} - -void enable_uart1_pin_mux(void) -{ - configure_module_pin_mux(uart1_pin_mux); -} - -void enable_uart2_pin_mux(void) -{ - configure_module_pin_mux(uart2_pin_mux); -} - -void enable_uart3_pin_mux(void) -{ - configure_module_pin_mux(uart3_pin_mux); -} - -void enable_uart4_pin_mux(void) -{ - configure_module_pin_mux(uart4_pin_mux); -} - -void enable_uart5_pin_mux(void) -{ - configure_module_pin_mux(uart5_pin_mux); -} - -void enable_uart_pin_mux(u32 addr) -{ - switch (addr) { - case CONFIG_SYS_NS16550_COM1: - enable_uart0_pin_mux(); - break; - case CONFIG_SYS_NS16550_COM2: - enable_uart1_pin_mux(); - break; - case CONFIG_SYS_NS16550_COM3: - enable_uart2_pin_mux(); - break; - case CONFIG_SYS_NS16550_COM4: - enable_uart3_pin_mux(); - break; - case CONFIG_SYS_NS16550_COM5: - enable_uart4_pin_mux(); - break; - case CONFIG_SYS_NS16550_COM6: - enable_uart5_pin_mux(); - break; - } -} - -void enable_i2c0_pin_mux(void) -{ - configure_module_pin_mux(i2c0_pin_mux); -} diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig deleted file mode 100644 index 065efca633e..00000000000 --- a/configs/am335x_pdu001_defconfig +++ /dev/null @@ -1,53 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_AM33XX=y -CONFIG_TARGET_PDU001=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_LOCALVERSION="-EETS-1.0.0" -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTDELAY=1 -# CONFIG_USE_BOOTCOMMAND is not set -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set -CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_XIMG is not set -CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y -CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001" -# CONFIG_NET is not set -CONFIG_SPL_DM=y -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MMC_SDHCI=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_SINGLE=y -CONFIG_DM_PMIC=y -CONFIG_DM_PMIC_TPS65910=y -CONFIG_DM_REGULATOR=y -CONFIG_SPL_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_TPS65910=y -CONFIG_CONS_INDEX=4 -CONFIG_SPI=y -# CONFIG_USE_TINY_PRINTF is not set -# CONFIG_EFI_LOADER is not set diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h deleted file mode 100644 index 7b809e2329b..00000000000 --- a/include/configs/pdu001.h +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * pdu001.h - * - * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef __CONFIG_PDU001_H -#define __CONFIG_PDU001_H - -#include <configs/ti_am335x_common.h> - -/* No more need for I2C legacy compatibility for this board. - * CONFIG_DM_I2C_COMPAT is defined in ti_armv7_common.h. See the comment there - * for the right moment to delete the following line. - */ -#undef CONFIG_DM_I2C_COMPAT - -/* Using 32K of volatile storage for environment */ -#define CONFIG_ENV_SIZE 0x4000 - -#define MACH_TYPE_PDU001 5075 -#define CONFIG_MACH_TYPE MACH_TYPE_PDU001 -#define CONFIG_BOARD_LATE_INIT - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#if CONFIG_CONS_INDEX == 1 - #define CONSOLE_DEV "ttyO0" -#elif CONFIG_CONS_INDEX == 2 - #define CONSOLE_DEV "ttyO1" -#elif CONFIG_CONS_INDEX == 3 - #define CONSOLE_DEV "ttyO2" -#elif CONFIG_CONS_INDEX == 4 - #define CONSOLE_DEV "ttyO3" -#elif CONFIG_CONS_INDEX == 5 - #define CONSOLE_DEV "ttyO4" -#elif CONFIG_CONS_INDEX == 6 - #define CONSOLE_DEV "ttyO5" -#endif - -#define CONFIG_BOOTCOMMAND \ - "run eval_boot_device;" \ - "setenv bootargs console=${console} " \ - "vt.global_cursor_default=0 " \ - "root=/dev/mmcblk${mmc_boot}p${root_fs_partition} " \ - "rootfstype=ext4 " \ - "rootwait " \ - "rootdelay=1;" \ - "fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};" \ - "fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};" \ - "bootz ${loadaddr} - ${fdtaddr}" - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "fdtfile=am335x-pdu001.dtb\0" \ - "bootfile=zImage\0" \ - "console=" CONSOLE_DEV ",115200n8\0" \ - "root_fs_partition=2\0" \ - "eval_boot_device=" \ - "if test $boot_device = emmc; then " \ - "setenv mmc_boot 0;" \ - "elif test $boot_device = sdcard; then " \ - "setenv mmc_boot 1;" \ - "else " \ - "echo Bootdevice is neither MMC0 nor MMC1;" \ - "reset;" \ - "fi;" \ - "\0" -#endif - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_NS16550_COM2 UART1_BASE -#define CONFIG_SYS_NS16550_COM3 UART2_BASE -#define CONFIG_SYS_NS16550_COM4 UART3_BASE -#define CONFIG_SYS_NS16550_COM5 UART4_BASE -#define CONFIG_SYS_NS16550_COM6 UART5_BASE -#define CONFIG_BAUDRATE 115200 - -#endif /* ! __CONFIG_PDU001_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-imx/mx6/Kconfig | 1 - board/phytec/pfla02/Kconfig | 18 - board/phytec/pfla02/MAINTAINERS | 6 - board/phytec/pfla02/Makefile | 7 - board/phytec/pfla02/README | 24 -- board/phytec/pfla02/pfla02.c | 707 -------------------------------- configs/pfla02_defconfig | 57 --- include/configs/pfla02.h | 157 ------- 8 files changed, 977 deletions(-) delete mode 100644 board/phytec/pfla02/Kconfig delete mode 100644 board/phytec/pfla02/MAINTAINERS delete mode 100644 board/phytec/pfla02/Makefile delete mode 100644 board/phytec/pfla02/README delete mode 100644 board/phytec/pfla02/pfla02.c delete mode 100644 configs/pfla02_defconfig delete mode 100644 include/configs/pfla02.h

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 8169bfb18e6..701973b3866 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -547,7 +547,6 @@ source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" source "board/freescale/mx6ullevk/Kconfig" source "board/grinn/liteboard/Kconfig" -source "board/phytec/pfla02/Kconfig" source "board/kosagi/novena/Kconfig" source "board/liebherr/display5/Kconfig" source "board/logicpd/imx6/Kconfig" diff --git a/board/phytec/pfla02/Kconfig b/board/phytec/pfla02/Kconfig deleted file mode 100644 index f4da68b5ba9..00000000000 --- a/board/phytec/pfla02/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if TARGET_PFLA02 - -config SYS_BOARD - default "pfla02" - -config SYS_VENDOR - default "phytec" - -config SYS_CONFIG_NAME - default "pfla02" - -config SPL_DRAM_1_BANK - bool "DRAM on just one bank" - help - activate, if the module has just one bank - of RAM - -endif diff --git a/board/phytec/pfla02/MAINTAINERS b/board/phytec/pfla02/MAINTAINERS deleted file mode 100644 index 4b069a90cdc..00000000000 --- a/board/phytec/pfla02/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PHYTEC PHYFLEX -M: Stefano Babic sbabic@denx.de -S: Maintained -F: board/phytec/pfla02/ -F: include/configs/pfla02.h -F: configs/pfla02_defconfig diff --git a/board/phytec/pfla02/Makefile b/board/phytec/pfla02/Makefile deleted file mode 100644 index c50f315d911..00000000000 --- a/board/phytec/pfla02/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. - -obj-y := pfla02.o diff --git a/board/phytec/pfla02/README b/board/phytec/pfla02/README deleted file mode 100644 index 0f46ab86233..00000000000 --- a/board/phytec/pfla02/README +++ /dev/null @@ -1,24 +0,0 @@ -Board information ------------------ - -The evaluation board "pbab01" is thought to be used -together with the SOM. - -More information on the board can be found on manufacturer's -website: - -http://www.phytec.de/produkt/system-on-modules/phyflex-imx-6/ - -Building U-Boot -------------------------------- - -$ make pfla02_defconfig -$ make - -This generates the artifacts SPL and u-boot.img. -The SOM can boot from NAND or from SD-Card, having the SPI-NOR -as second option. -The dip switch "SW3" on the board let choose the boot device. - -SW3_1(on), SW3_2(on), SW3_3(off): Boot first from SD, then try SPI -SW3_1(off), SW3_2(on), SW3_3(off): Boot from SPI diff --git a/board/phytec/pfla02/pfla02.c b/board/phytec/pfla02/pfla02.c deleted file mode 100644 index aae23a3e444..00000000000 --- a/board/phytec/pfla02/pfla02.c +++ /dev/null @@ -1,707 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Stefano Babic sbabic@denx.de - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/spi.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <mmc.h> -#include <i2c.h> -#include <fsl_esdhc.h> -#include <nand.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/sys_proto.h> -#include <asm/sections.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) - -#define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14) -#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) -#define GREEN_LED IMX_GPIO_NR(2, 31) -#define RED_LED IMX_GPIO_NR(1, 30) -#define IMX6Q_DRIVE_STRENGTH 0x30 - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - return 0; -} - -static iomux_v3_cfg_t const uart4_pads[] = { - IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const enet_pads[] = { - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const ecspi3_pads[] = { - IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const gpios_pads[] = { - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -#ifdef CONFIG_CMD_NAND -/* NAND */ -static iomux_v3_cfg_t const nfc_pads[] = { - IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL)), -}; -#endif - -static struct i2c_pads_info i2c_pad_info = { - .scl = { - .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | I2C_PAD, - .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | I2C_PAD, - .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD, - .gp = IMX_GPIO_NR(3, 28) - } -}; - -static struct fsl_esdhc_cfg usdhc_cfg[] = { - {USDHC3_BASE_ADDR, - .max_bus_width = 4}, - {.esdhc_base = USDHC2_BASE_ADDR, - .max_bus_width = 4}, -}; - -#if !defined(CONFIG_SPL_BUILD) -static iomux_v3_cfg_t const usdhc2_pads[] = { - IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; -#endif - -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; - -int board_mmc_get_env_dev(int devno) -{ - return devno - 1; -} - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - ret = 1; - break; - case USDHC3_BASE_ADDR: - ret = 1; - break; - } - - return ret; -} - -#ifndef CONFIG_SPL_BUILD -int board_mmc_init(bd_t *bis) -{ - int ret; - int i; - - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - case 1: - SETUP_IOMUX_PADS(usdhc2_pads); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} -#endif - -static void setup_iomux_uart(void) -{ - SETUP_IOMUX_PADS(uart4_pads); -} - -static void setup_iomux_enet(void) -{ - SETUP_IOMUX_PADS(enet_pads); - - gpio_direction_output(ENET_PHY_RESET_GPIO, 0); - mdelay(10); - gpio_set_value(ENET_PHY_RESET_GPIO, 1); - mdelay(30); -} - -static void setup_spi(void) -{ - gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0"); - gpio_direction_output(IMX_GPIO_NR(4, 24), 1); - - SETUP_IOMUX_PADS(ecspi3_pads); - - enable_spi_clk(true, 2); -} - -static void setup_gpios(void) -{ - SETUP_IOMUX_PADS(gpios_pads); -} - -#ifdef CONFIG_CMD_NAND -static void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - SETUP_IOMUX_PADS(nfc_pads); - - /* gate ENFC_CLK_ROOT clock first,before clk source switch */ - clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); - - /* config gpmi and bch clock to 100 MHz */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); - - /* enable ENFC_CLK_ROOT clock */ - setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); - - /* enable gpmi and bch clock gating */ - setbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} -#endif - -/* - * Board revision is coded in 4 GPIOs - */ -u32 get_board_rev(void) -{ - u32 rev; - int i; - - for (i = 0, rev = 0; i < 4; i++) - rev |= (gpio_get_value(IMX_GPIO_NR(2, 12 + i)) << i); - - return 16 - rev; -} - -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - if (bus != 2 || (cs != 0)) - return -EINVAL; - - return IMX_GPIO_NR(4, 24); -} - -int board_eth_init(bd_t *bis) -{ - setup_iomux_enet(); - - return cpu_eth_init(bis); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info); -#endif - -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif - - setup_gpios(); - -#ifdef CONFIG_CMD_NAND - setup_gpmi_nand(); -#endif - return 0; -} - - -#ifdef CONFIG_CMD_BMODE -/* - * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 - * see Table 8-11 and Table 5-9 - * BOOT_CFG1[7] = 1 (boot from NAND) - * BOOT_CFG1[5] = 0 - raw NAND - * BOOT_CFG1[4] = 0 - default pad settings - * BOOT_CFG1[3:2] = 00 - devices = 1 - * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 - * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 - * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 - * BOOT_CFG2[0] = 0 - Reset time 12ms - */ -static const struct boot_mode board_boot_modes[] = { - /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ - {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)}, - {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int board_late_init(void) -{ - char buf[10]; -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - - snprintf(buf, sizeof(buf), "%d", get_board_rev()); - env_set("board_rev", buf); - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -#include <asm/arch/mx6-ddr.h> -#include <spl.h> -#include <linux/libfdt.h> - -#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11) -static void phyflex_err006282_workaround(void) -{ - /* - * Boards beginning with 1362.2 have the SD4_DAT3 pin connected - * to the CMIC. If this pin isn't toggled within 10s the boards - * reset. The pin is unconnected on older boards, so we do not - * need a check for older boards before applying this fixup. - */ - - gpio_direction_output(MX6_PHYFLEX_ERR006282, 0); - mdelay(2); - gpio_direction_output(MX6_PHYFLEX_ERR006282, 1); - mdelay(2); - gpio_set_value(MX6_PHYFLEX_ERR006282, 0); - - gpio_direction_input(MX6_PHYFLEX_ERR006282); -} - -static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_sdclk_0 = 0x00000030, - .dram_sdclk_1 = 0x00000030, - .dram_cas = 0x00000030, - .dram_ras = 0x00000030, - .dram_reset = 0x00000030, - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - .dram_sdba2 = 0x00000030, - .dram_sdodt0 = 0x00000030, - .dram_sdodt1 = 0x00000030, - - .dram_sdqs0 = 0x00000028, - .dram_sdqs1 = 0x00000028, - .dram_sdqs2 = 0x00000028, - .dram_sdqs3 = 0x00000028, - .dram_sdqs4 = 0x00000028, - .dram_sdqs5 = 0x00000028, - .dram_sdqs6 = 0x00000028, - .dram_sdqs7 = 0x00000028, - .dram_dqm0 = 0x00000028, - .dram_dqm1 = 0x00000028, - .dram_dqm2 = 0x00000028, - .dram_dqm3 = 0x00000028, - .dram_dqm4 = 0x00000028, - .dram_dqm5 = 0x00000028, - .dram_dqm6 = 0x00000028, - .dram_dqm7 = 0x00000028, -}; - -static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { - .grp_ddr_type = 0x000C0000, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_addds = IMX6Q_DRIVE_STRENGTH, - .grp_ctlds = IMX6Q_DRIVE_STRENGTH, - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000028, - .grp_b1ds = 0x00000028, - .grp_b2ds = 0x00000028, - .grp_b3ds = 0x00000028, - .grp_b4ds = 0x00000028, - .grp_b5ds = 0x00000028, - .grp_b6ds = 0x00000028, - .grp_b7ds = 0x00000028, -}; - -static const struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x00110011, - .p0_mpwldectrl1 = 0x00240024, - .p1_mpwldectrl0 = 0x00260038, - .p1_mpwldectrl1 = 0x002C0038, - .p0_mpdgctrl0 = 0x03400350, - .p0_mpdgctrl1 = 0x03440340, - .p1_mpdgctrl0 = 0x034C0354, - .p1_mpdgctrl1 = 0x035C033C, - .p0_mprddlctl = 0x322A2A2A, - .p1_mprddlctl = 0x302C2834, - .p0_mpwrdlctl = 0x34303834, - .p1_mpwrdlctl = 0x422A3E36, -}; - -/* Index in RAM Chip array */ -enum { - RAM_MT64K, - RAM_MT128K, - RAM_MT256K -}; - -static struct mx6_ddr3_cfg mt41k_xx[] = { -/* MT41K64M16JT-125 (1Gb density) */ - { - .mem_speed = 1600, - .density = 1, - .width = 16, - .banks = 8, - .rowaddr = 13, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, - .SRT = 1, - }, - -/* MT41K256M16JT-125 (2Gb density) */ - { - .mem_speed = 1600, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, - .SRT = 1, - }, - -/* MT41K256M16JT-125 (4Gb density) */ - { - .mem_speed = 1600, - .density = 4, - .width = 16, - .banks = 8, - .rowaddr = 15, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, - .SRT = 1, - } -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC03, &ccm->CCGR1); - writel(0x0FFFC000, &ccm->CCGR2); - writel(0x3FF00000, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003FF, &ccm->CCGR6); -} - -static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo, - struct mx6_ddr3_cfg *mem_ddr) -{ - mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr); -} - -int board_mmc_init(bd_t *bis) -{ - if (spl_boot_device() == BOOT_DEVICE_SPI) - printf("MMC SEtup, Boot SPI"); - - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[0].max_bus_width = 4; - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - - -void board_boot_order(u32 *spl_boot_list) -{ - spl_boot_list[0] = spl_boot_device(); - printf("Boot device %x\n", spl_boot_list[0]); - switch (spl_boot_list[0]) { - case BOOT_DEVICE_SPI: - spl_boot_list[1] = BOOT_DEVICE_UART; - break; - case BOOT_DEVICE_MMC1: - spl_boot_list[1] = BOOT_DEVICE_SPI; - spl_boot_list[2] = BOOT_DEVICE_UART; - break; - default: - printf("Boot device %x\n", spl_boot_list[0]); - } -} - -/* - * This is used because get_ram_size() does not - * take care of cache, resulting a wrong size - * pfla02 has just 1, 2 or 4 GB option - * Function checks for mirrors in the first CS - */ -#define RAM_TEST_PATTERN 0xaa5555aa -#define MIN_BANK_SIZE (512 * 1024 * 1024) - -static unsigned int pfla02_detect_chiptype(void) -{ - u32 *p, *p1; - unsigned int offset = MIN_BANK_SIZE; - int i; - - for (i = 0; i < 2; i++) { - p = (u32 *)PHYS_SDRAM; - p1 = (u32 *)(PHYS_SDRAM + (i + 1) * offset); - - *p1 = 0; - *p = RAM_TEST_PATTERN; - - /* - * This is required to detect mirroring - * else we read back values from cache - */ - flush_dcache_all(); - - if (*p == *p1) - return i; - } - return RAM_MT256K; -} - -void board_init_f(ulong dummy) -{ - unsigned int ramchip; - - struct mx6_ddr_sysinfo sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ - .dsize = 2, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 512 MB */ - /* single chip select */ -#if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK) - .ncs = 1, -#else - .ncs = 2, -#endif - .cs1_mirror = 1, - .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ - .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; - -#ifdef CONFIG_CMD_NAND - /* Enable NAND */ - setup_gpmi_nand(); -#endif - - /* setup clock gating */ - ccgr_init(); - - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - /* setup AXI */ - gpr_init(); - - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - setup_spi(); - - setup_gpios(); - - /* DDR initialization */ - spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]); - ramchip = pfla02_detect_chiptype(); - debug("Detected chip %d\n", ramchip); -#if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK) - switch (ramchip) { - case RAM_MT64K: - sysinfo.cs_density = 6; - break; - case RAM_MT128K: - sysinfo.cs_density = 10; - break; - case RAM_MT256K: - sysinfo.cs_density = 18; - break; - } -#endif - spl_dram_init(&sysinfo, &mt41k_xx[ramchip]); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - phyflex_err006282_workaround(); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} -#endif diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig deleted file mode 100644 index 18d35a130f3..00000000000 --- a/configs/pfla02_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_PFLA02=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_CMD_HDMIDETECT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTDELAY=3 -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_DMA_SUPPORT=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_YMODEM_SUPPORT=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_NAND is not set -CONFIG_CMD_SF=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:-(nand);spi2.0:1024k(bootloader),64k(env1),64k(env2),-(rescue)" -CONFIG_CMD_UBI=y -# CONFIG_SPL_PARTITION_UUIDS is not set -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_NAND=y -CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_FEC_MXC=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_DM_THERMAL=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h deleted file mode 100644 index e2aae19484c..00000000000 --- a/include/configs/pfla02.h +++ /dev/null @@ -1,157 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Stefano Babic sbabic@denx.de - */ - - -#ifndef __PCM058_CONFIG_H -#define __PCM058_CONFIG_H - -#ifdef CONFIG_SPL -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) -#include "imx6_spl.h" -#endif - -#include "mx6_common.h" - -/* Thermal */ -#define CONFIG_IMX_THERMAL - -/* Serial */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART4_BASE -#define CONSOLE_DEV "ttymxc3" - -/* Early setup */ - - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) - -/* Ethernet */ -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 3 - -/* SPI Flash */ -#define CONFIG_SF_DEFAULT_BUS 2 -#define CONFIG_SF_DEFAULT_CS 0 -#define CONFIG_SF_DEFAULT_SPEED 20000000 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 0 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_CMD_NAND -/* Enable NAND support */ -#define CONFIG_CMD_NAND_TRIMFFS -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION -#endif - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* Filesystem support */ - -/* Various command support */ - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* Environment organization */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_ENV_OFFSET (1024 * SZ_1K) -#define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) -#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS -#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS -#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET (0x1E0000) -#define CONFIG_ENV_SECT_SIZE (128 * SZ_1K) -#endif - -/* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} ${miscargs}\0" \ - "addmtd=run mtdnand;run mtdspi;" \ - "setenv bootargs ${bootargs} ${mtdparts}\0" \ - "mtdnand=setenv mtdparts mtdparts=gpmi-nand:" \ - "40m(Kernels),400m(root),-(nand)\0" \ - "mtdspi=setenv mtdparts ${mtdparts}" \ - "';spi2.0:1024k(bootloader)," \ - "64k(env1),64k(env2),-(rescue)'\0" \ - "bootcmd=if test -n ${rescue};" \ - "then run swupdate;fi;run nandboot;run swupdate\0" \ - "bootfile=uImage\0" \ - "bootimage=uImage\0" \ - "console=ttymxc3\0" \ - "fdt_addr_r=0x18000000\0" \ - "fdt_file=pfla02.dtb\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "miscargs=panic=1 quiet\0" \ - "mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0" \ - "mmcboot=if run mmcload;then " \ - "run mmcargs addcons addmisc;" \ - "bootm;fi\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p1\0" \ - "ubiroot=1\0" \ - "nandargs=setenv bootargs ubi.mtd=1 " \ - "root=ubi0:rootfs${ubiroot} rootfstype=ubifs\0" \ - "nandboot=run mtdnand;ubi part nand0,0;" \ - "ubi readvol ${kernel_addr_r} kernel${ubiroot};" \ - "run nandargs addip addcons addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};" \ - "tftp ${fdt_addr_r} ${board_name}/${fdt_file};" \ - "run nfsargs addip addcons addmtd addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_nfs_fit=tftp ${kernel_addr_r} ${board_name}/${fitfile};" \ - "run nfsargs addip addcons addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "nfsargs=setenv bootargs root=/dev/nfs" \ - " nfsroot=${serverip}:${nfsroot},v3 panic=1\0" \ - "swupdate=setenv bootargs root=/dev/ram;" \ - "run addip addcons addmtd addmisc;" \ - "sf probe;" \ - "sf read ${kernel_addr_r} 120000 600000;" \ - "sf read 14000000 730000 800000;" \ - "bootm ${kernel_addr_r} 14000000\0" - -#endif

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/cpu/arm926ejs/lpc32xx/Kconfig | 1 - board/work-microwave/work_92105/Kconfig | 24 -- board/work-microwave/work_92105/MAINTAINERS | 6 - board/work-microwave/work_92105/Makefile | 10 - board/work-microwave/work_92105/README | 91 ----- board/work-microwave/work_92105/work_92105.c | 76 ---- .../work_92105/work_92105_display.c | 348 ------------------ .../work_92105/work_92105_display.h | 13 - .../work_92105/work_92105_spl.c | 84 ----- configs/work_92105_defconfig | 41 --- include/configs/work_92105.h | 161 -------- 11 files changed, 855 deletions(-) delete mode 100644 board/work-microwave/work_92105/Kconfig delete mode 100644 board/work-microwave/work_92105/MAINTAINERS delete mode 100644 board/work-microwave/work_92105/Makefile delete mode 100644 board/work-microwave/work_92105/README delete mode 100644 board/work-microwave/work_92105/work_92105.c delete mode 100644 board/work-microwave/work_92105/work_92105_display.c delete mode 100644 board/work-microwave/work_92105/work_92105_display.h delete mode 100644 board/work-microwave/work_92105/work_92105_spl.c delete mode 100644 configs/work_92105_defconfig delete mode 100644 include/configs/work_92105.h

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig b/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig index 407252c8c30..189884ad930 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig +++ b/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig @@ -14,6 +14,5 @@ config TARGET_WORK_92105

endchoice

-source "board/work-microwave/work_92105/Kconfig"

endif diff --git a/board/work-microwave/work_92105/Kconfig b/board/work-microwave/work_92105/Kconfig deleted file mode 100644 index 32632f5ab52..00000000000 --- a/board/work-microwave/work_92105/Kconfig +++ /dev/null @@ -1,24 +0,0 @@ -if TARGET_WORK_92105 - -config SYS_BOARD - default "work_92105" - -config SYS_VENDOR - default "work-microwave" - -config SYS_CONFIG_NAME - default "work_92105" - -config CMD_HD44760 - bool "Enable 'hd44780' LCD-control comand" - help - This controls the LCD driver. - -config CMD_MAX6957 - bool "Enable 'max6957aax' PMIC command" - help - DEPRECATED: Needs conversion to driver model. - - This allows PMIC registers to be read and written. - -endif diff --git a/board/work-microwave/work_92105/MAINTAINERS b/board/work-microwave/work_92105/MAINTAINERS deleted file mode 100644 index 29a92c5ffe2..00000000000 --- a/board/work-microwave/work_92105/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -WORK_92105 BOARD -M: Albert ARIBAUD albert.aribaud@3adev.fr -S: Maintained -F: board/work-microwave/work_92105/ -F: include/configs/work_92105.h -F: configs/work_92105_defconfig diff --git a/board/work-microwave/work_92105/Makefile b/board/work-microwave/work_92105/Makefile deleted file mode 100644 index e3803bb0431..00000000000 --- a/board/work-microwave/work_92105/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2014 DENX Software Engineering GmbH -# Written-by: Albert ARIBAUD albert.aribaud@3adev.fr - -ifdef CONFIG_SPL_BUILD -obj-y += work_92105_spl.o -else -obj-y += work_92105.o work_92105_display.o -endif diff --git a/board/work-microwave/work_92105/README b/board/work-microwave/work_92105/README deleted file mode 100644 index 3c256e0b2cd..00000000000 --- a/board/work-microwave/work_92105/README +++ /dev/null @@ -1,91 +0,0 @@ -Work_92105 from Work Microwave is an LPC3250- based board with the -following features: - - - 64MB SDR DRAM - - 1 GB SLC NAND, managed through MLC controller. - - Ethernet - - Ethernet + PHY SMSC8710 - - I2C: - - EEPROM (24M01-compatible) - - RTC (DS1374-compatible) - - Temperature sensor (DS620) - - DACs (2 x MAX518) - - SPI (through SSP interface) - - Port expander MAX6957 - - LCD display (HD44780-compatible), controlled - through the port expander and DACs - -Standard SPL and U-Boot binaries --------------------------------- - -The default 'make' (or the 'make all') command will produce the -following files: - -1. spl/u-boot-spl.bin SPL, intended to run from SRAM at address 0. - This file can be loaded in SRAM through a JTAG - debugger or through the LPC32XX Service Boot - mechanism. - -2. u-boot.bin The raw U-Boot image, which can be loaded in - DDR through a JTAG debugger (for instance by - breaking SPL after DDR init), or by a running - U-Boot through e.g. 'loady' or 'tftp' and then - executed with 'go'. - -3. u-boot.img A U-Boot image with a mkimage header prepended. - SPL assumes (even when loaded through JTAG or - Service Boot) that such an image will be found - at offset 0x00040000 in NAND. - -NAND cold-boot binaries ------------------------ - -The board can boot entirely from power-on with only SPL and U-Boot in -NAND. The LPC32XX-specific 'make lpc32xx-full.bin' command will produce -(in addition to spl/u-boot-spl.bin and u-boot.img if they were not made -already) the following files: - -4. lpc32xx-spl.img spl/u-boot-spl.bin, with a LPC32XX boot header - prepended. This header is required for the ROM - code to load SPL into SRAM and branch into it. - The content of this file is expected to reside - in NAND at addresses 0x00000000 and 0x00020000 - (two copies). - -5. lpc32xx-boot-0.bin lpc32xx-spl.img, padded with 0xFF bytes to a - size of 0x20000 bytes. This file covers exactly - the reserved area for the first bootloader copy - in NAND. - -6. lpc32xx-boot-1.bin Same as lpc32xx-boot-0.bin. This is intended to - be used as the second bootloader copy. - -7. lpc32xx-full.bin lpc32xx-boot-0.bin, lpc32xx-boot-1.bin and - u-boot.img concatenated. This file represents - the content of whole bootloader as present in - NAND at offset 00x00000000. - -Flashing instructions ---------------------- - -The following assumes a working U-Boot on the target, with the ability -to load files into DDR. - -To update the whole bootloader: - - nand erase 0x00000000 0x80000 - (load lpc32xx-full.bin at location $loadaddr) - nand write $loadaddr 0x00000000 $filesize - -To update SPL only (note the double nand write) : - - nand erase 0x00000000 0x40000 - (load lpc32xx-spl.img or lpc32xx-boot-N.bin at location $loadaddr) - nand write $loadaddr 0x00000000 $filesize - nand write $loadaddr 0x00020000 $filesize - -To update U-Boot only: - - nand erase 0x00040000 0x40000 - (load u-boot.img at location $loadaddr) - nand write $loadaddr 0x00040000 $filesize diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c deleted file mode 100644 index eb2e7d7eb88..00000000000 --- a/board/work-microwave/work_92105/work_92105.c +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * WORK Microwave work_92105 board support - * - * (C) Copyright 2014 DENX Software Engineering GmbH - * Written-by: Albert ARIBAUD albert.aribaud@3adev.fr - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/cpu.h> -#include <asm/arch/clk.h> -#include <asm/arch/emc.h> -#include <asm/arch/wdt.h> -#include <asm/gpio.h> -#include <spl.h> -#include "work_92105_display.h" - -DECLARE_GLOBAL_DATA_PTR; - -static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; -static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE; - -void reset_periph(void) -{ - setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); - writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl); - udelay(150); - writel(0, &wdt->mctrl); - clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); -} - -int board_early_init_f(void) -{ - /* initialize serial port for console */ - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); - /* enable I2C, SSP, MAC, NAND */ - lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */ - lpc32xx_ssp_init(); - lpc32xx_mac_init(); - lpc32xx_mlc_nand_init(); - /* Display must wait until after relocation and devices init */ - return 0; -} - -#define GPO_19 115 - -int board_early_init_r(void) -{ - /* Set NAND !WP to 1 through GPO_19 */ - gpio_request(GPO_19, "NAND_nWP"); - gpio_direction_output(GPO_19, 1); - - /* initialize display */ - work_92105_display_init(); - - return 0; -} - -int board_init(void) -{ - reset_periph(); - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - - return 0; -} diff --git a/board/work-microwave/work_92105/work_92105_display.c b/board/work-microwave/work_92105/work_92105_display.c deleted file mode 100644 index ffa0fcfa874..00000000000 --- a/board/work-microwave/work_92105/work_92105_display.c +++ /dev/null @@ -1,348 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * work_92105 display support - * - * (C) Copyright 2014 DENX Software Engineering GmbH - * Written-by: Albert ARIBAUD albert.aribaud@3adev.fr - * - * The work_92105 display is a HD44780-compatible module - * controlled through a MAX6957AAX SPI port expander, two - * MAX518 I2C DACs and native LPC32xx GPO 15. - */ - -#include <common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/cpu.h> -#include <asm/arch/emc.h> -#include <asm/gpio.h> -#include <spi.h> -#include <i2c.h> -#include <version.h> -#include <vsprintf.h> - -/* - * GPO 15 in port 3 is gpio 3*32+15 = 111 - */ - -#define GPO_15 111 - -/** - * MAX6957AAX registers that we will be using - */ - -#define MAX6957_CONF 0x04 - -#define MAX6957_CONF_08_11 0x0A -#define MAX6957_CONF_12_15 0x0B -#define MAX6957_CONF_16_19 0x0C - -/** - * Individual gpio ports (one per gpio) to HD44780 - */ - -#define MAX6957AAX_HD44780_RS 0x29 -#define MAX6957AAX_HD44780_R_W 0x2A -#define MAX6957AAX_HD44780_EN 0x2B -#define MAX6957AAX_HD44780_DATA 0x4C - -/** - * Display controller instructions - */ - -/* Function set: eight bits, two lines, 8-dot font */ -#define HD44780_FUNCTION_SET 0x38 - -/* Display ON / OFF: turn display on */ -#define HD44780_DISPLAY_ON_OFF_CONTROL 0x0C - -/* Entry mode: increment */ -#define HD44780_ENTRY_MODE_SET 0x06 - -/* Clear */ -#define HD44780_CLEAR_DISPLAY 0x01 - -/* Set DDRAM addr (to be ORed with exact address) */ -#define HD44780_SET_DDRAM_ADDR 0x80 - -/* Set CGRAM addr (to be ORed with exact address) */ -#define HD44780_SET_CGRAM_ADDR 0x40 - -/** - * Default value for contrats - */ - -#define CONTRAST_DEFAULT 25 - -/** - * Define slave as a module-wide local to save passing it around, - * plus we will need it after init for the "hd44780" command. - */ - -static struct spi_slave *slave; - -/* - * Write a value into a MAX6957AAX register. - */ - -static void max6957aax_write(uint8_t reg, uint8_t value) -{ - uint8_t dout[2]; - - dout[0] = reg; - dout[1] = value; - gpio_set_value(GPO_15, 0); - /* do SPI read/write (passing din==dout is OK) */ - spi_xfer(slave, 16, dout, dout, SPI_XFER_BEGIN | SPI_XFER_END); - gpio_set_value(GPO_15, 1); -} - -/* - * Read a value from a MAX6957AAX register. - * - * According to the MAX6957AAX datasheet, we should release the chip - * select halfway through the read sequence, when the actual register - * value is read; but the WORK_92105 hardware prevents the MAX6957AAX - * SPI OUT from reaching the LPC32XX SIP MISO if chip is not selected. - * so let's release the CS an hold it again while reading the result. - */ - -static uint8_t max6957aax_read(uint8_t reg) -{ - uint8_t dout[2], din[2]; - - /* send read command */ - dout[0] = reg | 0x80; /* set bit 7 to indicate read */ - dout[1] = 0; - gpio_set_value(GPO_15, 0); - /* do SPI read/write (passing din==dout is OK) */ - spi_xfer(slave, 16, dout, dout, SPI_XFER_BEGIN | SPI_XFER_END); - /* latch read command */ - gpio_set_value(GPO_15, 1); - /* read register -- din = noop on xmit, din[1] = reg on recv */ - din[0] = 0; - din[1] = 0; - gpio_set_value(GPO_15, 0); - /* do SPI read/write (passing din==dout is OK) */ - spi_xfer(slave, 16, din, din, SPI_XFER_BEGIN | SPI_XFER_END); - /* end of read. */ - gpio_set_value(GPO_15, 1); - return din[1]; -} - -static void hd44780_instruction(unsigned long instruction) -{ - max6957aax_write(MAX6957AAX_HD44780_RS, 0); - max6957aax_write(MAX6957AAX_HD44780_R_W, 0); - max6957aax_write(MAX6957AAX_HD44780_EN, 1); - max6957aax_write(MAX6957AAX_HD44780_DATA, instruction); - max6957aax_write(MAX6957AAX_HD44780_EN, 0); - /* HD44780 takes 37 us for most instructions, 1520 for clear */ - if (instruction == HD44780_CLEAR_DISPLAY) - udelay(2000); - else - udelay(100); -} - -static void hd44780_write_char(char c) -{ - max6957aax_write(MAX6957AAX_HD44780_RS, 1); - max6957aax_write(MAX6957AAX_HD44780_R_W, 0); - max6957aax_write(MAX6957AAX_HD44780_EN, 1); - max6957aax_write(MAX6957AAX_HD44780_DATA, c); - max6957aax_write(MAX6957AAX_HD44780_EN, 0); - /* HD44780 takes 37 us to write to DDRAM or CGRAM */ - udelay(100); -} - -static void hd44780_write_str(char *s) -{ - max6957aax_write(MAX6957AAX_HD44780_RS, 1); - max6957aax_write(MAX6957AAX_HD44780_R_W, 0); - while (*s) { - max6957aax_write(MAX6957AAX_HD44780_EN, 1); - max6957aax_write(MAX6957AAX_HD44780_DATA, *s); - max6957aax_write(MAX6957AAX_HD44780_EN, 0); - s++; - /* HD44780 takes 37 us to write to DDRAM or CGRAM */ - udelay(100); - } -} - -/* - * Existing user code might expect these custom characters to be - * recognized and displayed on the LCD - */ - -static u8 char_gen_chars[] = { - /* #8, empty rectangle */ - 0x1F, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x1F, - /* #9, filled right arrow */ - 0x10, 0x18, 0x1C, 0x1E, 0x1C, 0x18, 0x10, 0x00, - /* #10, filled left arrow */ - 0x01, 0x03, 0x07, 0x0F, 0x07, 0x03, 0x01, 0x00, - /* #11, up and down arrow */ - 0x04, 0x0E, 0x1F, 0x00, 0x00, 0x1F, 0x0E, 0x04, - /* #12, plus/minus */ - 0x04, 0x04, 0x1F, 0x04, 0x04, 0x00, 0x1F, 0x00, - /* #13, fat exclamation mark */ - 0x06, 0x06, 0x06, 0x06, 0x00, 0x06, 0x06, 0x00, - /* #14, empty square */ - 0x00, 0x1F, 0x11, 0x11, 0x11, 0x1F, 0x00, 0x00, - /* #15, struck out square */ - 0x00, 0x1F, 0x19, 0x15, 0x13, 0x1F, 0x00, 0x00, -}; - -static void hd44780_init_char_gen(void) -{ - int i; - - hd44780_instruction(HD44780_SET_CGRAM_ADDR); - - for (i = 0; i < sizeof(char_gen_chars); i++) - hd44780_write_char(char_gen_chars[i]); - - hd44780_instruction(HD44780_SET_DDRAM_ADDR); -} - -void work_92105_display_init(void) -{ - int claim_err; - char *display_contrast_str; - uint8_t display_contrast = CONTRAST_DEFAULT; - uint8_t enable_backlight = 0x96; - - slave = spi_setup_slave(0, 0, 500000, 0); - - if (!slave) { - printf("Failed to set up SPI slave\n"); - return; - } - - claim_err = spi_claim_bus(slave); - - if (claim_err) - debug("Failed to claim SPI bus: %d\n", claim_err); - - /* enable backlight */ - i2c_write(0x2c, 0x01, 1, &enable_backlight, 1); - - /* set display contrast */ - display_contrast_str = env_get("fwopt_dispcontrast"); - if (display_contrast_str) - display_contrast = simple_strtoul(display_contrast_str, - NULL, 10); - i2c_write(0x2c, 0x00, 1, &display_contrast, 1); - - /* request GPO_15 as an output initially set to 1 */ - gpio_request(GPO_15, "MAX6957_nCS"); - gpio_direction_output(GPO_15, 1); - - /* enable MAX6957 portexpander */ - max6957aax_write(MAX6957_CONF, 0x01); - /* configure pin 8 as input, pins 9..19 as outputs */ - max6957aax_write(MAX6957_CONF_08_11, 0x56); - max6957aax_write(MAX6957_CONF_12_15, 0x55); - max6957aax_write(MAX6957_CONF_16_19, 0x55); - - /* initialize HD44780 */ - max6957aax_write(MAX6957AAX_HD44780_EN, 0); - hd44780_instruction(HD44780_FUNCTION_SET); - hd44780_instruction(HD44780_DISPLAY_ON_OFF_CONTROL); - hd44780_instruction(HD44780_ENTRY_MODE_SET); - - /* write custom character glyphs */ - hd44780_init_char_gen(); - - /* Show U-Boot version, date and time as a sign-of-life */ - hd44780_instruction(HD44780_CLEAR_DISPLAY); - hd44780_instruction(HD44780_SET_DDRAM_ADDR | 0); - hd44780_write_str(U_BOOT_VERSION); - hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64); - hd44780_write_str(U_BOOT_DATE); - hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64 | 20); - hd44780_write_str(U_BOOT_TIME); -} - -#ifdef CONFIG_CMD_MAX6957 - -static int do_max6957aax(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]) -{ - int reg, val; - - if (argc != 3) - return CMD_RET_USAGE; - switch (argv[1][0]) { - case 'r': - case 'R': - reg = simple_strtoul(argv[2], NULL, 0); - val = max6957aax_read(reg); - printf("MAX6957 reg 0x%02x read 0x%02x\n", reg, val); - return 0; - default: - reg = simple_strtoul(argv[1], NULL, 0); - val = simple_strtoul(argv[2], NULL, 0); - max6957aax_write(reg, val); - printf("MAX6957 reg 0x%02x wrote 0x%02x\n", reg, val); - return 0; - } - return 1; -} - -#ifdef CONFIG_SYS_LONGHELP -static char max6957aax_help_text[] = - "max6957aax - write or read display register:\n" - "\tmax6957aax R|r reg - read display register;\n" - "\tmax6957aax reg val - write display register."; -#endif - -U_BOOT_CMD( - max6957aax, 6, 1, do_max6957aax, - "SPI MAX6957 display write/read", - max6957aax_help_text -); -#endif /* CONFIG_CMD_MAX6957 */ - -#ifdef CONFIG_CMD_HD44760 - -/* - * We need the HUSH parser because we need string arguments, and - * only HUSH can understand them. - */ - -#if !defined(CONFIG_HUSH_PARSER) -#error CONFIG_CMD_HD44760 requires CONFIG_HUSH_PARSER -#endif - -static int do_hd44780(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) -{ - char *cmd; - - if (argc != 3) - return CMD_RET_USAGE; - - cmd = argv[1]; - - if (strcasecmp(cmd, "cmd") == 0) - hd44780_instruction(simple_strtol(argv[2], NULL, 0)); - else if (strcasecmp(cmd, "data") == 0) - hd44780_write_char(simple_strtol(argv[2], NULL, 0)); - else if (strcasecmp(cmd, "str") == 0) - hd44780_write_str(argv[2]); - return 0; -} - -#ifdef CONFIG_SYS_LONGHELP -static char hd44780_help_text[] = - "hd44780 - control LCD driver:\n" - "\thd44780 cmd <val> - send command <val> to driver;\n" - "\thd44780 data <val> - send data <val> to driver;\n" - "\thd44780 str "<text>" - send "<text>" to driver."; -#endif - -U_BOOT_CMD( - hd44780, 6, 1, do_hd44780, - "HD44780 LCD driver control", - hd44780_help_text -); -#endif /* CONFIG_CMD_HD44760 */ diff --git a/board/work-microwave/work_92105/work_92105_display.h b/board/work-microwave/work_92105/work_92105_display.h deleted file mode 100644 index 17a9aa04e02..00000000000 --- a/board/work-microwave/work_92105/work_92105_display.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * work_92105 display support interface - * - * (C) Copyright 2014 DENX Software Engineering GmbH - * Written-by: Albert ARIBAUD albert.aribaud@3adev.fr - * - * The work_92105 display is a HD44780-compatible module - * controlled through a MAX6957AAX SPI port expander, two - * MAX518 I2C DACs and native LPC32xx GPO 15. - */ - -void work_92105_display_init(void); diff --git a/board/work-microwave/work_92105/work_92105_spl.c b/board/work-microwave/work_92105/work_92105_spl.c deleted file mode 100644 index a31553a2d25..00000000000 --- a/board/work-microwave/work_92105/work_92105_spl.c +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * WORK Microwave work_92105 board support - * - * (C) Copyright 2014 DENX Software Engineering GmbH - * Written-by: Albert ARIBAUD albert.aribaud@3adev.fr - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/cpu.h> -#include <asm/arch/emc.h> -#include <asm/gpio.h> -#include <spl.h> -#include "work_92105_display.h" - -struct emc_dram_settings dram_64mb = { - .cmddelay = 0x0001C000, - .config0 = 0x00005682, - .rascas0 = 0x00000302, - .rdconfig = 0x00000011, - .trp = 52631578, - .tras = 20833333, - .tsrex = 12500000, - .twr = 66666666, - .trc = 13888888, - .trfc = 10256410, - .txsr = 12500000, - .trrd = 1, - .tmrd = 1, - .tcdlr = 0, - .refresh = 128000, - .mode = 0x00018000, - .emode = 0x02000000 -}; - -const struct emc_dram_settings dram_128mb = { - .cmddelay = 0x0001C000, - .config0 = 0x00005882, - .rascas0 = 0x00000302, - .rdconfig = 0x00000011, - .trp = 52631578, - .tras = 22222222, - .tsrex = 8333333, - .twr = 66666666, - .trc = 14814814, - .trfc = 10256410, - .txsr = 8333333, - .trrd = 1, - .tmrd = 1, - .tcdlr = 0, - .refresh = 128000, - .mode = 0x00030000, - .emode = 0x02000000 -}; - -void spl_board_init(void) -{ - /* initialize serial port for console */ - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); - /* initialize console */ - preloader_console_init(); - /* init DDR and NAND to chainload U-Boot */ - ddr_init(&dram_128mb); - /* - * If this is actually a 64MB module, then the highest column - * bit in any address will be ignored, and thus address 0x80000000 - * should be mirrored at address 0x80000800. Test this. - */ - writel(0x31415926, 0x80000000); /* write Pi at 0x80000000 */ - writel(0x16180339, 0x80000800); /* write Phi at 0x80000800 */ - if (readl(0x80000000) == 0x16180339) /* check 0x80000000 */ { - /* actually 64MB mirrored: reconfigure controller */ - ddr_init(&dram_64mb); - } - /* initialize NAND controller to load U-Boot from NAND */ - lpc32xx_mlc_nand_init(); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_NAND; -} diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig deleted file mode 100644 index 105e51a4001..00000000000 --- a/configs/work_92105_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_LPC32XX=y -CONFIG_SYS_TEXT_BASE=0x80100000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_WORK_92105=y -CONFIG_CMD_HD44760=y -CONFIG_CMD_MAX6957=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS2,115200n8" -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_IS_IN_NAND=y -# CONFIG_MMC is not set -CONFIG_PHYLIB=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_LPC32XX_SSP=y diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h deleted file mode 100644 index 67b5e9aa113..00000000000 --- a/include/configs/work_92105.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * WORK Microwave work_92105 board configuration file - * - * (C) Copyright 2014 DENX Software Engineering GmbH - * Written-by: Albert ARIBAUD albert.aribaud@3adev.fr - */ - -#ifndef __CONFIG_WORK_92105_H__ -#define __CONFIG_WORK_92105_H__ - -/* SoC and board defines */ -#include <linux/sizes.h> -#include <asm/arch/cpu.h> - -/* - * Define work_92105 machine type by hand -- done only for compatibility - * with original board code - */ -#define CONFIG_MACH_TYPE 736 - -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* - * Memory configurations - */ -#define CONFIG_SYS_MALLOC_LEN SZ_1M -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ - - GENERATED_GBL_DATA_SIZE) - -/* - * Serial Driver - */ -#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ - -/* - * Ethernet Driver - */ - -#define CONFIG_PHY_SMSC -#define CONFIG_LPC32XX_ETH -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ - -/* - * I2C driver - */ - -#define CONFIG_SYS_I2C_LPC32XX -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SPEED 350000 - -/* - * I2C EEPROM - */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * I2C RTC - */ - -#define CONFIG_RTC_DS1374 - -/* - * U-Boot General Configurations - */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * NAND chip timings for FIXME: which one? - */ - -#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 -#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 -#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 -#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 -#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 -#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 -#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 - -/* - * NAND - */ - -/* driver configuration */ -#define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_MAX_NAND_CHIPS 1 -#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE -#define CONFIG_NAND_LPC32XX_MLC - -/* - * GPIO - */ - -#define CONFIG_LPC32XX_GPIO - -/* - * SSP/SPI/DISPLAY - */ - -#define CONFIG_LPC32XX_SSP_TIMEOUT 100000 -/* - * Environment - */ - -#define CONFIG_ENV_SIZE 0x00020000 -#define CONFIG_ENV_OFFSET 0x00100000 -#define CONFIG_ENV_OFFSET_REDUND 0x00120000 -#define CONFIG_ENV_ADDR 0x80000100 - -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x80008000 - -/* - * SPL - */ - -/* SPL will be executed at offset 0 */ -#define CONFIG_SPL_TEXT_BASE 0x00000000 -/* SPL will use SRAM as stack */ -#define CONFIG_SPL_STACK 0x0000FFF8 -/* Use the framework and generic lib */ -/* SPL will use serial */ -/* SPL will load U-Boot from NAND offset 0x40000 */ -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000 -#define CONFIG_SPL_PAD_TO 0x20000 -/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE - -/* - * Include SoC specific configuration - */ -#include <asm/arch/config.h> - -#endif /* __CONFIG_WORK_92105_H__*/

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-imx/mx7/Kconfig | 1 - board/compulab/cl-som-imx7/Kconfig | 28 -- board/compulab/cl-som-imx7/MAINTAINERS | 6 - board/compulab/cl-som-imx7/Makefile | 17 -- board/compulab/cl-som-imx7/cl-som-imx7.c | 331 ----------------------- board/compulab/cl-som-imx7/common.c | 45 --- board/compulab/cl-som-imx7/common.h | 31 --- board/compulab/cl-som-imx7/mux.c | 141 ---------- board/compulab/cl-som-imx7/spl.c | 210 -------------- configs/cl-som-imx7_defconfig | 67 ----- include/configs/cl-som-imx7.h | 182 ------------- 11 files changed, 1059 deletions(-) delete mode 100644 board/compulab/cl-som-imx7/Kconfig delete mode 100644 board/compulab/cl-som-imx7/MAINTAINERS delete mode 100644 board/compulab/cl-som-imx7/Makefile delete mode 100644 board/compulab/cl-som-imx7/cl-som-imx7.c delete mode 100644 board/compulab/cl-som-imx7/common.c delete mode 100644 board/compulab/cl-som-imx7/common.h delete mode 100644 board/compulab/cl-som-imx7/mux.c delete mode 100644 board/compulab/cl-som-imx7/spl.c delete mode 100644 configs/cl-som-imx7_defconfig delete mode 100644 include/configs/cl-som-imx7.h

diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 63b90f99500..248e5003575 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -65,7 +65,6 @@ endchoice config SYS_SOC default "mx7"

-source "board/compulab/cl-som-imx7/Kconfig" source "board/freescale/mx7dsabresd/Kconfig" source "board/toradex/colibri_imx7/Kconfig"

diff --git a/board/compulab/cl-som-imx7/Kconfig b/board/compulab/cl-som-imx7/Kconfig deleted file mode 100644 index 6d69cf31f44..00000000000 --- a/board/compulab/cl-som-imx7/Kconfig +++ /dev/null @@ -1,28 +0,0 @@ -if TARGET_CL_SOM_IMX7 - -config SYS_BOARD - default "cl-som-imx7" - -config SYS_VENDOR - default "compulab" - -config SYS_CONFIG_NAME - default "cl-som-imx7" - -config SYS_MMC_DEV - int - default 0 - -config SYS_USB_DEV - int - default 0 - -config SYS_MMC_IMG_LOAD_PART - int - default 1 - -config SYS_USB_IMG_LOAD_PART - int - default 1 - -endif diff --git a/board/compulab/cl-som-imx7/MAINTAINERS b/board/compulab/cl-som-imx7/MAINTAINERS deleted file mode 100644 index 2b917a5c807..00000000000 --- a/board/compulab/cl-som-imx7/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CL-SOM-IMX7 BOARD -M: Uri Mashiach uri.mashiach@compulab.co.il -S: Maintained -F: board/compulab/cl-som-imx7 -F: include/configs/cl-som-imx7.h -F: configs/cl-som-imx7_defconfig diff --git a/board/compulab/cl-som-imx7/Makefile b/board/compulab/cl-som-imx7/Makefile deleted file mode 100644 index 8f0e068b7e9..00000000000 --- a/board/compulab/cl-som-imx7/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# Makefile -# -# (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com -# -# Author: Uri Mashiach uri.mashiach@compulab.co.il -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mux.o common.o - -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -else -obj-y += cl-som-imx7.o -endif diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c deleted file mode 100644 index 1bc33b0a7ba..00000000000 --- a/board/compulab/cl-som-imx7/cl-som-imx7.c +++ /dev/null @@ -1,331 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * U-Boot board functions for CompuLab CL-SOM-iMX7 module - * - * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com - * - * Author: Uri Mashiach uri.mashiach@compulab.co.il - */ - -#include <common.h> -#include <environment.h> -#include <mmc.h> -#include <phy.h> -#include <netdev.h> -#include <fsl_esdhc.h> -#include <power/pmic.h> -#include <power/pfuze3000_pmic.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/arch-mx7/mx7-pins.h> -#include <asm/arch-mx7/sys_proto.h> -#include <asm/arch-mx7/clock.h> -#include "../common/eeprom.h" -#include "common.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SYS_I2C_MXC - -#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS) - -#define CL_SOM_IMX7_GPIO_I2C2_SCL IMX_GPIO_NR(1, 6) -#define CL_SOM_IMX7_GPIO_I2C2_SDA IMX_GPIO_NR(1, 7) - -static struct i2c_pads_info cl_som_imx7_i2c_pad_info2 = { - .scl = { - .i2c_mode = MX7D_PAD_GPIO1_IO06__I2C2_SCL | - MUX_PAD_CTRL(I2C_PAD_CTRL), - .gpio_mode = MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | - MUX_PAD_CTRL(I2C_PAD_CTRL), - .gp = CL_SOM_IMX7_GPIO_I2C2_SCL, - }, - .sda = { - .i2c_mode = MX7D_PAD_GPIO1_IO07__I2C2_SDA | - MUX_PAD_CTRL(I2C_PAD_CTRL), - .gpio_mode = MX7D_PAD_GPIO1_IO07__GPIO1_IO7 | - MUX_PAD_CTRL(I2C_PAD_CTRL), - .gp = CL_SOM_IMX7_GPIO_I2C2_SDA, - }, -}; - -/* - * cl_som_imx7_setup_i2c() - I2C pinmux configuration. - */ -static void cl_som_imx7_setup_i2c(void) -{ - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &cl_som_imx7_i2c_pad_info2); -} -#else /* !CONFIG_SYS_I2C_MXC */ -static void cl_som_imx7_setup_i2c(void) {} -#endif /* CONFIG_SYS_I2C_MXC */ - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -#ifdef CONFIG_FSL_ESDHC - -#define CL_SOM_IMX7_GPIO_USDHC3_PWR IMX_GPIO_NR(6, 11) - -static struct fsl_esdhc_cfg cl_som_imx7_usdhc_cfg[3] = { - {USDHC1_BASE_ADDR, 0, 4}, - {USDHC3_BASE_ADDR}, -}; - -int board_mmc_init(bd_t *bis) -{ - int i, ret; - /* - * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc2 USDHC3 (eMMC) - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - cl_som_imx7_usdhc1_pads_set(); - gpio_request(CL_SOM_IMX7_GPIO_USDHC1_CD, "usdhc1_cd"); - cl_som_imx7_usdhc_cfg[0].sdhc_clk = - mxc_get_clock(MXC_ESDHC_CLK); - break; - case 1: - cl_som_imx7_usdhc3_emmc_pads_set(); - gpio_request(CL_SOM_IMX7_GPIO_USDHC3_PWR, "usdhc3_pwr"); - gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 0); - udelay(500); - gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 1); - cl_som_imx7_usdhc_cfg[1].sdhc_clk = - mxc_get_clock(MXC_ESDHC3_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers " - "(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &cl_som_imx7_usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} -#endif /* CONFIG_FSL_ESDHC */ - -#ifdef CONFIG_FEC_MXC - -#define CL_SOM_IMX7_ETH1_PHY_NRST IMX_GPIO_NR(1, 4) - -/* - * cl_som_imx7_rgmii_rework() - Ethernet PHY configuration. - */ -static void cl_som_imx7_rgmii_rework(struct phy_device *phydev) -{ - unsigned short val; - - /* Ar8031 phy SmartEEE feature cause link status generates glitch, - * which cause ethernet link down/up issue, so disable SmartEEE - */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= ~(0x1 << 8); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); - - /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); -} - -int board_phy_config(struct phy_device *phydev) -{ - cl_som_imx7_rgmii_rework(phydev); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -/* - * cl_som_imx7_handle_mac_address() - set Ethernet MAC address environment. - * - * @env_var: MAC address environment variable - * @eeprom_bus: I2C bus of the environment EEPROM - * - * @return: 0 on success, < 0 on failure - */ -static int cl_som_imx7_handle_mac_address(char *env_var, uint eeprom_bus) -{ - int ret; - unsigned char enetaddr[6]; - - ret = eth_env_get_enetaddr(env_var, enetaddr); - if (ret) - return 0; - - ret = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus); - if (ret) - return ret; - - ret = is_valid_ethaddr(enetaddr); - if (!ret) - return -1; - - return eth_env_set_enetaddr(env_var, enetaddr); -} - -#define CL_SOM_IMX7_FEC_DEV_ID_PRI 0 - -int board_eth_init(bd_t *bis) -{ - /* set Ethernet MAC address environment */ - cl_som_imx7_handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS); - /* Ethernet interface pinmux configuration */ - cl_som_imx7_phy1_rst_pads_set(); - cl_som_imx7_fec1_pads_set(); - /* PHY reset */ - gpio_request(CL_SOM_IMX7_ETH1_PHY_NRST, "eth1_phy_nrst"); - gpio_direction_output(CL_SOM_IMX7_ETH1_PHY_NRST, 0); - mdelay(10); - gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1); - /* MAC initialization */ - return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI, - CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); -} - -/* - * cl_som_imx7_setup_fec() - Ethernet MAC 1 clock configuration. - * - ENET1 reference clock mode select. - * - ENET1_TX_CLK output driver is disabled when configured for ALT1. - */ -static void cl_som_imx7_setup_fec(void) -{ - struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs - = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ - clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], - (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | - IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); - - set_clk_enet(ENET_125MHZ); -} -#else /* !CONFIG_FEC_MXC */ -static void cl_som_imx7_setup_fec(void) {} -#endif /* CONFIG_FEC_MXC */ - -#ifdef CONFIG_SPI - -static void cl_som_imx7_spi_init(void) -{ - cl_som_imx7_espi1_pads_set(); -} -#else /* !CONFIG_SPI */ -static void cl_som_imx7_spi_init(void) {} -#endif /* CONFIG_SPI */ - -int board_early_init_f(void) -{ - cl_som_imx7_uart1_pads_set(); - cl_som_imx7_usb_otg1_pads_set(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - cl_som_imx7_setup_i2c(); - cl_som_imx7_setup_fec(); - cl_som_imx7_spi_init(); - - return 0; -} - -#ifdef CONFIG_POWER -#define I2C_PMIC 0 -int power_init_board(void) -{ - struct pmic *p; - int ret; - unsigned int reg, rev_id; - - ret = power_pfuze3000_init(I2C_PMIC); - if (ret) - return ret; - - p = pmic_get("PFUZE3000"); - ret = pmic_probe(p); - if (ret) - return ret; - - pmic_reg_read(p, PFUZE3000_DEVICEID, &reg); - pmic_reg_read(p, PFUZE3000_REVID, &rev_id); - printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); - - /* disable Low Power Mode during standby mode */ - pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1); - - return 0; -} -#endif /* CONFIG_POWER */ - -/* - * cl_som_imx7_setup_wdog() - watchdog configuration. - * - Output WDOG_B signal to reset external pmic. - * - Suspend the watchdog timer during low-power modes. - */ -void cl_som_imx7_setup_wdog(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - cl_som_imx7_wdog_pads_set(); - set_wdog_reset(wdog); - /* - * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), - * since we use PMIC_PWRON to reset the board. - */ - clrsetbits_le16(&wdog->wcr, 0, 0x10); -} - -int board_late_init(void) -{ - env_set("board_name", "CL-SOM-iMX7"); - cl_som_imx7_setup_wdog(); - return 0; -} - -int checkboard(void) -{ - char *mode; - - if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) - mode = "secure"; - else - mode = "non-secure"; - - printf("Board: CL-SOM-iMX7 in %s mode\n", mode); - - return 0; -} diff --git a/board/compulab/cl-som-imx7/common.c b/board/compulab/cl-som-imx7/common.c deleted file mode 100644 index e0f90fd5c48..00000000000 --- a/board/compulab/cl-som-imx7/common.c +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SPL/U-Boot common functions for CompuLab CL-SOM-iMX7 module - * - * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com - * - * Author: Uri Mashiach uri.mashiach@compulab.co.il - */ - -#include <common.h> -#include <fsl_esdhc.h> -#include <asm-generic/gpio.h> -#include "common.h" - -#ifdef CONFIG_SPI - -#define CL_SOM_IMX7_GPIO_SPI_CS IMX_GPIO_NR(4, 19) - -int board_spi_cs_gpio(unsigned int bus, unsigned int cs) -{ - return CL_SOM_IMX7_GPIO_SPI_CS; -} - -#endif /* CONFIG_SPI */ - -#ifdef CONFIG_FSL_ESDHC - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(CL_SOM_IMX7_GPIO_USDHC1_CD); - break; - case USDHC3_BASE_ADDR: - ret = 1; /* Assume uSDHC3 emmc is always present */ - break; - } - - return ret; -} - -#endif /* CONFIG_FSL_ESDHC */ diff --git a/board/compulab/cl-som-imx7/common.h b/board/compulab/cl-som-imx7/common.h deleted file mode 100644 index 8b15a59abeb..00000000000 --- a/board/compulab/cl-som-imx7/common.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * SPL/U-Boot common header file for CompuLab CL-SOM-iMX7 module - * - * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com - * - * Author: Uri Mashiach uri.mashiach@compulab.co.il - */ - -#define PADS_SET_PROT(pads_array) void cl_som_imx7_##pads_array##_set(void) - -#ifdef CONFIG_FSL_ESDHC -#define CL_SOM_IMX7_GPIO_USDHC1_CD IMX_GPIO_NR(5, 0) -PADS_SET_PROT(usdhc1_pads); -#endif /* CONFIG_FSL_ESDHC */ -PADS_SET_PROT(uart1_pads); -#ifdef CONFIG_SPI -PADS_SET_PROT(espi1_pads); -#endif /* CONFIG_SPI */ - -#ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_FSL_ESDHC -PADS_SET_PROT(usdhc3_emmc_pads); -#endif /* CONFIG_FSL_ESDHC */ -#ifdef CONFIG_FEC_MXC -PADS_SET_PROT(phy1_rst_pads); -PADS_SET_PROT(fec1_pads); -#endif /* CONFIG_FEC_MXC */ -PADS_SET_PROT(usb_otg1_pads); -PADS_SET_PROT(wdog_pads); -#endif /* !CONFIG_SPL_BUILD */ diff --git a/board/compulab/cl-som-imx7/mux.c b/board/compulab/cl-som-imx7/mux.c deleted file mode 100644 index e29d2deaf2b..00000000000 --- a/board/compulab/cl-som-imx7/mux.c +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SPL/U-Boot mux functions for CompuLab CL-SOM-iMX7 module - * - * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com - * - * Author: Uri Mashiach uri.mashiach@compulab.co.il - */ - -#include <common.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/arch-mx7/mx7-pins.h> - -#define PADS_SET(pads_array) \ -void cl_som_imx7_##pads_array##_set(void) \ -{ \ - imx_iomux_v3_setup_multiple_pads(pads_array, ARRAY_SIZE(pads_array)); \ -} - -#ifdef CONFIG_FSL_ESDHC - -#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | \ - PAD_CTL_PUS_PU47KOHM) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -PADS_SET(usdhc1_pads) - -#endif /* CONFIG_FSL_ESDHC */ - -#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ - PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) - -static iomux_v3_cfg_t const uart1_pads[] = { - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -PADS_SET(uart1_pads) - -#ifdef CONFIG_SPI - -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SRE_SLOW | \ - PAD_CTL_DSE_3P3V_32OHM) - -#define GPIO_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_PUE | \ - PAD_CTL_SRE_SLOW) - -static iomux_v3_cfg_t const espi1_pads[] = { - MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL), -}; - -PADS_SET(espi1_pads) - -#endif /* CONFIG_SPI */ - -#ifndef CONFIG_SPL_BUILD - -#ifdef CONFIG_FSL_ESDHC - -static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { - MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -PADS_SET(usdhc3_emmc_pads) - -#endif /* CONFIG_FSL_ESDHC */ - -#ifdef CONFIG_FEC_MXC - -#define ENET_PAD_CTRL (PAD_CTL_PUS_PD100KOHM | PAD_CTL_DSE_3P3V_49OHM) -#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU5KOHM) - -static iomux_v3_cfg_t const phy1_rst_pads[] = { - /* PHY1 RST */ - MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(GPIO_PAD_CTRL), -}; - -PADS_SET(phy1_rst_pads) - -static iomux_v3_cfg_t const fec1_pads[] = { - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | - MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | - MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), - MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), -}; - -PADS_SET(fec1_pads) - -#endif /* CONFIG_FEC_MXC */ - -static iomux_v3_cfg_t const usb_otg1_pads[] = { - MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -PADS_SET(usb_otg1_pads) - -static iomux_v3_cfg_t const wdog_pads[] = { - MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -PADS_SET(wdog_pads) - -#endif /* !CONFIG_SPL_BUILD */ diff --git a/board/compulab/cl-som-imx7/spl.c b/board/compulab/cl-som-imx7/spl.c deleted file mode 100644 index 76a4c8beb02..00000000000 --- a/board/compulab/cl-som-imx7/spl.c +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SPL board functions for CompuLab CL-SOM-iMX7 module - * - * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com - * - * Author: Uri Mashiach uri.mashiach@compulab.co.il - */ - -#include <common.h> -#include <spl.h> -#include <fsl_esdhc.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/arch-mx7/mx7-pins.h> -#include <asm/arch-mx7/clock.h> -#include <asm/arch-mx7/mx7-ddr.h> -#include "common.h" - -#ifdef CONFIG_FSL_ESDHC - -static struct fsl_esdhc_cfg cl_som_imx7_spl_usdhc_cfg = { - USDHC1_BASE_ADDR, 0, 4}; - -int board_mmc_init(bd_t *bis) -{ - cl_som_imx7_usdhc1_pads_set(); - cl_som_imx7_spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - return fsl_esdhc_initialize(bis, &cl_som_imx7_spl_usdhc_cfg); -} -#endif /* CONFIG_FSL_ESDHC */ - -static iomux_v3_cfg_t const led_pads[] = { - MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 | MUX_PAD_CTRL(PAD_CTL_PUS_PU5KOHM | - PAD_CTL_PUE | PAD_CTL_SRE_SLOW) -}; - -static struct ddrc cl_som_imx7_spl_ddrc_regs_val = { - .init1 = 0x00690000, - .init0 = 0x00020083, - .init3 = 0x09300004, - .init4 = 0x04080000, - .init5 = 0x00100004, - .rankctl = 0x0000033F, - .dramtmg1 = 0x0007020E, - .dramtmg2 = 0x03040407, - .dramtmg3 = 0x00002006, - .dramtmg4 = 0x04020305, - .dramtmg5 = 0x03030202, - .dramtmg8 = 0x00000803, - .zqctl0 = 0x00810021, - .dfitmg0 = 0x02098204, - .dfitmg1 = 0x00030303, - .dfiupd0 = 0x80400003, - .dfiupd1 = 0x00100020, - .dfiupd2 = 0x80100004, - .addrmap4 = 0x00000F0F, - .odtcfg = 0x06000604, - .odtmap = 0x00000001, -}; - -static struct ddrc_mp cl_som_imx7_spl_ddrc_mp_val = { - .pctrl_0 = 0x00000001, -}; - -static struct ddr_phy cl_som_imx7_spl_ddr_phy_regs_val = { - .phy_con0 = 0x17420F40, - .phy_con1 = 0x10210100, - .phy_con4 = 0x00060807, - .mdll_con0 = 0x1010007E, - .drvds_con0 = 0x00000D6E, - .cmd_sdll_con0 = 0x00000010, - .offset_lp_con0 = 0x0000000F, -}; - -struct mx7_calibration cl_som_imx7_spl_calib_param = { - .num_val = 5, - .values = { - 0x0E407304, - 0x0E447304, - 0x0E447306, - 0x0E447304, - 0x0E407304, - }, -}; - -static void cl_som_imx7_spl_dram_cfg_size(u32 ram_size) -{ - switch (ram_size) { - case SZ_256M: - cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01041001; - cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046; - cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; - cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000014; - cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00151515; - cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x03030303; - cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F0F0303; - cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0C0C0C0C; - cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404; - break; - case SZ_512M: - cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; - cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046; - cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; - cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000015; - cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00161616; - cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404; - cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F0F0404; - cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0C0C0C0C; - cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404; - break; - case SZ_1G: - cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; - cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046; - cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; - cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000016; - cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00171717; - cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404; - cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F040404; - cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0A0A0A0A; - cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x02020202; - break; - case SZ_2G: - cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; - cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x0040005E; - cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E110A; - cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000018; - cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00181818; - cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404; - cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x04040404; - cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0A0A0A0A; - cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404; - break; - } - - mx7_dram_cfg(&cl_som_imx7_spl_ddrc_regs_val, - &cl_som_imx7_spl_ddrc_mp_val, - &cl_som_imx7_spl_ddr_phy_regs_val, - &cl_som_imx7_spl_calib_param); -} - -static void cl_som_imx7_spl_dram_cfg(void) -{ - ulong ram_size_test, ram_size = 0; - - for (ram_size = SZ_2G; ram_size >= SZ_256M; ram_size >>= 1) { - cl_som_imx7_spl_dram_cfg_size(ram_size); - ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size); - if (ram_size_test == ram_size) - break; - } - - if (ram_size < SZ_256M) { - puts("!!!ERROR!!! DRAM detection failed!!!\n"); - hang(); - } -} - -#ifdef CONFIG_SPL_SPI_SUPPORT - -static void cl_som_imx7_spl_spi_init(void) -{ - cl_som_imx7_espi1_pads_set(); -} -#else /* !CONFIG_SPL_SPI_SUPPORT */ -static void cl_som_imx7_spl_spi_init(void) {} -#endif /* CONFIG_SPL_SPI_SUPPORT */ - -void board_init_f(ulong dummy) -{ - imx_iomux_v3_setup_multiple_pads(led_pads, 1); - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - /* setup GP timer */ - timer_init(); - cl_som_imx7_spl_spi_init(); - cl_som_imx7_uart1_pads_set(); - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - /* DRAM detection */ - cl_som_imx7_spl_dram_cfg(); - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} - -void spl_board_init(void) -{ - u32 boot_device = spl_boot_device(); - - if (boot_device == BOOT_DEVICE_SPI) - puts("Booting from SPI flash\n"); - else if (boot_device == BOOT_DEVICE_MMC1) - puts("Booting from SD card\n"); - else - puts("Unknown boot device\n"); -} - -void board_boot_order(u32 *spl_boot_list) -{ - spl_boot_list[0] = spl_boot_device(); - switch (spl_boot_list[0]) { - case BOOT_DEVICE_SPI: - spl_boot_list[1] = BOOT_DEVICE_MMC1; - break; - case BOOT_DEVICE_MMC1: - spl_boot_list[1] = BOOT_DEVICE_SPI; - break; - } -} diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig deleted file mode 100644 index 0eed5264f2a..00000000000 --- a/configs/cl-som-imx7_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_CL_SOM_IMX7=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ARMV7_BOOT_SEC_DEFAULT=y -CONFIG_IMX_RDC=y -CONFIG_IMX_BOOTAUX=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_SPI_BOOT=y -CONFIG_BOOTDELAY=3 -CONFIG_SPL_BOARD_INIT=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80 -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="CL-SOM-iMX7 # " -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_IMPORTENV is not set -CONFIG_CMD_GREPENV=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -# CONFIG_ENV_IS_IN_MMC is not set -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_FSL_ESDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_MXC_USB_OTG_HACTIVE=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_CI_UDC=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h deleted file mode 100644 index f84a11215e4..00000000000 --- a/include/configs/cl-som-imx7.h +++ /dev/null @@ -1,182 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 CompuLab, Ltd. - * - * Configuration settings for the CompuLab CL-SOM-iMX7 System-on-Module. - */ - -#ifndef __CL_SOM_IMX7_CONFIG_H -#define __CL_SOM_IMX7_CONFIG_H - -#include "mx7_common.h" - -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - -#define CONFIG_BOARD_LATE_INIT - -/* Uncomment to enable secure boot support */ -/* #define CONFIG_SECURE_BOOT */ -#define CONFIG_CSF_SIZE 0x4000 - -/* Network */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_PHYLIB -#define CONFIG_PHY_ATHEROS -/* ENET1 */ -#define IMX_FEC_BASE ENET_IPS_BASE_ADDR - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE3000 -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 - -#undef CONFIG_BOOTM_NETBSD -#undef CONFIG_BOOTM_PLAN9 -#undef CONFIG_BOOTM_RTEMS - -/* I2C configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C2 /* Enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define SYS_I2C_BUS_SOM 0 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS SYS_I2C_BUS_SOM - -#define CONFIG_PCA953X -#define CONFIG_CMD_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } - -#undef CONFIG_SYS_AUTOLOAD -#undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_SYS_AUTOLOAD "no" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=off\0" \ - "script=boot.scr\0" \ - "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \ - "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \ - "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${fdtfile};\0" \ - "bootscript=echo Running bootscript from ${storagetype} ...; source ${loadaddr};\0" \ - "storagebootcmd=echo Booting from ${storagetype} ...; run ${storagetype}args; run doboot;\0" \ - "kernel=zImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdtfile=imx7d-sbc-imx7.dtb\0" \ - "fdtaddr=0x83000000\0" \ - "mmcdev_def="__stringify(CONFIG_SYS_MMC_DEV)"\0" \ - "usbdev_def="__stringify(CONFIG_SYS_USB_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "usbpart=" __stringify(CONFIG_SYS_USB_IMG_LOAD_PART) "\0" \ - "doboot=bootz ${loadaddr} - ${fdtaddr}\0" \ - "mmc_config=mmc dev ${mmcdev}; mmc rescan\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/mmcblk${mmcblk}p2 rootwait rw\0" \ - "mmcbootscript=" \ - "if run mmc_config; then " \ - "setenv storagetype mmc;" \ - "setenv storagedev ${mmcdev}:${mmcpart};" \ - "if run loadscript; then " \ - "run bootscript; " \ - "fi; " \ - "fi;\0" \ - "mmcboot=" \ - "if run mmc_config; then " \ - "setenv storagetype mmc;" \ - "setenv storagedev ${mmcdev}:${mmcpart};" \ - "if run loadkernel; then " \ - "if run loadfdt; then " \ - "run storagebootcmd;" \ - "fi; " \ - "fi; " \ - "fi;\0" \ - "sdbootscript=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; " \ - "run mmcbootscript\0" \ - "usbbootscript=setenv usbdev ${usbdev_def}; " \ - "setenv storagetype usb;" \ - "setenv storagedev ${usbdev}:${usbpart};" \ - "if run loadscript; then " \ - "run bootscript; " \ - "fi; " \ - "sdboot=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; run mmcboot\0" \ - "emmcbootscript=setenv mmcdev 1; setenv mmcblk 2; run mmcbootscript\0" \ - "emmcboot=setenv mmcdev 1; setenv mmcblk 2; run mmcboot\0" \ - -#define CONFIG_BOOTCOMMAND \ - "echo SD boot attempt ...; run sdbootscript; run sdboot; " \ - "echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \ - "echo USB boot attempt ...; run usbbootscript; " - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* SPI Flash support */ -#define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS 0 -#define CONFIG_SF_DEFAULT_SPEED 20000000 -#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) - -/* FLASH and environment organization */ -#define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (768 * 1024) -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS -#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS -#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED - -/* MMC Config*/ -#define CONFIG_FSL_USDHC -#ifdef CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR - -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -#endif - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* Uncomment to enable iMX thermal driver support */ -/*#define CONFIG_IMX_THERMAL*/ - -/* SPL */ -#include "imx7_spl.h" -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) -#endif /* CONFIG_SPL_BUILD */ - -#endif /* __CONFIG_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/Kconfig | 1 - board/silica/pengwyn/Kconfig | 15 --- board/silica/pengwyn/MAINTAINERS | 6 - board/silica/pengwyn/Makefile | 11 -- board/silica/pengwyn/board.c | 201 ------------------------------- board/silica/pengwyn/board.h | 14 --- board/silica/pengwyn/mux.c | 97 --------------- configs/pengwyn_defconfig | 62 ---------- include/configs/pengwyn.h | 171 -------------------------- 9 files changed, 578 deletions(-) delete mode 100644 board/silica/pengwyn/Kconfig delete mode 100644 board/silica/pengwyn/MAINTAINERS delete mode 100644 board/silica/pengwyn/Makefile delete mode 100644 board/silica/pengwyn/board.c delete mode 100644 board/silica/pengwyn/board.h delete mode 100644 board/silica/pengwyn/mux.c delete mode 100644 configs/pengwyn_defconfig delete mode 100644 include/configs/pengwyn.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 740897539e8..4cb32325ed3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1521,7 +1521,6 @@ source "board/h2200/Kconfig" source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" -source "board/silica/pengwyn/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/board/silica/pengwyn/Kconfig b/board/silica/pengwyn/Kconfig deleted file mode 100644 index f2e1098f62a..00000000000 --- a/board/silica/pengwyn/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_PENGWYN - -config SYS_BOARD - default "pengwyn" - -config SYS_VENDOR - default "silica" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "pengwyn" - -endif diff --git a/board/silica/pengwyn/MAINTAINERS b/board/silica/pengwyn/MAINTAINERS deleted file mode 100644 index 14ef7750c54..00000000000 --- a/board/silica/pengwyn/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PENGWYN BOARD -M: Lothar Felten lothar.felten@gmail.com -S: Maintained -F: board/silica/pengwyn/ -F: include/configs/pengwyn.h -F: configs/pengwyn_defconfig diff --git a/board/silica/pengwyn/Makefile b/board/silica/pengwyn/Makefile deleted file mode 100644 index c34b9b1dd8a..00000000000 --- a/board/silica/pengwyn/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Makefile -# -# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - -ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) -obj-y := mux.o -endif - -obj-y += board.o diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c deleted file mode 100644 index 90ea8c601c4..00000000000 --- a/board/silica/pengwyn/board.c +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * board.c - * - * Copyright (C) 2013 Lothar Felten lothar.felten@gmail.com - */ - -#include <common.h> -#include <environment.h> -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> -#include <asm/arch/ddr_defs.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <i2c.h> -#include <phy.h> -#include <cpsw.h> -#include "board.h" - -DECLARE_GLOBAL_DATA_PTR; - -static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - -#if defined(CONFIG_SPL_BUILD) - -/* DDR3 RAM timings */ -static const struct ddr_data ddr3_data = { - .datardsratio0 = MT41K128MJT187E_RD_DQS, - .datawdsratio0 = MT41K128MJT187E_WR_DQS, - .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE, - .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA, -}; - -static const struct cmd_control ddr3_cmd_ctrl_data = { - .cmd0csratio = MT41K128MJT187E_RATIO, - .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT, - .cmd1csratio = MT41K128MJT187E_RATIO, - .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT, - .cmd2csratio = MT41K128MJT187E_RATIO, - .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT, -}; - -static struct emif_regs ddr3_emif_reg_data = { - .sdram_config = MT41K128MJT187E_EMIF_SDCFG, - .ref_ctrl = MT41K128MJT187E_EMIF_SDREF, - .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1, - .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2, - .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3, - .zq_config = MT41K128MJT187E_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY | - PHY_EN_DYN_PWRDN, -}; - -const struct ctrl_ioregs ddr3_ioregs = { - .cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE, - .cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE, - .cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE, - .dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE, - .dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE, -}; - -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - /* break into full u-boot on 'c' */ - return serial_tstc() && serial_getc() == 'c'; -} -#endif - -#define OSC (V_OSCK/1000000) -const struct dpll_params dpll_ddr_266 = { - 266, OSC-1, 1, -1, -1, -1, -1}; -const struct dpll_params dpll_ddr_303 = { - 303, OSC-1, 1, -1, -1, -1, -1}; -const struct dpll_params dpll_ddr_400 = { - 400, OSC-1, 1, -1, -1, -1, -1}; - -void am33xx_spl_board_init(void) -{ - /* - * The pengwyn board uses the TPS650250 PMIC without I2C - * interface and will output the following fixed voltages: - * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu) - * VLDO1=1V8 (IO) VLDO2=1V8(IO) - * Vcore=1V1 is fixed, generated by TPS62231 - */ - - /* Get the frequency */ - dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); - - /* Set CORE Frequencies to OPP100 */ - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); - - /* 720MHz cpu, this might change on newer board revisions */ - dpll_mpu_opp100.m = MPUPLL_M_720; - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); -} - -const struct dpll_params *get_dpll_ddr_params(void) -{ - /* future configs can return other clock settings */ - return &dpll_ddr_303; -} - -void set_uart_mux_conf(void) -{ - enable_uart0_pin_mux(); -} - -void set_mux_conf_regs(void) -{ - enable_board_pin_mux(); -} - -void sdram_init(void) -{ - config_ddr(303, &ddr3_ioregs, &ddr3_data, - &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -} -#endif /* if CONFIG_SPL_BUILD */ - -/* - * Basic board specific setup. Pinmux has been handled already. - */ -int board_init(void) -{ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - gpmc_init(); - return 0; -} - -#ifdef CONFIG_DRIVER_TI_CPSW -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ - return; -} - -static struct cpsw_slave_data cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 1, - .phy_if = PHY_INTERFACE_MODE_MII, - }, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 1, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; - -int board_eth_init(bd_t *bis) -{ - int rv, n = 0; - uint8_t mac_addr[6]; - uint32_t mac_hi, mac_lo; - - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { - printf("<ethaddr> not set. Reading from E-fuse\n"); - /* try reading mac address from efuse */ - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - mac_addr[0] = mac_hi & 0xFF; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - mac_addr[4] = mac_lo & 0xFF; - mac_addr[5] = (mac_lo & 0xFF00) >> 8; - - if (is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("ethaddr", mac_addr); - else - return n; - } - - writel(MII_MODE_ENABLE, &cdev->miisel); - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - else - n += rv; - return n; -} -#endif /* if CONFIG_DRIVER_TI_CPSW */ diff --git a/board/silica/pengwyn/board.h b/board/silica/pengwyn/board.h deleted file mode 100644 index 3d5ce6d3939..00000000000 --- a/board/silica/pengwyn/board.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * board.h - * - * Copyright (C) 2013 Lothar Felten lothar.felten@gmail.com - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -void enable_uart0_pin_mux(void); -void enable_board_pin_mux(void); - -#endif diff --git a/board/silica/pengwyn/mux.c b/board/silica/pengwyn/mux.c deleted file mode 100644 index 7583e833ed4..00000000000 --- a/board/silica/pengwyn/mux.c +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * mux.c - * - * Copyright (C) 2013 Lothar Felten lothar.felten@gmail.com - */ - -#include <common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/hardware.h> -#include <asm/arch/mux.h> -#include <asm/io.h> -#include "board.h" - -/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */ -static struct module_pin_mux uart0_pin_mux[] = { - {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ - {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ - {-1}, -}; - -/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */ - -/* I2C pins C16(scl)/C17(sda) */ -static struct module_pin_mux i2c0_pin_mux[] = { - {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | - PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */ - {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | - PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */ - {-1}, -}; - -/* MMC0 pins */ -static struct module_pin_mux mmc0_pin_mux[] = { - {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ - {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ - {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ - {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ - {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ - {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ - {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ - {-1}, -}; - -/* MII pins */ -static struct module_pin_mux mii1_pin_mux[] = { - {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ - {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ - {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ - {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ - {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ - {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ - {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ - {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ - {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ - {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ - {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ - {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ - {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ - {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ - {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ - {-1}, -}; - -/* NAND pins */ -static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ - {-1}, -}; - -void enable_uart0_pin_mux(void) -{ - configure_module_pin_mux(uart0_pin_mux); -} - -void enable_board_pin_mux() -{ - configure_module_pin_mux(i2c0_pin_mux); - configure_module_pin_mux(uart0_pin_mux); - configure_module_pin_mux(mii1_pin_mux); - configure_module_pin_mux(mmc0_pin_mux); - configure_module_pin_mux(nand_pin_mux); -} diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig deleted file mode 100644 index 3c8684ad958..00000000000 --- a/configs/pengwyn_defconfig +++ /dev/null @@ -1,62 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_AM33XX=y -CONFIG_TARGET_PENGWYN=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_ARCH_MISC_INIT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_ETH_SUPPORT=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_NET_SUPPORT=y -CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_CMD_SPL=y -CONFIG_CMD_SPL_NAND_OFS=0x240000 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_WOL=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(SPL),512k(SPL.backup1),512k(SPL.backup2),512k(SPL.backup3),1536k(u-boot),512k(u-boot-spl-os),512k(u-boot-env),5m(kernel),-(rootfs)" -CONFIG_CMD_DIAG=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_MMC_OMAP_HS=y -CONFIG_NAND=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_MUSB_HOST=y -CONFIG_USB_MUSB_GADGET=y -CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h deleted file mode 100644 index 48f1f7baccb..00000000000 --- a/include/configs/pengwyn.h +++ /dev/null @@ -1,171 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * pengwyn.h - * - * Copyright (C) 2013 Lothar Felten lothar.felten@gmail.com - * - * based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc. - */ - -#ifndef __CONFIG_PENGWYN_H -#define __CONFIG_PENGWYN_H - - -#include <configs/ti_am335x_common.h> - -/* Clock Defines */ -#define V_OSCK 24000000 -#define V_SCLK V_OSCK - -/* set env size */ -#define CONFIG_ENV_SIZE 0x4000 - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "fdtaddr=0x80F80000\0" \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "fdtfile=am335x-pengwyn.dtb\0" \ - "console=ttyO0,115200n8\0" \ - "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 ro\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "rootpath=/export/rootfs\0" \ - "nfsopts=nolock\0" \ - "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ - "::off\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "netargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=/dev/nfs " \ - "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ - "ip=dhcp\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "mmcloados=run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr};\0" \ - "mmcboot=mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loadimage; then " \ - "run loadfdt;" \ - "run mmcloados;" \ - "fi;" \ - "fi;\0" \ - "netboot=echo Booting from network ...; " \ - "setenv autoload no; " \ - "dhcp; " \ - "tftp ${loadaddr} ${bootfile}; " \ - "tftp ${fdtaddr} ${fdtfile}; " \ - "run netargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${fdtaddr} u-boot-spl-os; " \ - "nand read ${loadaddr} kernel; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" -#endif - -#define CONFIG_BOOTCOMMAND \ - "run mmcboot;" \ - "run nandboot;" - -/* NS16550 Configuration: primary UART via FTDI */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 - -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* SPL */ - -/* NAND support */ - -/* NAND Configuration. */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE 4096 -#define CONFIG_SYS_NAND_OOBSIZE 224 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*4096) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ - 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\ - 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,\ - 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65,\ - 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,\ - 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,\ - 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,\ - 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\ - 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153,\ - 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,\ - 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193,\ - 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209} - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 26 -#define CONFIG_SYS_NAND_ECCSTEPS 8 -#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ - CONFIG_SYS_NAND_ECCSTEPS) -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW -/* END NAND Configuration. */ - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -/* #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 - -/* Size must be a multiple of Nand erase size (524288 b) */ -#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#endif - -/* - * USB configuration. We enable MUSB support, both for host and for - * gadget. We set USB0 as peripheral and USB1 as host, based on the - * board schematic and physical port wired to each. Then for host we - * add mass storage support. - */ -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT -#define CONFIG_AM335X_USB0 -#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL -#define CONFIG_AM335X_USB1 -#define CONFIG_AM335X_USB1_MODE MUSB_HOST - -/* Network */ -#define CONFIG_PHY_RESET 1 -#define CONFIG_PHY_NATSEMI -#define CONFIG_PHY_REALTEK - -#endif /* ! __CONFIG_PENGWYN_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-imx/mx6/Kconfig | 1 - board/freescale/mx6sabreauto/Kconfig | 12 - board/freescale/mx6sabreauto/MAINTAINERS | 7 - board/freescale/mx6sabreauto/Makefile | 7 - board/freescale/mx6sabreauto/README | 82 -- board/freescale/mx6sabreauto/mx6sabreauto.c | 1099 ------------------- configs/mx6sabreauto_defconfig | 67 -- include/configs/mx6sabreauto.h | 78 -- 8 files changed, 1353 deletions(-) delete mode 100644 board/freescale/mx6sabreauto/Kconfig delete mode 100644 board/freescale/mx6sabreauto/MAINTAINERS delete mode 100644 board/freescale/mx6sabreauto/Makefile delete mode 100644 board/freescale/mx6sabreauto/README delete mode 100644 board/freescale/mx6sabreauto/mx6sabreauto.c delete mode 100644 configs/mx6sabreauto_defconfig delete mode 100644 include/configs/mx6sabreauto.h

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 701973b3866..face0f09827 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -538,7 +538,6 @@ source "board/engicam/imx6q/Kconfig" source "board/engicam/imx6ul/Kconfig" source "board/freescale/mx6qarm2/Kconfig" source "board/freescale/mx6memcal/Kconfig" -source "board/freescale/mx6sabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" source "board/freescale/mx6slevk/Kconfig" source "board/freescale/mx6sllevk/Kconfig" diff --git a/board/freescale/mx6sabreauto/Kconfig b/board/freescale/mx6sabreauto/Kconfig deleted file mode 100644 index 5b4faf6d5fd..00000000000 --- a/board/freescale/mx6sabreauto/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MX6SABREAUTO - -config SYS_BOARD - default "mx6sabreauto" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx6sabreauto" - -endif diff --git a/board/freescale/mx6sabreauto/MAINTAINERS b/board/freescale/mx6sabreauto/MAINTAINERS deleted file mode 100644 index a89f05a8293..00000000000 --- a/board/freescale/mx6sabreauto/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MX6SABREAUTO BOARD -M: Fabio Estevam fabio.estevam@nxp.com -M: Peng Fan peng.fan@nxp.com -S: Maintained -F: board/freescale/mx6sabreauto/ -F: include/configs/mx6sabreauto.h -F: configs/mx6sabreauto_defconfig diff --git a/board/freescale/mx6sabreauto/Makefile b/board/freescale/mx6sabreauto/Makefile deleted file mode 100644 index 7ecdb6b4ad2..00000000000 --- a/board/freescale/mx6sabreauto/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. - -obj-y := mx6sabreauto.o diff --git a/board/freescale/mx6sabreauto/README b/board/freescale/mx6sabreauto/README deleted file mode 100644 index e8c589b92aa..00000000000 --- a/board/freescale/mx6sabreauto/README +++ /dev/null @@ -1,82 +0,0 @@ -How to use and build U-Boot on mx6sabreauto -------------------------------------------- - -mx6sabreauto_defconfig target supports mx6q/mx6dl/mx6qp sabreauto variants. - -In order to build it: - -$ make mx6sabreauto_defconfig - -$ make - -This will generate the SPL and u-boot.img binaries. - -- Flash the SPL binary into the SD card: - -$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync - -- Flash the u-boot.img binary into the SD card: - -$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync - -Booting via Falcon mode ------------------------ - -Write in mx6sabreauto_defconfig the following define below: - -CONFIG_SPL_OS_BOOT=y - -In order to build it: - -$ make mx6sabreauto_defconfig - -$ make - -This will generate the SPL image called SPL and the u-boot.img. - -- Flash the SPL image into the SD card: - -$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync - -- Flash the u-boot.img image into the SD card: - -$ sudo dd if=u-boot.img of=/dev/sdb bs=1K seek=69 && sync - -Create a FAT16 boot partition to store uImage and the dtb file, then copy the files there: - -$ sudo cp uImage /media/boot - -$ sudo cp imx6dl-sabreauto.dtb /media/boot - -Create a partition for root file system and extract it there: - -$ sudo tar xvf rootfs.tar.gz -C /media/root - -The SD card must have enough space for raw "args" and "kernel". -To configure Falcon mode for the first time, on U-Boot do the following commands: - -- Load dtb file from boot partition: - -# load mmc 0:1 ${fdt_addr} imx6dl-sabreauto.dtb - -- Load kernel image from boot partition: - -# load mmc 0:1 ${loadaddr} uImage - -- Write kernel at 2MB offset: - -# mmc write ${loadaddr} 0x1000 0x4000 - -- Setup kernel bootargs: - -# setenv bootargs "console=ttymxc3,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait quiet rw" - -- Prepare args: - -# spl export fdt ${loadaddr} - ${fdt_addr} - -- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors) - -# mmc write 18000000 0x800 0x800 - -- Restart the board and then SPL binary will launch the kernel directly. diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c deleted file mode 100644 index c1bef8507c2..00000000000 --- a/board/freescale/mx6sabreauto/mx6sabreauto.c +++ /dev/null @@ -1,1099 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam fabio.estevam@freescale.com - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/spi.h> -#include <mmc.h> -#include <fsl_esdhc.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/sys_proto.h> -#include <i2c.h> -#include <input.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/mach-imx/video.h> -#include <asm/arch/crm_regs.h> -#include <pca953x.h> -#include <power/pmic.h> -#include <power/pfuze100_pmic.h> -#include "../common/pfuze.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) -#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ - PAD_CTL_SRE_FAST) -#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define I2C_PMIC 1 - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static iomux_v3_cfg_t const uart4_pads[] = { - IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const enet_pads[] = { - IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), -}; - -/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */ -static struct i2c_pads_info mx6q_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC, - .gp = IMX_GPIO_NR(2, 30) - }, - .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -static struct i2c_pads_info mx6dl_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC, - .gp = IMX_GPIO_NR(2, 30) - }, - .sda = { - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -#ifndef CONFIG_SYS_FLASH_CFI -/* - * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor, - * Compass Sensor, Accelerometer, Res Touch - */ -static struct i2c_pads_info mx6q_i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC, - .gp = IMX_GPIO_NR(3, 18) - } -}; - -static struct i2c_pads_info mx6dl_i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC, - .gp = IMX_GPIO_NR(3, 18) - } -}; -#endif - -static iomux_v3_cfg_t const i2c3_pads[] = { - IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const port_exp[] = { - IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -/*Define for building port exp gpio, pin starts from 0*/ -#define PORTEXP_IO_NR(chip, pin) \ - ((chip << 5) + pin) - -/*Get the chip addr from a ioexp gpio*/ -#define PORTEXP_IO_TO_CHIP(gpio_nr) \ - (gpio_nr >> 5) - -/*Get the pin number from a ioexp gpio*/ -#define PORTEXP_IO_TO_PIN(gpio_nr) \ - (gpio_nr & 0x1f) - -static int port_exp_direction_output(unsigned gpio, int value) -{ - int ret; - - i2c_set_bus_num(2); - ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio)); - if (ret) - return ret; - - ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio), - (1 << PORTEXP_IO_TO_PIN(gpio)), - (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio))); - - if (ret) - return ret; - - ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio), - (1 << PORTEXP_IO_TO_PIN(gpio)), - (value << PORTEXP_IO_TO_PIN(gpio))); - - if (ret) - return ret; - - return 0; -} - -#ifdef CONFIG_MTD_NOR_FLASH -static iomux_v3_cfg_t const eimnor_pads[] = { - IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static void eimnor_cs_setup(void) -{ - struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; - - writel(0x00020181, &weim_regs->cs0gcr1); - writel(0x00000001, &weim_regs->cs0gcr2); - writel(0x0a020000, &weim_regs->cs0rcr1); - writel(0x0000c000, &weim_regs->cs0rcr2); - writel(0x0804a240, &weim_regs->cs0wcr1); - writel(0x00000120, &weim_regs->wcr); - - set_chipselect_size(CS0_128); -} - -static void eim_clk_setup(void) -{ - struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int cscmr1, ccgr6; - - - /* Turn off EIM clock */ - ccgr6 = readl(&imx_ccm->CCGR6); - ccgr6 &= ~(0x3 << 10); - writel(ccgr6, &imx_ccm->CCGR6); - - /* - * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root - * and aclk_eim_slow_podf = 01 --> divide by 2 - * so that we can have EIM at the maximum clock of 132MHz - */ - cscmr1 = readl(&imx_ccm->cscmr1); - cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK | - MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK); - cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET); - writel(cscmr1, &imx_ccm->cscmr1); - - /* Turn on EIM clock */ - ccgr6 |= (0x3 << 10); - writel(ccgr6, &imx_ccm->CCGR6); -} - -static void setup_iomux_eimnor(void) -{ - SETUP_IOMUX_PADS(eimnor_pads); - - gpio_direction_output(IMX_GPIO_NR(5, 4), 0); - - eimnor_cs_setup(); -} -#endif - -static void setup_iomux_enet(void) -{ - SETUP_IOMUX_PADS(enet_pads); -} - -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static void setup_iomux_uart(void) -{ - SETUP_IOMUX_PADS(uart4_pads); -} - -#ifdef CONFIG_FSL_ESDHC -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC3_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - gpio_direction_input(IMX_GPIO_NR(6, 15)); - return !gpio_get_value(IMX_GPIO_NR(6, 15)); -} - -int board_mmc_init(bd_t *bis) -{ - SETUP_IOMUX_PADS(usdhc3_pads); - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} -#endif - -#ifdef CONFIG_NAND_MXS -static iomux_v3_cfg_t gpmi_pads[] = { - IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)), - IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1)), -}; - -static void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - SETUP_IOMUX_PADS(gpmi_pads); - - setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} -#endif - -static void setup_fec(void) -{ - if (is_mx6dqp()) { - /* - * select ENET MAC0 TX clock from PLL - */ - imx_iomux_set_gpr_register(5, 9, 1, 1); - enable_fec_anatop_clock(0, ENET_125MHZ); - } - - setup_iomux_enet(); -} - -int board_eth_init(bd_t *bis) -{ - setup_fec(); - - return cpu_eth_init(bis); -} - -u32 get_board_rev(void) -{ - int rev = nxp_board_rev(); - - return (get_cpu_rev() & ~(0xF << 8)) | rev; -} - -static int ar8031_phy_fixup(struct phy_device *phydev) -{ - unsigned short val; - - /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - ar8031_phy_fixup(phydev); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -#if defined(CONFIG_VIDEO_IPUV3) -static void disable_lvds(struct display_info_t const *dev) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - clrbits_le32(&iomux->gpr[2], - IOMUXC_GPR2_LVDS_CH0_MODE_MASK | - IOMUXC_GPR2_LVDS_CH1_MODE_MASK); -} - -static void do_enable_hdmi(struct display_info_t const *dev) -{ - disable_lvds(dev); - imx_enable_hdmi_phy(); -} - -struct display_info_t const displays[] = {{ - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB666, - .detect = NULL, - .enable = NULL, - .mode = { - .name = "Hannstar-XGA", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} }, { - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = do_enable_hdmi, - .mode = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED, -} } }; -size_t display_count = ARRAY_SIZE(displays); - -iomux_v3_cfg_t const backlight_pads[] = { - IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)), -}; - -static void setup_iomux_backlight(void) -{ - gpio_direction_output(IMX_GPIO_NR(2, 9), 1); - SETUP_IOMUX_PADS(backlight_pads); -} - -static void setup_display(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - int reg; - - setup_iomux_backlight(); - enable_ipu_clock(); - imx_setup_hdmi(); - - /* Turn on LDB_DI0 and LDB_DI1 clocks */ - reg = readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; - writel(reg, &mxc_ccm->CCGR3); - - /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */ - reg = readl(&mxc_ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | - MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | - (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); - writel(reg, &mxc_ccm->cs2cdr); - - reg = readl(&mxc_ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; - writel(reg, &mxc_ccm->cscmr2); - - reg = readl(&mxc_ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << - MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); - writel(reg, &mxc_ccm->chsccdr); - - reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW | - IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | - IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | - IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | - IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | - IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | - IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 | - IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED; - writel(reg, &iomux->gpr[2]); - - reg = readl(&iomux->gpr[3]); - reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | - IOMUXC_GPR3_HDMI_MUX_CTL_MASK); - reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << - IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) | - (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << - IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET); - writel(reg, &iomux->gpr[3]); -} -#endif /* CONFIG_VIDEO_IPUV3 */ - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - -#ifdef CONFIG_NAND_MXS - setup_gpmi_nand(); -#endif - -#ifdef CONFIG_MTD_NOR_FLASH - eim_clk_setup(); -#endif - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */ - if (is_mx6dq() || is_mx6dqp()) - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); - else - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); - /* I2C 3 Steer */ - gpio_direction_output(IMX_GPIO_NR(5, 4), 1); - SETUP_IOMUX_PADS(i2c3_pads); -#ifndef CONFIG_SYS_FLASH_CFI - if (is_mx6dq() || is_mx6dqp()) - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); - else - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); -#endif - gpio_direction_output(IMX_GPIO_NR(1, 15), 1); - SETUP_IOMUX_PADS(port_exp); - -#ifdef CONFIG_VIDEO_IPUV3 - setup_display(); -#endif - -#ifdef CONFIG_MTD_NOR_FLASH - setup_iomux_eimnor(); -#endif - return 0; -} - -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; -} -#endif - -int power_init_board(void) -{ - struct pmic *p; - unsigned int value; - - p = pfuze_common_init(I2C_PMIC); - if (!p) - return -ENODEV; - - if (is_mx6dqp()) { - /* set SW2 staby volatage 0.975V*/ - pmic_reg_read(p, PFUZE100_SW2STBY, &value); - value &= ~0x3f; - value |= 0x17; - pmic_reg_write(p, PFUZE100_SW2STBY, value); - } - - return pfuze_mode_init(p, APS_PFM); -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int board_late_init(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", "SABREAUTO"); - - if (is_mx6dqp()) - env_set("board_rev", "MX6QP"); - else if (is_mx6dq()) - env_set("board_rev", "MX6Q"); - else if (is_mx6sdl()) - env_set("board_rev", "MX6DL"); -#endif - - return 0; -} - -int checkboard(void) -{ - printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string()); - - return 0; -} - -#ifdef CONFIG_USB_EHCI_MX6 -#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7) -#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1) - -iomux_v3_cfg_t const usb_otg_pads[] = { - IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -int board_ehci_hcd_init(int port) -{ - switch (port) { - case 0: - SETUP_IOMUX_PADS(usb_otg_pads); - - /* - * Set daisy chain for otg_pin_id on 6q. - * For 6dl, this bit is reserved. - */ - imx_iomux_set_gpr_register(1, 13, 1, 0); - break; - case 1: - break; - default: - printf("MXC USB port %d not yet supported\n", port); - return -EINVAL; - } - return 0; -} - -int board_ehci_power(int port, int on) -{ - switch (port) { - case 0: - if (on) - port_exp_direction_output(USB_OTG_PWR, 1); - else - port_exp_direction_output(USB_OTG_PWR, 0); - break; - case 1: - if (on) - port_exp_direction_output(USB_HOST1_PWR, 1); - else - port_exp_direction_output(USB_HOST1_PWR, 0); - break; - default: - printf("MXC USB port %d not yet supported\n", port); - return -EINVAL; - } - - return 0; -} -#endif - -#ifdef CONFIG_SPL_BUILD -#include <asm/arch/mx6-ddr.h> -#include <spl.h> -#include <linux/libfdt.h> - -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - return 0; -} -#endif - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC03, &ccm->CCGR1); - writel(0x0FFFC000, &ccm->CCGR2); - writel(0x3FF00000, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003FF, &ccm->CCGR6); -} - -static int mx6q_dcd_table[] = { - 0x020e0798, 0x000C0000, - 0x020e0758, 0x00000000, - 0x020e0588, 0x00000030, - 0x020e0594, 0x00000030, - 0x020e056c, 0x00000030, - 0x020e0578, 0x00000030, - 0x020e074c, 0x00000030, - 0x020e057c, 0x00000030, - 0x020e058c, 0x00000000, - 0x020e059c, 0x00000030, - 0x020e05a0, 0x00000030, - 0x020e078c, 0x00000030, - 0x020e0750, 0x00020000, - 0x020e05a8, 0x00000028, - 0x020e05b0, 0x00000028, - 0x020e0524, 0x00000028, - 0x020e051c, 0x00000028, - 0x020e0518, 0x00000028, - 0x020e050c, 0x00000028, - 0x020e05b8, 0x00000028, - 0x020e05c0, 0x00000028, - 0x020e0774, 0x00020000, - 0x020e0784, 0x00000028, - 0x020e0788, 0x00000028, - 0x020e0794, 0x00000028, - 0x020e079c, 0x00000028, - 0x020e07a0, 0x00000028, - 0x020e07a4, 0x00000028, - 0x020e07a8, 0x00000028, - 0x020e0748, 0x00000028, - 0x020e05ac, 0x00000028, - 0x020e05b4, 0x00000028, - 0x020e0528, 0x00000028, - 0x020e0520, 0x00000028, - 0x020e0514, 0x00000028, - 0x020e0510, 0x00000028, - 0x020e05bc, 0x00000028, - 0x020e05c4, 0x00000028, - 0x021b0800, 0xa1390003, - 0x021b080c, 0x001F001F, - 0x021b0810, 0x001F001F, - 0x021b480c, 0x001F001F, - 0x021b4810, 0x001F001F, - 0x021b083c, 0x43260335, - 0x021b0840, 0x031A030B, - 0x021b483c, 0x4323033B, - 0x021b4840, 0x0323026F, - 0x021b0848, 0x483D4545, - 0x021b4848, 0x44433E48, - 0x021b0850, 0x41444840, - 0x021b4850, 0x4835483E, - 0x021b081c, 0x33333333, - 0x021b0820, 0x33333333, - 0x021b0824, 0x33333333, - 0x021b0828, 0x33333333, - 0x021b481c, 0x33333333, - 0x021b4820, 0x33333333, - 0x021b4824, 0x33333333, - 0x021b4828, 0x33333333, - 0x021b08b8, 0x00000800, - 0x021b48b8, 0x00000800, - 0x021b0004, 0x00020036, - 0x021b0008, 0x09444040, - 0x021b000c, 0x8A8F7955, - 0x021b0010, 0xFF328F64, - 0x021b0014, 0x01FF00DB, - 0x021b0018, 0x00001740, - 0x021b001c, 0x00008000, - 0x021b002c, 0x000026d2, - 0x021b0030, 0x008F1023, - 0x021b0040, 0x00000047, - 0x021b0000, 0x841A0000, - 0x021b001c, 0x04088032, - 0x021b001c, 0x00008033, - 0x021b001c, 0x00048031, - 0x021b001c, 0x09408030, - 0x021b001c, 0x04008040, - 0x021b0020, 0x00005800, - 0x021b0818, 0x00011117, - 0x021b4818, 0x00011117, - 0x021b0004, 0x00025576, - 0x021b0404, 0x00011006, - 0x021b001c, 0x00000000, - 0x020c4068, 0x00C03F3F, - 0x020c406c, 0x0030FC03, - 0x020c4070, 0x0FFFC000, - 0x020c4074, 0x3FF00000, - 0x020c4078, 0xFFFFF300, - 0x020c407c, 0x0F0000F3, - 0x020c4080, 0x00000FFF, - 0x020e0010, 0xF00000CF, - 0x020e0018, 0x007F007F, - 0x020e001c, 0x007F007F, -}; - -static int mx6qp_dcd_table[] = { - 0x020e0798, 0x000C0000, - 0x020e0758, 0x00000000, - 0x020e0588, 0x00000030, - 0x020e0594, 0x00000030, - 0x020e056c, 0x00000030, - 0x020e0578, 0x00000030, - 0x020e074c, 0x00000030, - 0x020e057c, 0x00000030, - 0x020e058c, 0x00000000, - 0x020e059c, 0x00000030, - 0x020e05a0, 0x00000030, - 0x020e078c, 0x00000030, - 0x020e0750, 0x00020000, - 0x020e05a8, 0x00000030, - 0x020e05b0, 0x00000030, - 0x020e0524, 0x00000030, - 0x020e051c, 0x00000030, - 0x020e0518, 0x00000030, - 0x020e050c, 0x00000030, - 0x020e05b8, 0x00000030, - 0x020e05c0, 0x00000030, - 0x020e0774, 0x00020000, - 0x020e0784, 0x00000030, - 0x020e0788, 0x00000030, - 0x020e0794, 0x00000030, - 0x020e079c, 0x00000030, - 0x020e07a0, 0x00000030, - 0x020e07a4, 0x00000030, - 0x020e07a8, 0x00000030, - 0x020e0748, 0x00000030, - 0x020e05ac, 0x00000030, - 0x020e05b4, 0x00000030, - 0x020e0528, 0x00000030, - 0x020e0520, 0x00000030, - 0x020e0514, 0x00000030, - 0x020e0510, 0x00000030, - 0x020e05bc, 0x00000030, - 0x020e05c4, 0x00000030, - 0x021b0800, 0xa1390003, - 0x021b080c, 0x001b001e, - 0x021b0810, 0x002e0029, - 0x021b480c, 0x001b002a, - 0x021b4810, 0x0019002c, - 0x021b083c, 0x43240334, - 0x021b0840, 0x0324031a, - 0x021b483c, 0x43340344, - 0x021b4840, 0x03280276, - 0x021b0848, 0x44383A3E, - 0x021b4848, 0x3C3C3846, - 0x021b0850, 0x2e303230, - 0x021b4850, 0x38283E34, - 0x021b081c, 0x33333333, - 0x021b0820, 0x33333333, - 0x021b0824, 0x33333333, - 0x021b0828, 0x33333333, - 0x021b481c, 0x33333333, - 0x021b4820, 0x33333333, - 0x021b4824, 0x33333333, - 0x021b4828, 0x33333333, - 0x021b08c0, 0x24912492, - 0x021b48c0, 0x24912492, - 0x021b08b8, 0x00000800, - 0x021b48b8, 0x00000800, - 0x021b0004, 0x00020036, - 0x021b0008, 0x09444040, - 0x021b000c, 0x898E7955, - 0x021b0010, 0xFF328F64, - 0x021b0014, 0x01FF00DB, - 0x021b0018, 0x00001740, - 0x021b001c, 0x00008000, - 0x021b002c, 0x000026d2, - 0x021b0030, 0x008E1023, - 0x021b0040, 0x00000047, - 0x021b0400, 0x14420000, - 0x021b0000, 0x841A0000, - 0x00bb0008, 0x00000004, - 0x00bb000c, 0x2891E41A, - 0x00bb0038, 0x00000564, - 0x00bb0014, 0x00000040, - 0x00bb0028, 0x00000020, - 0x00bb002c, 0x00000020, - 0x021b001c, 0x04088032, - 0x021b001c, 0x00008033, - 0x021b001c, 0x00048031, - 0x021b001c, 0x09408030, - 0x021b001c, 0x04008040, - 0x021b0020, 0x00005800, - 0x021b0818, 0x00011117, - 0x021b4818, 0x00011117, - 0x021b0004, 0x00025576, - 0x021b0404, 0x00011006, - 0x021b001c, 0x00000000, - 0x020c4068, 0x00C03F3F, - 0x020c406c, 0x0030FC03, - 0x020c4070, 0x0FFFC000, - 0x020c4074, 0x3FF00000, - 0x020c4078, 0xFFFFF300, - 0x020c407c, 0x0F0000F3, - 0x020c4080, 0x00000FFF, - 0x020e0010, 0xF00000CF, - 0x020e0018, 0x77177717, - 0x020e001c, 0x77177717, -}; - -static int mx6dl_dcd_table[] = { - 0x020e0774, 0x000C0000, - 0x020e0754, 0x00000000, - 0x020e04ac, 0x00000030, - 0x020e04b0, 0x00000030, - 0x020e0464, 0x00000030, - 0x020e0490, 0x00000030, - 0x020e074c, 0x00000030, - 0x020e0494, 0x00000030, - 0x020e04a0, 0x00000000, - 0x020e04b4, 0x00000030, - 0x020e04b8, 0x00000030, - 0x020e076c, 0x00000030, - 0x020e0750, 0x00020000, - 0x020e04bc, 0x00000028, - 0x020e04c0, 0x00000028, - 0x020e04c4, 0x00000028, - 0x020e04c8, 0x00000028, - 0x020e04cc, 0x00000028, - 0x020e04d0, 0x00000028, - 0x020e04d4, 0x00000028, - 0x020e04d8, 0x00000028, - 0x020e0760, 0x00020000, - 0x020e0764, 0x00000028, - 0x020e0770, 0x00000028, - 0x020e0778, 0x00000028, - 0x020e077c, 0x00000028, - 0x020e0780, 0x00000028, - 0x020e0784, 0x00000028, - 0x020e078c, 0x00000028, - 0x020e0748, 0x00000028, - 0x020e0470, 0x00000028, - 0x020e0474, 0x00000028, - 0x020e0478, 0x00000028, - 0x020e047c, 0x00000028, - 0x020e0480, 0x00000028, - 0x020e0484, 0x00000028, - 0x020e0488, 0x00000028, - 0x020e048c, 0x00000028, - 0x021b0800, 0xa1390003, - 0x021b080c, 0x001F001F, - 0x021b0810, 0x001F001F, - 0x021b480c, 0x001F001F, - 0x021b4810, 0x001F001F, - 0x021b083c, 0x42190217, - 0x021b0840, 0x017B017B, - 0x021b483c, 0x4176017B, - 0x021b4840, 0x015F016C, - 0x021b0848, 0x4C4C4D4C, - 0x021b4848, 0x4A4D4C48, - 0x021b0850, 0x3F3F3F40, - 0x021b4850, 0x3538382E, - 0x021b081c, 0x33333333, - 0x021b0820, 0x33333333, - 0x021b0824, 0x33333333, - 0x021b0828, 0x33333333, - 0x021b481c, 0x33333333, - 0x021b4820, 0x33333333, - 0x021b4824, 0x33333333, - 0x021b4828, 0x33333333, - 0x021b08b8, 0x00000800, - 0x021b48b8, 0x00000800, - 0x021b0004, 0x00020025, - 0x021b0008, 0x00333030, - 0x021b000c, 0x676B5313, - 0x021b0010, 0xB66E8B63, - 0x021b0014, 0x01FF00DB, - 0x021b0018, 0x00001740, - 0x021b001c, 0x00008000, - 0x021b002c, 0x000026d2, - 0x021b0030, 0x006B1023, - 0x021b0040, 0x00000047, - 0x021b0000, 0x841A0000, - 0x021b001c, 0x04008032, - 0x021b001c, 0x00008033, - 0x021b001c, 0x00048031, - 0x021b001c, 0x05208030, - 0x021b001c, 0x04008040, - 0x021b0020, 0x00005800, - 0x021b0818, 0x00011117, - 0x021b4818, 0x00011117, - 0x021b0004, 0x00025565, - 0x021b0404, 0x00011006, - 0x021b001c, 0x00000000, - 0x020c4068, 0x00C03F3F, - 0x020c406c, 0x0030FC03, - 0x020c4070, 0x0FFFC000, - 0x020c4074, 0x3FF00000, - 0x020c4078, 0xFFFFF300, - 0x020c407c, 0x0F0000C3, - 0x020c4080, 0x00000FFF, - 0x020e0010, 0xF00000CF, - 0x020e0018, 0x007F007F, - 0x020e001c, 0x007F007F, -}; - -static void ddr_init(int *table, int size) -{ - int i; - - for (i = 0; i < size / 2 ; i++) - writel(table[2 * i + 1], table[2 * i]); -} - -static void spl_dram_init(void) -{ - if (is_mx6dq()) - ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table)); - else if (is_mx6dqp()) - ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table)); - else if (is_mx6sdl()) - ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); -} - -void board_init_f(ulong dummy) -{ - /* DDR initialization */ - spl_dram_init(); - - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - gpr_init(); - - /* iomux and setup of i2c */ - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} -#endif diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig deleted file mode 100644 index 88565678467..00000000000 --- a/configs/mx6sabreauto_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_MX6SABREAUTO=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_NXP_BOARD_REVISION=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_DFU=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_PART=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_DFU_MMC=y -CONFIG_DFU_SF=y -CONFIG_FSL_ESDHC=y -CONFIG_NAND=y -CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHYLIB=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="FSL" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h deleted file mode 100644 index e444930dc87..00000000000 --- a/include/configs/mx6sabreauto.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6Q SabreAuto board. - */ - -#ifndef __MX6SABREAUTO_CONFIG_H -#define __MX6SABREAUTO_CONFIG_H - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#define CONFIG_MACH_TYPE 3529 -#define CONFIG_MXC_UART_BASE UART4_BASE -#define CONSOLE_DEV "ttymxc3" - -/* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } - -#include "mx6sabre_common.h" - -/* Falcon Mode */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ -#endif - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR -#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#endif - -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - -#endif /* __MX6SABREAUTO_CONFIG_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-imx/mx6/Kconfig | 1 - board/el/el6x/Kconfig | 25 -- board/el/el6x/MAINTAINERS | 8 - board/el/el6x/Makefile | 5 - board/el/el6x/el6x.c | 631 ---------------------------------- configs/zc5202_defconfig | 42 --- configs/zc5601_defconfig | 41 --- include/configs/zc5202.h | 30 -- include/configs/zc5601.h | 28 -- 9 files changed, 811 deletions(-) delete mode 100644 board/el/el6x/Kconfig delete mode 100644 board/el/el6x/MAINTAINERS delete mode 100644 board/el/el6x/Makefile delete mode 100644 board/el/el6x/el6x.c delete mode 100644 configs/zc5202_defconfig delete mode 100644 configs/zc5601_defconfig delete mode 100644 include/configs/zc5202.h delete mode 100644 include/configs/zc5601.h

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 7e0f9369eaf..6f59044d4ff 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -532,7 +532,6 @@ source "board/bticino/mamoj/Kconfig" source "board/compulab/cm_fx6/Kconfig" source "board/congatec/cgtqmx6eval/Kconfig" source "board/dhelectronics/dh_imx6/Kconfig" -source "board/el/el6x/Kconfig" source "board/embest/mx6boards/Kconfig" source "board/engicam/imx6q/Kconfig" source "board/engicam/imx6ul/Kconfig" diff --git a/board/el/el6x/Kconfig b/board/el/el6x/Kconfig deleted file mode 100644 index aa9bf25fb47..00000000000 --- a/board/el/el6x/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -if TARGET_ZC5202 - -config SYS_BOARD - default "el6x" - -config SYS_VENDOR - default "el" - -config SYS_CONFIG_NAME - default "zc5202" - -endif - -if TARGET_ZC5601 - -config SYS_BOARD - default "el6x" - -config SYS_VENDOR - default "el" - -config SYS_CONFIG_NAME - default "zc5601" - -endif diff --git a/board/el/el6x/MAINTAINERS b/board/el/el6x/MAINTAINERS deleted file mode 100644 index 9a40010f50e..00000000000 --- a/board/el/el6x/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -EL6X BOARD -M: Stefano Babic sbabic@denx.de -S: Maintained -F: board/el/el6x/ -F: include/configs/zc5202.h -F: include/configs/zc5601.h -F: configs/zc5202_defconfig -F: configs/zc5601_defconfig diff --git a/board/el/el6x/Makefile b/board/el/el6x/Makefile deleted file mode 100644 index 065a867475a..00000000000 --- a/board/el/el6x/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) Stefano Babic sbabic@denx.de - -obj-y := el6x.o diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c deleted file mode 100644 index dd0c1120888..00000000000 --- a/board/el/el6x/el6x.c +++ /dev/null @@ -1,631 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) Stefano Babic sbabic@denx.de - * - * Based on other i.MX6 boards - */ - -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/video.h> -#include <mmc.h> -#include <fsl_esdhc.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/arch/crm_regs.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <i2c.h> -#include <input.h> -#include <power/pmic.h> -#include <power/pfuze100_pmic.h> -#include <asm/arch/mx6-ddr.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define OPEN_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_DISABLE | (0 << 12)) - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define I2C_PMIC 1 - -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) - -#define ETH_PHY_RESET IMX_GPIO_NR(2, 4) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); -} - -#ifdef CONFIG_TARGET_ZC5202 -iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), - MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), - /* Switch Reset */ - MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), - /* Switch Interrupt */ - MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* use CRS and COL pads as GPIOs */ - MX6_PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(OPEN_PAD_CTRL), - MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(OPEN_PAD_CTRL), - -}; - -#define BOARD_NAME "EL6x-ZC5202" -#else -iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; -#define BOARD_NAME "EL6x-ZC5601" -#endif - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); - -#ifdef CONFIG_TARGET_ZC5202 - /* set CRS and COL to input */ - gpio_direction_input(IMX_GPIO_NR(4, 9)); - gpio_direction_input(IMX_GPIO_NR(4, 12)); - - /* Reset Switch */ - gpio_direction_output(ETH_PHY_RESET , 0); - mdelay(2); - gpio_set_value(ETH_PHY_RESET, 1); -#endif -} - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -#ifdef CONFIG_MXC_SPI -#ifdef CONFIG_TARGET_ZC5202 -iomux_v3_cfg_t const ecspi1_pads[] = { - MX6_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -iomux_v3_cfg_t const ecspi3_pads[] = { - MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT7__GPIO4_IO28 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT9__GPIO4_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT10__GPIO4_IO31 | MUX_PAD_CTRL(SPI_PAD_CTRL), -}; -#endif - -iomux_v3_cfg_t const ecspi4_pads[] = { - MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) - ? (IMX_GPIO_NR(3, 20)) : -1; -} - -static void setup_spi(void) -{ -#ifdef CONFIG_TARGET_ZC5202 - gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0"); - gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1"); - gpio_direction_output(IMX_GPIO_NR(5, 17), 1); - gpio_direction_output(IMX_GPIO_NR(5, 9), 1); - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); -#endif - - gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0"); - gpio_direction_output(IMX_GPIO_NR(3, 20), 1); - imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); - - enable_spi_clk(true, 3); -} -#endif - -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | I2C_PAD, - .gp = IMX_GPIO_NR(2, 30) - }, - .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD, - .gp = IMX_GPIO_NR(1, 5) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | I2C_PAD, - .gp = IMX_GPIO_NR(7, 11) - } -}; - -iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC2_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC4_BASE_ADDR: - ret = 1; /* eMMC/uSDHC4 is always present */ - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ -#ifndef CONFIG_SPL_BUILD - int ret; - int i; - - /* - * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) - * mmc0 SD2 - * mmc1 SD3 - * mmc2 eMMC - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -#else - struct src *psrc = (struct src *)SRC_BASE_ADDR; - unsigned reg = readl(&psrc->sbmr1) >> 11; - - /* - * Upon reading BOOT_CFG register the following map is done: - * Bit 11 and 12 of BOOT_CFG register can determine the current - * mmc port - * 0x1 SD1 - * 0x2 SD2 - * 0x3 SD4 - */ - - switch (reg & 0x3) { - case 0x1: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - break; - case 0x3: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - break; - } - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -#endif - -} -#endif - - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -int board_eth_init(bd_t *bis) -{ - setup_iomux_enet(); - enable_enet_clk(1); - - return cpu_eth_init(bis); -} - -int board_early_init_f(void) -{ - - setup_iomux_uart(); - setup_spi(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - - return 0; -} - -int power_init_board(void) -{ - struct pmic *p; - int ret; - unsigned int reg; - - ret = power_pfuze100_init(I2C_PMIC); - if (ret) - return ret; - - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) - return ret; - - pmic_reg_read(p, PFUZE100_DEVICEID, &reg); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - - /* Increase VGEN3 from 2.5 to 2.8V */ - pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg); - reg &= ~LDO_VOL_MASK; - reg |= LDOB_2_80V; - pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); - - /* Increase VGEN5 from 2.8 to 3V */ - pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg); - reg &= ~LDO_VOL_MASK; - reg |= LDOB_3_00V; - pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); - - /* Set SW1AB stanby volage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg); - reg &= ~SW1x_STBY_MASK; - reg |= SW1x_0_975V; - pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); - - /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg); - reg &= ~SW1xCONF_DVSSPEED_MASK; - reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); - - /* Set SW1C standby voltage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg); - reg &= ~SW1x_STBY_MASK; - reg |= SW1x_0_975V; - pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); - - /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1CCONF, &reg); - reg &= ~SW1xCONF_DVSSPEED_MASK; - reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PFUZE100_SW1CCONF, reg); - - return 0; -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, - /* 8 bit bus width */ - {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int board_late_init(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - - env_set("board_name", BOARD_NAME); - return 0; -} - -int checkboard(void) -{ - puts("Board: "); - puts(BOARD_NAME "\n"); - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -#include <spl.h> -#include <linux/libfdt.h> - -const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_sdclk_0 = 0x00020030, - .dram_sdclk_1 = 0x00020030, - .dram_cas = 0x00020030, - .dram_ras = 0x00020030, - .dram_reset = 0x00020030, - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x00003030, - .dram_sdodt1 = 0x00003030, - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_sdqs2 = 0x00000030, - .dram_sdqs3 = 0x00000030, - .dram_sdqs4 = 0x00000030, - .dram_sdqs5 = 0x00000030, - .dram_sdqs6 = 0x00000030, - .dram_sdqs7 = 0x00000030, - .dram_dqm0 = 0x00020030, - .dram_dqm1 = 0x00020030, - .dram_dqm2 = 0x00020030, - .dram_dqm3 = 0x00020030, - .dram_dqm4 = 0x00020030, - .dram_dqm5 = 0x00020030, - .dram_dqm6 = 0x00020030, - .dram_dqm7 = 0x00020030, -}; - -const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { - .grp_ddr_type = 0x000C0000, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_addds = 0x00000030, - .grp_ctlds = 0x00000030, - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_b2ds = 0x00000030, - .grp_b3ds = 0x00000030, - .grp_b4ds = 0x00000030, - .grp_b5ds = 0x00000030, - .grp_b6ds = 0x00000030, - .grp_b7ds = 0x00000030, -}; - -const struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x001F001F, - .p0_mpwldectrl1 = 0x001F001F, - .p1_mpwldectrl0 = 0x00440044, - .p1_mpwldectrl1 = 0x00440044, - .p0_mpdgctrl0 = 0x434B0350, - .p0_mpdgctrl1 = 0x034C0359, - .p1_mpdgctrl0 = 0x434B0350, - .p1_mpdgctrl1 = 0x03650348, - .p0_mprddlctl = 0x4436383B, - .p1_mprddlctl = 0x39393341, - .p0_mpwrdlctl = 0x35373933, - .p1_mpwrdlctl = 0x48254A36, -}; - -/* MT41K128M16JT-125 */ -static struct mx6_ddr3_cfg mem_ddr = { - .mem_speed = 1600, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC03, &ccm->CCGR1); - writel(0x0FFFC000, &ccm->CCGR2); - writel(0x3FF00000, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003FF, &ccm->CCGR6); -} - -/* - * This section requires the differentiation between iMX6 Sabre boards, but - * for now, it will configure only for the mx6q variant. - */ -static void spl_dram_init(void) -{ - struct mx6_ddr_sysinfo sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ - .dsize = 2, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 32Gb per CS */ - /* single chip select */ - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ - .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; - - mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); -} - -void board_init_f(ulong dummy) -{ - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - gpr_init(); - - /* iomux and setup of i2c */ - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* DDR initialization */ - spl_dram_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} - -#endif diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig deleted file mode 100644 index c79cd22936f..00000000000 --- a/configs/zc5202_defconfig +++ /dev/null @@ -1,42 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_ZC5202=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" -CONFIG_BOOTDELAY=3 -CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" -CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb" -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_FSL_ESDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MII=y -CONFIG_PCI=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_OF_LIBFDT=y diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig deleted file mode 100644 index e92c63df129..00000000000 --- a/configs/zc5601_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_ZC5601=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" -CONFIG_BOOTDELAY=3 -CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" -CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb" -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_FSL_ESDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHYLIB=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/zc5202.h b/include/configs/zc5202.h deleted file mode 100644 index 40d33f7830a..00000000000 --- a/include/configs/zc5202.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Stefano Babic sbabic@denx.de - * - * Configuration settings for the E+L i.MX6Q DO82 board. - */ - -#ifndef __EL_ZC5202_H -#define __EL_ZC5202_H - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" -#define CONFIG_MMCROOT "/dev/mmcblk0p2" - -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - -#include "el6x_common.h" - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE MII100 -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_MV88E6352_SWITCH - -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX - -#endif /*__EL6Q_CONFIG_H */ diff --git a/include/configs/zc5601.h b/include/configs/zc5601.h deleted file mode 100644 index b9673e2c065..00000000000 --- a/include/configs/zc5601.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Stefano Babic sbabic@denx.de - * - * Configuration settings for the E+L i.MX6Q DO82 board. - */ - -#ifndef __EL_ZC5601_H -#define __EL_ZC5601_H - - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" -#define CONFIG_MMCROOT "/dev/mmcblk0p1" - -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - -#include "el6x_common.h" - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0x10 -#define CONFIG_FEC_FIXED_SPEED 1000 /* No autoneg, fix Gb */ - -#endif /*__EL6Q_CONFIG_H */

This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-omap2/omap3/Kconfig | 1 - board/logicpd/omap3som/Kconfig | 14 -- board/logicpd/omap3som/MAINTAINERS | 9 - board/logicpd/omap3som/Makefile | 6 - board/logicpd/omap3som/README | 56 ----- board/logicpd/omap3som/omap3logic.c | 329 --------------------------- board/logicpd/omap3som/omap3logic.h | 236 ------------------- configs/omap35_logic_defconfig | 72 ------ configs/omap35_logic_somlv_defconfig | 78 ------- configs/omap3_logic_defconfig | 73 ------ configs/omap3_logic_somlv_defconfig | 78 ------- include/configs/omap3_logic.h | 210 ----------------- 12 files changed, 1162 deletions(-) delete mode 100644 board/logicpd/omap3som/Kconfig delete mode 100644 board/logicpd/omap3som/MAINTAINERS delete mode 100644 board/logicpd/omap3som/Makefile delete mode 100644 board/logicpd/omap3som/README delete mode 100644 board/logicpd/omap3som/omap3logic.c delete mode 100644 board/logicpd/omap3som/omap3logic.h delete mode 100644 configs/omap35_logic_defconfig delete mode 100644 configs/omap35_logic_somlv_defconfig delete mode 100644 configs/omap3_logic_defconfig delete mode 100644 configs/omap3_logic_somlv_defconfig delete mode 100644 include/configs/omap3_logic.h

diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index edd5e3f255b..6e3942ad2d3 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -203,7 +203,6 @@ source "board/ti/am3517crane/Kconfig" source "board/8dtech/eco5pk/Kconfig" source "board/corscience/tricorder/Kconfig" source "board/htkw/mcx/Kconfig" -source "board/logicpd/omap3som/Kconfig" source "board/nokia/rx51/Kconfig" source "board/technexion/tao3530/Kconfig" source "board/technexion/twister/Kconfig" diff --git a/board/logicpd/omap3som/Kconfig b/board/logicpd/omap3som/Kconfig deleted file mode 100644 index 68d40dcd62d..00000000000 --- a/board/logicpd/omap3som/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_OMAP3_LOGIC - -config SYS_BOARD - default "omap3som" - -config SYS_VENDOR - default "logicpd" - -config SYS_CONFIG_NAME - default "omap3_logic" - -source "board/ti/common/Kconfig" - -endif diff --git a/board/logicpd/omap3som/MAINTAINERS b/board/logicpd/omap3som/MAINTAINERS deleted file mode 100644 index 459393cf54c..00000000000 --- a/board/logicpd/omap3som/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -OMAP3SOM BOARD -M: Adam Ford aford173@gmail.com -S: Maintained -F: board/logicpd/omap3som/ -F: include/configs/omap3_logic.h -F: configs/omap3_logic_defconfig -F: configs/omap35_logic_defconfig -F: configs/omap35_logic_somlv_defconfig -F: configs/omap3_logic_somlv_defconfig diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile deleted file mode 100644 index 61ef14e87a0..00000000000 --- a/board/logicpd/omap3som/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y := omap3logic.o diff --git a/board/logicpd/omap3som/README b/board/logicpd/omap3som/README deleted file mode 100644 index 5aaf58f0a69..00000000000 --- a/board/logicpd/omap3som/README +++ /dev/null @@ -1,56 +0,0 @@ -Summary -======= - -The source for omap3logic.c encompases the OMAP35 and DM3730 SOM-LV and DM3730 Torpedo platforms, but there are device trees custom taylored to each board. - -omap3_logic_defconfig = DM37 Torpedo / Torpedo + Wireless -omap35_logic_defconfig = OMAP35 Torpedo -omap3_logic_somlv_defconfig = DM37 SOM-LV -omap35_logic_somlv_defconfig = OMAP35 SOM-LV - -The device tree included with each of the defconfig files will also direct the board as to which dtb file to load when loading the kernel, so it is not -recomended to mix and match the defconfig files. - -Falcon Mode: FAT SD cards -========================= - -In this case the additional file is written to the filesystem. In this -example we assume that the uImage and device tree to be used are already on -the FAT filesystem (only the uImage MUST be for this to function -afterwards) along with a Falcon Mode aware MLO and the FAT partition has -already been created and marked bootable: - -U-Boot # mmc rescan -# Load kernel and device tree into memory, perform export -U-Boot # fatload mmc 0 ${loadaddr} uImage -U-Boot # run loadfdt -U-Boot # setenv optargs quiet -U-Boot # run mmcargs -U-Boot # run common_bootargs -U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} - -This will print a number of lines and then end with something like: - Loading Device Tree to 8dec9000, end 8dee0295 ... OK - -So then note the starting address and write the args to mmc/sd: - -U-Boot # fatwrite mmc 0:1 0x8dec9000 args 0x20000 - -The size of 0x20000 matches the CMD_SPL_WRITE_SIZE. - -Falcon Mode: NAND -================= - -In this case the additional data is written to another partition of the -NAND. In this example we assume that the uImage and device tree to be are -already located on the NAND somewhere (such as filesystem or mtd partition) -along with a Falcon Mode aware MLO written to the correct locations for -booting and mtdparts have been configured correctly for the board: - -U-Boot # nand read ${loadaddr} kernel -U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb -U-Boot # run nandargs -U-Boot # run common_bootargs -U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} -U-Boot # nand erase.part u-boot-spl-os -U-Boot # nand write ${fdtaddr} u-boot-spl-os diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c deleted file mode 100644 index 691d38fdf27..00000000000 --- a/board/logicpd/omap3som/omap3logic.c +++ /dev/null @@ -1,329 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 - * Logic Product Development <www.logicpd.com> - * - * Author : - * Peter Barada peter.barada@logicpd.com - * - * Derived from Beagle Board and 3430 SDP code by - * Richard Woodruff r-woodruff2@ti.com - * Syed Mohammed Khasim khasim@ti.com - */ -#include <common.h> -#include <dm.h> -#include <ns16550.h> -#include <netdev.h> -#include <flash.h> -#include <nand.h> -#include <i2c.h> -#include <twl4030.h> -#include <asm/io.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/mux.h> -#include <asm/arch/mem.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/omap_mmc.h> -#include <asm/mach-types.h> -#include <linux/mtd/rawnand.h> -#include <asm/omap_musb.h> -#include <linux/errno.h> -#include <linux/usb/ch9.h> -#include <linux/usb/gadget.h> -#include <linux/usb/musb.h> -#include "omap3logic.h" -#ifdef CONFIG_USB_EHCI_HCD -#include <usb.h> -#include <asm/ehci-omap.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203 -#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302 -#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302 -#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303 -#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18 -#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000 -#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50 - -#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203 -#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102 -#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102 -#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103 -#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15 -#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000 -#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50 - -/* This is only needed until SPL gets OF support */ -#ifdef CONFIG_SPL_BUILD -static const struct ns16550_platdata omap3logic_serial = { - .base = OMAP34XX_UART1, - .reg_shift = 2, - .clock = V_NS16550_CLK, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DEVICE(omap3logic_uart) = { - "omap_serial", - &omap3logic_serial -}; - -static const struct omap_hsmmc_plat omap3_logic_mmc0_platdata = { - .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE, - .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT, - .cfg.f_min = 400000, - .cfg.f_max = 52000000, - .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, - .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, -}; - -U_BOOT_DEVICE(omap3_logic_mmc0) = { - .name = "omap_hsmmc", - .platdata = &omap3_logic_mmc0_platdata, -}; - -#endif - -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - /* break into full u-boot on 'c' */ - return serial_tstc() && serial_getc() == 'c'; -} -#endif - -#if defined(CONFIG_SPL_BUILD) -/* - * Routine: get_board_mem_timings - * Description: If we use SPL then there is no x-loader nor config header - * so we have to setup the DDR timings ourself on the first bank. This - * provides the timing values back to the function that configures - * the memory. - */ -void get_board_mem_timings(struct board_sdrc_timings *timings) -{ - timings->mr = MICRON_V_MR_165; - - if (get_cpu_family() == CPU_OMAP36XX) { - /* 200 MHz works for OMAP36/DM37 */ - /* 256MB DDR */ - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - } else { - /* 165 MHz works for OMAP35 */ - timings->mcfg = MICRON_V_MCFG_165(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - } -} - -#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c) -#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84) -#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80) - -void spl_board_prepare_for_linux(void) -{ - /* The Micron NAND starts locked which - * prohibits mounting the NAND as RW - * The following commands are what unlocks - * the NAND to become RW Falcon Mode does not - * have as many smarts as U-Boot, but Logic PD - * only makes NAND with 512MB so these hard coded - * values should work for all current models - */ - - writeb(0x70, GPMC_NAND_COMMAND_0); - writeb(-1, GPMC_NAND_DATA_0); - writeb(0x7a, GPMC_NAND_COMMAND_0); - writeb(0x00, GPMC_NAND_ADDRESS_0); - writeb(0x00, GPMC_NAND_ADDRESS_0); - writeb(0x00, GPMC_NAND_ADDRESS_0); - writeb(-1, GPMC_NAND_COMMAND_0); - - /* Begin address 0 */ - writeb(NAND_CMD_UNLOCK1, 0x6e00007c); - writeb(0x00, GPMC_NAND_ADDRESS_0); - writeb(0x00, GPMC_NAND_ADDRESS_0); - writeb(0x00, GPMC_NAND_ADDRESS_0); - writeb(-1, GPMC_NAND_DATA_0); - - /* Ending address at the end of Flash */ - writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0); - writeb(0xc0, GPMC_NAND_ADDRESS_0); - writeb(0xff, GPMC_NAND_ADDRESS_0); - writeb(0x03, GPMC_NAND_ADDRESS_0); - writeb(-1, GPMC_NAND_DATA_0); - writeb(0x79, GPMC_NAND_COMMAND_0); - writeb(-1, GPMC_NAND_DATA_0); - writeb(-1, GPMC_NAND_DATA_0); -} -#endif - -#if !CONFIG_IS_ENABLED(DM_USB) -#ifdef CONFIG_USB_MUSB_OMAP2PLUS -static struct musb_hdrc_config musb_config = { - .multipoint = 1, - .dyn_fifo = 1, - .num_eps = 16, - .ram_bits = 12, -}; - -static struct omap_musb_board_data musb_board_data = { - .interface_type = MUSB_INTERFACE_ULPI, -}; - -static struct musb_hdrc_platform_data musb_plat = { -#if defined(CONFIG_USB_MUSB_HOST) - .mode = MUSB_HOST, -#elif defined(CONFIG_USB_MUSB_GADGET) - .mode = MUSB_PERIPHERAL, -#else -#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET" -#endif - .config = &musb_config, - .power = 100, - .platform_ops = &omap2430_ops, - .board_data = &musb_board_data, -}; -#endif - -#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD) -/* Call usb_stop() before starting the kernel */ -void show_boot_progress(int val) -{ - if (val == BOOTSTAGE_ID_RUN_OS) - usb_stop(); -} - -static struct omap_usbhs_board_data usbhs_bdata = { - .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED -}; - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); -} - -int ehci_hcd_stop(int index) -{ - return omap_ehci_hcd_stop(); -} - -#endif /* CONFIG_USB_EHCI_HCD */ -#endif /* !DM_USB*/ -/* - * Routine: misc_init_r - * Description: Configure board specific parts - */ -int misc_init_r(void) -{ - twl4030_power_init(); - omap_die_id_display(); - -#if !CONFIG_IS_ENABLED(DM_USB) -#ifdef CONFIG_USB_MUSB_OMAP2PLUS - musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); -#endif -#endif - return 0; -} - -#if defined(CONFIG_FLASH_CFI_DRIVER) -static const u32 gpmc_dm37_c2nor_config[] = { - LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1, - LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2, - LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3, - LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4, - LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5, - LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6, - LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 -}; - -static const u32 gpmc_omap35_c2nor_config[] = { - LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1, - LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2, - LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3, - LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4, - LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5, - LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6, - LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 -}; -#endif - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); -#if defined(CONFIG_FLASH_CFI_DRIVER) - if (get_cpu_family() == CPU_OMAP36XX) { - /* Enable CS2 for NOR Flash */ - enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2], - 0x10000000, GPMC_SIZE_64M); - } else { - enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2], - 0x10000000, GPMC_SIZE_64M); - } -#endif - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT - -static void unlock_nand(void) -{ - int dev = nand_curr_device; - struct mtd_info *mtd; - - mtd = get_nand_dev_by_index(dev); - nand_unlock(mtd, 0, mtd->size, 0); -} - -int board_late_init(void) -{ -#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK - unlock_nand(); -#endif - return 0; -} -#endif - -#if defined(CONFIG_MMC) -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif - -#ifdef CONFIG_SMC911X -/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */ -static const u32 gpmc_lan92xx_config[] = { - NET_LAN92XX_GPMC_CONFIG1, - NET_LAN92XX_GPMC_CONFIG2, - NET_LAN92XX_GPMC_CONFIG3, - NET_LAN92XX_GPMC_CONFIG4, - NET_LAN92XX_GPMC_CONFIG5, - NET_LAN92XX_GPMC_CONFIG6, -}; - -int board_eth_init(bd_t *bis) -{ - enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1], - CONFIG_SMC911X_BASE, GPMC_SIZE_16M); - - return smc911x_initialize(0, CONFIG_SMC911X_BASE); -} -#endif diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h deleted file mode 100644 index aeb26b90d71..00000000000 --- a/board/logicpd/omap3som/omap3logic.h +++ /dev/null @@ -1,236 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Logic Product Development <www.logicpd.com> - * - * Author: - * Peter Barada peter.barada@logicpd.com - */ -#ifndef _OMAP3LOGIC_H_ -#define _OMAP3LOGIC_H_ - -/* - * OMAP3 GPMC register settings for CS1 LAN922x - */ -#define NET_LAN92XX_GPMC_CONFIG1 0x00001000 -#define NET_LAN92XX_GPMC_CONFIG2 0x00080801 -#define NET_LAN92XX_GPMC_CONFIG3 0x00000000 -#define NET_LAN92XX_GPMC_CONFIG4 0x08010801 -#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a -#define NET_LAN92XX_GPMC_CONFIG6 0x03000280 - - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "Logic DM37x/OMAP35x reference board", - "NAND", -}; - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/ - - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /*GPMC_nCS1*/ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /*GPMC_nCS2*/ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /*GPMC_nCS3*/ - MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); /*GPMC_nCS5*/ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)); /*GPMC_nCS6*/ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); /*GPMC_nCS7*/ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); /*GPMC_CLK*/ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*GPMC_nBE0_CLE*/ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); /*GPMC_nBE1*/ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/ - - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ - - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/ - - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /*JTAG_EMU0*/ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /*JTAG_EMU1*/ - - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /*ETK_CLK*/ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); /*ETK_D0*/ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); /*ETK_D1*/ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); /*ETK_D2*/ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); /*ETK_D3*/ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /*ETK_D4*/ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /*ETK_D5*/ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /*ETK_D6*/ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/ - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/ - MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/ - - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /*d2d_mcad3*/ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /*d2d_mcad4*/ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /*d2d_mcad5*/ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /*d2d_mcad6*/ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /*d2d_mcad7*/ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /*d2d_mcad8*/ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /*d2d_mcad9*/ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /*d2d_mcad10*/ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /*d2d_mcad11*/ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /*d2d_mcad12*/ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /*d2d_mcad13*/ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /*d2d_mcad14*/ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /*d2d_mcad15*/ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /*d2d_mcad16*/ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /*d2d_mcad17*/ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /*d2d_mcad18*/ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /*d2d_mcad19*/ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /*d2d_mcad20*/ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /*d2d_mcad21*/ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /*d2d_mcad22*/ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /*d2d_mcad23*/ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /*d2d_mcad24*/ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /*d2d_mcad25*/ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /*d2d_mcad26*/ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /*d2d_mcad27*/ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /*d2d_mcad28*/ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /*d2d_mcad29*/ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /*d2d_mcad30*/ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /*d2d_mcad31*/ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /*d2d_mcad32*/ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /*d2d_mcad33*/ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /*d2d_mcad34*/ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /*d2d_mcad35*/ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /*d2d_mcad36*/ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /*d2d_clk26mi*/ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /*d2d_nrespwron*/ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /*d2d_nreswarm */ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /*d2d_arm9nirq */ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /*d2d_uma2p6fiq*/ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /*d2d_spint*/ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /*d2d_frint*/ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /*d2d_dmareq0*/ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /*d2d_dmareq1*/ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /*d2d_dmareq2*/ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /*d2d_dmareq3*/ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /*d2d_n3gtrst*/ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /*d2d_n3gtdi*/ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /*d2d_n3gtdo*/ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /*d2d_n3gtms*/ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /*d2d_n3gtck*/ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /*d2d_n3grtck*/ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /*d2d_mstdby*/ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /*d2d_swakeup*/ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /*d2d_idlereq*/ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /*d2d_idleack*/ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /*d2d_mwrite*/ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /*d2d_swrite*/ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /*d2d_mread*/ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/ -} - -#endif diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig deleted file mode 100644 index 80219eeacfa..00000000000 --- a/configs/omap35_logic_defconfig +++ /dev/null @@ -1,72 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80100000 -CONFIG_TI_COMMON_CMD_OPTIONS=y -# CONFIG_SPL_GPIO_SUPPORT is not set -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_OMAP3_LOGIC=y -# CONFIG_SPL_OMAP3_ID_NAND is not set -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_PROMPT="OMAP Logic # " -# CONFIG_CMD_IMI is not set -CONFIG_CMD_SPL=y -CONFIG_CMD_SPL_NAND_OFS=0x240000 -CONFIG_CMD_SPL_WRITE_SIZE=0x20000 -# CONFIG_CMD_EEPROM is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_LOCK_UNLOCK=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)" -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-35xx-devkit" -# CONFIG_ENV_IS_IN_FAT is not set -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SPL_DM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_MMC_OMAP_HS=y -CONFIG_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x08000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_SINGLE=y -CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPECIFY_CONSOLE_INDEX=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_MUSB_GADGET=y -CONFIG_USB_MUSB_OMAP2PLUS=y -CONFIG_TWL4030_USB=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="TI" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 -CONFIG_USB_ETHER=y -CONFIG_BCH=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig deleted file mode 100644 index 8a8c7147c3a..00000000000 --- a/configs/omap35_logic_somlv_defconfig +++ /dev/null @@ -1,78 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80100000 -CONFIG_TI_COMMON_CMD_OPTIONS=y -# CONFIG_SPL_GPIO_SUPPORT is not set -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_OMAP3_LOGIC=y -# CONFIG_SPL_OMAP3_ID_NAND is not set -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_PROMPT="OMAP Logic # " -# CONFIG_CMD_IMI is not set -CONFIG_CMD_SPL=y -CONFIG_CMD_SPL_NAND_OFS=0x240000 -CONFIG_CMD_SPL_WRITE_SIZE=0x20000 -# CONFIG_CMD_EEPROM is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_LOCK_UNLOCK=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)" -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-35xx-devkit" -# CONFIG_ENV_IS_IN_FAT is not set -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SPL_DM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x08000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_SINGLE=y -CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPECIFY_CONSOLE_INDEX=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_MUSB_GADGET=y -CONFIG_USB_MUSB_OMAP2PLUS=y -CONFIG_TWL4030_USB=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="TI" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 -CONFIG_USB_ETHER=y -CONFIG_BCH=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig deleted file mode 100644 index 969387a37cb..00000000000 --- a/configs/omap3_logic_defconfig +++ /dev/null @@ -1,73 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80100000 -CONFIG_TI_COMMON_CMD_OPTIONS=y -# CONFIG_SPL_GPIO_SUPPORT is not set -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_OMAP3_LOGIC=y -# CONFIG_SPL_OMAP3_ID_NAND is not set -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_PROMPT="OMAP Logic # " -# CONFIG_CMD_IMI is not set -CONFIG_CMD_SPL=y -CONFIG_CMD_SPL_NAND_OFS=0x240000 -CONFIG_CMD_SPL_WRITE_SIZE=0x20000 -# CONFIG_CMD_EEPROM is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_LOCK_UNLOCK=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)" -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit" -# CONFIG_ENV_IS_IN_FAT is not set -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SPL_DM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MMC_OMAP36XX_PINS=y -CONFIG_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x08000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_SINGLE=y -CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPECIFY_CONSOLE_INDEX=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_MUSB_GADGET=y -CONFIG_USB_MUSB_OMAP2PLUS=y -CONFIG_TWL4030_USB=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="TI" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 -CONFIG_USB_ETHER=y -CONFIG_BCH=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig deleted file mode 100644 index 396543e56bc..00000000000 --- a/configs/omap3_logic_somlv_defconfig +++ /dev/null @@ -1,78 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80100000 -CONFIG_TI_COMMON_CMD_OPTIONS=y -# CONFIG_SPL_GPIO_SUPPORT is not set -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_OMAP3_LOGIC=y -# CONFIG_SPL_OMAP3_ID_NAND is not set -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=2 -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_PROMPT="OMAP Logic # " -# CONFIG_CMD_IMI is not set -CONFIG_CMD_SPL=y -CONFIG_CMD_SPL_NAND_OFS=0x240000 -CONFIG_CMD_SPL_WRITE_SIZE=0x20000 -# CONFIG_CMD_EEPROM is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_LOCK_UNLOCK=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)" -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-37xx-devkit" -# CONFIG_ENV_IS_IN_FAT is not set -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SPL_DM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MMC_OMAP36XX_PINS=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x08000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_SINGLE=y -CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPECIFY_CONSOLE_INDEX=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_MUSB_GADGET=y -CONFIG_USB_MUSB_OMAP2PLUS=y -CONFIG_TWL4030_USB=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="TI" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 -CONFIG_USB_ETHER=y -CONFIG_BCH=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h deleted file mode 100644 index fe557f91caa..00000000000 --- a/include/configs/omap3_logic.h +++ /dev/null @@ -1,210 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Logic Product Development <www.logicpd.com> - * Peter Barada peter.barada@logicpd.com - * - * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo - * reference boards. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ - -#include <configs/ti_omap3_common.h> - -/* - * We are only ever GP parts and will utilize all of the "downloaded image" - * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in - * order to allow for BCH8 to fit in. - */ -#undef CONFIG_SPL_TEXT_BASE -#define CONFIG_SPL_TEXT_BASE 0x40200000 - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Hardware drivers */ - -/* I2C */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ - -/* Board NAND Info. */ -#ifdef CONFIG_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ - /* NAND devices */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ - 13, 14, 16, 17, 18, 19, 20, 21, 22, \ - 23, 24, 25, 26, 27, 28, 30, 31, 32, \ - 33, 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 44, 45, 46, 47, 48, 49, 50, 51, \ - 52, 53, 54, 55, 56} - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 13 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 -#endif - -/* Environment information */ - -#define CONFIG_PREBOOT \ - "setenv preboot;" \ - "saveenv;" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \ - "nandrootfstype=ubifs rootwait\0" \ - "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "run defaultboot;" \ - "fi; " \ - "else run defaultboot; fi\0" \ - "defaultboot=run mmcramboot\0" \ - "consoledevice=ttyS0\0" \ - "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \ - "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \ - "rotation=0\0" \ - "vrfb_arg=if itest ${rotation} -ne 0; then " \ - "setenv bootargs ${bootargs} omapfb.vrfb=y " \ - "omapfb.rotate=${rotation}; " \ - "fi\0" \ - "optargs=ignore_loglevel early_printk no_console_suspend\0" \ - "common_bootargs=run setconsole; setenv bootargs " \ - "${bootargs} "\ - "console=${console} " \ - "${mtdparts} "\ - "${optargs}; " \ - "run vrfb_arg\0" \ - "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo 'Running bootscript from mmc ...'; " \ - "source ${loadaddr}\0" \ - "loadimage=mmc rescan; " \ - "load mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ - "ramdisksize=64000\0" \ - "ramdiskimage=rootfs.ext2.gz.uboot\0" \ - "loadramdisk=mmc rescan; " \ - "load mmc ${mmcdev} ${rdaddr} ${ramdiskimage}\0" \ - "ramargs=setenv bootargs "\ - "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \ - "mmcargs=setenv bootargs "\ - "root=${mmcroot} rootfstype=${mmcrootfstype}\0" \ - "nandargs=setenv bootargs "\ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "nfsargs=setenv serverip ${tftpserver}; " \ - "setenv bootargs root=/dev/nfs " \ - "nfsroot=${nfsrootpath} " \ - "ip=${ipaddr}:${tftpserver}:${gatewayip}:${netmask}::eth0:off\0" \ - "nfsrootpath=/opt/nfs-exports/omap\0" \ - "autoload=no\0" \ - "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - "loadfdt=mmc rescan; " \ - "load mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \ - "mmcbootcommon=echo Booting with DT from mmc${mmcdev} ...; " \ - "run mmcargs; " \ - "run common_bootargs; " \ - "run dump_bootargs; " \ - "run loadimage; " \ - "run loadfdt;\0 " \ - "mmcbootz=setenv bootfile zImage; " \ - "run mmcbootcommon; "\ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "mmcboot=setenv bootfile uImage; "\ - "run mmcbootcommon; "\ - "bootm ${loadaddr} - ${fdtaddr}\0" \ - "mmcrambootcommon=echo 'Booting kernel from MMC w/ramdisk...'; " \ - "run ramargs; " \ - "run common_bootargs; " \ - "run dump_bootargs; " \ - "run loadimage; " \ - "run loadfdt; " \ - "run loadramdisk\0" \ - "mmcramboot=setenv bootfile uImage; " \ - "run mmcrambootcommon; " \ - "bootm ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ - "mmcrambootz=setenv bootfile zImage; " \ - "run mmcrambootcommon; " \ - "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ - "tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \ - "run ramargs; " \ - "run common_bootargs; " \ - "run dump_bootargs; " \ - "tftpboot ${loadaddr} ${zimage}; " \ - "tftpboot ${rdaddr} ${ramdiskimage}; " \ - "bootm ${loadaddr} ${rdaddr}\0" \ - "tftpbootz=echo 'Booting kernel NFS rootfs...'; " \ - "dhcp;" \ - "run nfsargs;" \ - "run common_bootargs;" \ - "run dump_bootargs;" \ - "tftpboot $loadaddr zImage;" \ - "bootz $loadaddr\0" \ - "nandbootcommon=echo 'Booting kernel from NAND...';" \ - "run nandargs;" \ - "run common_bootargs;" \ - "run dump_bootargs;" \ - "nand read ${loadaddr} kernel;" \ - "nand read ${fdtaddr} spl-os;\0" \ - "nandbootz=run nandbootcommon; "\ - "bootz ${loadaddr} - ${fdtaddr}\0"\ - "nandboot=run nandbootcommon; "\ - "bootm ${loadaddr} - ${fdtaddr}\0"\ - -#define CONFIG_BOOTCOMMAND \ - "run autoboot" - -/* Miscellaneous configurable options */ - -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -/* FLASH and environment organization */ - -/* **** PISMO SUPPORT *** */ -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#endif - -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_SIZE 0x4000000 - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET 0x260000 -#define CONFIG_ENV_ADDR 0x260000 - -/* Defines for SPL */ - -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#endif - -#endif /* __CONFIG_H */