Commit 7400d34ba992 ("riscv: semihosting: replace inline assembly with assembly file") reduced the alignment of function smh_trap().

As described in the "RISC-V Semihosting" specification [1] the ssli, ebreak, and srai statements must all reside in the same memory page.

[1] RISC-V Semihosting, Version 0.4, 12th June 2024 https://github.com/riscv-non-isa/riscv-semihosting

Fixes: 7400d34ba992 ("riscv: semihosting: replace inline assembly with assembly file") Signed-off-by: Heinrich Schuchardt heinrich.schuchardt@canonical.com --- arch/riscv/lib/semihosting.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/lib/semihosting.S b/arch/riscv/lib/semihosting.S index c0c571bce9b..49bb419a962 100644 --- a/arch/riscv/lib/semihosting.S +++ b/arch/riscv/lib/semihosting.S @@ -8,7 +8,7 @@

.pushsection .text.smh_trap, "ax" ENTRY(smh_trap) - .align 2 + .align 4 /* keep slli, ebreak, srai in same page */ .option push .option norvc /* semihosting sequence must be 32-bit wide */