[U-Boot] [PATCH V2 1/1] mx5: board: code clean up for checkboard code
The boot cause code has been factor out to soc common code,we need drop the part from the board support code
This patch also remove the redundant cpu version print
Signed-off-by: Jason Liu jason.hui@linaro.org --- changes since v1 -include more clean up by remove the redundant cpu version print --- board/efikamx/efikamx.c | 42 +------------------------------------ board/freescale/mx51evk/mx51evk.c | 36 +------------------------------ board/freescale/mx53evk/mx53evk.c | 21 +----------------- board/ttcontrol/vision2/vision2.c | 42 +------------------------------------ 4 files changed, 4 insertions(+), 137 deletions(-)
diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c index f735260..16be532 100644 --- a/board/efikamx/efikamx.c +++ b/board/efikamx/efikamx.c @@ -643,47 +643,7 @@ int board_late_init(void)
int checkboard(void) { - u32 system_rev = get_cpu_rev(); - u32 cause; - struct src *src_regs = (struct src *)SRC_BASE_ADDR; - - puts("Board: Efika MX "); - - switch (system_rev & 0xff) { - case CHIP_REV_3_0: - puts("3.0 ["); - break; - case CHIP_REV_2_5: - puts("2.5 ["); - break; - case CHIP_REV_2_0: - puts("2.0 ["); - break; - case CHIP_REV_1_1: - puts("1.1 ["); - break; - case CHIP_REV_1_0: - default: - puts("1.0 ["); - break; - } - - cause = src_regs->srsr; - switch (cause) { - case 0x0001: - puts("POR"); - break; - case 0x0009: - puts("RST"); - break; - case 0x0010: - case 0x0011: - puts("WDOG"); - break; - default: - printf("unknown 0x%x", cause); - } - puts("]\n"); + puts("Board: Efika MX\n");
return 0; } diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 02a765d..e2d3d74 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -431,41 +431,7 @@ int board_late_init(void)
int checkboard(void) { - puts("Board: MX51EVK "); - - switch (system_rev & 0xff) { - case CHIP_REV_3_0: - puts("3.0 ["); - break; - case CHIP_REV_2_5: - puts("2.5 ["); - break; - case CHIP_REV_2_0: - puts("2.0 ["); - break; - case CHIP_REV_1_1: - puts("1.1 ["); - break; - case CHIP_REV_1_0: - default: - puts("1.0 ["); - break; - } + puts("Board: MX51EVK\n");
- switch (__raw_readl(SRC_BASE_ADDR + 0x8)) { - case 0x0001: - puts("POR"); - break; - case 0x0009: - puts("RST"); - break; - case 0x0010: - case 0x0011: - puts("WDOG"); - break; - default: - puts("unknown"); - } - puts("]\n"); return 0; } diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index e71701b..a89aa25 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -372,26 +372,7 @@ int board_late_init(void)
int checkboard(void) { - u32 cause; - struct src *src_regs = (struct src *)SRC_BASE_ADDR; + puts("Board: MX53EVK\n");
- puts("Board: MX53EVK ["); - - cause = src_regs->srsr; - switch (cause) { - case 0x0001: - printf("POR"); - break; - case 0x0009: - printf("RST"); - break; - case 0x0010: - case 0x0011: - printf("WDOG"); - break; - default: - printf("unknown"); - } - printf("]\n"); return 0; } diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index f8ef4fc..7f37bad 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -700,47 +700,7 @@ int board_late_init(void)
int checkboard(void) { - u32 system_rev = get_cpu_rev(); - u32 cause; - struct src *src_regs = (struct src *)SRC_BASE_ADDR; - - puts("Board: TTControl Vision II CPU V"); - - switch (system_rev & 0xff) { - case CHIP_REV_3_0: - puts("3.0 ["); - break; - case CHIP_REV_2_5: - puts("2.5 ["); - break; - case CHIP_REV_2_0: - puts("2.0 ["); - break; - case CHIP_REV_1_1: - puts("1.1 ["); - break; - case CHIP_REV_1_0: - default: - puts("1.0 ["); - break; - } - - cause = src_regs->srsr; - switch (cause) { - case 0x0001: - puts("POR"); - break; - case 0x0009: - puts("RST"); - break; - case 0x0010: - case 0x0011: - puts("WDOG"); - break; - default: - printf("unknown 0x%x", cause); - } - puts("]\n"); + puts("Board: TTControl Vision II CPU V\n");
return 0; }
Add clock config interface support, so that we can configure CPU or DDR clock in the later init
Signed-off-by: Jason Liu jason.hui@linaro.org --- arch/arm/cpu/armv7/mx5/clock.c | 551 +++++++++++++++++++++++++++++- arch/arm/include/asm/arch-mx5/clock.h | 4 + arch/arm/include/asm/arch-mx5/crm_regs.h | 6 + arch/arm/include/asm/arch-mx5/imx-regs.h | 1 + 4 files changed, 559 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 0b04a88..04d9f71 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -24,6 +24,7 @@ */
#include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/imx-regs.h> @@ -34,6 +35,7 @@ enum pll_clocks { PLL1_CLOCK = 0, PLL2_CLOCK, PLL3_CLOCK, + PLL4_CLOCK, PLL_CLOCKS, };
@@ -41,8 +43,42 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR, [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR, [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR, + [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR, };
+#define AHB_CLK_ROOT 133333333 +#define SZ_DEC_1M 1000000 +#define PLL_PD_MAX 16 /* Actual pd+1 */ +#define PLL_MFI_MAX 15 +#define PLL_MFI_MIN 5 +#define ARM_DIV_MAX 8 +#define IPG_DIV_MAX 4 +#define AHB_DIV_MAX 8 +#define EMI_DIV_MAX 8 +#define NFC_DIV_MAX 8 + +struct fixed_pll_mfd { + u32 ref_clk_hz; + u32 mfd; +}; + +const struct fixed_pll_mfd fixed_mfd[] = { + {CONFIG_SYS_MX5_HCLK, 24 * 16}, +}; + +struct pll_param { + u32 pd; + u32 mfi; + u32 mfn; + u32 mfd; +}; + +#define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX) +#define PLL_FREQ_MIN(ref_clk) \ + ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX) +#define MAX_DDR_CLK 420000000 +#define NFC_CLK_MAX 34000000 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
/* @@ -175,7 +211,7 @@ static u32 get_uart_clk(void) /* * This function returns the low power audio clock. */ -u32 get_lp_apm(void) +static u32 get_lp_apm(void) { u32 ret_val = 0; u32 ccsr = __raw_readl(&mxc_ccm->ccsr); @@ -191,7 +227,7 @@ u32 get_lp_apm(void) /* * get cspi clock rate. */ -u32 imx_get_cspiclk(void) +static u32 get_cspi_clk(void) { u32 ret_val = 0, pdf, pre_pdf, clk_sel; u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1); @@ -228,6 +264,94 @@ u32 imx_get_cspiclk(void) return ret_val; }
+static u32 get_axi_a_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \ + >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET; + + return get_periph_clk() / (pdf + 1); +} + +static u32 get_axi_b_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \ + >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET; + + return get_periph_clk() / (pdf + 1); +} + +static u32 get_ahb_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AHB_PODF_MASK) \ + >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; + + return get_periph_clk() / (pdf + 1); +} + +static u32 get_emi_slow_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL; + u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \ + >> MXC_CCM_CBCDR_EMI_PODF_OFFSET; + + if (emi_clk_sel) + return get_ahb_clk() / (pdf + 1); + + return get_periph_clk() / (pdf + 1); +} + +static u32 get_nfc_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_NFC_PODF_MASK) \ + >> MXC_CCM_CBCDR_NFC_PODF_OFFSET; + + return get_emi_slow_clk() / (pdf + 1); +} + +static u32 get_ddr_clk(void) +{ + u32 ret_val = 0; + u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr); + u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \ + >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET; +#ifdef CONFIG_MX51 + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) { + u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \ + MXC_CCM_CBCDR_DDR_PODF_OFFSET; + + ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); + ret_val /= ddr_clk_podf + 1; + + return ret_val; + } +#endif + switch (ddr_clk_sel) { + case 0: + ret_val = get_axi_a_clk(); + break; + case 1: + ret_val = get_axi_b_clk(); + break; + case 2: + ret_val = get_emi_slow_clk(); + break; + case 3: + ret_val = get_ahb_clk(); + break; + default: + break; + } + + return ret_val; +} + + /* * The API of get mxc clockes. */ @@ -245,10 +369,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_UART_CLK: return get_uart_clk(); case MXC_CSPI_CLK: - return imx_get_cspiclk(); + return get_cspi_clk(); case MXC_FEC_CLK: return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); + case MXC_DDR_CLK: + return get_ddr_clk(); default: break; } @@ -267,6 +393,424 @@ u32 imx_get_fecclk(void) }
/* + * Clock config code start here + */ + +/* precondition: m>0 and n>0. Let g=gcd(m,n). */ +static int gcd(int m, int n) +{ + int t; + while (m > 0) { + if (n > m) { + t = m; + m = n; + n = t; + } /* swap */ + m -= n; + } + return n; +} + +/* + * This is to calculate various parameters based on reference clock and + * targeted clock based on the equation: + * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1) + * This calculation is based on a fixed MFD value for simplicity. + * + * @param ref reference clock freq in Hz + * @param target targeted clock in Hz + * @param pll pll_param structure. + * + * @return 0 if successful; non-zero otherwise. + */ +static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) +{ + u64 pd, mfi = 1, mfn, mfd, t1; + u32 n_target = target; + u32 n_ref = ref, i; + + /* + * Make sure targeted freq is in the valid range. + * Otherwise the following calculation might be wrong!!! + */ + if (n_target < PLL_FREQ_MIN(ref) || + n_target > PLL_FREQ_MAX(ref)) { + printf("Targeted peripheral clock should be" + "within [%d - %d]\n", + PLL_FREQ_MIN(ref) / SZ_DEC_1M, + PLL_FREQ_MAX(ref) / SZ_DEC_1M); + return -1; + } + + for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) { + if (fixed_mfd[i].ref_clk_hz == ref) { + mfd = fixed_mfd[i].mfd; + break; + } + } + + if (i == ARRAY_SIZE(fixed_mfd)) + return -1; + + /* Use n_target and n_ref to avoid overflow */ + for (pd = 1; pd <= PLL_PD_MAX; pd++) { + t1 = n_target * pd; + do_div(t1, (4 * n_ref)); + mfi = t1; + if (mfi > PLL_MFI_MAX) + return -1; + else if (mfi < 5) + continue; + break; + } + /* Now got pd and mfi already */ + /* + mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref; + */ + t1 = n_target * pd; + do_div(t1, 4); + t1 -= n_ref * mfi; + t1 *= mfd; + do_div(t1, n_ref); + mfn = t1; +#ifdef CMD_CLOCK_DEBUG + printf("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n", + ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd); +#endif + i = 1; + if (mfn != 0) + i = gcd(mfd, mfn); + pll->pd = (u32)pd; + pll->mfi = (u32)mfi; + do_div(mfn, i); + pll->mfn = (u32)mfn; + do_div(mfd, i); + pll->mfd = (u32)mfd; + + return 0; +} + +#define calc_div(tgt_clk, src_clk, limit) ({ \ + u32 v = 0; \ + if (((src_clk) % (tgt_clk)) <= 100) \ + v = (src_clk) / (tgt_clk); \ + else \ + v = ((src_clk) / (tgt_clk)) + 1;\ + if (v > limit) \ + v = limit; \ + (v - 1); \ + }) + +static u32 calc_per_cbcdr_val(u32 per_clk) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 tmp_clk = 0, div = 0, clk_sel = 0; + + cbcdr &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; + + /* emi_slow_podf divider */ + tmp_clk = get_emi_slow_clk(); + clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL; + if (clk_sel) { + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_EMI_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_EMI_PODF_OFFSET); + } + + /* axi_b_podf divider */ + tmp_clk = get_axi_b_clk(); + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_AXI_B_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET); + + /* axi_b_podf divider */ + tmp_clk = get_axi_a_clk(); + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_AXI_A_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET); + + /* ahb podf divider */ + tmp_clk = AHB_CLK_ROOT; + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET); + + return cbcdr; +} + +#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \ + { \ + __raw_writel(0x1232, &pll->ctrl); \ + __raw_writel(0x2, &pll->config); \ + __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \ + &pll->op); \ + __raw_writel(fn, &(pll->mfn)); \ + __raw_writel((fd) - 1, &pll->mfd); \ + __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \ + &pll->hfs_op); \ + __raw_writel(fn, &pll->hfs_mfn); \ + __raw_writel((fd) - 1, &pll->hfs_mfd); \ + __raw_writel(0x1232, &pll->ctrl); \ + while (!__raw_readl(&pll->ctrl) & 0x1) \ + ;\ + } + +static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param) +{ + u32 ccsr = __raw_readl(&mxc_ccm->ccsr); + struct mxc_pll_reg *pll = mxc_plls[index]; + + switch (index) { + case PLL1_CLOCK: + /* Switch ARM to PLL2 clock */ + __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr); + break; + case PLL2_CLOCK: + /* Switch to pll2 bypass clock */ + __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr); + break; + case PLL3_CLOCK: + /* Switch to pll3 bypass clock */ + __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr); + break; + case PLL4_CLOCK: + /* Switch to pll4 bypass clock */ + __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr); + break; + default: + return -1; + } + + return 0; +} + +/* Config CPU clock */ +static int config_core_clk(u32 ref, u32 freq) +{ + int ret = 0; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + /* The case that periph uses PLL1 is not considered here */ + ret = calc_pll_params(ref, freq, &pll_param); + if (ret != 0) { + printf("Error:Can't find pll parameters: %d\n", ret); + return ret; + } + + return config_pll_clk(PLL1_CLOCK, &pll_param); +} + +static int config_nfc_clk(u32 nfc_clk) +{ + u32 reg; + u32 parent_rate = get_emi_slow_clk(); + u32 div = parent_rate / nfc_clk; + + if (nfc_clk <= 0) + return -1; + if (div == 0) + div++; + if (parent_rate / div > NFC_CLK_MAX) + div++; + reg = __raw_readl(&mxc_ccm->cbcdr); + reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET; + __raw_writel(reg, &mxc_ccm->cbcdr); + while (__raw_readl(&mxc_ccm->cdhipr) != 0) + ; + return 0; +} + +/* Config main_bus_clock for periphs */ +static int config_periph_clk(u32 ref, u32 freq) +{ + int ret = 0; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { + ret = calc_pll_params(ref, freq, &pll_param); + if (ret != 0) { + printf("Error:Can't find pll parameters: %d\n", + ret); + return ret; + } + switch ((__raw_readl(&mxc_ccm->cbcmr) & \ + MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \ + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { + case 0: + return config_pll_clk(PLL1_CLOCK, &pll_param); + break; + case 1: + return config_pll_clk(PLL3_CLOCK, &pll_param); + break; + default: + return -1; + } + } else { + u32 old_cbcmr = __raw_readl(&mxc_ccm->cbcmr); + u32 new_cbcdr = calc_per_cbcdr_val(freq); + u32 old_nfc = get_nfc_clk(); + + /* Switch peripheral to PLL3 */ + __raw_writel(0x00015154, &mxc_ccm->cbcmr); + __raw_writel(0x02888945, &mxc_ccm->cbcdr); + + /* Make sure change is effective */ + while (__raw_readl(&mxc_ccm->cdhipr) != 0) + ; + + /* Setup PLL2 */ + ret = calc_pll_params(ref, freq, &pll_param); + if (ret != 0) { + printf("Error:Can't find pll parameters: %d\n", + ret); + return ret; + } + config_pll_clk(PLL2_CLOCK, &pll_param); + + /* Switch peripheral back */ + __raw_writel(new_cbcdr, &mxc_ccm->cbcdr); + __raw_writel(old_cbcmr, &mxc_ccm->cbcmr); + + /* Make sure change is effective */ + while (__raw_readl(&mxc_ccm->cdhipr) != 0) + ; + /* restore to old NFC clock */ + config_nfc_clk(old_nfc); + } + + return 0; +} + +static int config_ddr_clk(u32 emi_clk) +{ + u32 clk_src; + s32 shift = 0, clk_sel, div = 1; + u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr); + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + + if (emi_clk > MAX_DDR_CLK) { + printf("Warning:DDR clock should not exceed %d MHz\n", + MAX_DDR_CLK / SZ_DEC_1M); + emi_clk = MAX_DDR_CLK; + } + + clk_src = get_periph_clk(); + /* Find DDR clock input */ + clk_sel = (cbcmr >> 10) & 0x3; + switch (clk_sel) { + case 0: + shift = 16; + break; + case 1: + shift = 19; + break; + case 2: + shift = 22; + break; + case 3: + shift = 10; + break; + default: + return -1; + } + + if ((clk_src % emi_clk) < 10000000) + div = clk_src / emi_clk; + else + div = (clk_src / emi_clk) + 1; + if (div > 8) + div = 8; + + cbcdr = cbcdr & ~(0x7 << shift); + cbcdr |= ((div - 1) << shift); + __raw_writel(cbcdr, &mxc_ccm->cbcdr); + while (__raw_readl(&mxc_ccm->cdhipr) != 0) + ; + __raw_writel(0x0, &mxc_ccm->ccdr); + + return 0; +} + +/*! + * This function assumes the expected core clock has to be changed by + * modifying the PLL. This is NOT true always but for most of the times, + * it is. So it assumes the PLL output freq is the same as the expected + * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN. + * In the latter case, it will try to increase the presc value until + * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to + * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based + * on the targeted PLL and reference input clock to the PLL. Lastly, + * it sets the register based on these values along with the dividers. + * Note 1) There is no value checking for the passed-in divider values + * so the caller has to make sure those values are sensible. + * 2) Also adjust the NFC divider such that the NFC clock doesn't + * exceed NFC_CLK_MAX. + * 3) IPU HSP clock is independent of AHB clock. Even it can go up to + * 177MHz for higher voltage, this function fixes the max to 133MHz. + * 4) This function should not have allowed diag_printf() calls since + * the serial driver has been stoped. But leave then here to allow + * easy debugging by NOT calling the cyg_hal_plf_serial_stop(). + * + * @param ref pll input reference clock (24MHz) + * @param freq core clock in Hz + * @param clk clock type, e.g CPU_CLK, DDR_CLK, etc. + * @return 0 if successful; non-zero otherwise + */ +int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) +{ + freq *= SZ_DEC_1M; + + switch (clk) { + case MXC_ARM_CLK: + if (config_core_clk(ref, freq)) + return -1; + break; + case MXC_PERIPH_CLK: + if (config_periph_clk(ref, freq)) + return -1; + break; + case MXC_DDR_CLK: + if (config_ddr_clk(freq)) + return -1; + break; + case MXC_NFC_CLK: + if (config_nfc_clk(freq)) + return -1; + break; + default: + printf("Warning:Unsupported or invalid clock type\n"); + } + + return 0; +} + + +/* * Dump some core clockes. */ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -281,6 +825,7 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("pll3: %dMHz\n", freq / 1000000); printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK)); printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK)); + printf("ddr clock : %dHz\n", mxc_get_clock(MXC_DDR_CLK));
return 0; } diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 1f8a537..bcecd45 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -32,6 +32,9 @@ enum mxc_clock { MXC_UART_CLK, MXC_CSPI_CLK, MXC_FEC_CLK, + MXC_DDR_CLK, + MXC_NFC_CLK, + MXC_PERIPH_CLK, };
unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); @@ -39,5 +42,6 @@ unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); +int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index 4ed8eb3..735e4bd 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -76,6 +76,9 @@ struct mxc_ccm_reg { u32 CCGR4; u32 CCGR5; u32 CCGR6; /* 0x0080 */ +#ifdef CONFIG_MX53 + u32 CCGR7; /* 0x0084 */ +#endif u32 cmeor; };
@@ -84,6 +87,9 @@ struct mxc_ccm_reg { #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
/* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30) +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27 #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index a1849f8..896a229 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -98,6 +98,7 @@ #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) +#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000) #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
Add dialog pmic(DA9053) driver with I2C interface support
Signed-off-by: Jason Liu jason.hui@linaro.org --- drivers/misc/Makefile | 1 + drivers/misc/dialog_pmic.c | 123 +++++++++++++++++++++++++++++ include/da9053.h | 186 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 310 insertions(+), 0 deletions(-)
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index b152486..c557a14 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -35,6 +35,7 @@ COBJS-$(CONFIG_NS87308) += ns87308.o COBJS-$(CONFIG_PDSP188x) += pdsp188x.o COBJS-$(CONFIG_STATUS_LED) += status_led.o COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o +COBJS-$(CONFIG_DIALOG_PMIC) += dialog_pmic.o
COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/misc/dialog_pmic.c b/drivers/misc/dialog_pmic.c new file mode 100644 index 0000000..95dc6ea --- /dev/null +++ b/drivers/misc/dialog_pmic.c @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2011 Freescale Semiconductor, Inc. + * Based on drivers/misc/fsl_pmic.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <i2c.h> +#include <asm/errno.h> +#include <linux/types.h> + +static int check_param(u32 reg, u32 write) +{ + if (reg > 142 || write > 1) { + printf("<reg num> = %d is invalid. Should be less then 142\n", + reg); + return -1; + } + + return 0; +} + +static u32 pmic_reg(u32 reg, u32 val, u32 write) +{ + unsigned char buf[1] = { 0 }; + u32 ret_val = 0; + + if (check_param(reg, write)) + return -1; + + if (write) { + buf[0] = (val) & 0xff; + if (i2c_write(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR, reg, 1, buf, 1)) + return -1; + } else { + if (i2c_read(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR, reg, 1, buf, 1)) + return -1; + ret_val = buf[0]; + } + + return ret_val; +} + +void pmic_reg_write(u32 reg, u32 value) +{ + pmic_reg(reg, value, 1); +} + +u32 pmic_reg_read(u32 reg) +{ + return pmic_reg(reg, 0, 0); +} + +static void pmic_dump(int numregs) +{ + u32 val; + int i; + + for (i = 0; i < numregs; i++) { + val = pmic_reg_read(i); + if (!(i % 8)) + printf("\n0x%02x: ", i); + printf("%02x ", val); + } + puts("\n"); +} + +int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *cmd; + int nregs; + u32 val; + + /* at least two arguments please */ + if (argc < 2) + return cmd_usage(cmdtp); + + cmd = argv[1]; + if (strcmp(cmd, "dump") == 0) { + if (argc < 3) + return cmd_usage(cmdtp); + + nregs = simple_strtoul(argv[2], NULL, 16); + pmic_dump(nregs); + return 0; + } + if (strcmp(cmd, "write") == 0) { + if (argc < 4) + return cmd_usage(cmdtp); + + nregs = simple_strtoul(argv[2], NULL, 16); + val = simple_strtoul(argv[3], NULL, 16); + pmic_reg_write(nregs, val); + return 0; + } + /* No subcommand found */ + return 1; +} + +U_BOOT_CMD( + pmic, CONFIG_SYS_MAXARGS, 1, do_pmic, + "Dialog PMIC (DA905x)", + "dump [numregs] dump registers\n" + "pmic write <reg> <value> - write register" +); diff --git a/include/da9053.h b/include/da9053.h new file mode 100644 index 0000000..f69408a --- /dev/null +++ b/include/da9053.h @@ -0,0 +1,186 @@ +/* + * da9053 register declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __DA9053_REG_H__ +#define __DA9053_REG_H__ + +enum { + DA9053_PAGECON0_REG = 0, + DA9053_STATUSA_REG, + DA9053_STATUSB_REG, + DA9053_STATUSC_REG, + DA9053_STATUSD_REG, + DA9053_EVENTA_REG, + DA9053_EVENTB_REG, + DA9053_EVENTC_REG, + DA9053_EVENTD_REG, + DA9053_FAULTLOG_REG, + DA9053_IRQMASKA_REG, + DA9053_IRQMASKB_REG, + DA9053_IRQMASKC_REG, + DA9053_IRQMASKD_REG, + DA9053_CONTROLA_REG, + DA9053_CONTROLB_REG, + DA9053_CONTROLC_REG, + DA9053_CONTROLD_REG, + DA9053_PDDIS_REG, + DA9053_INTERFACE_REG, + DA9053_RESET_REG, + DA9053_GPIO0001_REG, + DA9053_GPIO0203_REG, + DA9053_GPIO0405_REG, + DA9053_GPIO0607_REG, + DA9053_GPIO0809_REG, + DA9053_GPIO1011_REG, + DA9053_GPIO1213_REG, + DA9053_GPIO1415_REG, + DA9053_ID01_REG, + DA9053_ID23_REG, + DA9053_ID45_REG, + DA9053_ID67_REG, + DA9053_ID89_REG, + DA9053_ID1011_REG, + DA9053_ID1213_REG, + DA9053_ID1415_REG, + DA9053_ID1617_REG, + DA9053_ID1819_REG, + DA9053_ID2021_REG, + DA9053_SEQSTATUS_REG, + DA9053_SEQA_REG, + DA9053_SEQB_REG, + DA9053_SEQTIMER_REG, + DA9053_BUCKA_REG, + DA9053_BUCKB_REG, + DA9053_BUCKCORE_REG, + DA9053_BUCKPRO_REG, + DA9053_BUCKMEM_REG, + DA9053_BUCKPERI_REG, + DA9053_LDO1_REG, + DA9053_LDO2_REG, + DA9053_LDO3_REG, + DA9053_LDO4_REG, + DA9053_LDO5_REG, + DA9053_LDO6_REG, + DA9053_LDO7_REG, + DA9053_LDO8_REG, + DA9053_LDO9_REG, + DA9053_LDO10_REG, + DA9053_SUPPLY_REG, + DA9053_PULLDOWN_REG, + DA9053_CHGBUCK_REG, + DA9053_WAITCONT_REG, + DA9053_ISET_REG, + DA9053_BATCHG_REG, + DA9053_CHGCONT_REG, + DA9053_INPUTCONT_REG, + DA9053_CHGTIME_REG, + DA9053_BBATCONT_REG, + DA9053_BOOST_REG, + DA9053_LEDCONT_REG, + DA9053_LEDMIN123_REG, + DA9053_LED1CONF_REG, + DA9053_LED2CONF_REG, + DA9053_LED3CONF_REG, + DA9053_LED1CONT_REG, + DA9053_LED2CONT_REG, + DA9053_LED3CONT_REG, + DA9053_LED4CONT_REG, + DA9053_LED5CONT_REG, + DA9053_ADCMAN_REG, + DA9053_ADCCONT_REG, + DA9053_ADCRESL_REG, + DA9053_ADCRESH_REG, + DA9053_VDDRES_REG, + DA9053_VDDMON_REG, + DA9053_ICHGAV_REG, + DA9053_ICHGTHD_REG, + DA9053_ICHGEND_REG, + DA9053_TBATRES_REG, + DA9053_TBATHIGHP_REG, + DA9053_TBATHIGHIN_REG, + DA9053_TBATLOW_REG, + DA9053_TOFFSET_REG, + DA9053_ADCIN4RES_REG, + DA9053_AUTO4HIGH_REG, + DA9053_AUTO4LOW_REG, + DA9053_ADCIN5RES_REG, + DA9053_AUTO5HIGH_REG, + DA9053_AUTO5LOW_REG, + DA9053_ADCIN6RES_REG, + DA9053_AUTO6HIGH_REG, + DA9053_AUTO6LOW_REG, + DA9053_TJUNCRES_REG, + DA9053_TSICONTA_REG, + DA9053_TSICONTB_REG, + DA9053_TSIXMSB_REG, + DA9053_TSIYMSB_REG, + DA9053_TSILSB_REG, + DA9053_TSIZMSB_REG, + DA9053_COUNTS_REG, + DA9053_COUNTMI_REG, + DA9053_COUNTH_REG, + DA9053_COUNTD_REG, + DA9053_COUNTMO_REG, + DA9053_COUNTY_REG, + DA9053_ALARMMI_REG, + DA9053_ALARMH_REG, + DA9053_ALARMD_REG, + DA9053_ALARMMO_REG, + DA9053_ALARMY_REG, + DA9053_SECONDA_REG, + DA9053_SECONDB_REG, + DA9053_SECONDC_REG, + DA9053_SECONDD_REG, + DA9053_PAGECON128_REG, + DA9053_CHIPID_REG, + DA9053_CONFIGID_REG, + DA9053_OTPCONT_REG, + DA9053_OSCTRIM_REG, + DA9053_GPID0_REG, + DA9053_GPID1_REG, + DA9053_GPID2_REG, + DA9053_GPID3_REG, + DA9053_GPID4_REG, + DA9053_GPID5_REG, + DA9053_GPID6_REG, + DA9053_GPID7_REG, + DA9053_GPID8_REG, + DA9053_GPID9_REG, +}; + +#define DA_BUCKCORE_VBCORE_1_250V 0x1e + +/* BUCKCORE REGISTER */ +#define DA9052_BUCKCORE_BCORECONF (1<<7) +#define DA9052_BUCKCORE_BCOREEN (1<<6) +#define DA9052_BUCKCORE_VBCORE (63<<0) + +/* SUPPLY REGISTER */ +#define DA9052_SUPPLY_VLOCK (1<<7) +#define DA9052_SUPPLY_VMEMSWEN (1<<6) +#define DA9052_SUPPLY_VPERISWEN (1<<5) +#define DA9052_SUPPLY_VLDO3GO (1<<4) +#define DA9052_SUPPLY_VLDO2GO (1<<3) +#define DA9052_SUPPLY_VBMEMGO (1<<2) +#define DA9052_SUPPLY_VBPROGO (1<<1) +#define DA9052_SUPPLY_VBCOREGO (1<<0) + +#endif /* __DA9053_REG_H__ */
On 04/22/2011 02:55 PM, Jason Liu wrote:
Add dialog pmic(DA9053) driver with I2C interface support
Hi Jason,
diff --git a/drivers/misc/dialog_pmic.c b/drivers/misc/dialog_pmic.c new file mode 100644 index 0000000..95dc6ea --- /dev/null +++ b/drivers/misc/dialog_pmic.c @@ -0,0 +1,123 @@ +/*
- (C) Copyright 2011 Freescale Semiconductor, Inc.
- Based on drivers/misc/fsl_pmic.c
As I can see now, this driver is quite a copy of fsl_pmic.c, with slightly changes. Are you sure we cannot simply change the already provided driver, adding support for the new chip ?
I have not read the DA9053 datasheet, but from your patch it seems to me that the relevant changes are: - registers are 1 byte wide instead of 32 bit - different size of register area
Really not enough to justify a new driver. All functions are really copied from the old one. Please consider to adapt fsl_pmic.c instead of adding a slightly different new one.
Best regards, Stefano Babic
Hi, Stefano,
2011/4/22 Stefano Babic sbabic@denx.de:
On 04/22/2011 02:55 PM, Jason Liu wrote:
Add dialog pmic(DA9053) driver with I2C interface support
Hi Jason,
diff --git a/drivers/misc/dialog_pmic.c b/drivers/misc/dialog_pmic.c new file mode 100644 index 0000000..95dc6ea --- /dev/null +++ b/drivers/misc/dialog_pmic.c @@ -0,0 +1,123 @@ +/*
- (C) Copyright 2011 Freescale Semiconductor, Inc.
- Based on drivers/misc/fsl_pmic.c
As I can see now, this driver is quite a copy of fsl_pmic.c, with slightly changes. Are you sure we cannot simply change the already provided driver, adding support for the new chip ?
I have not read the DA9053 datasheet, but from your patch it seems to me that the relevant changes are: - registers are 1 byte wide instead of 32 bit - different size of register area
Really not enough to justify a new driver. All functions are really copied from the old one. Please consider to adapt fsl_pmic.c instead of adding a slightly different new one.
fsl_pmic is about freescale mc13892 and fsl_pmic.c is dedicated for fsl pmic as you write this file, right?
As I add the Dialog PMIC support, I do want to not add one new file, but I find it's not easy to add it and it will make the file very mess, so, I decide not to touch the original file and add one new file. The head of this file tell it clear that this patch is Based on drivers/misc/fsl_pmic.c.
If you still want me to include the DA9053 support into fsl_pmic, could you please extend the fsl_pmic support to easily add another vender's pmic support first?
Jason
Best regards, Stefano Babic
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de ===================================================================== _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Am 22/04/2011 16:50, schrieb Jason Liu:
Hi Jason,
As I can see now, this driver is quite a copy of fsl_pmic.c, with slightly changes. Are you sure we cannot simply change the already provided driver, adding support for the new chip ?
I have not read the DA9053 datasheet, but from your patch it seems to me that the relevant changes are: - registers are 1 byte wide instead of 32 bit - different size of register area
Really not enough to justify a new driver. All functions are really copied from the old one. Please consider to adapt fsl_pmic.c instead of adding a slightly different new one.
fsl_pmic is about freescale mc13892 and fsl_pmic.c is dedicated for fsl pmic as you write this file, right?
It was for MC13892, but it is for MC13783 as well, used in i.MX31 boards.
As I add the Dialog PMIC support, I do want to not add one new file, but I find it's not easy to add it and it will make the file very mess, so, I decide not to touch the original file and add one new file. The head of this file tell it clear that this patch is Based on drivers/misc/fsl_pmic.c.
I do not mind an issue related to set where the driver is coming from. My concern is due to the fact that your patch is very similar (for the i2c part) to the fsl_pmic.c file, and I want to avoid to have two different driver making the same things, having then the necessity to maintain both. At the end, this file expones only a common interface to the board maintainers to access the pmic registers (via I2c or SPI as well). Running diff on the two files I do not see a lot of differences.
If you still want me to include the DA9053 support into fsl_pmic, could you please extend the fsl_pmic support to easily add another vender's pmic support first?
Really I have not understood your question. What do you mean ?
Best regards, Stefano Babic
Hi, Stefano,
On Sat, Apr 23, 2011 at 3:45 PM, stefano babic sbabic@denx.de wrote:
Am 22/04/2011 16:50, schrieb Jason Liu:
Hi Jason,
As I can see now, this driver is quite a copy of fsl_pmic.c, with slightly changes. Are you sure we cannot simply change the already provided driver, adding support for the new chip ?
I have not read the DA9053 datasheet, but from your patch it seems to me that the relevant changes are: - registers are 1 byte wide instead of 32 bit - different size of register area
Really not enough to justify a new driver. All functions are really copied from the old one. Please consider to adapt fsl_pmic.c instead of adding a slightly different new one.
fsl_pmic is about freescale mc13892 and fsl_pmic.c is dedicated for fsl pmic as you write this file, right?
It was for MC13892, but it is for MC13783 as well, used in i.MX31 boards.
As I add the Dialog PMIC support, I do want to not add one new file, but I find it's not easy to add it and it will make the file very mess, so, I decide not to touch the original file and add one new file. The head of this file tell it clear that this patch is Based on drivers/misc/fsl_pmic.c.
I do not mind an issue related to set where the driver is coming from. My concern is due to the fact that your patch is very similar (for the i2c part) to the fsl_pmic.c file, and I want to avoid to have two different driver making the same things, having then the necessity to maintain both. At the end, this file expones only a common interface to the board maintainers to access the pmic registers (via I2c or SPI as well). Running diff on the two files I do not see a lot of differences.
If you still want me to include the DA9053 support into fsl_pmic, could you please extend the fsl_pmic support to easily add another vender's pmic support first?
Really I have not understood your question. What do you mean ?
Then, Can you tell me how to add the dialog pmic support into fsl_pmi.c file which is dedicated for freescale mc13xxx? Thanks,
Best regards, Stefano Babic
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
On 04/25/2011 04:59 AM, Jason Hui wrote:
Hi, Stefano,
Hi Jason,
If you still want me to include the DA9053 support into fsl_pmic, could you please extend the fsl_pmic support to easily add another vender's pmic support first?
Really I have not understood your question. What do you mean ?
Then, Can you tell me how to add the dialog pmic support into fsl_pmi.c file which is dedicated for freescale mc13xxx? Thanks,
IMHO the details for each Power Controllers are inside the corresponding header, that contains the register description, in your xace DA09053.h. The fsl_pmic.c expones only a general way to speak with the controller via SPI or I2C interface. If I see your patch, the only real difference with the original file is that a single byte is read/written with the DA09053, while the mc13xxx have 32-bit registers. You can add this option as CONFIG_ switch, or in another way.
Only the board is aware about which PMIC is used. In fact, the fsl_pmic.c does not include neither mc13892.h nor mc13783.h.
Best regards, Stefano Babic
Hi Stefano,
On 04/25/2011 04:59 AM, Jason Hui wrote:
Hi, Stefano,
Hi Jason,
If you still want me to include the DA9053 support into fsl_pmic, could you please extend the fsl_pmic support to easily add another vender's pmic support first?
Really I have not understood your question. What do you mean ?
Then, Can you tell me how to add the dialog pmic support into fsl_pmi.c file which is dedicated for freescale mc13xxx? Thanks,
IMHO the details for each Power Controllers are inside the corresponding header, that contains the register description, in your xace DA09053.h. The fsl_pmic.c expones only a general way to speak with the controller via SPI or I2C interface. If I see your patch, the only real difference with the original file is that a single byte is read/written with the DA09053, while the mc13xxx have 32-bit registers. You can add this option as CONFIG_ switch, or in another way.
Only the board is aware about which PMIC is used. In fact, the fsl_pmic.c does not include neither mc13892.h nor mc13783.h.
Then why not rename the driver to something else than "fsl_pmic"? Maybe this is what Jason really is asking? I have not looked any deeper, but maybe something like "i2c_pmic" or such...
Cheers Detlev
On 04/27/2011 11:39 AM, Detlev Zundel wrote:
Then why not rename the driver to something else than "fsl_pmic"? Maybe this is what Jason really is asking?
Yes, of course, no problem at all. Jason, if you meant to drop the fsl_ to make the driver more general, I completely agree. Sorry, I have not got the point.
Best regards, Stefano
Hi, Stefano,
2011/4/27 Stefano Babic sbabic@denx.de:
On 04/27/2011 11:39 AM, Detlev Zundel wrote:
Then why not rename the driver to something else than "fsl_pmic"? Maybe this is what Jason really is asking?
Yes, of course, no problem at all. Jason, if you meant to drop the fsl_ to make the driver more general, I completely agree. Sorry, I have not got the point.
Sorry for the late response due to some reason. :(
Yes, We had better rename fsl_ to something else, I would like use generic_pmic or something else, what's your idea?
Jason
Best regards, Stefano
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de ===================================================================== _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On 05/10/2011 07:39 AM, Jason Liu wrote:
Hi, Stefano,
Hi Jason,
2011/4/27 Stefano Babic sbabic@denx.de:
On 04/27/2011 11:39 AM, Detlev Zundel wrote:
Then why not rename the driver to something else than "fsl_pmic"? Maybe this is what Jason really is asking?
Yes, of course, no problem at all. Jason, if you meant to drop the fsl_ to make the driver more general, I completely agree. Sorry, I have not got the point.
Sorry for the late response due to some reason. :(
No problem at all.
Yes, We had better rename fsl_ to something else, I would like use generic_pmic or something else, what's your idea?
I am open for new names. Probably we should state that this driver is a wrapper when SPI or I2C is used, and something like spi_i2c_pmic gives a better idea. With generic_pmic we could think there is a general layout for PMICs (and it is not true).
Best regards, Stefano Babic
Hi, Stefano,
On Tue, May 10, 2011 at 4:35 PM, Stefano Babic sbabic@denx.de wrote:
On 05/10/2011 07:39 AM, Jason Liu wrote:
Hi, Stefano,
Hi Jason,
2011/4/27 Stefano Babic sbabic@denx.de:
On 04/27/2011 11:39 AM, Detlev Zundel wrote:
Then why not rename the driver to something else than "fsl_pmic"? Maybe this is what Jason really is asking?
Yes, of course, no problem at all. Jason, if you meant to drop the fsl_ to make the driver more general, I completely agree. Sorry, I have not got the point.
Sorry for the late response due to some reason. :(
No problem at all.
Yes, We had better rename fsl_ to something else, I would like use generic_pmic or something else, what's your idea?
I am open for new names. Probably we should state that this driver is a wrapper when SPI or I2C is used, and something like spi_i2c_pmic gives a better idea. With generic_pmic we could think there is a general layout for PMICs (and it is not true).
OK, agree. I will change it to spi_i2c_pmic.c. :)
Best regards, Stefano Babic
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
Dear Jason Liu,
In message BANLkTin-CUD+y7MeQyJF3W1Jq49zzTSAiw@mail.gmail.com you wrote:
Really not enough to justify a new driver. All functions are really copied from the old one. Please consider to adapt fsl_pmic.c instead of adding a slightly different new one.
fsl_pmic is about freescale mc13892 and fsl_pmic.c is dedicated for fsl pmic as you write this file, right?
As I add the Dialog PMIC support, I do want to not add one new file, but I find it's not easy to add it and it will make the file very mess, so, I decide not to touch the original file and add one new file. The head of this file tell it clear that this patch is Based on drivers/misc/fsl_pmic.c.
Stefano is right. We cannot accept such duplication of code. Please merge into a single common driver.
Best regards,
Wolfgang Denk
This patch add initial support for freescale MX53LOCO board. Network(FEC),SD/MMC,UART have been supported by this patch
The patch also config CPU:1GHZ,DDR:400MHZ for better peformance
Signed-off-by: Jason Liu jason.hui@linaro.org --- Changes since v5: - merge the "Add power init support" patch changes since v4: - remove the boot reset cause from board support changes since v3: - include other two small patch into this commit, mx53loco: set mmc env to MMC slot1 MX5: Enable flat-device-tree support on mx53 loco board changes since V2: -factor out the boot cause function to common code, -fix gd->ram_size with full memory size -remove the '1' from all #defines that just enable features -correct memory test end address value --- MAINTAINERS | 1 + arch/arm/cpu/armv7/mx5/soc.c | 2 +- arch/arm/include/asm/arch-mx5/sys_proto.h | 2 + board/freescale/mx53loco/Makefile | 47 ++++ board/freescale/mx53loco/imximage.cfg | 96 +++++++ board/freescale/mx53loco/mx53loco.c | 395 +++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/mx53loco.h | 198 +++++++++++++++ 8 files changed, 741 insertions(+), 1 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS index 1299cbb..c00a196 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -567,6 +567,7 @@ Stefano Babic sbabic@denx.de Jason Liu r64343@freescale.com
mx53evk i.MX53 + mx53loco i.MX53
Enric Balletbo i Serra eballetbo@iseebcn.com
diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 6f4e8db..9c03474 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -116,7 +116,7 @@ int print_cpuinfo(void) (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); - printf("Reset cause: %s\n", get_reset_cause()); + printf("Reset cause: %s\n", get_reset_cause()); return 0; } #endif diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index f687503..2d7e9ed 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -27,5 +27,7 @@ u32 get_cpu_rev(void); #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) void sdelay(unsigned long); +void pmic_reg_write(u32 reg, u32 value); +u32 pmic_reg_read(u32 reg);
#endif diff --git a/board/freescale/mx53loco/Makefile b/board/freescale/mx53loco/Makefile new file mode 100644 index 0000000..2088a48 --- /dev/null +++ b/board/freescale/mx53loco/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# Jason Liu r64343@freescale.com +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := mx53loco.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg new file mode 100644 index 0000000..ce9c8fc --- /dev/null +++ b/board/freescale/mx53loco/imximage.cfg @@ -0,0 +1,96 @@ +# Copyright (C) 2011 Freescale Semiconductor, Inc. +# Jason Liu r64343@freescale.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# image version + +IMAGE_VERSION 2 + +# Boot Device : one of +# spi, sd (the board has no nand neither onenand) + +BOOT_FROM sd + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register + +DATA 4 0x53fa8554 0x00300000 +DATA 4 0x53fa8558 0x00300040 +DATA 4 0x53fa8560 0x00300000 +DATA 4 0x53fa8564 0x00300040 +DATA 4 0x53fa8568 0x00300040 +DATA 4 0x53fa8570 0x00300000 +DATA 4 0x53fa8574 0x00300000 +DATA 4 0x53fa8578 0x00300000 +DATA 4 0x53fa857c 0x00300040 +DATA 4 0x53fa8580 0x00300040 +DATA 4 0x53fa8584 0x00300000 +DATA 4 0x53fa8588 0x00300000 +DATA 4 0x53fa8590 0x00300040 +DATA 4 0x53fa8594 0x00300000 +DATA 4 0x53fa86f0 0x00300000 +DATA 4 0x53fa86f4 0x00000000 +DATA 4 0x53fa86fc 0x00000000 +DATA 4 0x53fa8714 0x00000000 +DATA 4 0x53fa8718 0x00300000 +DATA 4 0x53fa871c 0x00300000 +DATA 4 0x53fa8720 0x00300000 +DATA 4 0x53fa8724 0x04000000 +DATA 4 0x53fa8728 0x00300000 +DATA 4 0x53fa872c 0x00300000 +DATA 4 0x63fd9088 0x35343535 +DATA 4 0x63fd9090 0x4d444c44 +DATA 4 0x63fd907c 0x01370138 +DATA 4 0x63fd9080 0x013b013c +DATA 4 0x63fd9018 0x00011740 +DATA 4 0x63fd9000 0xc3190000 +DATA 4 0x63fd900c 0x9f5152e3 +DATA 4 0x63fd9010 0xb68e8a63 +DATA 4 0x63fd9014 0x01ff00db +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x009f0e21 +DATA 4 0x63fd9008 0x12273030 +DATA 4 0x63fd9004 0x0002002d +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9040 0x04b80003 +DATA 4 0x63fd9058 0x00022227 +DATA 4 0x63fd901c 0x00000000 diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c new file mode 100644 index 0000000..62ed400 --- /dev/null +++ b/board/freescale/mx53loco/mx53loco.c @@ -0,0 +1,395 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu r64343@freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx5x_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/clock.h> +#include <asm/errno.h> +#include <netdev.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <mxc_gpio.h> +#include <da9053.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int dram_init(void) +{ + u32 size1, size2; + + size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + + gd->ram_size = size1 + size2; + + return 0; +} +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +} + +static void setup_iomux_uart(void) +{ + /* UART1 RXD */ + mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX53_PIN_CSI0_D11, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); + + /* UART1 TXD */ + mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX53_PIN_CSI0_D10, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_ENABLE); +} + +static void setup_iomux_fec(void) +{ + /*FEC_MDIO*/ + mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); + mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); + + /*FEC_MDC*/ + mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); + + /* FEC RXD1 */ + mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + + /* FEC RXD0 */ + mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + + /* FEC TXD1 */ + mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); + + /* FEC TXD0 */ + mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); + + /* FEC TX_EN */ + mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); + + /* FEC TX_CLK */ + mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + + /* FEC RX_ER */ + mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + + /* FEC CRS */ + mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1}, + {MMC_SDHC3_BASE_ADDR, 1}, +}; + +int board_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) + *cd = mxc_gpio_get(77); /*GPIO3_13*/ + else + *cd = mxc_gpio_get(75); /*GPIO3_11*/ + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + u32 index; + s32 status = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { + switch (index) { + case 0: + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_EIM_DA13, + IOMUX_CONFIG_ALT1); + + mxc_iomux_set_pad(MX53_PIN_SD1_CMD, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_CLK, + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + break; + case 1: + mxc_request_iomux(MX53_PIN_ATA_RESET_B, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_IORDY, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_DATA8, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA9, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA10, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA11, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA0, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA1, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA2, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA3, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_EIM_DA11, + IOMUX_CONFIG_ALT1); + + mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + } + + return status; +} +#endif + +static void setup_i2c(unsigned int port_number) +{ + switch (port_number) { + case 0: + /* i2c1 SDA */ + mxc_request_iomux(MX53_PIN_CSI0_D8, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + /* i2c1 SCL */ + mxc_request_iomux(MX53_PIN_CSI0_D9, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + break; + case 1: + /* i2c2 SDA */ + mxc_request_iomux(MX53_PIN_KEY_ROW3, + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_KEY_ROW3, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + + /* i2c2 SCL */ + mxc_request_iomux(MX53_PIN_KEY_COL3, + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_KEY_COL3, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + break; + default: + printf("Warning: Wrong I2C port number\n"); + break; + } +} + +static void clock_init(void) +{ + int ret; + u32 ref_clk = CONFIG_SYS_MX5_HCLK; + /* + * After increase voltage to 1.25V, We can switch + * CPU clokc to 1Ghz and DDR to 400Mhz safely now + */ + ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); + if (!ret) + printf("CPU: Switch CPU clock to 1GHZ OK\n"); + else + printf("CPU: Switch CPU clock to 1GHZ failed\n"); + + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); + if (!ret) + printf("DDR: Switch DDR clock to 400MHz OK\n"); + else + printf("CPU: Switch DDR clock to 1GHZ failed\n"); +} + +static void power_init(void) +{ + unsigned int val; + + /* Set VDDA to 1.25V */ + val = DA9052_BUCKCORE_BCOREEN; + val |= DA_BUCKCORE_VBCORE_1_250V; + pmic_reg_write(DA9053_BUCKCORE_REG, val); + val = pmic_reg_read(DA9053_SUPPLY_REG); + val |= DA9052_SUPPLY_VBCOREGO; + pmic_reg_write(DA9053_SUPPLY_REG, val); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_fec(); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_MX53_LOCO; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + +#ifdef CONFIG_I2C_MXC + setup_i2c(0); + power_init(); + clock_init(); +#endif + return 0; +} + +int checkboard(void) +{ + puts("Board: MX53 LOCO\n"); + + return 0; +} diff --git a/boards.cfg b/boards.cfg index 55c21f2..4d1b211 100644 --- a/boards.cfg +++ b/boards.cfg @@ -110,6 +110,7 @@ ca9x4_ct_vxp arm armv7 vexpress armltd efikamx arm armv7 efikamx - mx5 mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg +mx53loco arm armv7 mx53loco freescale mx5 mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg vision2 arm armv7 vision2 ttcontrol mx5 cm_t35 arm armv7 cm_t35 - omap3 omap3_overo arm armv7 overo - omap3 diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h new file mode 100644 index 0000000..11df9b8 --- /dev/null +++ b/include/configs/mx53loco.h @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu r64343@freescale.com + * + * Configuration settings for Freescale MX53 low cost board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX53 + +#define CONFIG_SYS_MX5_HCLK 24000000 +#define CONFIG_SYS_MX5_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_L2_OFF + +#include <asm/arch/imx-regs.h> + +#define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX53_UART1 + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_MX53_PORT1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +/* PMIC Configs */ +#define CONFIG_DIALOG_PMIC +#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Eth Configs */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_SYS_TEXT_BASE 0x77800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm\0" \ + "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "dhcp ${uimage}; bootm\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "MX53LOCO U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x70000000 +#define CONFIG_SYS_MEMTEST_END 0x70010000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_CMDLINE_EDITING + +/* Stack sizes */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) +#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_OF_LIBFDT +#define CONFIG_SYS_BOOTMAPSZ 0x800000 + +#endif /* __CONFIG_H */
Hi, Stefano,
2011/4/22 Jason Liu jason.hui@linaro.org:
The boot cause code has been factor out to soc common code,we need drop the part from the board support code
This patch also remove the redundant cpu version print
Signed-off-by: Jason Liu jason.hui@linaro.org
changes since v1
-include more clean up by remove the redundant cpu version print
board/efikamx/efikamx.c | 42 +------------------------------------ board/freescale/mx51evk/mx51evk.c | 36 +------------------------------ board/freescale/mx53evk/mx53evk.c | 21 +----------------- board/ttcontrol/vision2/vision2.c | 42 +------------------------------------ 4 files changed, 4 insertions(+), 137 deletions(-)
Ping, any comments about this patch?
Jason
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Hi,Stefano,
2011/5/11 Jason Liu liu.h.jason@gmail.com:
Hi, Stefano,
2011/4/22 Jason Liu jason.hui@linaro.org:
The boot cause code has been factor out to soc common code,we need drop the part from the board support code
This patch also remove the redundant cpu version print
Signed-off-by: Jason Liu jason.hui@linaro.org
changes since v1
-include more clean up by remove the redundant cpu version print
board/efikamx/efikamx.c | 42 +------------------------------------ board/freescale/mx51evk/mx51evk.c | 36 +------------------------------ board/freescale/mx53evk/mx53evk.c | 21 +----------------- board/ttcontrol/vision2/vision2.c | 42 +------------------------------------ 4 files changed, 4 insertions(+), 137 deletions(-)
Ping, any comments about this patch?
Any comments, if not, please pull it, thanks.
Jason
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On 05/16/2011 07:48 AM, Jason Liu wrote:
Hi,Stefano,
Any comments, if not, please pull it, thanks.
No, I have not. I will pull it.
Best regards, Stefano Babic
On 04/22/2011 02:55 PM, Jason Liu wrote:
The boot cause code has been factor out to soc common code,we need drop the part from the board support code
This patch also remove the redundant cpu version print
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
participants (7)
-
Detlev Zundel -
Jason Hui -
Jason Liu
-
Jason Liu -
Stefano Babic -
stefano babic
-
Wolfgang Denk