Currently driver accepts all resolution which won't work on 4k screens. Add validation callback which limits acceptable resolutions to 297 MHz.

Reviewed-by: Andre Przywara andre.przywara@arm.com Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/video/sunxi/sunxi_dw_hdmi.c | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 0b8cefc311ef..e3811a2ec15f 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -305,6 +305,12 @@ static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size) return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size); }

+static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev, + const struct display_timing *timing) +{ + return timing->pixelclock.typ <= 297000000; +} + static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, const struct display_timing *edid) { @@ -388,6 +394,7 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) static const struct dm_display_ops sunxi_dw_hdmi_ops = { .read_edid = sunxi_dw_hdmi_read_edid, .enable = sunxi_dw_hdmi_enable, + .mode_valid = sunxi_dw_hdmi_mode_valid, };

U_BOOT_DRIVER(sunxi_dw_hdmi) = {

Code which searches for valid detailed timing entry will be used in more places. Extract it.

No functional change is made. However, descriptors are casted to edid_detailed_timing instead of edid_monitor_descriptor. Descriptor can be of either type, but since we're interested only in DTD, it is more fitting to cast to edid_detailed_timing.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- common/edid.c | 49 ++++++++++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 21 deletions(-)

diff --git a/common/edid.c b/common/edid.c index 1cb7177742e8..a6c875d9c8e8 100644 --- a/common/edid.c +++ b/common/edid.c @@ -169,6 +169,29 @@ static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) return false; }

+static bool edid_find_valid_timing(void *buf, int count, + struct display_timing *timing, + bool (*mode_valid)(void *priv, + const struct display_timing *timing), + void *mode_valid_priv) +{ + struct edid_detailed_timing *t = buf; + bool found = false; + int i; + + for (i = 0; i < count && !found; i++, t++) + if (EDID_DETAILED_TIMING_PIXEL_CLOCK(*t) != 0) { + decode_timing((u8 *)t, timing); + if (mode_valid) + found = mode_valid(mode_valid_priv, + timing); + else + found = true; + } + + return found; +} + int edid_get_timing_validate(u8 *buf, int buf_size, struct display_timing *timing, int *panel_bits_per_colourp, @@ -177,8 +200,7 @@ int edid_get_timing_validate(u8 *buf, int buf_size, void *mode_valid_priv) { struct edid1_info *edid = (struct edid1_info *)buf; - bool timing_done; - int i; + bool found;

if (buf_size < sizeof(*edid) || edid_check_info(edid)) { debug("%s: Invalid buffer\n", __func__); @@ -195,25 +217,10 @@ int edid_get_timing_validate(u8 *buf, int buf_size, return -ENOENT; }

- /* Look for detailed timing */ - timing_done = false; - for (i = 0; i < 4; i++) { - struct edid_monitor_descriptor *desc; - - desc = &edid->monitor_details.descriptor[i]; - if (desc->zero_flag_1 != 0) { - decode_timing((u8 *)desc, timing); - if (mode_valid) - timing_done = mode_valid(mode_valid_priv, - timing); - else - timing_done = true; - - if (timing_done) - break; - } - } - if (!timing_done) + /* Look for detailed timing in base EDID */ + found = edid_find_valid_timing(edid->monitor_details.descriptor, 4, + timing, mode_valid, mode_valid_priv); + if (!found) return -EINVAL;

if (edid->version != 1 || edid->revision < 4) {

One of my monitors have only 4k@60 timing in base EDID block which is out of range for devices with HDMI 1.4. It turns out that it has additional detailed timings in CTA-861 Extension Block and two of them are appropriate for HDMI 1.4.

Add additional search for valid detailed timing in extension block.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- common/edid.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)

diff --git a/common/edid.c b/common/edid.c index a6c875d9c8e8..14d8836c360e 100644 --- a/common/edid.c +++ b/common/edid.c @@ -220,6 +220,24 @@ int edid_get_timing_validate(u8 *buf, int buf_size, /* Look for detailed timing in base EDID */ found = edid_find_valid_timing(edid->monitor_details.descriptor, 4, timing, mode_valid, mode_valid_priv); + + /* Look for detailed timing in CTA-861 Extension Block */ + if (!found && edid->extension_flag && buf_size >= EDID_EXT_SIZE) { + struct edid_cea861_info *info = + (struct edid_cea861_info *)(buf + sizeof(*edid)); + + if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) { + int count = EDID_CEA861_DTD_COUNT(*info); + int offset = info->dtd_offset; + int size = count * sizeof(struct edid_detailed_timing); + + if (offset >= 4 && offset + size < EDID_SIZE) + found = edid_find_valid_timing( + (u8*)info + offset, count, timing, + mode_valid, mode_valid_priv); + } + } + if (!found) return -EINVAL;

TV driver was never fully implemented. Remove search for it from DE2 driver.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/video/sunxi/sunxi_de2.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index a3e21aa5f13e..6b836a011944 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -281,20 +281,7 @@ static int sunxi_de2_probe(struct udevice *dev)

debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);

- ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_tve", &disp); - if (ret) { - debug("%s: tv not found (ret=%d)\n", __func__, ret); - return ret; - } - - ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true); - if (ret) - return ret; - - video_set_flush_dcache(dev, 1); - - return 0; + return -ENODEV; }

static int sunxi_de2_bind(struct udevice *dev)

Currently DE2 driver uses functions which are defined in internal headers. They are not meant to be used outside of uclass framework. Switch DE2 driver to public ones. This has additional benefit that device_probe doesn't need to be called manually.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/video/sunxi/sunxi_de2.c | 29 ++++++++++------------------- 1 file changed, 10 insertions(+), 19 deletions(-)

diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index 6b836a011944..e02d359cd259 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -19,8 +19,6 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/display2.h> -#include <dm/device-internal.h> -#include <dm/uclass-internal.h> #include <linux/bitops.h> #include "simplefb_common.h"

@@ -198,13 +196,6 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase,

disp_uc_plat->source_id = mux;

- ret = device_probe(disp); - if (ret) { - debug("%s: device '%s' display won't probe (ret=%d)\n", - __func__, dev->name, ret); - return ret; - } - ret = display_read_timing(disp, &timing); if (ret) { debug("%s: Failed to read timings\n", __func__); @@ -245,8 +236,8 @@ static int sunxi_de2_probe(struct udevice *dev) if (!(gd->flags & GD_FLG_RELOC)) return 0;

- ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_lcd", &disp); + ret = uclass_get_device_by_driver(UCLASS_DISPLAY, + DM_DRIVER_GET(sunxi_lcd), &disp); if (!ret) { int mux;

@@ -262,8 +253,8 @@ static int sunxi_de2_probe(struct udevice *dev)

debug("%s: lcd display not found (ret=%d)\n", __func__, ret);

- ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_dw_hdmi", &disp); + ret = uclass_get_device_by_driver(UCLASS_DISPLAY, + DM_DRIVER_GET(sunxi_dw_hdmi), &disp); if (!ret) { int mux; if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) @@ -332,8 +323,8 @@ int sunxi_simplefb_setup(void *blob) mux = 1;

/* Skip simplefb setting if DE2 / HDMI is not present */ - ret = uclass_find_device_by_name(UCLASS_VIDEO, - "sunxi_de2", &de2); + ret = uclass_get_device_by_driver(UCLASS_VIDEO, + DM_DRIVER_GET(sunxi_de2), &de2); if (ret) { debug("DE2 not present\n"); return 0; @@ -342,8 +333,8 @@ int sunxi_simplefb_setup(void *blob) return 0; }

- ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_dw_hdmi", &hdmi); + ret = uclass_get_device_by_driver(UCLASS_DISPLAY, + DM_DRIVER_GET(sunxi_dw_hdmi), &hdmi); if (ret) { debug("HDMI not present\n"); } else if (device_active(hdmi)) { @@ -355,8 +346,8 @@ int sunxi_simplefb_setup(void *blob) debug("HDMI present but not probed\n"); }

- ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_lcd", &lcd); + ret = uclass_get_device_by_driver(UCLASS_DISPLAY, + DM_DRIVER_GET(sunxi_lcd), &lcd); if (ret) debug("LCD not present\n"); else if (device_active(lcd))

Currently DE2 uses hardcoded address based on SoC for which U-Boot is built. Read it from DT instead so there is no need to specify it when support for new SoC is added.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/video/sunxi/sunxi_de2.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index 81576e45e9ef..f6c8ca075aba 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -64,11 +64,10 @@ static void sunxi_de2_composer_init(void) setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE); }

-static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, +static void sunxi_de2_mode_set(ulong de_mux_base, int mux, + const struct display_timing *mode, int bpp, ulong address, bool is_composite) { - ulong de_mux_base = (mux == 0) ? - SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE; struct de_clk * const de_clk_regs = (struct de_clk *)(SUNXI_DE2_BASE); struct de_glb * const de_glb_regs = @@ -208,7 +207,8 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, }

sunxi_de2_composer_init(); - sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite); + sunxi_de2_mode_set((ulong)dev_read_addr(dev), mux, &timing, + 1 << l2bpp, fbbase, is_composite);

ret = display_enable(disp, 1 << l2bpp, &timing); if (ret) {

These clocks and resets are needed for video drivers.

Cc: Lukasz Majewski lukma@denx.de Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/clk/sunxi/clk_a64.c | 12 ++++++++++++ drivers/clk/sunxi/clk_h3.c | 12 ++++++++++++ 2 files changed, 24 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 0553ffa4399a..28131240652f 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -26,6 +26,9 @@ static const struct ccu_clk_gate a64_gates[] = { [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)), [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),

+ [CLK_BUS_HDMI] = GATE(0x064, BIT(11)), + [CLK_BUS_DE] = GATE(0x064, BIT(12)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -41,6 +44,11 @@ static const struct ccu_clk_gate a64_gates[] = { [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)), [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)), [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)), + + [CLK_DE] = GATE(0x104, BIT(31)), + + [CLK_HDMI] = GATE(0x150, BIT(31)), + [CLK_HDMI_DDC] = GATE(0x154, BIT(31)), };

static const struct ccu_reset a64_resets[] = { @@ -60,6 +68,10 @@ static const struct ccu_reset a64_resets[] = { [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)), [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),

+ [RST_BUS_HDMI0] = RESET(0x2c4, BIT(10)), + [RST_BUS_HDMI1] = RESET(0x2c4, BIT(11)), + [RST_BUS_DE] = RESET(0x2c4, BIT(12)), + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index f81633b92d5a..806a35b37435 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -30,6 +30,9 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)), [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),

+ [CLK_BUS_HDMI] = GATE(0x064, BIT(11)), + [CLK_BUS_DE] = GATE(0x064, BIT(12)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -48,6 +51,11 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)), [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)), [CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)), + + [CLK_DE] = GATE(0x104, BIT(31)), + + [CLK_HDMI] = GATE(0x150, BIT(31)), + [CLK_HDMI_DDC] = GATE(0x154, BIT(31)), };

static struct ccu_reset h3_resets[] = { @@ -72,6 +80,10 @@ static struct ccu_reset h3_resets[] = { [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)), [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),

+ [RST_BUS_HDMI0] = RESET(0x2c4, BIT(10)), + [RST_BUS_HDMI1] = RESET(0x2c4, BIT(11)), + [RST_BUS_DE] = RESET(0x2c4, BIT(12)), + [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),

[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),

Video driver currently manages clocks and resets by directly writing to registers. This is already a bit messy because each SoC has some specifics. It's much better to implement proper clock and reset driver which takes information from device tree file.

Note that this driver is not perfect yet. It still sets PLL and parent by hand. Sunxi clock framework still doesn't know how to set parents or rates. However, this is already big step in right direction.

Cc: Lukasz Majewski lukma@denx.de Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/clk/sunxi/Kconfig | 5 +++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_de2.c | 85 +++++++++++++++++++++++++++++++++++++ 3 files changed, 91 insertions(+) create mode 100644 drivers/clk/sunxi/clk_de2.c

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index bf084fa7a84a..6c96affb1f87 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -44,6 +44,11 @@ config CLK_SUN8I_A83T This enables common clock driver support for platforms based on Allwinner A83T SoC.

+config CLK_SUN8I_DE2 + bool "Clock driver for Allwinner Display Engine 2 and 3" + help + This enables common clock driver support for Display Engine 2 and 3. + config CLK_SUN8I_R40 bool "Clock driver for Allwinner R40" default MACH_SUN8I_R40 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 0dfc0593fb1c..620ff96ac6f5 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o +obj-$(CONFIG_CLK_SUN8I_DE2) += clk_de2.o obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o diff --git a/drivers/clk/sunxi/clk_de2.c b/drivers/clk/sunxi/clk_de2.c new file mode 100644 index 000000000000..b8c45404c1b6 --- /dev/null +++ b/drivers/clk/sunxi/clk_de2.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Jernej Skrabec jernej.skrabec@siol.net + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/arch/ccu.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <dt-bindings/clock/sun8i-de2.h> +#include <dt-bindings/reset/sun8i-de2.h> +#include <linux/bitops.h> + +static struct ccu_clk_gate de2_gates[] = { + [CLK_MIXER0] = GATE(0x00, BIT(0)), + [CLK_MIXER1] = GATE(0x00, BIT(1)), + [CLK_WB] = GATE(0x00, BIT(2)), + + [CLK_BUS_MIXER0] = GATE(0x04, BIT(0)), + [CLK_BUS_MIXER1] = GATE(0x04, BIT(1)), + [CLK_BUS_WB] = GATE(0x04, BIT(2)), +}; + +static struct ccu_reset de2_resets[] = { + [RST_MIXER0] = RESET(0x08, BIT(0)), + [RST_MIXER1] = RESET(0x08, BIT(1)), + [RST_WB] = RESET(0x08, BIT(2)), +}; + +static const struct ccu_desc de2_ccu_desc = { + .gates = de2_gates, + .resets = de2_resets, +}; + +static int de2_clk_probe(struct udevice *dev) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + u32 val; + + if (device_is_compatible(dev_get_parent(dev), + "allwinner,sun50i-a64-de2")) { + /* set SRAM for video use */ + val = readl(SUNXI_SRAMC_BASE + 0x04); + val &= ~(0x01 << 24); + writel(val, SUNXI_SRAMC_BASE + 0x04); + } + + /* clock driver doesn't know how to set rate or parent yet */ + clock_set_pll10(432000000); + + /* Set DE parent to pll10 */ + clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, + CCM_DE2_CTRL_PLL10); + + return sunxi_clk_probe(dev); +} + +static int de2_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, ARRAY_SIZE(de2_resets)); +} + +static const struct udevice_id de2_ccu_ids[] = { + { .compatible = "allwinner,sun8i-h3-de2-clk", + .data = (ulong)&de2_ccu_desc }, + { .compatible = "allwinner,sun50i-a64-de2-clk", + .data = (ulong)&de2_ccu_desc }, + { .compatible = "allwinner,sun50i-h5-de2-clk", + .data = (ulong)&de2_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun8i_de2) = { + .name = "sun8i_de2_ccu", + .id = UCLASS_CLK, + .of_match = de2_ccu_ids, + .priv_auto = sizeof(struct ccu_priv), + .ops = &sunxi_clk_ops, + .probe = de2_clk_probe, + .bind = de2_clk_bind, +};

Now that proper DM clock and reset driver exists for Display Engine 2 and 3, remove all clock and reset related code and use appropriate framework instead.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- arch/arm/mach-sunxi/Kconfig | 1 + drivers/video/sunxi/sunxi_de2.c | 67 +++++++++++---------------------- 2 files changed, 23 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 9149196b223e..34ef1f4b030f 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -970,6 +970,7 @@ config SUNXI_DE2 config VIDEO_DE2 bool "Display Engine 2 video driver" depends on SUNXI_DE2 + select CLK_SUN8I_DE2 select DM_VIDEO select DISPLAY select VIDEO_DW_HDMI diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index f6c8ca075aba..cee9b46b1259 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -6,6 +6,7 @@ */

#include <common.h> +#include <clk.h> #include <display.h> #include <dm.h> #include <edid.h> @@ -14,10 +15,10 @@ #include <fdt_support.h> #include <log.h> #include <part.h> +#include <reset.h> #include <video.h> #include <asm/global_data.h> #include <asm/io.h> -#include <asm/arch/clock.h> #include <asm/arch/display2.h> #include <linux/bitops.h> #include "simplefb_common.h" @@ -36,40 +37,10 @@ struct sunxi_de2_data { const char *disp_drv_name; };

-static void sunxi_de2_composer_init(void) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - -#ifdef CONFIG_MACH_SUN50I - u32 reg_value; - - /* set SRAM for video use (A64 only) */ - reg_value = readl(SUNXI_SRAMC_BASE + 0x04); - reg_value &= ~(0x01 << 24); - writel(reg_value, SUNXI_SRAMC_BASE + 0x04); -#endif - - clock_set_pll10(432000000); - - /* Set DE parent to pll10 */ - clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, - CCM_DE2_CTRL_PLL10); - - /* Set ahb gating to pass */ - setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); - setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE); - - /* Clock on */ - setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE); -} - -static void sunxi_de2_mode_set(ulong de_mux_base, int mux, +static void sunxi_de2_mode_set(ulong de_mux_base, const struct display_timing *mode, int bpp, ulong address, bool is_composite) { - struct de_clk * const de_clk_regs = - (struct de_clk *)(SUNXI_DE2_BASE); struct de_glb * const de_glb_regs = (struct de_glb *)(de_mux_base + SUNXI_DE2_MUX_GLB_REGS); @@ -87,17 +58,6 @@ static void sunxi_de2_mode_set(ulong de_mux_base, int mux, int channel; u32 format;

- /* enable clock */ -#ifdef CONFIG_MACH_SUN8I_H3 - setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4); -#else - setbits_le32(&de_clk_regs->rst_cfg, BIT(mux)); -#endif - setbits_le32(&de_clk_regs->gate_cfg, BIT(mux)); - setbits_le32(&de_clk_regs->bus_cfg, BIT(mux)); - - clrbits_le32(&de_clk_regs->sel_cfg, 1); - writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl); writel(0, &de_glb_regs->status); writel(1, &de_glb_regs->dbuff); @@ -189,6 +149,8 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct display_timing timing; struct display_plat *disp_uc_plat; + struct reset_ctl_bulk resets; + struct clk_bulk clocks; int ret;

disp_uc_plat = dev_get_uclass_plat(disp); @@ -206,8 +168,23 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, return ret; }

- sunxi_de2_composer_init(); - sunxi_de2_mode_set((ulong)dev_read_addr(dev), mux, &timing, + ret = reset_get_bulk(dev, &resets); + if (ret) + return ret; + + ret = clk_get_bulk(dev, &clocks); + if (ret) + return ret; + + ret = clk_enable_bulk(&clocks); + if (ret) + return ret; + + ret = reset_deassert_bulk(&resets); + if (ret) + return ret; + + sunxi_de2_mode_set((ulong)dev_read_addr(dev), &timing, 1 << l2bpp, fbbase, is_composite);

ret = display_enable(disp, 1 << l2bpp, &timing);

Currently PHY init callback has only pixel clock as a parameter, but other timing parameters may be needed for custom PHYs. Modify callback signature to include full timings.

Cc: Neil Armstrong narmstrong@baylibre.com Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/video/dw_hdmi.c | 6 +++--- drivers/video/meson/meson_dw_hdmi.c | 5 +++-- drivers/video/sunxi/sunxi_dw_hdmi.c | 7 ++++--- include/dw_hdmi.h | 4 ++-- 4 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c index c4fbb1829446..8d71f713f99f 100644 --- a/drivers/video/dw_hdmi.c +++ b/drivers/video/dw_hdmi.c @@ -901,7 +901,7 @@ static const u8 pre_buf[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9, };

-int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, const struct display_timing *edid) { int i, ret;

@@ -912,7 +912,7 @@ int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) hdmi_phy_enable_tmds(hdmi, 0); hdmi_phy_enable_power(hdmi, 0);

- ret = hdmi_phy_configure(hdmi, mpixelclock); + ret = hdmi_phy_configure(hdmi, edid->pixelclock.typ); if (ret) { debug("hdmi phy config failure %d\n", ret); return ret; @@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid)

hdmi_av_composer(hdmi, edid);

- ret = hdmi->phy_set(hdmi, edid->pixelclock.typ); + ret = hdmi->phy_set(hdmi, edid); if (ret) return ret;

diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c index e5f281320534..7558814b3491 100644 --- a/drivers/video/meson/meson_dw_hdmi.c +++ b/drivers/video/meson/meson_dw_hdmi.c @@ -292,7 +292,8 @@ static void meson_dw_hdmi_phy_setup_mode(struct meson_dw_hdmi *priv, } }

-static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock) +static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, + const struct display_timing *edid) { struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi, hdmi); @@ -322,7 +323,7 @@ static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock) dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);

/* Setup PHY parameters */ - meson_dw_hdmi_phy_setup_mode(priv, pixel_clock); + meson_dw_hdmi_phy_setup_mode(priv, edid->pixelclock.typ);

/* Setup PHY */ dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 0744954fa15f..483d57293155 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -266,12 +266,13 @@ static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid, lcdc_enable(lcdc, bpp); }

-static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) +static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, + const struct display_timing *edid) { int phy_div;

- sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div); - sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div); + sunxi_dw_hdmi_pll_set(edid->pixelclock.typ / 1000, &phy_div); + sunxi_dw_hdmi_phy_set(hdmi, edid->pixelclock.typ, phy_div);

return 0; } diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h index 8acae3839fb3..46b87916b8bb 100644 --- a/include/dw_hdmi.h +++ b/include/dw_hdmi.h @@ -544,12 +544,12 @@ struct dw_hdmi { struct hdmi_data_info hdmi_data; struct udevice *ddc_bus;

- int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); + int (*phy_set)(struct dw_hdmi *hdmi, const struct display_timing *edid); void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset); u8 (*read_reg)(struct dw_hdmi *hdmi, int offset); };

-int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock); +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, const struct display_timing *edid); int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi); void dw_hdmi_phy_init(struct dw_hdmi *hdmi);

Remove direct PHY managing from dw-hdmi platform driver and use dedicated driver instead. While at it, enable clocks and deassert reset lines through clk and reset framework instead of manually configuring bits.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net --- drivers/video/sunxi/sunxi_dw_hdmi.c | 225 +++++----------------------- 1 file changed, 36 insertions(+), 189 deletions(-)

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 483d57293155..16051baca8c5 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -5,190 +5,26 @@ * (C) Copyright 2017 Jernej Skrabec jernej.skrabec@siol.net */

+#include <clk.h> #include <common.h> #include <display.h> #include <dm.h> #include <dw_hdmi.h> #include <edid.h> -#include <log.h> -#include <time.h> +#include <generic-phy.h> +#include <reset.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/lcdc.h> #include <linux/bitops.h> -#include <linux/delay.h> +#include "sunxi_dw_hdmi_phy.h"

struct sunxi_dw_hdmi_priv { struct dw_hdmi hdmi; int mux; + struct phy phy; };

-struct sunxi_hdmi_phy { - u32 pol; - u32 res1[3]; - u32 read_en; - u32 unscramble; - u32 res2[2]; - u32 ctrl; - u32 unk1; - u32 unk2; - u32 pll; - u32 clk; - u32 unk3; - u32 status; -}; - -#define HDMI_PHY_OFFS 0x10000 - -static int sunxi_dw_hdmi_get_divider(uint clock) -{ - /* - * Due to missing documentaion of HDMI PHY, we know correct - * settings only for following four PHY dividers. Select one - * based on clock speed. - */ - if (clock <= 27000000) - return 11; - else if (clock <= 74250000) - return 4; - else if (clock <= 148500000) - return 2; - else - return 1; -} - -static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi) -{ - struct sunxi_hdmi_phy * const phy = - (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS); - unsigned long tmo; - u32 tmp; - - /* - * HDMI PHY settings are taken as-is from Allwinner BSP code. - * There is no documentation. - */ - writel(0, &phy->ctrl); - setbits_le32(&phy->ctrl, BIT(0)); - udelay(5); - setbits_le32(&phy->ctrl, BIT(16)); - setbits_le32(&phy->ctrl, BIT(1)); - udelay(10); - setbits_le32(&phy->ctrl, BIT(2)); - udelay(5); - setbits_le32(&phy->ctrl, BIT(3)); - udelay(40); - setbits_le32(&phy->ctrl, BIT(19)); - udelay(100); - setbits_le32(&phy->ctrl, BIT(18)); - setbits_le32(&phy->ctrl, 7 << 4); - - /* Note that Allwinner code doesn't fail in case of timeout */ - tmo = timer_get_us() + 2000; - while ((readl(&phy->status) & 0x80) == 0) { - if (timer_get_us() > tmo) { - printf("Warning: HDMI PHY init timeout!\n"); - break; - } - } - - setbits_le32(&phy->ctrl, 0xf << 8); - setbits_le32(&phy->ctrl, BIT(7)); - - writel(0x39dc5040, &phy->pll); - writel(0x80084343, &phy->clk); - udelay(10000); - writel(1, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - udelay(100000); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - setbits_le32(&phy->pll, tmp); - writel(0x01FF0F7F, &phy->ctrl); - writel(0x80639000, &phy->unk1); - writel(0x0F81C405, &phy->unk2); - - /* enable read access to HDMI controller */ - writel(0x54524545, &phy->read_en); - /* descramble register offsets */ - writel(0x42494E47, &phy->unscramble); -} - -static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div) -{ - struct sunxi_hdmi_phy * const phy = - (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS); - int div = sunxi_dw_hdmi_get_divider(clock); - u32 tmp; - - /* - * Unfortunately, we don't know much about those magic - * numbers. They are taken from Allwinner BSP driver. - */ - switch (div) { - case 1: - writel(0x30dc5fc0, &phy->pll); - writel(0x800863C0 | (phy_div - 1), &phy->clk); - mdelay(10); - writel(0x00000001, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - mdelay(200); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - if (tmp < 0x3d) - setbits_le32(&phy->pll, tmp + 2); - else - setbits_le32(&phy->pll, 0x3f); - mdelay(100); - writel(0x01FFFF7F, &phy->ctrl); - writel(0x8063b000, &phy->unk1); - writel(0x0F8246B5, &phy->unk2); - break; - case 2: - writel(0x39dc5040, &phy->pll); - writel(0x80084380 | (phy_div - 1), &phy->clk); - mdelay(10); - writel(0x00000001, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - mdelay(100); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - setbits_le32(&phy->pll, tmp); - writel(0x01FFFF7F, &phy->ctrl); - writel(0x8063a800, &phy->unk1); - writel(0x0F81C485, &phy->unk2); - break; - case 4: - writel(0x39dc5040, &phy->pll); - writel(0x80084340 | (phy_div - 1), &phy->clk); - mdelay(10); - writel(0x00000001, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - mdelay(100); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - setbits_le32(&phy->pll, tmp); - writel(0x01FFFF7F, &phy->ctrl); - writel(0x8063b000, &phy->unk1); - writel(0x0F81C405, &phy->unk2); - break; - case 11: - writel(0x39dc5040, &phy->pll); - writel(0x80084300 | (phy_div - 1), &phy->clk); - mdelay(10); - writel(0x00000001, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - mdelay(100); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - setbits_le32(&phy->pll, tmp); - writel(0x01FFFF7F, &phy->ctrl); - writel(0x8063b000, &phy->unk1); - writel(0x0F81C405, &phy->unk2); - break; - } -} - static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div) { int value, n, m, div, diff; @@ -269,10 +105,12 @@ static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid, static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, const struct display_timing *edid) { + struct sunxi_dw_hdmi_priv *priv = + container_of(hdmi, struct sunxi_dw_hdmi_priv, hdmi); int phy_div;

sunxi_dw_hdmi_pll_set(edid->pixelclock.typ / 1000, &phy_div); - sunxi_dw_hdmi_phy_set(hdmi, edid->pixelclock.typ, phy_div); + sunxi_dw_hdmi_phy_set(&priv->phy, edid, phy_div);

return 0; } @@ -294,8 +132,6 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, const struct display_timing *edid) { struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); - struct sunxi_hdmi_phy * const phy = - (struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS); int ret;

ret = dw_hdmi_enable(&priv->hdmi, edid); @@ -304,21 +140,13 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,

sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);

- if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW) - setbits_le32(&phy->pol, 0x200); - - if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW) - setbits_le32(&phy->pol, 0x100); - - setbits_le32(&phy->ctrl, 0xf << 12); - /* * This is last hdmi access before boot, so scramble addresses * again or othwerwise BSP driver won't work. Dummy read is * needed or otherwise last write doesn't get written correctly. */ (void)readb(priv->hdmi.ioaddr); - writel(0, &phy->unscramble); + generic_phy_exit(&priv->phy);

return 0; } @@ -343,8 +171,14 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct reset_ctl_bulk resets; + struct clk_bulk clocks; int ret;

+ ret = generic_phy_get_by_name(dev, "phy", &priv->phy); + if (ret) + return ret; + /* Set pll3 to 297 MHz */ clock_set_pll3(297000000);

@@ -352,19 +186,32 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK, CCM_HDMI_CTRL_PLL3);

- /* Set ahb gating to pass */ - setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); - setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2); - setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); - setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE); + ret = generic_phy_init(&priv->phy); + if (ret) + return ret;

- /* Clock on */ - setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); + ret = reset_get_bulk(dev, &resets); + if (ret) + return ret;

- sunxi_dw_hdmi_phy_init(&priv->hdmi); + ret = clk_get_bulk(dev, &clocks); + if (ret) + return ret; + + ret = clk_enable_bulk(&clocks); + if (ret) + return ret; + + ret = reset_deassert_bulk(&resets); + if (ret) + return ret;

priv->mux = uc_plat->source_id;

+ ret = generic_phy_power_on(&priv->phy); + if (ret) + return ret; + ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi); if (ret < 0) { debug("hdmi can not get hpd signal\n");