[U-Boot] [PATCH 0/5] zynq: Fun with board and CPU info display
This series aims at adding support for CPU information display. While here, following suggestions from Michal, the FPGA initialization is cleaned up.
Ezequiel Garcia (5): zynq: Define macros for the device names zynq: Rework FPGA initialization zynq: Support CPU info display zynq: board: Remove checkboard configs: zynq: Enable DISPLAY_CPUINFO
arch/arm/mach-zynq/cpu.c | 87 ++++++++++++++++++++++++++++- arch/arm/mach-zynq/include/mach/sys_proto.h | 3 + board/xilinx/zynq/board.c | 76 +------------------------ configs/syzygy_hub_defconfig | 1 - configs/topic_miami_defconfig | 1 - configs/topic_miamilite_defconfig | 1 - configs/topic_miamiplus_defconfig | 1 - configs/zynq_cc108_defconfig | 1 - configs/zynq_cse_qspi_defconfig | 1 - configs/zynq_microzed_defconfig | 1 - configs/zynq_picozed_defconfig | 1 - configs/zynq_z_turn_defconfig | 1 - configs/zynq_zc702_defconfig | 1 - configs/zynq_zc706_defconfig | 1 - configs/zynq_zc770_xm010_defconfig | 1 - configs/zynq_zc770_xm011_defconfig | 1 - configs/zynq_zc770_xm012_defconfig | 1 - configs/zynq_zc770_xm013_defconfig | 1 - configs/zynq_zed_defconfig | 1 - configs/zynq_zybo_defconfig | 1 - include/zynqpl.h | 32 +++++++---- 21 files changed, 112 insertions(+), 103 deletions(-)
This will allow to reuse the macros when showing the CPU info.
Signed-off-by: Ezequiel Garcia ezequiel@vanguardiasur.com.ar --- include/zynqpl.h | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/include/zynqpl.h b/include/zynqpl.h index 5a34a17daefe..e10a266643bd 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -42,45 +42,57 @@ extern struct xilinx_fpga_op zynq_op; #define XILINX_XC7Z045_SIZE 106571232/8 #define XILINX_XC7Z100_SIZE 139330784/8
+/* Device Names */ +#define XILINX_XC7Z007S_NAME "7z007s" +#define XILINX_XC7Z010_NAME "7z010" +#define XILINX_XC7Z012S_NAME "7z012s" +#define XILINX_XC7Z014S_NAME "7z014s" +#define XILINX_XC7Z015_NAME "7z015" +#define XILINX_XC7Z020_NAME "7z020" +#define XILINX_XC7Z030_NAME "7z030" +#define XILINX_XC7Z035_NAME "7z035" +#define XILINX_XC7Z045_NAME "7z045" +#define XILINX_XC7Z100_NAME "7z100" + /* Descriptor Macros */ #define XILINX_XC7Z007S_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z007s" } + XILINX_XC7Z007S_NAME }
#define XILINX_XC7Z010_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z010" } + XILINX_XC7Z010_NAME }
#define XILINX_XC7Z012S_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z012s" } + XILINX_XC7Z012S_NAME }
#define XILINX_XC7Z014S_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z014s" } + XILINX_XC7Z014S_NAME }
#define XILINX_XC7Z015_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z015" } + XILINX_XC7Z015_NAME }
#define XILINX_XC7Z020_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z020" } + XILINX_XC7Z020_NAME }
#define XILINX_XC7Z030_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z030" } + XILINX_XC7Z030_NAME }
#define XILINX_XC7Z035_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z035" } + XILINX_XC7Z035_NAME }
#define XILINX_XC7Z045_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z045" } + XILINX_XC7Z045_NAME }
#define XILINX_XC7Z100_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z100" } + XILINX_XC7Z100_NAME }
#endif /* _ZYNQPL_H_ */
This commit moves the FPGA descriptor definition to mach-zynq, where it makes more sense.
Also, the implementation is reworked to be cleaner and a bit smaller.
add/remove: 2/11 grow/shrink: 0/1 up/down: 420/-608 (-188) function old new delta zynq_fpga_descs - 352 +352 zynq_fpga_desc - 68 +68 fpga100 28 - -28 fpga045 28 - -28 fpga035 28 - -28 fpga030 28 - -28 fpga020 28 - -28 fpga015 28 - -28 fpga014s 28 - -28 fpga012s 28 - -28 fpga010 28 - -28 fpga007s 28 - -28 fpga 28 - -28 board_init 332 32 -300 Total: Before=574182, After=573994, chg -0.03%
Signed-off-by: Ariel D'Alessandro ariel@vanguardiasur.com.ar Signed-off-by: Ezequiel Garcia ezequiel@vanguardiasur.com.ar --- arch/arm/mach-zynq/cpu.c | 41 +++++++++++++++++++- arch/arm/mach-zynq/include/mach/sys_proto.h | 3 ++ board/xilinx/zynq/board.c | 59 +---------------------------- 3 files changed, 44 insertions(+), 59 deletions(-)
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index ee1c1a943b66..53a07b0059c2 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -5,14 +5,36 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <zynqpl.h> #include <asm/io.h> #include <asm/arch/clk.h> -#include <asm/arch/sys_proto.h> #include <asm/arch/hardware.h> +#include <asm/arch/ps7_init_gpl.h> +#include <asm/arch/sys_proto.h>
#define ZYNQ_SILICON_VER_MASK 0xF0000000 #define ZYNQ_SILICON_VER_SHIFT 28
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static const struct { + u8 idcode; + xilinx_desc desc; +} zynq_fpga_descs[] = { + { .idcode = XILINX_ZYNQ_7007S, .desc = XILINX_XC7Z007S_DESC(0x07) }, + { .idcode = XILINX_ZYNQ_7010, .desc = XILINX_XC7Z010_DESC(0x10) }, + { .idcode = XILINX_ZYNQ_7012S, .desc = XILINX_XC7Z012S_DESC(0x12) }, + { .idcode = XILINX_ZYNQ_7014S, .desc = XILINX_XC7Z014S_DESC(0x14) }, + { .idcode = XILINX_ZYNQ_7015, .desc = XILINX_XC7Z015_DESC(0x15) }, + { .idcode = XILINX_ZYNQ_7020, .desc = XILINX_XC7Z020_DESC(0x20) }, + { .idcode = XILINX_ZYNQ_7030, .desc = XILINX_XC7Z030_DESC(0x30) }, + { .idcode = XILINX_ZYNQ_7035, .desc = XILINX_XC7Z035_DESC(0x35) }, + { .idcode = XILINX_ZYNQ_7045, .desc = XILINX_XC7Z045_DESC(0x45) }, + { .idcode = XILINX_ZYNQ_7100, .desc = XILINX_XC7Z100_DESC(0x100) }, + { /* Sentinel */ }, +}; +#endif + int arch_cpu_init(void) { zynq_slcr_unlock(); @@ -60,3 +82,20 @@ void enable_caches(void) dcache_enable(); } #endif + +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) +const xilinx_desc *zynq_fpga_desc(void) +{ + u32 idcode; + u8 i; + + idcode = zynq_slcr_get_idcode(); + for (i = 0; zynq_fpga_descs[i].idcode; i++) { + if (zynq_fpga_descs[i].idcode == idcode) { + return &zynq_fpga_descs[i].desc; + } + } + return NULL; +} +#endif diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h index af61352dd110..fd5744c4e85e 100644 --- a/arch/arm/mach-zynq/include/mach/sys_proto.h +++ b/arch/arm/mach-zynq/include/mach/sys_proto.h @@ -7,6 +7,8 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_
+#include <xilinx.h> + extern void zynq_slcr_lock(void); extern void zynq_slcr_unlock(void); extern void zynq_slcr_cpu_reset(void); @@ -16,6 +18,7 @@ extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); extern int zynq_slcr_get_mio_pin_status(const char *periph); extern void zynq_ddrc_init(void); +extern const xilinx_desc *zynq_fpga_desc(void); extern unsigned int zynq_get_silicon_version(void);
int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index e59038106aa6..f9e7bca4ee40 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -15,69 +15,12 @@
DECLARE_GLOBAL_DATA_PTR;
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) -static xilinx_desc fpga; - -/* It can be done differently */ -static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7); -static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); -static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12); -static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14); -static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); -static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); -static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); -static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35); -static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); -static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); -#endif - int board_init(void) { -#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) - u32 idcode; - - idcode = zynq_slcr_get_idcode(); - - switch (idcode) { - case XILINX_ZYNQ_7007S: - fpga = fpga007s; - break; - case XILINX_ZYNQ_7010: - fpga = fpga010; - break; - case XILINX_ZYNQ_7012S: - fpga = fpga012s; - break; - case XILINX_ZYNQ_7014S: - fpga = fpga014s; - break; - case XILINX_ZYNQ_7015: - fpga = fpga015; - break; - case XILINX_ZYNQ_7020: - fpga = fpga020; - break; - case XILINX_ZYNQ_7030: - fpga = fpga030; - break; - case XILINX_ZYNQ_7035: - fpga = fpga035; - break; - case XILINX_ZYNQ_7045: - fpga = fpga045; - break; - case XILINX_ZYNQ_7100: - fpga = fpga100; - break; - } -#endif - #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); - fpga_add(fpga_xilinx, &fpga); + fpga_add(fpga_xilinx, (void *)zynq_fpga_desc()); #endif
return 0;
This commit adds CPU and silicon version information consuming the SLCR IDCODE and DEVCFG MCTRL registers, respectively.
Signed-off-by: Ariel D'Alessandro ariel@vanguardiasur.com.ar Signed-off-by: Ezequiel Garcia ezequiel@vanguardiasur.com.ar --- arch/arm/mach-zynq/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 53a07b0059c2..602f483c162b 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -35,6 +35,25 @@ static const struct { }; #endif
+#ifdef CONFIG_DISPLAY_CPUINFO +static const struct { + u8 idcode; + const char *cpuinfo; +} zynq_cpu_info[] = { + { .idcode = XILINX_ZYNQ_7007S, .cpuinfo = XILINX_XC7Z007S_NAME }, + { .idcode = XILINX_ZYNQ_7010, .cpuinfo = XILINX_XC7Z010_NAME }, + { .idcode = XILINX_ZYNQ_7012S, .cpuinfo = XILINX_XC7Z012S_NAME }, + { .idcode = XILINX_ZYNQ_7014S, .cpuinfo = XILINX_XC7Z014S_NAME }, + { .idcode = XILINX_ZYNQ_7015, .cpuinfo = XILINX_XC7Z015_NAME }, + { .idcode = XILINX_ZYNQ_7020, .cpuinfo = XILINX_XC7Z020_NAME }, + { .idcode = XILINX_ZYNQ_7030, .cpuinfo = XILINX_XC7Z030_NAME }, + { .idcode = XILINX_ZYNQ_7035, .cpuinfo = XILINX_XC7Z035_NAME }, + { .idcode = XILINX_ZYNQ_7045, .cpuinfo = XILINX_XC7Z045_NAME }, + { .idcode = XILINX_ZYNQ_7100, .cpuinfo = XILINX_XC7Z100_NAME }, + { /* Sentinel */ }, +}; +#endif + int arch_cpu_init(void) { zynq_slcr_unlock(); @@ -99,3 +118,30 @@ const xilinx_desc *zynq_fpga_desc(void) return NULL; } #endif + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + u32 idcode, version; + bool found; + u8 i; + + idcode = zynq_slcr_get_idcode(); + found = false; + for (i = 0; zynq_cpu_info[i].idcode; i++) { + if (zynq_cpu_info[i].idcode == idcode) { + found = true; + break; + } + } + + version = zynq_get_silicon_version() << 1; + if (version > (PCW_SILICON_VERSION_3 << 1)) + version += 1; + if (found) { + printf("CPU: Zynq %s\n", zynq_cpu_info[i].cpuinfo); + printf("Silicon: v%d.%d\n", version >> 1, version & 1); + } + return 0; +} +#endif
Hi,
On 17.1.2018 14:56, Ezequiel Garcia wrote:
This commit adds CPU and silicon version information consuming the SLCR IDCODE and DEVCFG MCTRL registers, respectively.
Signed-off-by: Ariel D'Alessandro ariel@vanguardiasur.com.ar Signed-off-by: Ezequiel Garcia ezequiel@vanguardiasur.com.ar
arch/arm/mach-zynq/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 53a07b0059c2..602f483c162b 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -35,6 +35,25 @@ static const struct { }; #endif
+#ifdef CONFIG_DISPLAY_CPUINFO +static const struct {
- u8 idcode;
- const char *cpuinfo;
+} zynq_cpu_info[] = {
- { .idcode = XILINX_ZYNQ_7007S, .cpuinfo = XILINX_XC7Z007S_NAME },
- { .idcode = XILINX_ZYNQ_7010, .cpuinfo = XILINX_XC7Z010_NAME },
- { .idcode = XILINX_ZYNQ_7012S, .cpuinfo = XILINX_XC7Z012S_NAME },
- { .idcode = XILINX_ZYNQ_7014S, .cpuinfo = XILINX_XC7Z014S_NAME },
- { .idcode = XILINX_ZYNQ_7015, .cpuinfo = XILINX_XC7Z015_NAME },
- { .idcode = XILINX_ZYNQ_7020, .cpuinfo = XILINX_XC7Z020_NAME },
- { .idcode = XILINX_ZYNQ_7030, .cpuinfo = XILINX_XC7Z030_NAME },
- { .idcode = XILINX_ZYNQ_7035, .cpuinfo = XILINX_XC7Z035_NAME },
- { .idcode = XILINX_ZYNQ_7045, .cpuinfo = XILINX_XC7Z045_NAME },
- { .idcode = XILINX_ZYNQ_7100, .cpuinfo = XILINX_XC7Z100_NAME },
- { /* Sentinel */ },
This table pretty much reflect what it is in 2/5.
static const struct { u8 idcode; const char *cpuinfo; /* or better name devicename */ u32 fpga_size; } zynq_cpu_info[] = {
From xilinx_desc I think size is unused but we can keep in filled and
cookie is also not used and can be 0. The rest of data for xilinx_desc is static anyway.
It means doing this properly will be the best to fill that xilinx_desc and also it doesn't make sense to call zynq_slcr_get_idcode() twice. It should be enough to detect chip once and fill pointer to actual configuration. And then when fpga should be add then use them. The same for cpuinfo. Link is already setup and you can just use it.
Thanks, Michal
On 26 January 2018 at 09:33, Michal Simek michal.simek@xilinx.com wrote:
Hi,
On 17.1.2018 14:56, Ezequiel Garcia wrote:
This commit adds CPU and silicon version information consuming the SLCR IDCODE and DEVCFG MCTRL registers, respectively.
Signed-off-by: Ariel D'Alessandro ariel@vanguardiasur.com.ar Signed-off-by: Ezequiel Garcia ezequiel@vanguardiasur.com.ar
arch/arm/mach-zynq/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 53a07b0059c2..602f483c162b 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -35,6 +35,25 @@ static const struct { }; #endif
+#ifdef CONFIG_DISPLAY_CPUINFO +static const struct {
u8 idcode;const char *cpuinfo;+} zynq_cpu_info[] = {
{ .idcode = XILINX_ZYNQ_7007S, .cpuinfo = XILINX_XC7Z007S_NAME },{ .idcode = XILINX_ZYNQ_7010, .cpuinfo = XILINX_XC7Z010_NAME },{ .idcode = XILINX_ZYNQ_7012S, .cpuinfo = XILINX_XC7Z012S_NAME },{ .idcode = XILINX_ZYNQ_7014S, .cpuinfo = XILINX_XC7Z014S_NAME },{ .idcode = XILINX_ZYNQ_7015, .cpuinfo = XILINX_XC7Z015_NAME },{ .idcode = XILINX_ZYNQ_7020, .cpuinfo = XILINX_XC7Z020_NAME },{ .idcode = XILINX_ZYNQ_7030, .cpuinfo = XILINX_XC7Z030_NAME },{ .idcode = XILINX_ZYNQ_7035, .cpuinfo = XILINX_XC7Z035_NAME },{ .idcode = XILINX_ZYNQ_7045, .cpuinfo = XILINX_XC7Z045_NAME },{ .idcode = XILINX_ZYNQ_7100, .cpuinfo = XILINX_XC7Z100_NAME },{ /* Sentinel */ },This table pretty much reflect what it is in 2/5.
static const struct { u8 idcode; const char *cpuinfo; /* or better name devicename */ u32 fpga_size; } zynq_cpu_info[] = {
From xilinx_desc I think size is unused but we can keep in filled and cookie is also not used and can be 0. The rest of data for xilinx_desc is static anyway.
It means doing this properly will be the best to fill that xilinx_desc and also it doesn't make sense to call zynq_slcr_get_idcode() twice. It should be enough to detect chip once and fill pointer to actual configuration. And then when fpga should be add then use them. The same for cpuinfo. Link is already setup and you can just use it.
So you propose to have just one table instead of two zynq_cpu_info and zynq_fpga_descs ?
I guess that'll work and might result in simpler code. On the other side, the reason I kept them separate is because each of them are compiled-in via different compile-time options.
Having a single table will mean playing nasty ifdef games, which usually mean trouble.
Regarding calling zynq_slcr_get_idcode twice, is it really that bad?
On 31.1.2018 22:25, Ezequiel Garcia wrote:
On 26 January 2018 at 09:33, Michal Simek michal.simek@xilinx.com wrote:
Hi,
On 17.1.2018 14:56, Ezequiel Garcia wrote:
This commit adds CPU and silicon version information consuming the SLCR IDCODE and DEVCFG MCTRL registers, respectively.
Signed-off-by: Ariel D'Alessandro ariel@vanguardiasur.com.ar Signed-off-by: Ezequiel Garcia ezequiel@vanguardiasur.com.ar
arch/arm/mach-zynq/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 53a07b0059c2..602f483c162b 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -35,6 +35,25 @@ static const struct { }; #endif
+#ifdef CONFIG_DISPLAY_CPUINFO +static const struct {
u8 idcode;const char *cpuinfo;+} zynq_cpu_info[] = {
{ .idcode = XILINX_ZYNQ_7007S, .cpuinfo = XILINX_XC7Z007S_NAME },{ .idcode = XILINX_ZYNQ_7010, .cpuinfo = XILINX_XC7Z010_NAME },{ .idcode = XILINX_ZYNQ_7012S, .cpuinfo = XILINX_XC7Z012S_NAME },{ .idcode = XILINX_ZYNQ_7014S, .cpuinfo = XILINX_XC7Z014S_NAME },{ .idcode = XILINX_ZYNQ_7015, .cpuinfo = XILINX_XC7Z015_NAME },{ .idcode = XILINX_ZYNQ_7020, .cpuinfo = XILINX_XC7Z020_NAME },{ .idcode = XILINX_ZYNQ_7030, .cpuinfo = XILINX_XC7Z030_NAME },{ .idcode = XILINX_ZYNQ_7035, .cpuinfo = XILINX_XC7Z035_NAME },{ .idcode = XILINX_ZYNQ_7045, .cpuinfo = XILINX_XC7Z045_NAME },{ .idcode = XILINX_ZYNQ_7100, .cpuinfo = XILINX_XC7Z100_NAME },{ /* Sentinel */ },This table pretty much reflect what it is in 2/5.
static const struct { u8 idcode; const char *cpuinfo; /* or better name devicename */ u32 fpga_size; } zynq_cpu_info[] = {
From xilinx_desc I think size is unused but we can keep in filled and cookie is also not used and can be 0. The rest of data for xilinx_desc is static anyway.
It means doing this properly will be the best to fill that xilinx_desc and also it doesn't make sense to call zynq_slcr_get_idcode() twice. It should be enough to detect chip once and fill pointer to actual configuration. And then when fpga should be add then use them. The same for cpuinfo. Link is already setup and you can just use it.
So you propose to have just one table instead of two zynq_cpu_info and zynq_fpga_descs ?
I was playing with it last Friday and I have sent that 2 patches as RFC.
I guess that'll work and might result in simpler code. On the other side, the reason I kept them separate is because each of them are compiled-in via different compile-time options.
Having a single table will mean playing nasty ifdef games, which usually mean trouble.
Regarding calling zynq_slcr_get_idcode twice, is it really that bad?
It is not that bad. It is probably better than having global variable.
Take a look at that RFC. Buildman is also showing pretty nice size reduction but there are still some pieces which can be done better. It is based on your code that's why fell free to rework it.
Thanks, Michal
On 1 February 2018 at 05:26, Michal Simek michal.simek@xilinx.com wrote:
On 31.1.2018 22:25, Ezequiel Garcia wrote:
On 26 January 2018 at 09:33, Michal Simek michal.simek@xilinx.com wrote:
Hi,
On 17.1.2018 14:56, Ezequiel Garcia wrote:
This commit adds CPU and silicon version information consuming the SLCR IDCODE and DEVCFG MCTRL registers, respectively.
Signed-off-by: Ariel D'Alessandro ariel@vanguardiasur.com.ar Signed-off-by: Ezequiel Garcia ezequiel@vanguardiasur.com.ar
arch/arm/mach-zynq/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 53a07b0059c2..602f483c162b 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -35,6 +35,25 @@ static const struct { }; #endif
+#ifdef CONFIG_DISPLAY_CPUINFO +static const struct {
u8 idcode;const char *cpuinfo;+} zynq_cpu_info[] = {
{ .idcode = XILINX_ZYNQ_7007S, .cpuinfo = XILINX_XC7Z007S_NAME },{ .idcode = XILINX_ZYNQ_7010, .cpuinfo = XILINX_XC7Z010_NAME },{ .idcode = XILINX_ZYNQ_7012S, .cpuinfo = XILINX_XC7Z012S_NAME },{ .idcode = XILINX_ZYNQ_7014S, .cpuinfo = XILINX_XC7Z014S_NAME },{ .idcode = XILINX_ZYNQ_7015, .cpuinfo = XILINX_XC7Z015_NAME },{ .idcode = XILINX_ZYNQ_7020, .cpuinfo = XILINX_XC7Z020_NAME },{ .idcode = XILINX_ZYNQ_7030, .cpuinfo = XILINX_XC7Z030_NAME },{ .idcode = XILINX_ZYNQ_7035, .cpuinfo = XILINX_XC7Z035_NAME },{ .idcode = XILINX_ZYNQ_7045, .cpuinfo = XILINX_XC7Z045_NAME },{ .idcode = XILINX_ZYNQ_7100, .cpuinfo = XILINX_XC7Z100_NAME },{ /* Sentinel */ },This table pretty much reflect what it is in 2/5.
static const struct { u8 idcode; const char *cpuinfo; /* or better name devicename */ u32 fpga_size; } zynq_cpu_info[] = {
From xilinx_desc I think size is unused but we can keep in filled and cookie is also not used and can be 0. The rest of data for xilinx_desc is static anyway.
It means doing this properly will be the best to fill that xilinx_desc and also it doesn't make sense to call zynq_slcr_get_idcode() twice. It should be enough to detect chip once and fill pointer to actual configuration. And then when fpga should be add then use them. The same for cpuinfo. Link is already setup and you can just use it.
So you propose to have just one table instead of two zynq_cpu_info and zynq_fpga_descs ?
I was playing with it last Friday and I have sent that 2 patches as RFC.
I see.
I guess that'll work and might result in simpler code. On the other side, the reason I kept them separate is because each of them are compiled-in via different compile-time options.
Having a single table will mean playing nasty ifdef games, which usually mean trouble.
Regarding calling zynq_slcr_get_idcode twice, is it really that bad?
It is not that bad. It is probably better than having global variable.
Take a look at that RFC. Buildman is also showing pretty nice size reduction but there are still some pieces which can be done better. It is based on your code that's why fell free to rework it.
Indeed, it doesn't look bad at all. Let me try those patches, see how they work.
Now that showing silicon version is part of the CPU info display, let's remove checkboard().
Note that the generic show_board_info() will still show the DT 'model' property. For instance:
U-Boot 2018.01-00172-g5e296ab7317a (Jan 17 2018 - 09:57:36 -0300)
CPU: Zynq 7z010 Silicon: v3.1 Model: Bitmain Antminer S9 Board
Signed-off-by: Ezequiel Garcia ezequiel@vanguardiasur.com.ar --- board/xilinx/zynq/board.c | 17 ----------------- 1 file changed, 17 deletions(-)
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index f9e7bca4ee40..2374da68328f 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -11,7 +11,6 @@ #include <zynqpl.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> -#include <asm/arch/ps7_init_gpl.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -52,22 +51,6 @@ int board_late_init(void) return 0; }
-#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - u32 version = zynq_get_silicon_version(); - - version <<= 1; - if (version > (PCW_SILICON_VERSION_3 << 1)) - version += 1; - - puts("Board: Xilinx Zynq\n"); - printf("Silicon: v%d.%d\n", version >> 1, version & 1); - - return 0; -} -#endif - int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) { #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
Now that silicon version has been moved from checkboard() to print_cpuinfo(), we need to enable DISPLAY_CPUINFO option.
Signed-off-by: Ezequiel Garcia ezequiel@vanguardiasur.com.ar --- configs/syzygy_hub_defconfig | 1 - configs/topic_miami_defconfig | 1 - configs/topic_miamilite_defconfig | 1 - configs/topic_miamiplus_defconfig | 1 - configs/zynq_cc108_defconfig | 1 - configs/zynq_cse_qspi_defconfig | 1 - configs/zynq_microzed_defconfig | 1 - configs/zynq_picozed_defconfig | 1 - configs/zynq_z_turn_defconfig | 1 - configs/zynq_zc702_defconfig | 1 - configs/zynq_zc706_defconfig | 1 - configs/zynq_zc770_xm010_defconfig | 1 - configs/zynq_zc770_xm011_defconfig | 1 - configs/zynq_zc770_xm012_defconfig | 1 - configs/zynq_zc770_xm013_defconfig | 1 - configs/zynq_zed_defconfig | 1 - configs/zynq_zybo_defconfig | 1 - 17 files changed, 17 deletions(-)
diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index 8bdc4be67d70..b4a41b484885 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index aabd705da0fb..866c91276d95 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -8,7 +8,6 @@ CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt" CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami" CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=0 -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index 7228283b3c6b..1cae54c2da5e 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -8,7 +8,6 @@ CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt" CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite" CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=0 -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index d511a942838b..13f69eb4b1ca 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -8,7 +8,6 @@ CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt" CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus" CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=0 -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig index bdba0d1cc9ba..31d5dda12b06 100644 --- a/configs/zynq_cc108_defconfig +++ b/configs/zynq_cc108_defconfig @@ -7,7 +7,6 @@ CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 9659faefbf33..f5201a72d6be 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -8,7 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single" CONFIG_DEBUG_UART=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTDELAY=-1 -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index fc21eb8f67a3..fbce9631f893 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -6,7 +6,6 @@ CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index f36e7bd849f4..e58b90b710ca 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig index c727b2acbf28..d4934c8d1673 100644 --- a/configs/zynq_z_turn_defconfig +++ b/configs/zynq_z_turn_defconfig @@ -7,7 +7,6 @@ CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 0d0efc223dd4..df0a1adf793d 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 4b186c9fffc6..a010777804aa 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 897ca91e5606..12de2935baab 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -8,7 +8,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 2b8a12ee6906..9e8afe6060aa 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -8,7 +8,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index d53fe94db36b..854d129fa38b 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -8,7 +8,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index e6445f735c57..11df33d199f2 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -8,7 +8,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index c18f056debc4..0277ae55f1f1 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -6,7 +6,6 @@ CONFIG_DEFAULT_DEVICE_TREE="zynq-zed" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 21f8c08fd824..4f06c44578fa 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y
participants (2)
-
Ezequiel Garcia -
Michal Simek