Objective of this target to have concatenate binary having - SPL binary in PBL command format - U-boot binary

Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com --- Changes for v2: Updated target Changes for v3: Sending as it is Changes for v4: Updated Makefile with latest build format

Makefile | 19 +++++++++++++++++++ README | 4 ++++ 2 files changed, 23 insertions(+)

diff --git a/Makefile b/Makefile index ee16d8c..3f9ca40 100644 --- a/Makefile +++ b/Makefile @@ -707,7 +707,11 @@ ALL-y += u-boot.srec u-boot.bin System.map

ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin +ifeq ($(CONFIG_RAMBOOT_SPLPBL),y) +ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin +else ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl +endif ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin @@ -890,6 +894,21 @@ endif u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE $(call if_changed,cat)

+#Add a target to create boot binary having SPL binary in PBI format +#concatenated with u-boot binary. It is need by PowerPC SoC having +#internal SRAM <= 512KB. +MKIMAGEFLAGS_u-boot-spl.pbl = -n $(CONFIG_SYS_FSL_PBL_RCW) \ + -R $(CONFIG_SYS_FSL_PBL_PBI) -T pblimage + +spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ + --gap-fill=0xff + +u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl u-boot.bin FORCE + $(call if_changed,pad_cat) + # PPC4xx needs the SPL at the end of the image, since the reset vector # is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target # and need to introduce a new build target with the full blown U-Boot diff --git a/README b/README index 413a844..91ef97c 100644 --- a/README +++ b/README @@ -486,6 +486,10 @@ The following options need to be configured: PBI commands can be used to configure SoC before it starts the execution. Please refer doc/README.pblimage for more details

+ CONFIG_RAMBOOT_SPLPBL + It adds a target to create boot binary having SPL binary in PBI format + concatenated with u-boot binary. + CONFIG_SYS_FSL_DDR_BE Defines the DDR controller register space as Big Endian