Add simplified, generalised, bx50v3 device tree and enable CONFIG_DM.

Signed-off-by: Ian Ray ian.ray@ge.com --- arch/arm/dts/Makefile | 2 ++ arch/arm/dts/imx6q-bx50v3.dts | 15 +++++++++++++++ configs/ge_bx50v3_defconfig | 4 ++++ 3 files changed, 21 insertions(+) create mode 100644 arch/arm/dts/imx6q-bx50v3.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 46f1d69..a902775 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -582,6 +582,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ mt7629-rfb.dtb

+dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb + targets += $(dtb-y)

# Add any required device tree compiler flags here diff --git a/arch/arm/dts/imx6q-bx50v3.dts b/arch/arm/dts/imx6q-bx50v3.dts new file mode 100644 index 0000000..10b1299 --- /dev/null +++ b/arch/arm/dts/imx6q-bx50v3.dts @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ +/* + * Copyright 2015 Timesys Corporation. + * Copyright 2018 General Electric Company + * Based on imx6q-ba16.dtsi and imx6q-bx50v3.dtsi from kernel 4.20.5. + */ + +/dts-v1/; + +#include "imx6q.dtsi" + +/ { + model = "General Electric Bx50v3"; + compatible = "ge,imx6q-bx50v3", "advantech,imx6q-ba16", "fsl,imx6q"; +}; diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 4180050..58fa000 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -51,3 +51,7 @@ CONFIG_MXC_SPI=y CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y # CONFIG_EFI_LOADER is not set +CONFIG_DM=y +CONFIG_CMD_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-bx50v3"

Use MMC device model, and remove USDHC pin configuration code since the pinctrl driver is used.

Signed-off-by: Ian Ray ian.ray@ge.com --- arch/arm/dts/imx6q-bx50v3.dts | 47 ++++++++++++++++++ board/ge/bx50v3/bx50v3.c | 113 ------------------------------------------ configs/ge_bx50v3_defconfig | 4 ++ include/configs/ge_bx50v3.h | 6 +-- 4 files changed, 52 insertions(+), 118 deletions(-)

diff --git a/arch/arm/dts/imx6q-bx50v3.dts b/arch/arm/dts/imx6q-bx50v3.dts index 10b1299..0fff219 100644 --- a/arch/arm/dts/imx6q-bx50v3.dts +++ b/arch/arm/dts/imx6q-bx50v3.dts @@ -13,3 +13,50 @@ model = "General Electric Bx50v3"; compatible = "ge,imx6q-bx50v3", "advantech,imx6q-ba16", "fsl,imx6q"; }; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_reset: usdhc3grp-reset { + fsl,pins = < + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9 + >; + }; +}; + +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc4 { + status = "disabled"; +}; diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 079d302..fe3fa27 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -44,10 +44,6 @@ static struct vpd_cache vpd; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS)

-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)

@@ -116,45 +112,6 @@ static void setup_iomux_enet(void) mdelay(1); }

-static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -229,76 +186,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); }

-#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC2_BASE_ADDR}, - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) -#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = 1; /* eMMC is always present */ - break; - case USDHC4_BASE_ADDR: - ret = !gpio_get_value(USDHC4_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - int i; - - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - gpio_direction_input(USDHC4_CD_GPIO); - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers\n" - "(%d) then supported by the board (%d)\n", - i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} -#endif - static int mx6_rgmii_rework(struct phy_device *phydev) { /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */ diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 58fa000..af8a243 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -55,3 +55,7 @@ CONFIG_DM=y CONFIG_CMD_DM=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-bx50v3" +CONFIG_DM_MMC=y +CONFIG_BLK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 040b3ac..7d62483 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -45,10 +45,6 @@ #define CONFIG_LBA48 #endif

-/* MMC Configs */ -#define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - /* USB Configs */ #ifdef CONFIG_USB #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 @@ -88,7 +84,7 @@ "image=/boot/fitImage\0" \ "fdt_high=0xffffffff\0" \ "dev=mmc\0" \ - "devnum=1\0" \ + "devnum=2\0" \ "rootdev=mmcblk0p\0" \ "quiet=quiet loglevel=0\0" \ "console=" CONSOLE_DEV "\0" \

Enable CONFIG_DM_GPIO as a pre-requisite for enabling CONFIG_DM_SPI.

Add explicit gpio_requests.

Signed-off-by: Ian Ray ian.ray@ge.com --- board/ge/bx50v3/bx50v3.c | 11 ++++++++++- configs/ge_bx50v3_defconfig | 1 + 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index fe3fa27..dac063d 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -106,6 +106,7 @@ static void setup_iomux_enet(void) imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));

/* Reset AR8033 PHY */ + gpio_request(IMX_GPIO_NR(1, 28), "fec_rst"); gpio_direction_output(IMX_GPIO_NR(1, 28), 0); mdelay(10); gpio_set_value(IMX_GPIO_NR(1, 28), 1); @@ -420,8 +421,8 @@ static void setup_display_bx50v3(void) /* backlights off until needed */ imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); + gpio_request(LVDS_POWER_GP, "lvds_power"); gpio_direction_input(LVDS_POWER_GP); - gpio_direction_input(LVDS_BACKLIGHT_GP); } #endif /* CONFIG_VIDEO_IPUV3 */

@@ -574,14 +575,22 @@ int board_init(void) set_confidx(&vpd); }

+ gpio_request(SUS_S3_OUT, "sus_s3_out"); gpio_direction_output(SUS_S3_OUT, 1); + + gpio_request(WIFI_EN, "wifi_en"); gpio_direction_output(WIFI_EN, 1); + #if defined(CONFIG_VIDEO_IPUV3) if (is_b850v3()) setup_display_b850v3(); else setup_display_bx50v3(); + + gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight"); + gpio_direction_input(LVDS_BACKLIGHT_GP); #endif + /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index af8a243..10a8b67 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -59,3 +59,4 @@ CONFIG_DM_MMC=y CONFIG_BLK=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_GPIO=y

Use SPI flash device model, and remove SPI pin configuration code since the pinctrl driver is used.

Signed-off-by: Ian Ray ian.ray@ge.com --- arch/arm/dts/imx6q-bx50v3.dts | 27 +++++++++++++++++++++++++++ board/ge/bx50v3/bx50v3.c | 25 ------------------------- configs/ge_bx50v3_defconfig | 2 ++ 3 files changed, 29 insertions(+), 25 deletions(-)

diff --git a/arch/arm/dts/imx6q-bx50v3.dts b/arch/arm/dts/imx6q-bx50v3.dts index 0fff219..deaec63 100644 --- a/arch/arm/dts/imx6q-bx50v3.dts +++ b/arch/arm/dts/imx6q-bx50v3.dts @@ -8,6 +8,7 @@ /dts-v1/;

#include "imx6q.dtsi" +#include <dt-bindings/gpio/gpio.h>

/ { model = "General Electric Bx50v3"; @@ -17,6 +18,16 @@ &iomuxc { pinctrl-names = "default";

+ pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* SPI1 CS */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 @@ -60,3 +71,19 @@ &usdhc4 { status = "disabled"; }; + +/* SPI NOR */ +&ecspi1 { + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: n25q032@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index dac063d..b69b9e7 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -53,9 +53,6 @@ static struct vpd_cache vpd; #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)

-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) @@ -113,13 +110,6 @@ static void setup_iomux_enet(void) mdelay(1); }

-static iomux_v3_cfg_t const ecspi1_pads[] = { - MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, @@ -159,18 +149,6 @@ static struct i2c_pads_info i2c_pad_info3 = { } };

-#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1; -} - -static void setup_spi(void) -{ - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); -} -#endif - static iomux_v3_cfg_t const pcie_pads[] = { MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -594,9 +572,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

-#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif return 0; }

diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 10a8b67..71bf9d6 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -60,3 +60,5 @@ CONFIG_BLK=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y

Add simplified, generalised, ppd device tree and enable CONFIG_DM.

Signed-off-by: Ian Ray ian.ray@ge.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx53-ppd.dts | 14 ++++++++++++++ configs/mx53ppd_defconfig | 4 ++++ 3 files changed, 19 insertions(+) create mode 100644 arch/arm/dts/imx53-ppd.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a902775..1fd778b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -583,6 +583,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7629-rfb.dtb

dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb +dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb

targets += $(dtb-y)

diff --git a/arch/arm/dts/imx53-ppd.dts b/arch/arm/dts/imx53-ppd.dts new file mode 100644 index 0000000..98e7dad --- /dev/null +++ b/arch/arm/dts/imx53-ppd.dts @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ +/* + * Copyright 2018 General Electric Company + * Based on imx53-ppd.dts from kernel 4.20.5. + */ + +/dts-v1/; + +#include "imx53.dtsi" + +/ { + model = "General Electric CS ONE"; + compatible = "ge,imx53-cpuvo", "fsl,imx53"; +}; diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 77af2ae..7556c0c 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -45,3 +45,7 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y +CONFIG_DM=y +CONFIG_CMD_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx53-ppd"

These nodes are required by mx53ppd when built with CONFIG_DM_MMC=y. They are copied from Linux 4.20.5.

Signed-off-by: Ian Ray ian.ray@ge.com --- arch/arm/dts/imx53.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)

diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi index e13009c..0fd4acc 100644 --- a/arch/arm/dts/imx53.dtsi +++ b/arch/arm/dts/imx53.dtsi @@ -33,6 +33,8 @@ i2c2 = &i2c3; mmc0 = &esdhc1; mmc1 = &esdhc2; + mmc2 = &esdhc3; + mmc3 = &esdhc4; };

tzic: tz-interrupt-controller@fffc000 { @@ -86,6 +88,30 @@ bus-width = <4>; status = "disabled"; }; + + esdhc3: esdhc@50020000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x50020000 0x4000>; + interrupts = <3>; + clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC3_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + esdhc4: esdhc@50024000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x50024000 0x4000>; + interrupts = <4>; + clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC4_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; };

iomuxc: iomuxc@53fa8000 {

Use MMC device model, and remove USDHC pin configuration code since the pinctrl driver is used.

Signed-off-by: Ian Ray ian.ray@ge.com --- arch/arm/dts/imx53-ppd.dts | 29 ++++++++++++++++++ board/ge/mx53ppd/mx53ppd.c | 73 ---------------------------------------------- configs/mx53ppd_defconfig | 4 +++ include/configs/mx53ppd.h | 6 +--- 4 files changed, 34 insertions(+), 78 deletions(-)

diff --git a/arch/arm/dts/imx53-ppd.dts b/arch/arm/dts/imx53-ppd.dts index 98e7dad..f89d6f4 100644 --- a/arch/arm/dts/imx53-ppd.dts +++ b/arch/arm/dts/imx53-ppd.dts @@ -12,3 +12,32 @@ model = "General Electric CS ONE"; compatible = "ge,imx53-cpuvo", "fsl,imx53"; }; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 + >; + }; +}; + +/* eMMC */ +&esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3>; + compatible = "fsl,esdhc"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index 23bfe55..9e13a24 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -122,79 +122,6 @@ static void setup_iomux_fec(void) imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); }

-#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC3_BASE_ADDR}, - {MMC_SDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), - MX53_PAD_EIM_DA11__GPIO3_11, - }; - - static const iomux_v3_cfg_t sd2_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), - MX53_PAD_EIM_DA13__GPIO3_13, - }; - - u32 index; - int ret; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads(sd1_pads, - ARRAY_SIZE(sd1_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads(sd2_pads, - ARRAY_SIZE(sd2_pads)); - break; - default: - printf("Warning: you configured more ESDHC controller (%d) as supported by the board(2)\n", - CONFIG_SYS_FSL_ESDHC_NUM); - return -EINVAL; - } - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} -#endif - #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)

diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 7556c0c..cd19e9b 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -49,3 +49,7 @@ CONFIG_DM=y CONFIG_CMD_DM=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx53-ppd" +CONFIG_DM_MMC=y +CONFIG_BLK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX5=y diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 467547e..efc2f31 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -30,10 +30,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE

-/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 - /* Eth Configs */

#define CONFIG_FEC_MXC @@ -101,7 +97,7 @@ "image=/boot/fitImage\0" \ "fdt_high=0xffffffff\0" \ "dev=mmc\0" \ - "devnum=0\0" \ + "devnum=2\0" \ "rootdev=mmcblk0p\0" \ "quiet=quiet loglevel=0\0" \ "console=" CONSOLE_DEV "\0" \

Add board-specific FDT function to store U-Boot version in device tree.

Signed-off-by: Ian Ray ian.ray@ge.com --- board/ge/bx50v3/bx50v3.c | 11 +++++++++++ board/ge/mx53ppd/mx53ppd.c | 11 +++++++++++ configs/ge_bx50v3_defconfig | 1 + configs/mx53ppd_defconfig | 1 + 4 files changed, 24 insertions(+)

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index b69b9e7..f42d2ce 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -10,6 +10,7 @@ #include <asm/arch/iomux.h> #include <asm/arch/mx6-pins.h> #include <linux/errno.h> +#include <linux/libfdt.h> #include <asm/gpio.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/iomux-v3.h> @@ -27,6 +28,7 @@ #include <i2c.h> #include <input.h> #include <pwm.h> +#include <version.h> #include <stdlib.h> #include "../common/ge_common.h" #include "../common/vpd_reader.h" @@ -689,6 +691,15 @@ int checkboard(void) return 0; }

+#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + fdt_setprop(blob, 0, "ge,boot-ver", version_string, + strlen(version_string) + 1); + return 0; +} +#endif + static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { #ifdef CONFIG_VIDEO_IPUV3 diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index 9e13a24..5411e42 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -17,6 +17,7 @@ #include <asm/arch/iomux-mx53.h> #include <asm/arch/clock.h> #include <linux/errno.h> +#include <linux/libfdt.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/mx5_video.h> #include <environment.h> @@ -30,6 +31,7 @@ #include <fsl_pmic.h> #include <linux/fb.h> #include <ipu_pixfmt.h> +#include <version.h> #include <watchdog.h> #include "ppd_gpio.h" #include <stdlib.h> @@ -307,3 +309,12 @@ int checkboard(void)

return 0; } + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + fdt_setprop(blob, 0, "ge,boot-ver", version_string, + strlen(version_string) + 1); + return 0; +} +#endif diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 71bf9d6..d2ed2c1 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -62,3 +62,4 @@ CONFIG_PINCTRL_IMX6=y CONFIG_DM_GPIO=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y +CONFIG_OF_BOARD_SETUP=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index cd19e9b..fc6ea71 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -53,3 +53,4 @@ CONFIG_DM_MMC=y CONFIG_BLK=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX5=y +CONFIG_OF_BOARD_SETUP=y

From: Joonas Aijala joonas.aijala@ge.com

Specific ARP timeout sometimes causes ARP timeout during nfs loading of the fitImage.

Signed-off-by: Joonas Aijala joonas.aijala@ge.com Signed-off-by: Ian Ray ian.ray@ge.com --- include/configs/ge_bx50v3.h | 1 - 1 file changed, 1 deletion(-)

diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 7d62483..d48228b 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -148,7 +148,6 @@ #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND #endif

-#define CONFIG_ARP_TIMEOUT 200UL

/* Miscellaneous configurable options */

From: Joonas Aijala joonas.aijala@ge.com

New boot command introduced to automate network booting.

Signed-off-by: Joonas Aijala joonas.aijala@ge.com Signed-off-by: Ian Ray ian.ray@ge.com --- include/configs/ge_bx50v3.h | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index d48228b..bc63861 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -79,7 +79,32 @@

#define CONFIG_LOADADDR 0x12000000

+#ifdef CONFIG_NFS_CMD +#define NETWORKBOOT \ + "setnetworkboot=" \ + "setenv ipaddr 172.16.2.10; setenv serverip 172.16.2.20; " \ + "setenv gatewayip 172.16.2.20; setenv nfsserver 172.16.2.20; " \ + "setenv netmask 255.255.255.0; setenv ethaddr ca:fe:de:ca:f0:11; " \ + "setenv bootargs root=/dev/nfs nfsroot=${nfsserver}:/srv/nfs/,v3,tcp rw rootwait" \ + "setenv bootargs $bootargs ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off " \ + "setenv bootargs $bootargs cma=128M bootcause=POR console=${console} ${videoargs} " \ + "setenv bootargs $bootargs systemd.mask=helix-network-defaults.service " \ + "setenv bootargs $bootargs watchdog.handle_boot_enabled=1\0" \ + "networkboot=" \ + "run setnetworkboot; " \ + "nfs ${loadaddr} /srv/nfs/fitImage; " \ + "bootm ${loadaddr}#conf@${confidx}\0" \ + +#define CONFIG_NETWORKBOOTCOMMAND \ + "run networkboot; " \ + +#else +#define NETWORKBOOT \ + +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ + NETWORKBOOT \ "bootcause=POR\0" \ "image=/boot/fitImage\0" \ "fdt_high=0xffffffff\0" \ @@ -142,7 +167,9 @@ #define CONFIG_USBBOOTCOMMAND \ "echo Unsupported; " \

-#ifdef CONFIG_CMD_USB +#ifdef CONFIG_NFS_CMD +#define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND +#elif CONFIG_CMD_USB #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND #else #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND

Configure GPIO BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N to bring the dock out of reset at boot.

Signed-off-by: Ian Ray ian.ray@ge.com --- board/ge/mx53ppd/ppd_gpio.h | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/board/ge/mx53ppd/ppd_gpio.h b/board/ge/mx53ppd/ppd_gpio.h index e3b84c7..ba2d1ba 100644 --- a/board/ge/mx53ppd/ppd_gpio.h +++ b/board/ge/mx53ppd/ppd_gpio.h @@ -36,6 +36,8 @@ static const iomux_v3_cfg_t ppd_pads[] = { MX53_PAD_KEY_COL2__GPIO4_10, MX53_PAD_KEY_ROW2__GPIO4_11, MX53_PAD_KEY_COL3__GPIO4_12, + + MX53_PAD_PATA_DATA7__GPIO2_7, /* BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */ };

struct gpio_cfg { @@ -61,6 +63,7 @@ struct gpio_cfg { #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) #define ECSPI1_CS2 IMX_GPIO_NR(4, 11) #define ECSPI1_CS3 IMX_GPIO_NR(4, 12) +#define BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N IMX_GPIO_NR(2, 7)

static const struct gpio_cfg ppd_gpios[] = { /* FEC */ @@ -90,6 +93,7 @@ static const struct gpio_cfg ppd_gpios[] = { { ECSPI1_CS1, 1 }, { ECSPI1_CS2, 1 }, { ECSPI1_CS3, 1 }, + { BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N, 1 }, };

#endif /* __PPD_GPIO_H_ */

Fix the NFS commands which used `set' to instead use `setenv'.

Signed-off-by: Ian Ray ian.ray@ge.com --- include/configs/mx53ppd.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index efc2f31..e34693e 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -85,10 +85,10 @@ "nfsroot=/opt/springdale/rd\0" \ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ "${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \ - "choose_ip=if test $use_dhcp = 1; then set kern_ipconf ip=dhcp; " \ - "set getcmd dhcp; else set kern_ipconf " \ + "choose_ip=if test $use_dhcp = 1; then setenv kern_ipconf ip=dhcp; " \ + "setenv getcmd dhcp; else setenv kern_ipconf " \ "ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \ - "set getcmd tftp; fi\0" \ + "setenv getcmd tftp; fi\0" \ "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \ "${nfsserver}:${image}; bootm ${loadaddr}\0" \

Since 2018.11, the pattern of bootcount load and store has changed such that bootcount_inc() and bootcount_error() will load, increment, store, and load *again*. The second load exposes a timing problem whereby the i2c read fails. The root cause _seems_ to relate to performance of the 24c08 EEPROM. Insert a delay after writing to work around this.

Signed-off-by: Ian Ray ian.ray@ge.com --- drivers/bootcount/bootcount_i2c.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/drivers/bootcount/bootcount_i2c.c b/drivers/bootcount/bootcount_i2c.c index ed22389..dd86426 100644 --- a/drivers/bootcount/bootcount_i2c.c +++ b/drivers/bootcount/bootcount_i2c.c @@ -64,6 +64,10 @@ void bootcount_store(ulong a) CONFIG_BOOTCOUNT_ALEN, buf, sizeof(buf)); if (ret != 0) puts("Error writing bootcount\n"); + else + /* Datasheet claims 2 ms typical write cycle time. + * This delay ensures that next read will succeed. */ + mdelay(5);

bootcount_set_bus_back(prev_i2c_bus); }