On 01. 06. 20 7:34, Milan Obuch wrote:

...

Hello,

I just noticed that the support for the board Zybo-Z7 in mainline U-Boot is no longer available.

Are there some reasons why it was dropped? Couldn't find any information in the list archive.

Thanks in advance!

-- Best regards,

Johannes K.

I was about to ask similar question already, slightly different way. Michal decided to somehow unify Zynq based board support with common zynq_virtconfig (sp?) configuration, but I did not understand the details yet. So I would rephrase the question another way...

How should one compile u-boot for Zybo Z7 board now and how should bootable image be created?

export DEVICE_TREE=zynq-zybo-z7 make xilinx_zynq_virt_defconfig make -j8

M

On 01. 06. 20 8:59, Johannes Krottmayer wrote:

Okay, thanks for the fast reply!

At the time I wrote this mail, I didn't read the docs.

Off-topic:

Are there plans for U-Boot to create a default image (including FSBL, bitstream and U-Boot)?

For example (additional build step): $ export BITSTREAM=/path/to/fpga.bit

For now I use Vivado to create the bitstream file, Vitis for the FSBL and then bootgen to create the SD card image.

SPL is community effort and not supported flow by Xilinx. If you want to use it, use it but don't expect any help from Xilinx to help you with issues. I take care about it, use it but there is no planning behind. I am fixing issues for me and for the rest please send a patch and I will take a look. As far as I know JTAG, SD and qspi(but limited) flows should work. I use SD boot most of the time.

If you want to pack bitstream to u-boot.img/itb then it should be quite easy to do and all things are in place. Using FSBL as the part of open source flow. I don't think this is going to happen because mainline u-boot is using mkimage for boot.bin generation and fsbl requires more partitions in boot.bin which is not supported.

Definitely patches welcome.

Thanks, Michal

On 01. 06. 20 16:08, Johannes Krottmayer wrote:

On 01.06.20 at 10:18, Michal Simek wrote:

...

SPL is community effort and not supported flow by Xilinx. If you want to use it, use it but don't expect any help from Xilinx to help you with issues. I take care about it, use it but there is no planning behind. I am fixing issues for me and for the rest please send a patch and I will take a look. As far as I know JTAG, SD and qspi(but limited) flows should work. I use SD boot most of the time.

Thanks for the clarification.

...

If you want to pack bitstream to u-boot.img/itb then it should be quite easy to do and all things are in place.

How is the official U-Boot way, to use the created image on ZYNQ boards or which generated files must be placed on a SD card? Unfortunately I couldn't find any information in the docs at this time. I have tried to create the image with the (custom) bitstream file. Used a FIT source (based on <arch/arm/mach-zynqmp/mkimage_fit_atf.sh>) which I have attached. But I have no idea how place the image on the SD card. Tried a simple...

$ dd=if=/path/to/U-Boot/u-boot.img of=/dev/sdf

but didn't work. Also tried to rename the image to BOOT.BIN and place it in the root directory of a FAT32 filesystem.

When I use the Xilinx tools to generate the image with following, it works:

• Vivado: Create bitstream from design
• Vitis: Create and build FSBL
• Build U-Boot
• Create BIF:

image { [bootloader]fsbl.elf fpga.bit u-boot.elf }

• Use bootgen to create the image
• Create FAT32 filesystem on SD card
• Place generated image (BOOT.BIN) to root directory

It is just about putting boot.bin to the first fat partition. Anyway this is of topic for this mailing list and please take a look at xilinx wiki pages and manuals. If you have any issue like this you can consider to use xilinx forums where support team will take care about it.

Thanks, Michal