[U-Boot] [PATCH] rockchip: video: fix mpixelclock in rockchip HDMI
Correct mpixelclock errors in rockchip_phy_config[] and rockchip_mpll_cfg[].
Signed-off-by: Nickey Yang nickey.yang@rock-chips.com --- drivers/video/rockchip/rk_hdmi.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index 7976c5e..1f55ef6 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -85,13 +85,13 @@ struct hdmi_phy_config {
static const struct hdmi_phy_config rockchip_phy_config[] = { { - .mpixelclock = 74250, + .mpixelclock = 74250000, .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272, }, { - .mpixelclock = 148500, + .mpixelclock = 148500000, .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d, }, { - .mpixelclock = 297000, + .mpixelclock = 297000000, .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d, }, { .mpixelclock = ~0ul, @@ -101,22 +101,22 @@ static const struct hdmi_phy_config rockchip_phy_config[] = {
static const struct hdmi_mpll_config rockchip_mpll_cfg[] = { { - .mpixelclock = 40000, + .mpixelclock = 40000000, .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018, }, { - .mpixelclock = 65000, + .mpixelclock = 65000000, .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028, }, { - .mpixelclock = 66000, + .mpixelclock = 66000000, .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038, }, { - .mpixelclock = 83500, + .mpixelclock = 835000000, .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028, }, { - .mpixelclock = 146250, + .mpixelclock = 146250000, .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038, }, { - .mpixelclock = 148500, + .mpixelclock = 148500000, .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000, }, { .mpixelclock = ~0ul, @@ -870,7 +870,7 @@ static int rk_hdmi_probe(struct udevice *dev) clk_free(&clk); } if (ret) { - debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret); + debug("%s: Failed to set hdmi clock: ret=%d\n", __func__, ret); return ret; }
On 28 December 2016 at 23:01, Nickey Yang nickey.yang@rock-chips.com wrote:
Correct mpixelclock errors in rockchip_phy_config[] and rockchip_mpll_cfg[].
Signed-off-by: Nickey Yang nickey.yang@rock-chips.com
drivers/video/rockchip/rk_hdmi.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)
Applied to u-boot-rockchip, thanks!
Hi,
On 11 January 2017 at 22:08, Simon Glass sjg@chromium.org wrote:
On 28 December 2016 at 23:01, Nickey Yang nickey.yang@rock-chips.com wrote:
Correct mpixelclock errors in rockchip_phy_config[] and rockchip_mpll_cfg[].
Signed-off-by: Nickey Yang nickey.yang@rock-chips.com
drivers/video/rockchip/rk_hdmi.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)
Applied to u-boot-rockchip, thanks!
I only just noticed, but this patch breaks HDMI output on firefly. Can you please take a look? What does this patch actually fix?
Regards, Simon
Hi Simon,
在 2017年02月23日 11:52, Simon Glass 写道:
Hi,
On 11 January 2017 at 22:08, Simon Glass sjg@chromium.org wrote:
On 28 December 2016 at 23:01, Nickey Yang nickey.yang@rock-chips.com wrote:
Correct mpixelclock errors in rockchip_phy_config[] and rockchip_mpll_cfg[].
Signed-off-by: Nickey Yang nickey.yang@rock-chips.com
drivers/video/rockchip/rk_hdmi.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)
Applied to u-boot-rockchip, thanks!
I only just noticed, but this patch breaks HDMI output on firefly. Can you please take a look? What does this patch actually fix?
Regards, Simon
You can add
printf("---YYS mpll.cpce = %x \n",rockchip_mpll_cfg[i].cpce); printf("---YYS mpll.gmp = %x \n",rockchip_mpll_cfg[i].gmp); printf("---YYS mpll.curr = %x \n",rockchip_mpll_cfg[i].curr);
in hdmi_phy_configure(rk_hdmi.c line 409), all of those value will be 0 without this patch. We want to get those different value by near clock settings between rockchip_mpll_cfg[] in fact.
by the way,HDMI output on firefly will work well when reset this patch?
Hi Nickey,
On 22 February 2017 at 23:56, Nickey.Yang nickey.yang@rock-chips.com wrote:
Hi Simon,
在 2017年02月23日 11:52, Simon Glass 写道:
Hi,
On 11 January 2017 at 22:08, Simon Glass sjg@chromium.org wrote:
On 28 December 2016 at 23:01, Nickey Yang nickey.yang@rock-chips.com wrote:
Correct mpixelclock errors in rockchip_phy_config[] and rockchip_mpll_cfg[].
Signed-off-by: Nickey Yang nickey.yang@rock-chips.com
drivers/video/rockchip/rk_hdmi.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)
Applied to u-boot-rockchip, thanks!
I only just noticed, but this patch breaks HDMI output on firefly. Can you please take a look? What does this patch actually fix?
Regards, Simon
You can add
printf("---YYS mpll.cpce = %x \n",rockchip_mpll_cfg[i].cpce); printf("---YYS mpll.gmp = %x \n",rockchip_mpll_cfg[i].gmp); printf("---YYS mpll.curr = %x \n",rockchip_mpll_cfg[i].curr);in hdmi_phy_configure(rk_hdmi.c line 409), all of those value will be 0 without this patch. We want to get those different value by near clock settings between rockchip_mpll_cfg[] in fact.
Yes it makes sense
by the way,HDMI output on firefly will work well when reset this patch?
Yes it works when I revert.
Regards, Simon
Hi Simon,
在 2017年02月24日 00:19, Simon Glass 写道:
Hi Nickey,
On 22 February 2017 at 23:56, Nickey.Yang nickey.yang@rock-chips.com wrote:
Hi Simon,
在 2017年02月23日 11:52, Simon Glass 写道:
Hi,
On 11 January 2017 at 22:08, Simon Glass sjg@chromium.org wrote:
On 28 December 2016 at 23:01, Nickey Yang nickey.yang@rock-chips.com wrote:
Correct mpixelclock errors in rockchip_phy_config[] and rockchip_mpll_cfg[].
Signed-off-by: Nickey Yang nickey.yang@rock-chips.com
drivers/video/rockchip/rk_hdmi.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)
Applied to u-boot-rockchip, thanks!
I only just noticed, but this patch breaks HDMI output on firefly. Can you please take a look? What does this patch actually fix?
Regards, Simon
You can add
printf("---YYS mpll.cpce = %x \n",rockchip_mpll_cfg[i].cpce); printf("---YYS mpll.gmp = %x \n",rockchip_mpll_cfg[i].gmp); printf("---YYS mpll.curr = %x \n",rockchip_mpll_cfg[i].curr);in hdmi_phy_configure(rk_hdmi.c line 409), all of those value will be 0 without this patch. We want to get those different value by near clock settings between rockchip_mpll_cfg[] in fact.
Yes it makes sense
by the way,HDMI output on firefly will work well when reset this patch?
Yes it works when I revert.
Regards, Simon
I am sorry for my mistake. There is one "0" too many in 83500000 mpixelclock in rockchip_mpll_cfg[]. I have send new patch rockchip: video: fix 83500000 clock mistake in rockchip HDMI to fix it.
Regards, Nickey
participants (3)
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Nickey Yang -
Nickey.Yang
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Simon Glass