[U-Boot] [PATCH] mmc: sunxi: Only update timing mode bit when enabling new timing mode
When enabling the new mmc timing mode, we inadvertently clear all the remaining bits in the new timing mode register. The bits cleared include a default phase delay on the output clock. The BSP kernel states that the default values are supposed to be used. Clearing them results in decreased performance or transfer errors on some boards.
Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode") Signed-off-by: Chen-Yu Tsai wens@csie.org --- drivers/mmc/sunxi_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index a76e763bfd4f..4edb4be46c81 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -167,7 +167,7 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) if (new_mode) { #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE val = CCM_MMC_CTRL_MODE_SEL_NEW; - writel(SUNXI_MMC_NTSR_MODE_SEL_NEW, &priv->reg->ntsr); + setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW); #endif } else { val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
On Thu, Aug 31, 2017 at 09:57:48PM +0800, Chen-Yu Tsai wrote:
When enabling the new mmc timing mode, we inadvertently clear all the remaining bits in the new timing mode register. The bits cleared include a default phase delay on the output clock. The BSP kernel states that the default values are supposed to be used. Clearing them results in decreased performance or transfer errors on some boards.
Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode") Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Maxime Ripard maxime.ripard@free-electrons.com
Thanks! Maxime
On Thu, Aug 31, 2017 at 7:34 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Thu, Aug 31, 2017 at 09:57:48PM +0800, Chen-Yu Tsai wrote:
When enabling the new mmc timing mode, we inadvertently clear all the remaining bits in the new timing mode register. The bits cleared include a default phase delay on the output clock. The BSP kernel states that the default values are supposed to be used. Clearing them results in decreased performance or transfer errors on some boards.
Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode") Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Maxime Ripard maxime.ripard@free-electrons.com
Reviewed-by: Jagan Teki jagan@openedev.com
thanks!
On Thu, Aug 31, 2017 at 7:36 PM, Jagan Teki jagannadh.teki@gmail.com wrote:
On Thu, Aug 31, 2017 at 7:34 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Thu, Aug 31, 2017 at 09:57:48PM +0800, Chen-Yu Tsai wrote:
When enabling the new mmc timing mode, we inadvertently clear all the remaining bits in the new timing mode register. The bits cleared include a default phase delay on the output clock. The BSP kernel states that the default values are supposed to be used. Clearing them results in decreased performance or transfer errors on some boards.
Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode") Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Maxime Ripard maxime.ripard@free-electrons.com
Reviewed-by: Jagan Teki jagan@openedev.com
Applied to u-boot-sunxi/master
thanks!
participants (3)
-
Chen-Yu Tsai -
Jagan Teki -
Maxime Ripard