[PATCH v1 0/4] arm64: mvebu: Sync Marvell armada8k MMU setup with Marvell version
This patchset adds some Armada8k MMU setup related patches from the Marvell SDK. This is needed to resolve some PCI related issues that I exprienced while porting mainline U-Boot to the CN9132 DB board.
Thanks, Stefan
Grzegorz Jaszczyk (3): arm64: mvebu: do not map firmware RT service region arm64: mvebu: a8k: move firmware related definitions to fw info arm64: mvebu: extend the mmio region
jinghua (1): arm64: mvebu: a8k: align memory regions
arch/arm/mach-mvebu/armada8k/cpu.c | 70 +++++----------------- arch/arm/mach-mvebu/include/mach/fw_info.h | 18 ++++++ 2 files changed, 34 insertions(+), 54 deletions(-) create mode 100644 arch/arm/mach-mvebu/include/mach/fw_info.h
From: jinghua jinghua@marvell.com
1. RAM: base address 0x0 size 2Gbytes 2. MMIO: base address 0xf0000000 size 1Gbytes
Signed-off-by: Ofir Fedida ofedida@marvell.com Signed-off-by: Stefan Roese sr@denx.de ---
arch/arm/mach-mvebu/armada8k/cpu.c | 62 ++++-------------------------- 1 file changed, 7 insertions(+), 55 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index 474327a8e1c9..99531711ee34 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -8,6 +8,7 @@ #include <dm.h> #include <fdtdec.h> #include <linux/libfdt.h> +#include <linux/sizes.h> #include <asm/io.h> #include <asm/system.h> #include <asm/arch/cpu.h> @@ -23,62 +24,22 @@ #define BOOT_MODE_MASK 0x3f #define BOOT_MODE_OFFSET 4
-/* - * The following table includes all memory regions for Armada 7k and - * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets - * define these regions at the beginning of the struct so that they - * can be easier removed later dynamically if an Armada 7k device is detected. - * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt - */ -#define ARMADA_7K8K_COMMON_REGIONS_START 2 static struct mm_region mvebu_mem_map[] = { /* Armada 80x0 memory regions include the CP1 (slave) units */ - { - /* SRAM, MMIO regions - CP110 slave region */ - .phys = 0xf4000000UL, - .virt = 0xf4000000UL, - .size = 0x02000000UL, /* 32MiB internal registers */ - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE - }, - { - /* PCI CP1 regions */ - .phys = 0xfa000000UL, - .virt = 0xfa000000UL, - .size = 0x04000000UL, /* 64MiB CP110 slave PCI space */ - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE - }, - /* Armada 80x0 and 70x0 common memory regions start here */ { /* RAM */ .phys = 0x0UL, .virt = 0x0UL, - .size = 0x80000000UL, + .size = SZ_2G, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - /* SRAM, MMIO regions - AP806 region */ - .phys = 0xf0000000UL, - .virt = 0xf0000000UL, - .size = 0x01000000UL, /* 16MiB internal registers */ - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE - }, - { - /* SRAM, MMIO regions - CP110 master region */ - .phys = 0xf2000000UL, - .virt = 0xf2000000UL, - .size = 0x02000000UL, /* 32MiB internal registers */ - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE - }, - { - /* PCI CP0 regions */ - .phys = 0xf6000000UL, - .virt = 0xf6000000UL, - .size = 0x04000000UL, /* 64MiB CP110 master PCI space */ + /* MMIO regions */ + .phys = SOC_REGS_PHY_BASE, + .virt = SOC_REGS_PHY_BASE, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, @@ -91,15 +52,6 @@ struct mm_region *mem_map = mvebu_mem_map;
void enable_caches(void) { - /* - * Armada 7k is not equipped with the CP110 slave CP. In case this - * code runs on an Armada 7k device, lets remove the CP110 slave - * entries from the memory mapping by moving the start to the - * common regions. - */ - if (of_machine_is_compatible("marvell,armada7040")) - mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START]; - icache_enable(); dcache_enable(); }
From: Grzegorz Jaszczyk jaz@semihalf.com
There is region left by ATF, which needs to remain in memory to provide RT services. To prevent overwriting it by u-boot, do not provide any mapping for this memory region, so any attempt to access it will trigger synchronous exception.
Update sr 2021-04-12: Don't update armada3700/cpu.c mmu table, as this has specific changes included in mainline.
Signed-off-by: Grzegorz Jaszczyk jaz@semihalf.com Signed-off-by: Stefan Roese sr@denx.de ---
arch/arm/mach-mvebu/armada8k/cpu.c | 12 +++++++++++- arch/arm/mach-mvebu/include/mach/fw_info.h | 13 +++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-mvebu/include/mach/fw_info.h
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index 99531711ee34..d76e17632556 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -14,6 +14,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <asm/armv8/mmu.h> +#include <mach/fw_info.h>
/* Armada 7k/8k */ #define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000)) @@ -27,9 +28,18 @@ static struct mm_region mvebu_mem_map[] = { /* Armada 80x0 memory regions include the CP1 (slave) units */ { - /* RAM */ + /* RAM 0-64MB */ .phys = 0x0UL, .virt = 0x0UL, + .size = ATF_REGION_START, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + /* ATF and TEE region 0x4000000-0x5400000 not mapped */ + { + /* RAM 66MB-2GB */ + .phys = ATF_REGION_END, + .virt = ATF_REGION_END, .size = SZ_2G, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE diff --git a/arch/arm/mach-mvebu/include/mach/fw_info.h b/arch/arm/mach-mvebu/include/mach/fw_info.h new file mode 100644 index 000000000000..ab2bb91bd5b3 --- /dev/null +++ b/arch/arm/mach-mvebu/include/mach/fw_info.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Marvell International Ltd. + */ + +#ifndef _FW_INFO_H_ +#define _FW_INFO_H_ + +/* Protected ATF and TEE region */ +#define ATF_REGION_START 0x4000000 +#define ATF_REGION_END 0x5400000 + +#endif /* _FW_INFO_H_ */
From: Grzegorz Jaszczyk jaz@semihalf.com
Signed-off-by: Grzegorz Jaszczyk jaz@semihalf.com Signed-off-by: Stefan Roese sr@denx.de ---
arch/arm/mach-mvebu/include/mach/fw_info.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-mvebu/include/mach/fw_info.h b/arch/arm/mach-mvebu/include/mach/fw_info.h index ab2bb91bd5b3..6ab972e36e93 100644 --- a/arch/arm/mach-mvebu/include/mach/fw_info.h +++ b/arch/arm/mach-mvebu/include/mach/fw_info.h @@ -10,4 +10,7 @@ #define ATF_REGION_START 0x4000000 #define ATF_REGION_END 0x5400000
+/* Firmware related definition used for SMC calls */ +#define MV_SIP_DRAM_SIZE 0x82000010 + #endif /* _FW_INFO_H_ */
From: Grzegorz Jaszczyk jaz@semihalf.com
Some of the setups including cn9130 opens mmio window starting from 0xc0000000, reflect it in the u-boot code.
Signed-off-by: Grzegorz Jaszczyk jaz@semihalf.com Signed-off-by: Kostya Porotchkin kostap@marvell.com Signed-off-by: Stefan Roese sr@denx.de ---
arch/arm/mach-mvebu/armada8k/cpu.c | 4 ++-- arch/arm/mach-mvebu/include/mach/fw_info.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index d76e17632556..939abce000f6 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -46,8 +46,8 @@ static struct mm_region mvebu_mem_map[] = { }, { /* MMIO regions */ - .phys = SOC_REGS_PHY_BASE, - .virt = SOC_REGS_PHY_BASE, + .phys = MMIO_REGS_PHY_BASE, + .virt = MMIO_REGS_PHY_BASE, .size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | diff --git a/arch/arm/mach-mvebu/include/mach/fw_info.h b/arch/arm/mach-mvebu/include/mach/fw_info.h index 6ab972e36e93..1382438e390e 100644 --- a/arch/arm/mach-mvebu/include/mach/fw_info.h +++ b/arch/arm/mach-mvebu/include/mach/fw_info.h @@ -13,4 +13,6 @@ /* Firmware related definition used for SMC calls */ #define MV_SIP_DRAM_SIZE 0x82000010
+#define MMIO_REGS_PHY_BASE 0xc0000000 + #endif /* _FW_INFO_H_ */
participants (1)
-
Stefan Roese