[PATCH 1/3] arm: dts: imx8mm: Sync with Linux 6.3
From: Fabio Estevam festevam@denx.de
Sync imx8mm.dtsi with Linux 6.3.
The motivation for doing this sync was a bug when doing "ums 0 mmc 1" on imx8mm-evk. It worked well for the first time, but after doing a CTRL+C and launching the ums again, the command did not work.
Adam Ford suggested to sync imx8mm.dtsi with the Linux dts, as there was a recent USB power domain reorganization there.
After syncing the imx8mm.dtsi with Linux, the ums command works without problem after a CTRL+C.
Suggested-by: Adam Ford aford173@gmail.com Signed-off-by: Fabio Estevam festevam@denx.de --- arch/arm/dts/imx8mm.dtsi | 52 +++++++++++++++++++++++++++++----------- 1 file changed, 38 insertions(+), 14 deletions(-)
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index afb90f59c83c..31f4548f85cf 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; @@ -276,6 +277,7 @@ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk"; + power-domains = <&pgc_otg1>; };
usbphynop2: usbphynop2 { @@ -285,6 +287,7 @@ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk"; + power-domains = <&pgc_otg2>; };
soc: soc@0 { @@ -493,6 +496,8 @@ compatible = "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; };
@@ -547,8 +552,8 @@ reg = <0x30330000 0x10000>; };
- gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; + gpr: syscon@30340000 { + compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };
@@ -560,22 +565,40 @@ #address-cells = <1>; #size-cells = <1>;
- imx8mm_uid: unique-id@410 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = <ADDR SIZE>; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mm_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; };
- cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
- fec_mac_address: mac-address@90 { + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; };
- anatop: anatop@30360000 { - compatible = "fsl,imx8mm-anatop", "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; };
snvs: snvs@30370000 { @@ -674,13 +697,11 @@ pgc_otg1: power-domain@2 { #power-domain-cells = <0>; reg = <IMX8MM_POWER_DOMAIN_OTG1>; - power-domains = <&pgc_hsiomix>; };
pgc_otg2: power-domain@3 { #power-domain-cells = <0>; reg = <IMX8MM_POWER_DOMAIN_OTG2>; - power-domains = <&pgc_hsiomix>; };
pgc_gpumix: power-domain@4 { @@ -1186,7 +1207,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; - power-domains = <&pgc_otg1>; + power-domains = <&pgc_hsiomix>; status = "disabled"; };
@@ -1206,7 +1227,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; - power-domains = <&pgc_otg2>; + power-domains = <&pgc_hsiomix>; status = "disabled"; };
@@ -1238,16 +1259,15 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; };
- gpmi: nand-controller@33002000{ + gpmi: nand-controller@33002000 { compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; @@ -1282,6 +1302,10 @@ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; linux,pci-domain = <0>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
From: Fabio Estevam festevam@denx.de
Sync imx8mn.dtsi with Linux 6.3.
Signed-off-by: Fabio Estevam festevam@denx.de --- arch/arm/dts/imx8mn.dtsi | 46 ++++++++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index cb2836bfbd95..9e0ddd6b7a32 100644 --- a/arch/arm/dts/imx8mn.dtsi +++ b/arch/arm/dts/imx8mn.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; @@ -295,6 +296,7 @@ sai2: sai@30020000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI2_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -309,6 +311,7 @@ sai3: sai@30030000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30030000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -323,6 +326,7 @@ sai5: sai@30050000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -339,6 +343,7 @@ sai6: sai@30060000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI6_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -396,6 +401,7 @@ sai7: sai@300b0000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x300b0000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI7_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -497,6 +503,8 @@ compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MN_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; };
@@ -551,7 +559,7 @@ reg = <0x30330000 0x10000>; };
- gpr: iomuxc-gpr@30340000 { + gpr: syscon@30340000 { compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -563,23 +571,40 @@ #address-cells = <1>; #size-cells = <1>;
- imx8mn_uid: unique-id@410 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = <ADDR SIZE>; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; };
- cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
- fec_mac_address: mac-address@90 { + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; };
- anatop: anatop@30360000 { - compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", - "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; };
snvs: snvs@30370000 { @@ -662,7 +687,6 @@ pgc_otg1: power-domain@1 { #power-domain-cells = <0>; reg = <IMX8MN_POWER_DOMAIN_OTG1>; - power-domains = <&pgc_hsiomix>; };
pgc_gpumix: power-domain@2 { @@ -1076,7 +1100,7 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; - power-domains = <&pgc_otg1>; + power-domains = <&pgc_hsiomix>; status = "disabled"; };
@@ -1094,7 +1118,6 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; @@ -1103,7 +1126,7 @@ gpmi: nand-controller@33002000 { compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; @@ -1175,5 +1198,6 @@ assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; clock-names = "main_clk"; + power-domains = <&pgc_otg1>; }; };
On Thu, Apr 27, 2023 at 1:08 PM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Sync imx8mn.dtsi with Linux 6.3.
Signed-off-by: Fabio Estevam festevam@denx.de
Reviewed-by: Adam Ford aford173@gmail.com
arch/arm/dts/imx8mn.dtsi | 46 ++++++++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index cb2836bfbd95..9e0ddd6b7a32 100644 --- a/arch/arm/dts/imx8mn.dtsi +++ b/arch/arm/dts/imx8mn.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>;
cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>;@@ -295,6 +296,7 @@ sai2: sai@30020000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI2_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -309,6 +311,7 @@ sai3: sai@30030000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30030000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -323,6 +326,7 @@ sai5: sai@30050000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -339,6 +343,7 @@ sai6: sai@30060000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI6_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -396,6 +401,7 @@ sai7: sai@300b0000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x300b0000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI7_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -497,6 +503,8 @@ compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
nvmem-cells = <&tmu_calib>;nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; };@@ -551,7 +559,7 @@ reg = <0x30330000 0x10000>; };
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 { compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };@@ -563,23 +571,40 @@ #address-cells = <1>; #size-cells = <1>;
imx8mn_uid: unique-id@410 {
/** The register address below maps to the MX8M* Fusemap Description Table entries this way.* Assuming* reg = <ADDR SIZE>;* then* Fuse Address = (ADDR * 4) + 0x400* Note that if SIZE is greater than 4, then* each subsequent fuse is located at offset* +0x10 in Fusemap Description Table (e.g.* reg = <0x4 0x8> describes fuses 0x410 and* 0x420).*/imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; };
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
fec_mac_address: mac-address@90 {
tmu_calib: calib@3c { /* 0x4f0 */reg = <0x3c 4>;};fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; };
anatop: anatop@30360000 {compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop","syscon";
anatop: clock-controller@30360000 {compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>;#clock-cells = <1>; }; snvs: snvs@30370000 {@@ -662,7 +687,6 @@ pgc_otg1: power-domain@1 { #power-domain-cells = <0>; reg = <IMX8MN_POWER_DOMAIN_OTG1>;
power-domains = <&pgc_hsiomix>; }; pgc_gpumix: power-domain@2 {@@ -1076,7 +1100,7 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_otg1>;
power-domains = <&pgc_hsiomix>; status = "disabled"; };@@ -1094,7 +1118,6 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;@@ -1103,7 +1126,7 @@ gpmi: nand-controller@33002000 { compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;@@ -1175,5 +1198,6 @@ assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; clock-names = "main_clk";
power-domains = <&pgc_otg1>; };};
2.34.1
On Thu, Apr 27, 2023 at 11:08 AM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Sync imx8mn.dtsi with Linux 6.3.
Signed-off-by: Fabio Estevam festevam@denx.de
arch/arm/dts/imx8mn.dtsi | 46 ++++++++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index cb2836bfbd95..9e0ddd6b7a32 100644 --- a/arch/arm/dts/imx8mn.dtsi +++ b/arch/arm/dts/imx8mn.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>;
cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>;@@ -295,6 +296,7 @@ sai2: sai@30020000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI2_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -309,6 +311,7 @@ sai3: sai@30030000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30030000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -323,6 +326,7 @@ sai5: sai@30050000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -339,6 +343,7 @@ sai6: sai@30060000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI6_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -396,6 +401,7 @@ sai7: sai@300b0000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x300b0000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI7_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -497,6 +503,8 @@ compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
nvmem-cells = <&tmu_calib>;nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; };@@ -551,7 +559,7 @@ reg = <0x30330000 0x10000>; };
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 { compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };@@ -563,23 +571,40 @@ #address-cells = <1>; #size-cells = <1>;
imx8mn_uid: unique-id@410 {
/** The register address below maps to the MX8M* Fusemap Description Table entries this way.* Assuming* reg = <ADDR SIZE>;* then* Fuse Address = (ADDR * 4) + 0x400* Note that if SIZE is greater than 4, then* each subsequent fuse is located at offset* +0x10 in Fusemap Description Table (e.g.* reg = <0x4 0x8> describes fuses 0x410 and* 0x420).*/imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; };
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
fec_mac_address: mac-address@90 {
tmu_calib: calib@3c { /* 0x4f0 */reg = <0x3c 4>;};fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; };
anatop: anatop@30360000 {compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop","syscon";
anatop: clock-controller@30360000 {compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>;#clock-cells = <1>; }; snvs: snvs@30370000 {@@ -662,7 +687,6 @@ pgc_otg1: power-domain@1 { #power-domain-cells = <0>; reg = <IMX8MN_POWER_DOMAIN_OTG1>;
power-domains = <&pgc_hsiomix>; }; pgc_gpumix: power-domain@2 {@@ -1076,7 +1100,7 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_otg1>;
power-domains = <&pgc_hsiomix>; status = "disabled"; };@@ -1094,7 +1118,6 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;@@ -1103,7 +1126,7 @@ gpmi: nand-controller@33002000 { compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;@@ -1175,5 +1198,6 @@ assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; clock-names = "main_clk";
power-domains = <&pgc_otg1>; };};
2.34.1
with commit bb6ea0fe9290 ("usb: ehci-mx6: move phy setup before register access") now in imx/master: Tested-by: Tim Harvey tharvey@gateworks.com #imx8mn-venice-gw7902
Best Regards,
Tim
On Wed, May 3, 2023 at 9:12 AM Tim Harvey tharvey@gateworks.com wrote:
On Thu, Apr 27, 2023 at 11:08 AM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Sync imx8mn.dtsi with Linux 6.3.
Signed-off-by: Fabio Estevam festevam@denx.de
arch/arm/dts/imx8mn.dtsi | 46 ++++++++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index cb2836bfbd95..9e0ddd6b7a32 100644 --- a/arch/arm/dts/imx8mn.dtsi +++ b/arch/arm/dts/imx8mn.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>;
cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>;@@ -295,6 +296,7 @@ sai2: sai@30020000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI2_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -309,6 +311,7 @@ sai3: sai@30030000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30030000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -323,6 +326,7 @@ sai5: sai@30050000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -339,6 +343,7 @@ sai6: sai@30060000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI6_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -396,6 +401,7 @@ sai7: sai@300b0000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x300b0000 0x10000>;
#sound-dai-cells = <0>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI7_IPG>, <&clk IMX8MN_CLK_DUMMY>,@@ -497,6 +503,8 @@ compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
nvmem-cells = <&tmu_calib>;nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; };@@ -551,7 +559,7 @@ reg = <0x30330000 0x10000>; };
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 { compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };@@ -563,23 +571,40 @@ #address-cells = <1>; #size-cells = <1>;
imx8mn_uid: unique-id@410 {
/** The register address below maps to the MX8M* Fusemap Description Table entries this way.* Assuming* reg = <ADDR SIZE>;* then* Fuse Address = (ADDR * 4) + 0x400* Note that if SIZE is greater than 4, then* each subsequent fuse is located at offset* +0x10 in Fusemap Description Table (e.g.* reg = <0x4 0x8> describes fuses 0x410 and* 0x420).*/imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; };
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
fec_mac_address: mac-address@90 {
tmu_calib: calib@3c { /* 0x4f0 */reg = <0x3c 4>;};fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; };
anatop: anatop@30360000 {compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop","syscon";
anatop: clock-controller@30360000 {compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>;#clock-cells = <1>; }; snvs: snvs@30370000 {@@ -662,7 +687,6 @@ pgc_otg1: power-domain@1 { #power-domain-cells = <0>; reg = <IMX8MN_POWER_DOMAIN_OTG1>;
power-domains = <&pgc_hsiomix>; }; pgc_gpumix: power-domain@2 {@@ -1076,7 +1100,7 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_otg1>;
power-domains = <&pgc_hsiomix>; status = "disabled"; };@@ -1094,7 +1118,6 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;@@ -1103,7 +1126,7 @@ gpmi: nand-controller@33002000 { compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;@@ -1175,5 +1198,6 @@ assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; clock-names = "main_clk";
power-domains = <&pgc_otg1>; };};
2.34.1
with commit bb6ea0fe9290 ("usb: ehci-mx6: move phy setup before register access") now in imx/master: Tested-by: Tim Harvey tharvey@gateworks.com #imx8mn-venice-gw7902
Stefano,
It doesn't look like this got picked up in your latest tree for some reason.
Best regards,
Tim
From: Fabio Estevam festevam@denx.de
Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
Signed-off-by: Fabio Estevam festevam@denx.de --- arch/arm/dts/imx8mp.dtsi | 374 ++++++++++++++++------- include/dt-bindings/clock/imx8mp-clock.h | 14 +- 2 files changed, 270 insertions(+), 118 deletions(-)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index bb916a0948a8..a237275ee017 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -123,6 +123,7 @@
A53_L2: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>; @@ -379,6 +380,8 @@ compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; };
@@ -411,7 +414,7 @@ reg = <0x30330000 0x10000>; };
- gpr: iomuxc-gpr@30340000 { + gpr: syscon@30340000 { compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -424,27 +427,44 @@ #address-cells = <1>; #size-cells = <1>;
- imx8mp_uid: unique-id@420 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = <ADDR SIZE>; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x8 0x8> describes fuses 0x420 and + * 0x430). + */ + imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ reg = <0x8 0x8>; };
- cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
- eth_mac1: mac-address@90 { + eth_mac1: mac-address@90 { /* 0x640 */ reg = <0x90 6>; };
- eth_mac2: mac-address@96 { + eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; }; + + tmu_calib: calib@264 { /* 0xd90-0xdc0 */ + reg = <0x264 0x10>; + }; };
- anatop: anatop@30360000 { - compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", - "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; };
snvs: snvs@30370000 { @@ -523,6 +543,7 @@ compatible = "fsl,imx8mp-gpc"; reg = <0x303a0000 0x1000>; interrupt-parent = <&gic>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>;
@@ -589,7 +610,7 @@ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; };
- pgc_hsiomix: power-domains@17 { + pgc_hsiomix: power-domain@17 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; clocks = <&clk IMX8MP_CLK_HSIO_AXI>, @@ -631,6 +652,14 @@ reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; }; + + pgc_mlmix: power-domain@24 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_MLMIX>; + clocks = <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>, + <&clk IMX8MP_CLK_NPU_ROOT>; + }; }; }; }; @@ -702,112 +731,129 @@ #size-cells = <1>; ranges;
- ecspi1: spi@30820000 { + spba-bus@30800000 { + compatible = "fsl,spba-bus", "simple-bus"; + reg = <0x30800000 0x100000>; #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, - <&clk IMX8MP_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + #size-cells = <1>; + ranges;
- ecspi2: spi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, - <&clk IMX8MP_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi1: spi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, + <&clk IMX8MP_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + };
- ecspi3: spi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, - <&clk IMX8MP_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi2: spi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, + <&clk IMX8MP_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + };
- uart1: serial@30860000 { - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_UART1_ROOT>, - <&clk IMX8MP_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi3: spi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, + <&clk IMX8MP_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + };
- uart3: serial@30880000 { - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_UART3_ROOT>, - <&clk IMX8MP_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart1: serial@30860000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_UART1_ROOT>, + <&clk IMX8MP_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + };
- uart2: serial@30890000 { - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_UART2_ROOT>, - <&clk IMX8MP_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart3: serial@30880000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_UART3_ROOT>, + <&clk IMX8MP_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + };
- flexcan1: can@308c0000 { - compatible = "fsl,imx8mp-flexcan"; - reg = <0x308c0000 0x10000>; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_IPG_ROOT>, - <&clk IMX8MP_CLK_CAN1_ROOT>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8MP_CLK_CAN1>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - fsl,stop-mode = <&gpr 0x10 4>; - status = "disabled"; - }; + uart2: serial@30890000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_UART2_ROOT>, + <&clk IMX8MP_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + };
- flexcan2: can@308d0000 { - compatible = "fsl,imx8mp-flexcan"; - reg = <0x308d0000 0x10000>; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_IPG_ROOT>, - <&clk IMX8MP_CLK_CAN2_ROOT>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8MP_CLK_CAN2>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - fsl,stop-mode = <&gpr 0x10 5>; - status = "disabled"; + flexcan1: can@308c0000 { + compatible = "fsl,imx8mp-flexcan"; + reg = <0x308c0000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN1_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&gpr 0x10 4>; + status = "disabled"; + }; + + flexcan2: can@308d0000 { + compatible = "fsl,imx8mp-flexcan"; + reg = <0x308d0000 0x10000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN2_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&gpr 0x10 5>; + status = "disabled"; + }; };
crypto: crypto@30900000 { @@ -1063,11 +1109,11 @@ noc_opp_table: opp-table { compatible = "operating-points-v2";
- opp-200M { + opp-200000000 { opp-hz = /bits/ 64 <200000000>; };
- opp-1000M { + opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; }; }; @@ -1080,10 +1126,35 @@ #size-cells = <1>; ranges;
+ lcdif2: display-controller@32e90000 { + compatible = "fsl,imx8mp-lcdif"; + reg = <0x32e90000 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_VIDEO_PLL1_REF_SEL>; + assigned-clock-rates = <0>, <1039500000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; + status = "disabled"; + + port { + lcdif2_to_ldb: endpoint { + remote-endpoint = <&ldb_from_lcdif2>; + }; + }; + }; + media_blk_ctrl: blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl", - "syscon"; + "simple-bus", "syscon"; reg = <0x32ec0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; power-domains = <&pgc_mediamix>, <&pgc_mipi_phy1>, <&pgc_mipi_phy1>, @@ -1128,6 +1199,44 @@ assigned-clock-rates = <500000000>, <200000000>;
#power-domain-cells = <1>; + + lvds_bridge: bridge@5c { + compatible = "fsl,imx8mp-ldb"; + clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + clock-names = "ldb"; + reg = <0x5c 0x4>, <0x128 0x4>; + reg-names = "ldb", "lvds"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ldb_from_lcdif2: endpoint { + remote-endpoint = <&lcdif2_to_ldb>; + }; + }; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + }; + }; + + port@2 { + reg = <2>; + + ldb_lvds_ch1: endpoint { + }; + }; + }; + }; };
pcie_phy: pcie-phy@32f00000 { @@ -1158,6 +1267,7 @@ <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; #power-domain-cells = <1>; + #clock-cells = <0>; }; };
@@ -1165,6 +1275,13 @@ compatible = "fsl,imx8mp-pcie"; reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; reg-names = "dbi", "config"; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -1223,6 +1340,28 @@ power-domains = <&pgc_gpu2d>; };
+ vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mm-vpu-g1"; + reg = <0x38300000 0x10000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>; + power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <500000000>; + power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; + }; + vpumix_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>; @@ -1234,6 +1373,9 @@ <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; clock-names = "g1", "g2", "vc8000e"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>, <600000000>; interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; @@ -1279,7 +1421,7 @@ reg = <0x32f10100 0x8>, <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, - <&clk IMX8MP_CLK_USB_ROOT>; + <&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; @@ -1292,9 +1434,9 @@ usb_dwc3_0: usb@38100000 { compatible = "snps,dwc3"; reg = <0x38100000 0x10000>; - clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>, - <&clk IMX8MP_CLK_USB_ROOT>; + <&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy0>, <&usb3_phy0>; @@ -1321,7 +1463,7 @@ reg = <0x32f10108 0x8>, <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, - <&clk IMX8MP_CLK_USB_ROOT>; + <&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; @@ -1334,9 +1476,9 @@ usb_dwc3_1: usb@38200000 { compatible = "snps,dwc3"; reg = <0x38200000 0x10000>; - clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>, - <&clk IMX8MP_CLK_USB_ROOT>; + <&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy1>, <&usb3_phy1>; diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde89..3f28ce685f41 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,18 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319 - -#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 +#define IMX8MP_CLK_END 330
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
On Thu, Apr 27, 2023 at 1:09 PM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
Signed-off-by: Fabio Estevam festevam@denx.de
Reviewed-by: Adam Ford aford173@gmail.com
arch/arm/dts/imx8mp.dtsi | 374 ++++++++++++++++------- include/dt-bindings/clock/imx8mp-clock.h | 14 +- 2 files changed, 270 insertions(+), 118 deletions(-)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index bb916a0948a8..a237275ee017 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -123,6 +123,7 @@
A53_L2: l2-cache0 { compatible = "cache";
cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>;@@ -379,6 +380,8 @@ compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
nvmem-cells = <&tmu_calib>;nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; };@@ -411,7 +414,7 @@ reg = <0x30330000 0x10000>; };
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 { compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };@@ -424,27 +427,44 @@ #address-cells = <1>; #size-cells = <1>;
imx8mp_uid: unique-id@420 {
/** The register address below maps to the MX8M* Fusemap Description Table entries this way.* Assuming* reg = <ADDR SIZE>;* then* Fuse Address = (ADDR * 4) + 0x400* Note that if SIZE is greater than 4, then* each subsequent fuse is located at offset* +0x10 in Fusemap Description Table (e.g.* reg = <0x8 0x8> describes fuses 0x420 and* 0x430).*/imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ reg = <0x8 0x8>; };
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
eth_mac1: mac-address@90 {
eth_mac1: mac-address@90 { /* 0x640 */ reg = <0x90 6>; };
eth_mac2: mac-address@96 {
eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; };tmu_calib: calib@264 { /* 0xd90-0xdc0 */reg = <0x264 0x10>;}; };
anatop: anatop@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop","syscon";
anatop: clock-controller@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>;#clock-cells = <1>; }; snvs: snvs@30370000 {@@ -523,6 +543,7 @@ compatible = "fsl,imx8mp-gpc"; reg = <0x303a0000 0x1000>; interrupt-parent = <&gic>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>;@@ -589,7 +610,7 @@ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; };
pgc_hsiomix: power-domains@17 {
pgc_hsiomix: power-domain@17 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; clocks = <&clk IMX8MP_CLK_HSIO_AXI>,@@ -631,6 +652,14 @@ reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; };
pgc_mlmix: power-domain@24 {#power-domain-cells = <0>;reg = <IMX8MP_POWER_DOMAIN_MLMIX>;clocks = <&clk IMX8MP_CLK_ML_AXI>,<&clk IMX8MP_CLK_ML_AHB>,<&clk IMX8MP_CLK_NPU_ROOT>;}; }; }; };@@ -702,112 +731,129 @@ #size-cells = <1>; ranges;
ecspi1: spi@30820000 {
spba-bus@30800000 {compatible = "fsl,spba-bus", "simple-bus";reg = <0x30800000 0x100000>; #address-cells = <1>;
#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
#size-cells = <1>;ranges;
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi1: spi@30820000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";}; }; crypto: crypto@30900000 {@@ -1063,11 +1109,11 @@ noc_opp_table: opp-table { compatible = "operating-points-v2";
opp-200M {
opp-200000000 { opp-hz = /bits/ 64 <200000000>; };
opp-1000M {
opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; }; };@@ -1080,10 +1126,35 @@ #size-cells = <1>; ranges;
lcdif2: display-controller@32e90000 {compatible = "fsl,imx8mp-lcdif";reg = <0x32e90000 0x10000>;interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;clock-names = "pix", "axi", "disp_axi";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,<&clk IMX8MP_VIDEO_PLL1>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,<&clk IMX8MP_VIDEO_PLL1_REF_SEL>;assigned-clock-rates = <0>, <1039500000>;power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;status = "disabled";port {lcdif2_to_ldb: endpoint {remote-endpoint = <&ldb_from_lcdif2>;};};};media_blk_ctrl: blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl",
"syscon";
"simple-bus", "syscon"; reg = <0x32ec0000 0x10000>;#address-cells = <1>;#size-cells = <1>; power-domains = <&pgc_mediamix>, <&pgc_mipi_phy1>, <&pgc_mipi_phy1>,@@ -1128,6 +1199,44 @@ assigned-clock-rates = <500000000>, <200000000>;
#power-domain-cells = <1>;
lvds_bridge: bridge@5c {compatible = "fsl,imx8mp-ldb";clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;clock-names = "ldb";reg = <0x5c 0x4>, <0x128 0x4>;reg-names = "ldb", "lvds";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;ldb_from_lcdif2: endpoint {remote-endpoint = <&lcdif2_to_ldb>;};};port@1 {reg = <1>;ldb_lvds_ch0: endpoint {};};port@2 {reg = <2>;ldb_lvds_ch1: endpoint {};};};}; }; pcie_phy: pcie-phy@32f00000 {@@ -1158,6 +1267,7 @@ <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; #power-domain-cells = <1>;
#clock-cells = <0>; }; };@@ -1165,6 +1275,13 @@ compatible = "fsl,imx8mp-pcie"; reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; reg-names = "dbi", "config";
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,<&clk IMX8MP_CLK_HSIO_AXI>,<&clk IMX8MP_CLK_PCIE_ROOT>;clock-names = "pcie", "pcie_bus", "pcie_aux";assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;assigned-clock-rates = <10000000>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; #address-cells = <3>; #size-cells = <2>; device_type = "pci";@@ -1223,6 +1340,28 @@ power-domains = <&pgc_gpu2d>; };
vpu_g1: video-codec@38300000 {compatible = "nxp,imx8mm-vpu-g1";reg = <0x38300000 0x10000>;interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;};vpu_g2: video-codec@38310000 {compatible = "nxp,imx8mq-vpu-g2";reg = <0x38310000 0x10000>;interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;assigned-clock-rates = <500000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;};vpumix_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>;@@ -1234,6 +1373,9 @@ <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; clock-names = "g1", "g2", "vc8000e";
assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>, <600000000>; interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;@@ -1279,7 +1421,7 @@ reg = <0x32f10100 0x8>, <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1292,9 +1434,9 @@ usb_dwc3_0: usb@38100000 { compatible = "snps,dwc3"; reg = <0x38100000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy0>, <&usb3_phy0>;@@ -1321,7 +1463,7 @@ reg = <0x32f10108 0x8>, <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1334,9 +1476,9 @@ usb_dwc3_1: usb@38200000 { compatible = "snps,dwc3"; reg = <0x38200000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy1>, <&usb3_phy1>;diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde89..3f28ce685f41 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,18 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319
-#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 +#define IMX8MP_CLK_END 330
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
2.34.1
On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
Signed-off-by: Fabio Estevam festevam@denx.de
arch/arm/dts/imx8mp.dtsi | 374 ++++++++++++++++------- include/dt-bindings/clock/imx8mp-clock.h | 14 +- 2 files changed, 270 insertions(+), 118 deletions(-)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index bb916a0948a8..a237275ee017 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -123,6 +123,7 @@
A53_L2: l2-cache0 { compatible = "cache";
cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>;@@ -379,6 +380,8 @@ compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
nvmem-cells = <&tmu_calib>;nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; };@@ -411,7 +414,7 @@ reg = <0x30330000 0x10000>; };
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 { compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };@@ -424,27 +427,44 @@ #address-cells = <1>; #size-cells = <1>;
imx8mp_uid: unique-id@420 {
/** The register address below maps to the MX8M* Fusemap Description Table entries this way.* Assuming* reg = <ADDR SIZE>;* then* Fuse Address = (ADDR * 4) + 0x400* Note that if SIZE is greater than 4, then* each subsequent fuse is located at offset* +0x10 in Fusemap Description Table (e.g.* reg = <0x8 0x8> describes fuses 0x420 and* 0x430).*/imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ reg = <0x8 0x8>; };
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
eth_mac1: mac-address@90 {
eth_mac1: mac-address@90 { /* 0x640 */ reg = <0x90 6>; };
eth_mac2: mac-address@96 {
eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; };tmu_calib: calib@264 { /* 0xd90-0xdc0 */reg = <0x264 0x10>;}; };
anatop: anatop@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop","syscon";
anatop: clock-controller@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>;#clock-cells = <1>; }; snvs: snvs@30370000 {@@ -523,6 +543,7 @@ compatible = "fsl,imx8mp-gpc"; reg = <0x303a0000 0x1000>; interrupt-parent = <&gic>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>;@@ -589,7 +610,7 @@ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; };
pgc_hsiomix: power-domains@17 {
pgc_hsiomix: power-domain@17 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; clocks = <&clk IMX8MP_CLK_HSIO_AXI>,@@ -631,6 +652,14 @@ reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; };
pgc_mlmix: power-domain@24 {#power-domain-cells = <0>;reg = <IMX8MP_POWER_DOMAIN_MLMIX>;clocks = <&clk IMX8MP_CLK_ML_AXI>,<&clk IMX8MP_CLK_ML_AHB>,<&clk IMX8MP_CLK_NPU_ROOT>;}; }; }; };@@ -702,112 +731,129 @@ #size-cells = <1>; ranges;
ecspi1: spi@30820000 {
spba-bus@30800000 {compatible = "fsl,spba-bus", "simple-bus";reg = <0x30800000 0x100000>; #address-cells = <1>;
#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
#size-cells = <1>;ranges;
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi1: spi@30820000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";}; }; crypto: crypto@30900000 {@@ -1063,11 +1109,11 @@ noc_opp_table: opp-table { compatible = "operating-points-v2";
opp-200M {
opp-200000000 { opp-hz = /bits/ 64 <200000000>; };
opp-1000M {
opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; }; };@@ -1080,10 +1126,35 @@ #size-cells = <1>; ranges;
lcdif2: display-controller@32e90000 {compatible = "fsl,imx8mp-lcdif";reg = <0x32e90000 0x10000>;interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;clock-names = "pix", "axi", "disp_axi";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,<&clk IMX8MP_VIDEO_PLL1>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,<&clk IMX8MP_VIDEO_PLL1_REF_SEL>;assigned-clock-rates = <0>, <1039500000>;power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;status = "disabled";port {lcdif2_to_ldb: endpoint {remote-endpoint = <&ldb_from_lcdif2>;};};};media_blk_ctrl: blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl",
"syscon";
"simple-bus", "syscon"; reg = <0x32ec0000 0x10000>;#address-cells = <1>;#size-cells = <1>; power-domains = <&pgc_mediamix>, <&pgc_mipi_phy1>, <&pgc_mipi_phy1>,@@ -1128,6 +1199,44 @@ assigned-clock-rates = <500000000>, <200000000>;
#power-domain-cells = <1>;
lvds_bridge: bridge@5c {compatible = "fsl,imx8mp-ldb";clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;clock-names = "ldb";reg = <0x5c 0x4>, <0x128 0x4>;reg-names = "ldb", "lvds";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;ldb_from_lcdif2: endpoint {remote-endpoint = <&lcdif2_to_ldb>;};};port@1 {reg = <1>;ldb_lvds_ch0: endpoint {};};port@2 {reg = <2>;ldb_lvds_ch1: endpoint {};};};}; }; pcie_phy: pcie-phy@32f00000 {@@ -1158,6 +1267,7 @@ <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; #power-domain-cells = <1>;
#clock-cells = <0>; }; };@@ -1165,6 +1275,13 @@ compatible = "fsl,imx8mp-pcie"; reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; reg-names = "dbi", "config";
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,<&clk IMX8MP_CLK_HSIO_AXI>,<&clk IMX8MP_CLK_PCIE_ROOT>;clock-names = "pcie", "pcie_bus", "pcie_aux";assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;assigned-clock-rates = <10000000>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; #address-cells = <3>; #size-cells = <2>; device_type = "pci";@@ -1223,6 +1340,28 @@ power-domains = <&pgc_gpu2d>; };
vpu_g1: video-codec@38300000 {compatible = "nxp,imx8mm-vpu-g1";reg = <0x38300000 0x10000>;interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;};vpu_g2: video-codec@38310000 {compatible = "nxp,imx8mq-vpu-g2";reg = <0x38310000 0x10000>;interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;assigned-clock-rates = <500000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;};vpumix_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>;@@ -1234,6 +1373,9 @@ <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; clock-names = "g1", "g2", "vc8000e";
assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>, <600000000>; interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;@@ -1279,7 +1421,7 @@ reg = <0x32f10100 0x8>, <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1292,9 +1434,9 @@ usb_dwc3_0: usb@38100000 { compatible = "snps,dwc3"; reg = <0x38100000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy0>, <&usb3_phy0>;@@ -1321,7 +1463,7 @@ reg = <0x32f10108 0x8>, <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1334,9 +1476,9 @@ usb_dwc3_1: usb@38200000 { compatible = "snps,dwc3"; reg = <0x38200000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy1>, <&usb3_phy1>;diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde89..3f28ce685f41 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,18 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319
-#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 +#define IMX8MP_CLK_END 330
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
2.34.1
Tested-by: Tim Harvey tharvey@gateworks.com #imx8mp-venice-gw74xx
On Wed, May 3, 2023 at 9:11 AM Tim Harvey tharvey@gateworks.com wrote:
On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
Signed-off-by: Fabio Estevam festevam@denx.de
arch/arm/dts/imx8mp.dtsi | 374 ++++++++++++++++------- include/dt-bindings/clock/imx8mp-clock.h | 14 +- 2 files changed, 270 insertions(+), 118 deletions(-)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index bb916a0948a8..a237275ee017 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -123,6 +123,7 @@
A53_L2: l2-cache0 { compatible = "cache";
cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>;@@ -379,6 +380,8 @@ compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
nvmem-cells = <&tmu_calib>;nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; };@@ -411,7 +414,7 @@ reg = <0x30330000 0x10000>; };
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 { compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };@@ -424,27 +427,44 @@ #address-cells = <1>; #size-cells = <1>;
imx8mp_uid: unique-id@420 {
/** The register address below maps to the MX8M* Fusemap Description Table entries this way.* Assuming* reg = <ADDR SIZE>;* then* Fuse Address = (ADDR * 4) + 0x400* Note that if SIZE is greater than 4, then* each subsequent fuse is located at offset* +0x10 in Fusemap Description Table (e.g.* reg = <0x8 0x8> describes fuses 0x420 and* 0x430).*/imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ reg = <0x8 0x8>; };
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
eth_mac1: mac-address@90 {
eth_mac1: mac-address@90 { /* 0x640 */ reg = <0x90 6>; };
eth_mac2: mac-address@96 {
eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; };tmu_calib: calib@264 { /* 0xd90-0xdc0 */reg = <0x264 0x10>;}; };
anatop: anatop@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop","syscon";
anatop: clock-controller@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>;#clock-cells = <1>; }; snvs: snvs@30370000 {@@ -523,6 +543,7 @@ compatible = "fsl,imx8mp-gpc"; reg = <0x303a0000 0x1000>; interrupt-parent = <&gic>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>;@@ -589,7 +610,7 @@ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; };
pgc_hsiomix: power-domains@17 {
pgc_hsiomix: power-domain@17 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; clocks = <&clk IMX8MP_CLK_HSIO_AXI>,@@ -631,6 +652,14 @@ reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; };
pgc_mlmix: power-domain@24 {#power-domain-cells = <0>;reg = <IMX8MP_POWER_DOMAIN_MLMIX>;clocks = <&clk IMX8MP_CLK_ML_AXI>,<&clk IMX8MP_CLK_ML_AHB>,<&clk IMX8MP_CLK_NPU_ROOT>;}; }; }; };@@ -702,112 +731,129 @@ #size-cells = <1>; ranges;
ecspi1: spi@30820000 {
spba-bus@30800000 {compatible = "fsl,spba-bus", "simple-bus";reg = <0x30800000 0x100000>; #address-cells = <1>;
#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
#size-cells = <1>;ranges;
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi1: spi@30820000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";}; }; crypto: crypto@30900000 {@@ -1063,11 +1109,11 @@ noc_opp_table: opp-table { compatible = "operating-points-v2";
opp-200M {
opp-200000000 { opp-hz = /bits/ 64 <200000000>; };
opp-1000M {
opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; }; };@@ -1080,10 +1126,35 @@ #size-cells = <1>; ranges;
lcdif2: display-controller@32e90000 {compatible = "fsl,imx8mp-lcdif";reg = <0x32e90000 0x10000>;interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;clock-names = "pix", "axi", "disp_axi";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,<&clk IMX8MP_VIDEO_PLL1>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,<&clk IMX8MP_VIDEO_PLL1_REF_SEL>;assigned-clock-rates = <0>, <1039500000>;power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;status = "disabled";port {lcdif2_to_ldb: endpoint {remote-endpoint = <&ldb_from_lcdif2>;};};};media_blk_ctrl: blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl",
"syscon";
"simple-bus", "syscon"; reg = <0x32ec0000 0x10000>;#address-cells = <1>;#size-cells = <1>; power-domains = <&pgc_mediamix>, <&pgc_mipi_phy1>, <&pgc_mipi_phy1>,@@ -1128,6 +1199,44 @@ assigned-clock-rates = <500000000>, <200000000>;
#power-domain-cells = <1>;
lvds_bridge: bridge@5c {compatible = "fsl,imx8mp-ldb";clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;clock-names = "ldb";reg = <0x5c 0x4>, <0x128 0x4>;reg-names = "ldb", "lvds";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;ldb_from_lcdif2: endpoint {remote-endpoint = <&lcdif2_to_ldb>;};};port@1 {reg = <1>;ldb_lvds_ch0: endpoint {};};port@2 {reg = <2>;ldb_lvds_ch1: endpoint {};};};}; }; pcie_phy: pcie-phy@32f00000 {@@ -1158,6 +1267,7 @@ <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; #power-domain-cells = <1>;
#clock-cells = <0>; }; };@@ -1165,6 +1275,13 @@ compatible = "fsl,imx8mp-pcie"; reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; reg-names = "dbi", "config";
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,<&clk IMX8MP_CLK_HSIO_AXI>,<&clk IMX8MP_CLK_PCIE_ROOT>;clock-names = "pcie", "pcie_bus", "pcie_aux";assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;assigned-clock-rates = <10000000>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; #address-cells = <3>; #size-cells = <2>; device_type = "pci";@@ -1223,6 +1340,28 @@ power-domains = <&pgc_gpu2d>; };
vpu_g1: video-codec@38300000 {compatible = "nxp,imx8mm-vpu-g1";reg = <0x38300000 0x10000>;interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;};vpu_g2: video-codec@38310000 {compatible = "nxp,imx8mq-vpu-g2";reg = <0x38310000 0x10000>;interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;assigned-clock-rates = <500000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;};vpumix_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>;@@ -1234,6 +1373,9 @@ <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; clock-names = "g1", "g2", "vc8000e";
assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>, <600000000>; interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;@@ -1279,7 +1421,7 @@ reg = <0x32f10100 0x8>, <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1292,9 +1434,9 @@ usb_dwc3_0: usb@38100000 { compatible = "snps,dwc3"; reg = <0x38100000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy0>, <&usb3_phy0>;@@ -1321,7 +1463,7 @@ reg = <0x32f10108 0x8>, <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1334,9 +1476,9 @@ usb_dwc3_1: usb@38200000 { compatible = "snps,dwc3"; reg = <0x38200000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy1>, <&usb3_phy1>;diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde89..3f28ce685f41 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,18 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319
-#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 +#define IMX8MP_CLK_END 330
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
2.34.1
Tested-by: Tim Harvey tharvey@gateworks.com #imx8mp-venice-gw74xx
Fabio,
Apparently I didn't do a very good job of testing this. This patch is causing imx8mp-venice-* and imx8mp-evk boards to no longer boot with no SPL banner. The specific change that causes breakage is the one that encapsulates the spi/uart/flexcan children with spba-bus@30800000.
Hopefully someone else can verify the same findings and speculate as to what might cause this to break the SPL?
Best Regards,
Tim
On Fri, May 19, 2023 at 5:19 PM Tim Harvey tharvey@gateworks.com wrote:
On Wed, May 3, 2023 at 9:11 AM Tim Harvey tharvey@gateworks.com wrote:
On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
Signed-off-by: Fabio Estevam festevam@denx.de
arch/arm/dts/imx8mp.dtsi | 374 ++++++++++++++++------- include/dt-bindings/clock/imx8mp-clock.h | 14 +- 2 files changed, 270 insertions(+), 118 deletions(-)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index bb916a0948a8..a237275ee017 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -123,6 +123,7 @@
A53_L2: l2-cache0 { compatible = "cache";
cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>;@@ -379,6 +380,8 @@ compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
nvmem-cells = <&tmu_calib>;nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; };@@ -411,7 +414,7 @@ reg = <0x30330000 0x10000>; };
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 { compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };@@ -424,27 +427,44 @@ #address-cells = <1>; #size-cells = <1>;
imx8mp_uid: unique-id@420 {
/** The register address below maps to the MX8M* Fusemap Description Table entries this way.* Assuming* reg = <ADDR SIZE>;* then* Fuse Address = (ADDR * 4) + 0x400* Note that if SIZE is greater than 4, then* each subsequent fuse is located at offset* +0x10 in Fusemap Description Table (e.g.* reg = <0x8 0x8> describes fuses 0x420 and* 0x430).*/imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ reg = <0x8 0x8>; };
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
eth_mac1: mac-address@90 {
eth_mac1: mac-address@90 { /* 0x640 */ reg = <0x90 6>; };
eth_mac2: mac-address@96 {
eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; };tmu_calib: calib@264 { /* 0xd90-0xdc0 */reg = <0x264 0x10>;}; };
anatop: anatop@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop","syscon";
anatop: clock-controller@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>;#clock-cells = <1>; }; snvs: snvs@30370000 {@@ -523,6 +543,7 @@ compatible = "fsl,imx8mp-gpc"; reg = <0x303a0000 0x1000>; interrupt-parent = <&gic>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>;@@ -589,7 +610,7 @@ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; };
pgc_hsiomix: power-domains@17 {
pgc_hsiomix: power-domain@17 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; clocks = <&clk IMX8MP_CLK_HSIO_AXI>,@@ -631,6 +652,14 @@ reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; };
pgc_mlmix: power-domain@24 {#power-domain-cells = <0>;reg = <IMX8MP_POWER_DOMAIN_MLMIX>;clocks = <&clk IMX8MP_CLK_ML_AXI>,<&clk IMX8MP_CLK_ML_AHB>,<&clk IMX8MP_CLK_NPU_ROOT>;}; }; }; };@@ -702,112 +731,129 @@ #size-cells = <1>; ranges;
ecspi1: spi@30820000 {
spba-bus@30800000 {compatible = "fsl,spba-bus", "simple-bus";reg = <0x30800000 0x100000>; #address-cells = <1>;
#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
#size-cells = <1>;ranges;
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi1: spi@30820000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";}; }; crypto: crypto@30900000 {@@ -1063,11 +1109,11 @@ noc_opp_table: opp-table { compatible = "operating-points-v2";
opp-200M {
opp-200000000 { opp-hz = /bits/ 64 <200000000>; };
opp-1000M {
opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; }; };@@ -1080,10 +1126,35 @@ #size-cells = <1>; ranges;
lcdif2: display-controller@32e90000 {compatible = "fsl,imx8mp-lcdif";reg = <0x32e90000 0x10000>;interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;clock-names = "pix", "axi", "disp_axi";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,<&clk IMX8MP_VIDEO_PLL1>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,<&clk IMX8MP_VIDEO_PLL1_REF_SEL>;assigned-clock-rates = <0>, <1039500000>;power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;status = "disabled";port {lcdif2_to_ldb: endpoint {remote-endpoint = <&ldb_from_lcdif2>;};};};media_blk_ctrl: blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl",
"syscon";
"simple-bus", "syscon"; reg = <0x32ec0000 0x10000>;#address-cells = <1>;#size-cells = <1>; power-domains = <&pgc_mediamix>, <&pgc_mipi_phy1>, <&pgc_mipi_phy1>,@@ -1128,6 +1199,44 @@ assigned-clock-rates = <500000000>, <200000000>;
#power-domain-cells = <1>;
lvds_bridge: bridge@5c {compatible = "fsl,imx8mp-ldb";clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;clock-names = "ldb";reg = <0x5c 0x4>, <0x128 0x4>;reg-names = "ldb", "lvds";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;ldb_from_lcdif2: endpoint {remote-endpoint = <&lcdif2_to_ldb>;};};port@1 {reg = <1>;ldb_lvds_ch0: endpoint {};};port@2 {reg = <2>;ldb_lvds_ch1: endpoint {};};};}; }; pcie_phy: pcie-phy@32f00000 {@@ -1158,6 +1267,7 @@ <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; #power-domain-cells = <1>;
#clock-cells = <0>; }; };@@ -1165,6 +1275,13 @@ compatible = "fsl,imx8mp-pcie"; reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; reg-names = "dbi", "config";
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,<&clk IMX8MP_CLK_HSIO_AXI>,<&clk IMX8MP_CLK_PCIE_ROOT>;clock-names = "pcie", "pcie_bus", "pcie_aux";assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;assigned-clock-rates = <10000000>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; #address-cells = <3>; #size-cells = <2>; device_type = "pci";@@ -1223,6 +1340,28 @@ power-domains = <&pgc_gpu2d>; };
vpu_g1: video-codec@38300000 {compatible = "nxp,imx8mm-vpu-g1";reg = <0x38300000 0x10000>;interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;};vpu_g2: video-codec@38310000 {compatible = "nxp,imx8mq-vpu-g2";reg = <0x38310000 0x10000>;interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;assigned-clock-rates = <500000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;};vpumix_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>;@@ -1234,6 +1373,9 @@ <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; clock-names = "g1", "g2", "vc8000e";
assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>, <600000000>; interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;@@ -1279,7 +1421,7 @@ reg = <0x32f10100 0x8>, <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1292,9 +1434,9 @@ usb_dwc3_0: usb@38100000 { compatible = "snps,dwc3"; reg = <0x38100000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy0>, <&usb3_phy0>;@@ -1321,7 +1463,7 @@ reg = <0x32f10108 0x8>, <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1334,9 +1476,9 @@ usb_dwc3_1: usb@38200000 { compatible = "snps,dwc3"; reg = <0x38200000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy1>, <&usb3_phy1>;diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde89..3f28ce685f41 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,18 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319
-#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 +#define IMX8MP_CLK_END 330
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
2.34.1
Tested-by: Tim Harvey tharvey@gateworks.com #imx8mp-venice-gw74xx
Fabio,
Apparently I didn't do a very good job of testing this. This patch is causing imx8mp-venice-* and imx8mp-evk boards to no longer boot with no SPL banner. The specific change that causes breakage is the one that encapsulates the spi/uart/flexcan children with spba-bus@30800000.
The SPI, UART, and Flexcan are part of the spba-bus.
We'll need to add the spba bus to imx8mp-u-boot.dtsi. Since it had no node name, it'll have to fall under aip3.
Try this:
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index 18d1728e1d..0e6811b129 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -44,6 +44,10 @@
&aips3 { bootph-pre-ram; + + spba-bus@30800000 { + bootph-pre-ram; + }; };
&iomuxc {
Hopefully someone else can verify the same findings and speculate as to what might cause this to break the SPL?
Best Regards,
Tim
On Fri, May 19, 2023 at 3:27 PM Adam Ford aford173@gmail.com wrote:
On Fri, May 19, 2023 at 5:19 PM Tim Harvey tharvey@gateworks.com wrote:
On Wed, May 3, 2023 at 9:11 AM Tim Harvey tharvey@gateworks.com wrote:
On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
Signed-off-by: Fabio Estevam festevam@denx.de
arch/arm/dts/imx8mp.dtsi | 374 ++++++++++++++++------- include/dt-bindings/clock/imx8mp-clock.h | 14 +- 2 files changed, 270 insertions(+), 118 deletions(-)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index bb916a0948a8..a237275ee017 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -123,6 +123,7 @@
A53_L2: l2-cache0 { compatible = "cache";
cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>;@@ -379,6 +380,8 @@ compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
nvmem-cells = <&tmu_calib>;nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; };@@ -411,7 +414,7 @@ reg = <0x30330000 0x10000>; };
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 { compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };@@ -424,27 +427,44 @@ #address-cells = <1>; #size-cells = <1>;
imx8mp_uid: unique-id@420 {
/** The register address below maps to the MX8M* Fusemap Description Table entries this way.* Assuming* reg = <ADDR SIZE>;* then* Fuse Address = (ADDR * 4) + 0x400* Note that if SIZE is greater than 4, then* each subsequent fuse is located at offset* +0x10 in Fusemap Description Table (e.g.* reg = <0x8 0x8> describes fuses 0x420 and* 0x430).*/imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ reg = <0x8 0x8>; };
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
eth_mac1: mac-address@90 {
eth_mac1: mac-address@90 { /* 0x640 */ reg = <0x90 6>; };
eth_mac2: mac-address@96 {
eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; };tmu_calib: calib@264 { /* 0xd90-0xdc0 */reg = <0x264 0x10>;}; };
anatop: anatop@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop","syscon";
anatop: clock-controller@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>;#clock-cells = <1>; }; snvs: snvs@30370000 {@@ -523,6 +543,7 @@ compatible = "fsl,imx8mp-gpc"; reg = <0x303a0000 0x1000>; interrupt-parent = <&gic>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>;@@ -589,7 +610,7 @@ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; };
pgc_hsiomix: power-domains@17 {
pgc_hsiomix: power-domain@17 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; clocks = <&clk IMX8MP_CLK_HSIO_AXI>,@@ -631,6 +652,14 @@ reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; };
pgc_mlmix: power-domain@24 {#power-domain-cells = <0>;reg = <IMX8MP_POWER_DOMAIN_MLMIX>;clocks = <&clk IMX8MP_CLK_ML_AXI>,<&clk IMX8MP_CLK_ML_AHB>,<&clk IMX8MP_CLK_NPU_ROOT>;}; }; }; };@@ -702,112 +731,129 @@ #size-cells = <1>; ranges;
ecspi1: spi@30820000 {
spba-bus@30800000 {compatible = "fsl,spba-bus", "simple-bus";reg = <0x30800000 0x100000>; #address-cells = <1>;
#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
#size-cells = <1>;ranges;
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi1: spi@30820000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";}; }; crypto: crypto@30900000 {@@ -1063,11 +1109,11 @@ noc_opp_table: opp-table { compatible = "operating-points-v2";
opp-200M {
opp-200000000 { opp-hz = /bits/ 64 <200000000>; };
opp-1000M {
opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; }; };@@ -1080,10 +1126,35 @@ #size-cells = <1>; ranges;
lcdif2: display-controller@32e90000 {compatible = "fsl,imx8mp-lcdif";reg = <0x32e90000 0x10000>;interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;clock-names = "pix", "axi", "disp_axi";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,<&clk IMX8MP_VIDEO_PLL1>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,<&clk IMX8MP_VIDEO_PLL1_REF_SEL>;assigned-clock-rates = <0>, <1039500000>;power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;status = "disabled";port {lcdif2_to_ldb: endpoint {remote-endpoint = <&ldb_from_lcdif2>;};};};media_blk_ctrl: blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl",
"syscon";
"simple-bus", "syscon"; reg = <0x32ec0000 0x10000>;#address-cells = <1>;#size-cells = <1>; power-domains = <&pgc_mediamix>, <&pgc_mipi_phy1>, <&pgc_mipi_phy1>,@@ -1128,6 +1199,44 @@ assigned-clock-rates = <500000000>, <200000000>;
#power-domain-cells = <1>;
lvds_bridge: bridge@5c {compatible = "fsl,imx8mp-ldb";clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;clock-names = "ldb";reg = <0x5c 0x4>, <0x128 0x4>;reg-names = "ldb", "lvds";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;ldb_from_lcdif2: endpoint {remote-endpoint = <&lcdif2_to_ldb>;};};port@1 {reg = <1>;ldb_lvds_ch0: endpoint {};};port@2 {reg = <2>;ldb_lvds_ch1: endpoint {};};};}; }; pcie_phy: pcie-phy@32f00000 {@@ -1158,6 +1267,7 @@ <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; #power-domain-cells = <1>;
#clock-cells = <0>; }; };@@ -1165,6 +1275,13 @@ compatible = "fsl,imx8mp-pcie"; reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; reg-names = "dbi", "config";
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,<&clk IMX8MP_CLK_HSIO_AXI>,<&clk IMX8MP_CLK_PCIE_ROOT>;clock-names = "pcie", "pcie_bus", "pcie_aux";assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;assigned-clock-rates = <10000000>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; #address-cells = <3>; #size-cells = <2>; device_type = "pci";@@ -1223,6 +1340,28 @@ power-domains = <&pgc_gpu2d>; };
vpu_g1: video-codec@38300000 {compatible = "nxp,imx8mm-vpu-g1";reg = <0x38300000 0x10000>;interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;};vpu_g2: video-codec@38310000 {compatible = "nxp,imx8mq-vpu-g2";reg = <0x38310000 0x10000>;interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;assigned-clock-rates = <500000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;};vpumix_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>;@@ -1234,6 +1373,9 @@ <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; clock-names = "g1", "g2", "vc8000e";
assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>, <600000000>; interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;@@ -1279,7 +1421,7 @@ reg = <0x32f10100 0x8>, <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1292,9 +1434,9 @@ usb_dwc3_0: usb@38100000 { compatible = "snps,dwc3"; reg = <0x38100000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy0>, <&usb3_phy0>;@@ -1321,7 +1463,7 @@ reg = <0x32f10108 0x8>, <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1334,9 +1476,9 @@ usb_dwc3_1: usb@38200000 { compatible = "snps,dwc3"; reg = <0x38200000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy1>, <&usb3_phy1>;diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde89..3f28ce685f41 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,18 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319
-#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 +#define IMX8MP_CLK_END 330
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
2.34.1
Tested-by: Tim Harvey tharvey@gateworks.com #imx8mp-venice-gw74xx
Fabio,
Apparently I didn't do a very good job of testing this. This patch is causing imx8mp-venice-* and imx8mp-evk boards to no longer boot with no SPL banner. The specific change that causes breakage is the one that encapsulates the spi/uart/flexcan children with spba-bus@30800000.
The SPI, UART, and Flexcan are part of the spba-bus.
We'll need to add the spba bus to imx8mp-u-boot.dtsi. Since it had no node name, it'll have to fall under aip3.
Try this:
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index 18d1728e1d..0e6811b129 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -44,6 +44,10 @@
&aips3 { bootph-pre-ram;
spba-bus@30800000 {bootph-pre-ram;};};
&iomuxc {
Adam,
Yup... that's it! Thanks. Want to send a patch or want me to do it?
Best Regards,
Tim
On Fri, May 19, 2023 at 3:31 PM Tim Harvey tharvey@gateworks.com wrote:
On Fri, May 19, 2023 at 3:27 PM Adam Ford aford173@gmail.com wrote:
On Fri, May 19, 2023 at 5:19 PM Tim Harvey tharvey@gateworks.com wrote:
On Wed, May 3, 2023 at 9:11 AM Tim Harvey tharvey@gateworks.com wrote:
On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
Signed-off-by: Fabio Estevam festevam@denx.de
arch/arm/dts/imx8mp.dtsi | 374 ++++++++++++++++------- include/dt-bindings/clock/imx8mp-clock.h | 14 +- 2 files changed, 270 insertions(+), 118 deletions(-)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index bb916a0948a8..a237275ee017 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -123,6 +123,7 @@
A53_L2: l2-cache0 { compatible = "cache";
cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>;@@ -379,6 +380,8 @@ compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
nvmem-cells = <&tmu_calib>;nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; };@@ -411,7 +414,7 @@ reg = <0x30330000 0x10000>; };
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 { compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };@@ -424,27 +427,44 @@ #address-cells = <1>; #size-cells = <1>;
imx8mp_uid: unique-id@420 {
/** The register address below maps to the MX8M* Fusemap Description Table entries this way.* Assuming* reg = <ADDR SIZE>;* then* Fuse Address = (ADDR * 4) + 0x400* Note that if SIZE is greater than 4, then* each subsequent fuse is located at offset* +0x10 in Fusemap Description Table (e.g.* reg = <0x8 0x8> describes fuses 0x420 and* 0x430).*/imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ reg = <0x8 0x8>; };
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
eth_mac1: mac-address@90 {
eth_mac1: mac-address@90 { /* 0x640 */ reg = <0x90 6>; };
eth_mac2: mac-address@96 {
eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; };tmu_calib: calib@264 { /* 0xd90-0xdc0 */reg = <0x264 0x10>;}; };
anatop: anatop@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop","syscon";
anatop: clock-controller@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>;#clock-cells = <1>; }; snvs: snvs@30370000 {@@ -523,6 +543,7 @@ compatible = "fsl,imx8mp-gpc"; reg = <0x303a0000 0x1000>; interrupt-parent = <&gic>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>;@@ -589,7 +610,7 @@ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; };
pgc_hsiomix: power-domains@17 {
pgc_hsiomix: power-domain@17 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; clocks = <&clk IMX8MP_CLK_HSIO_AXI>,@@ -631,6 +652,14 @@ reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; };
pgc_mlmix: power-domain@24 {#power-domain-cells = <0>;reg = <IMX8MP_POWER_DOMAIN_MLMIX>;clocks = <&clk IMX8MP_CLK_ML_AXI>,<&clk IMX8MP_CLK_ML_AHB>,<&clk IMX8MP_CLK_NPU_ROOT>;}; }; }; };@@ -702,112 +731,129 @@ #size-cells = <1>; ranges;
ecspi1: spi@30820000 {
spba-bus@30800000 {compatible = "fsl,spba-bus", "simple-bus";reg = <0x30800000 0x100000>; #address-cells = <1>;
#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
#size-cells = <1>;ranges;
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi1: spi@30820000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";}; }; crypto: crypto@30900000 {@@ -1063,11 +1109,11 @@ noc_opp_table: opp-table { compatible = "operating-points-v2";
opp-200M {
opp-200000000 { opp-hz = /bits/ 64 <200000000>; };
opp-1000M {
opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; }; };@@ -1080,10 +1126,35 @@ #size-cells = <1>; ranges;
lcdif2: display-controller@32e90000 {compatible = "fsl,imx8mp-lcdif";reg = <0x32e90000 0x10000>;interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;clock-names = "pix", "axi", "disp_axi";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,<&clk IMX8MP_VIDEO_PLL1>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,<&clk IMX8MP_VIDEO_PLL1_REF_SEL>;assigned-clock-rates = <0>, <1039500000>;power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;status = "disabled";port {lcdif2_to_ldb: endpoint {remote-endpoint = <&ldb_from_lcdif2>;};};};media_blk_ctrl: blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl",
"syscon";
"simple-bus", "syscon"; reg = <0x32ec0000 0x10000>;#address-cells = <1>;#size-cells = <1>; power-domains = <&pgc_mediamix>, <&pgc_mipi_phy1>, <&pgc_mipi_phy1>,@@ -1128,6 +1199,44 @@ assigned-clock-rates = <500000000>, <200000000>;
#power-domain-cells = <1>;
lvds_bridge: bridge@5c {compatible = "fsl,imx8mp-ldb";clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;clock-names = "ldb";reg = <0x5c 0x4>, <0x128 0x4>;reg-names = "ldb", "lvds";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;ldb_from_lcdif2: endpoint {remote-endpoint = <&lcdif2_to_ldb>;};};port@1 {reg = <1>;ldb_lvds_ch0: endpoint {};};port@2 {reg = <2>;ldb_lvds_ch1: endpoint {};};};}; }; pcie_phy: pcie-phy@32f00000 {@@ -1158,6 +1267,7 @@ <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; #power-domain-cells = <1>;
#clock-cells = <0>; }; };@@ -1165,6 +1275,13 @@ compatible = "fsl,imx8mp-pcie"; reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; reg-names = "dbi", "config";
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,<&clk IMX8MP_CLK_HSIO_AXI>,<&clk IMX8MP_CLK_PCIE_ROOT>;clock-names = "pcie", "pcie_bus", "pcie_aux";assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;assigned-clock-rates = <10000000>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; #address-cells = <3>; #size-cells = <2>; device_type = "pci";@@ -1223,6 +1340,28 @@ power-domains = <&pgc_gpu2d>; };
vpu_g1: video-codec@38300000 {compatible = "nxp,imx8mm-vpu-g1";reg = <0x38300000 0x10000>;interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;};vpu_g2: video-codec@38310000 {compatible = "nxp,imx8mq-vpu-g2";reg = <0x38310000 0x10000>;interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;assigned-clock-rates = <500000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;};vpumix_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>;@@ -1234,6 +1373,9 @@ <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; clock-names = "g1", "g2", "vc8000e";
assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>, <600000000>; interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;@@ -1279,7 +1421,7 @@ reg = <0x32f10100 0x8>, <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1292,9 +1434,9 @@ usb_dwc3_0: usb@38100000 { compatible = "snps,dwc3"; reg = <0x38100000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy0>, <&usb3_phy0>;@@ -1321,7 +1463,7 @@ reg = <0x32f10108 0x8>, <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1334,9 +1476,9 @@ usb_dwc3_1: usb@38200000 { compatible = "snps,dwc3"; reg = <0x38200000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy1>, <&usb3_phy1>;diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde89..3f28ce685f41 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,18 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319
-#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 +#define IMX8MP_CLK_END 330
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
2.34.1
Tested-by: Tim Harvey tharvey@gateworks.com #imx8mp-venice-gw74xx
Fabio,
Apparently I didn't do a very good job of testing this. This patch is causing imx8mp-venice-* and imx8mp-evk boards to no longer boot with no SPL banner. The specific change that causes breakage is the one that encapsulates the spi/uart/flexcan children with spba-bus@30800000.
The SPI, UART, and Flexcan are part of the spba-bus.
We'll need to add the spba bus to imx8mp-u-boot.dtsi. Since it had no node name, it'll have to fall under aip3.
Try this:
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index 18d1728e1d..0e6811b129 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -44,6 +44,10 @@
&aips3 { bootph-pre-ram;
spba-bus@30800000 {bootph-pre-ram;};};
&iomuxc {
Adam,
Yup... that's it! Thanks. Want to send a patch or want me to do it?
Actually Fabio I think you should re-submit this patch with the required change to imx8mp-u-boot.dtsi included?
Tim
On Fri, May 19, 2023 at 5:34 PM Tim Harvey tharvey@gateworks.com wrote:
On Fri, May 19, 2023 at 3:31 PM Tim Harvey tharvey@gateworks.com wrote:
On Fri, May 19, 2023 at 3:27 PM Adam Ford aford173@gmail.com wrote:
On Fri, May 19, 2023 at 5:19 PM Tim Harvey tharvey@gateworks.com wrote:
On Wed, May 3, 2023 at 9:11 AM Tim Harvey tharvey@gateworks.com wrote:
On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
Signed-off-by: Fabio Estevam festevam@denx.de
arch/arm/dts/imx8mp.dtsi | 374 ++++++++++++++++------- include/dt-bindings/clock/imx8mp-clock.h | 14 +- 2 files changed, 270 insertions(+), 118 deletions(-)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index bb916a0948a8..a237275ee017 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -123,6 +123,7 @@
A53_L2: l2-cache0 { compatible = "cache";
cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>;@@ -379,6 +380,8 @@ compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
nvmem-cells = <&tmu_calib>;nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; };@@ -411,7 +414,7 @@ reg = <0x30330000 0x10000>; };
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 { compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };@@ -424,27 +427,44 @@ #address-cells = <1>; #size-cells = <1>;
imx8mp_uid: unique-id@420 {
/** The register address below maps to the MX8M* Fusemap Description Table entries this way.* Assuming* reg = <ADDR SIZE>;* then* Fuse Address = (ADDR * 4) + 0x400* Note that if SIZE is greater than 4, then* each subsequent fuse is located at offset* +0x10 in Fusemap Description Table (e.g.* reg = <0x8 0x8> describes fuses 0x420 and* 0x430).*/imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ reg = <0x8 0x8>; };
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
eth_mac1: mac-address@90 {
eth_mac1: mac-address@90 { /* 0x640 */ reg = <0x90 6>; };
eth_mac2: mac-address@96 {
eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; };tmu_calib: calib@264 { /* 0xd90-0xdc0 */reg = <0x264 0x10>;}; };
anatop: anatop@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop","syscon";
anatop: clock-controller@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>;#clock-cells = <1>; }; snvs: snvs@30370000 {@@ -523,6 +543,7 @@ compatible = "fsl,imx8mp-gpc"; reg = <0x303a0000 0x1000>; interrupt-parent = <&gic>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>;@@ -589,7 +610,7 @@ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; };
pgc_hsiomix: power-domains@17 {
pgc_hsiomix: power-domain@17 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; clocks = <&clk IMX8MP_CLK_HSIO_AXI>,@@ -631,6 +652,14 @@ reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; };
pgc_mlmix: power-domain@24 {#power-domain-cells = <0>;reg = <IMX8MP_POWER_DOMAIN_MLMIX>;clocks = <&clk IMX8MP_CLK_ML_AXI>,<&clk IMX8MP_CLK_ML_AHB>,<&clk IMX8MP_CLK_NPU_ROOT>;}; }; }; };@@ -702,112 +731,129 @@ #size-cells = <1>; ranges;
ecspi1: spi@30820000 {
spba-bus@30800000 {compatible = "fsl,spba-bus", "simple-bus";reg = <0x30800000 0x100000>; #address-cells = <1>;
#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
#size-cells = <1>;ranges;
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi1: spi@30820000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";}; }; crypto: crypto@30900000 {@@ -1063,11 +1109,11 @@ noc_opp_table: opp-table { compatible = "operating-points-v2";
opp-200M {
opp-200000000 { opp-hz = /bits/ 64 <200000000>; };
opp-1000M {
opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; }; };@@ -1080,10 +1126,35 @@ #size-cells = <1>; ranges;
lcdif2: display-controller@32e90000 {compatible = "fsl,imx8mp-lcdif";reg = <0x32e90000 0x10000>;interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;clock-names = "pix", "axi", "disp_axi";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,<&clk IMX8MP_VIDEO_PLL1>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,<&clk IMX8MP_VIDEO_PLL1_REF_SEL>;assigned-clock-rates = <0>, <1039500000>;power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;status = "disabled";port {lcdif2_to_ldb: endpoint {remote-endpoint = <&ldb_from_lcdif2>;};};};media_blk_ctrl: blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl",
"syscon";
"simple-bus", "syscon"; reg = <0x32ec0000 0x10000>;#address-cells = <1>;#size-cells = <1>; power-domains = <&pgc_mediamix>, <&pgc_mipi_phy1>, <&pgc_mipi_phy1>,@@ -1128,6 +1199,44 @@ assigned-clock-rates = <500000000>, <200000000>;
#power-domain-cells = <1>;
lvds_bridge: bridge@5c {compatible = "fsl,imx8mp-ldb";clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;clock-names = "ldb";reg = <0x5c 0x4>, <0x128 0x4>;reg-names = "ldb", "lvds";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;ldb_from_lcdif2: endpoint {remote-endpoint = <&lcdif2_to_ldb>;};};port@1 {reg = <1>;ldb_lvds_ch0: endpoint {};};port@2 {reg = <2>;ldb_lvds_ch1: endpoint {};};};}; }; pcie_phy: pcie-phy@32f00000 {@@ -1158,6 +1267,7 @@ <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; #power-domain-cells = <1>;
#clock-cells = <0>; }; };@@ -1165,6 +1275,13 @@ compatible = "fsl,imx8mp-pcie"; reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; reg-names = "dbi", "config";
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,<&clk IMX8MP_CLK_HSIO_AXI>,<&clk IMX8MP_CLK_PCIE_ROOT>;clock-names = "pcie", "pcie_bus", "pcie_aux";assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;assigned-clock-rates = <10000000>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; #address-cells = <3>; #size-cells = <2>; device_type = "pci";@@ -1223,6 +1340,28 @@ power-domains = <&pgc_gpu2d>; };
vpu_g1: video-codec@38300000 {compatible = "nxp,imx8mm-vpu-g1";reg = <0x38300000 0x10000>;interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;};vpu_g2: video-codec@38310000 {compatible = "nxp,imx8mq-vpu-g2";reg = <0x38310000 0x10000>;interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;assigned-clock-rates = <500000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;};vpumix_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>;@@ -1234,6 +1373,9 @@ <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; clock-names = "g1", "g2", "vc8000e";
assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>, <600000000>; interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;@@ -1279,7 +1421,7 @@ reg = <0x32f10100 0x8>, <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1292,9 +1434,9 @@ usb_dwc3_0: usb@38100000 { compatible = "snps,dwc3"; reg = <0x38100000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy0>, <&usb3_phy0>;@@ -1321,7 +1463,7 @@ reg = <0x32f10108 0x8>, <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1334,9 +1476,9 @@ usb_dwc3_1: usb@38200000 { compatible = "snps,dwc3"; reg = <0x38200000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy1>, <&usb3_phy1>;diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde89..3f28ce685f41 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,18 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319
-#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 +#define IMX8MP_CLK_END 330
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
2.34.1
Tested-by: Tim Harvey tharvey@gateworks.com #imx8mp-venice-gw74xx
Fabio,
Apparently I didn't do a very good job of testing this. This patch is causing imx8mp-venice-* and imx8mp-evk boards to no longer boot with no SPL banner. The specific change that causes breakage is the one that encapsulates the spi/uart/flexcan children with spba-bus@30800000.
The SPI, UART, and Flexcan are part of the spba-bus.
We'll need to add the spba bus to imx8mp-u-boot.dtsi. Since it had no node name, it'll have to fall under aip3.
Try this:
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index 18d1728e1d..0e6811b129 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -44,6 +44,10 @@
&aips3 { bootph-pre-ram;
spba-bus@30800000 {bootph-pre-ram;};};
&iomuxc {
Adam,
Yup... that's it! Thanks. Want to send a patch or want me to do it?
Actually Fabio I think you should re-submit this patch with the required change to imx8mp-u-boot.dtsi included?
I was just about to say the same thing.
adam
Tim
On Fri, May 19, 2023 at 3:35 PM Adam Ford aford173@gmail.com wrote:
On Fri, May 19, 2023 at 5:34 PM Tim Harvey tharvey@gateworks.com wrote:
On Fri, May 19, 2023 at 3:31 PM Tim Harvey tharvey@gateworks.com wrote:
On Fri, May 19, 2023 at 3:27 PM Adam Ford aford173@gmail.com wrote:
On Fri, May 19, 2023 at 5:19 PM Tim Harvey tharvey@gateworks.com wrote:
On Wed, May 3, 2023 at 9:11 AM Tim Harvey tharvey@gateworks.com wrote:
On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam festevam@gmail.com wrote: > > From: Fabio Estevam festevam@denx.de > > Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3. > > Signed-off-by: Fabio Estevam festevam@denx.de > --- > arch/arm/dts/imx8mp.dtsi | 374 ++++++++++++++++------- > include/dt-bindings/clock/imx8mp-clock.h | 14 +- > 2 files changed, 270 insertions(+), 118 deletions(-) > > diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi > index bb916a0948a8..a237275ee017 100644 > --- a/arch/arm/dts/imx8mp.dtsi > +++ b/arch/arm/dts/imx8mp.dtsi > @@ -123,6 +123,7 @@ > > A53_L2: l2-cache0 { > compatible = "cache"; > + cache-unified; > cache-level = <2>; > cache-size = <0x80000>; > cache-line-size = <64>; > @@ -379,6 +380,8 @@ > compatible = "fsl,imx8mp-tmu"; > reg = <0x30260000 0x10000>; > clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; > + nvmem-cells = <&tmu_calib>; > + nvmem-cell-names = "calib"; > #thermal-sensor-cells = <1>; > }; > > @@ -411,7 +414,7 @@ > reg = <0x30330000 0x10000>; > }; > > - gpr: iomuxc-gpr@30340000 { > + gpr: syscon@30340000 { > compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; > reg = <0x30340000 0x10000>; > }; > @@ -424,27 +427,44 @@ > #address-cells = <1>; > #size-cells = <1>; > > - imx8mp_uid: unique-id@420 { > + /* > + * The register address below maps to the MX8M > + * Fusemap Description Table entries this way. > + * Assuming > + * reg = <ADDR SIZE>; > + * then > + * Fuse Address = (ADDR * 4) + 0x400 > + * Note that if SIZE is greater than 4, then > + * each subsequent fuse is located at offset > + * +0x10 in Fusemap Description Table (e.g. > + * reg = <0x8 0x8> describes fuses 0x420 and > + * 0x430). > + */ > + imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ > reg = <0x8 0x8>; > }; > > - cpu_speed_grade: speed-grade@10 { > + cpu_speed_grade: speed-grade@10 { /* 0x440 */ > reg = <0x10 4>; > }; > > - eth_mac1: mac-address@90 { > + eth_mac1: mac-address@90 { /* 0x640 */ > reg = <0x90 6>; > }; > > - eth_mac2: mac-address@96 { > + eth_mac2: mac-address@96 { /* 0x658 */ > reg = <0x96 6>; > }; > + > + tmu_calib: calib@264 { /* 0xd90-0xdc0 */ > + reg = <0x264 0x10>; > + }; > }; > > - anatop: anatop@30360000 { > - compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", > - "syscon"; > + anatop: clock-controller@30360000 { > + compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; > reg = <0x30360000 0x10000>; > + #clock-cells = <1>; > }; > > snvs: snvs@30370000 { > @@ -523,6 +543,7 @@ > compatible = "fsl,imx8mp-gpc"; > reg = <0x303a0000 0x1000>; > interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; > interrupt-controller; > #interrupt-cells = <3>; > > @@ -589,7 +610,7 @@ > reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; > }; > > - pgc_hsiomix: power-domains@17 { > + pgc_hsiomix: power-domain@17 { > #power-domain-cells = <0>; > reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; > clocks = <&clk IMX8MP_CLK_HSIO_AXI>, > @@ -631,6 +652,14 @@ > reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; > clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; > }; > + > + pgc_mlmix: power-domain@24 { > + #power-domain-cells = <0>; > + reg = <IMX8MP_POWER_DOMAIN_MLMIX>; > + clocks = <&clk IMX8MP_CLK_ML_AXI>, > + <&clk IMX8MP_CLK_ML_AHB>, > + <&clk IMX8MP_CLK_NPU_ROOT>; > + }; > }; > }; > }; > @@ -702,112 +731,129 @@ > #size-cells = <1>; > ranges; > > - ecspi1: spi@30820000 { > + spba-bus@30800000 { > + compatible = "fsl,spba-bus", "simple-bus"; > + reg = <0x30800000 0x100000>; > #address-cells = <1>; > - #size-cells = <0>; > - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; > - reg = <0x30820000 0x10000>; > - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, > - <&clk IMX8MP_CLK_ECSPI1_ROOT>; > - clock-names = "ipg", "per"; > - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; > - dma-names = "rx", "tx"; > - status = "disabled"; > - }; > + #size-cells = <1>; > + ranges; > > - ecspi2: spi@30830000 { > - #address-cells = <1>; > - #size-cells = <0>; > - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; > - reg = <0x30830000 0x10000>; > - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, > - <&clk IMX8MP_CLK_ECSPI2_ROOT>; > - clock-names = "ipg", "per"; > - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; > - dma-names = "rx", "tx"; > - status = "disabled"; > - }; > + ecspi1: spi@30820000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; > + reg = <0x30820000 0x10000>; > + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, > + <&clk IMX8MP_CLK_ECSPI1_ROOT>; > + clock-names = "ipg", "per"; > + assigned-clock-rates = <80000000>; > + assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; > + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > > - ecspi3: spi@30840000 { > - #address-cells = <1>; > - #size-cells = <0>; > - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; > - reg = <0x30840000 0x10000>; > - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, > - <&clk IMX8MP_CLK_ECSPI3_ROOT>; > - clock-names = "ipg", "per"; > - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; > - dma-names = "rx", "tx"; > - status = "disabled"; > - }; > + ecspi2: spi@30830000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; > + reg = <0x30830000 0x10000>; > + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, > + <&clk IMX8MP_CLK_ECSPI2_ROOT>; > + clock-names = "ipg", "per"; > + assigned-clock-rates = <80000000>; > + assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; > + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > > - uart1: serial@30860000 { > - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; > - reg = <0x30860000 0x10000>; > - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk IMX8MP_CLK_UART1_ROOT>, > - <&clk IMX8MP_CLK_UART1_ROOT>; > - clock-names = "ipg", "per"; > - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; > - dma-names = "rx", "tx"; > - status = "disabled"; > - }; > + ecspi3: spi@30840000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; > + reg = <0x30840000 0x10000>; > + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, > + <&clk IMX8MP_CLK_ECSPI3_ROOT>; > + clock-names = "ipg", "per"; > + assigned-clock-rates = <80000000>; > + assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; > + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > > - uart3: serial@30880000 { > - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; > - reg = <0x30880000 0x10000>; > - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk IMX8MP_CLK_UART3_ROOT>, > - <&clk IMX8MP_CLK_UART3_ROOT>; > - clock-names = "ipg", "per"; > - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; > - dma-names = "rx", "tx"; > - status = "disabled"; > - }; > + uart1: serial@30860000 { > + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; > + reg = <0x30860000 0x10000>; > + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MP_CLK_UART1_ROOT>, > + <&clk IMX8MP_CLK_UART1_ROOT>; > + clock-names = "ipg", "per"; > + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > > - uart2: serial@30890000 { > - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; > - reg = <0x30890000 0x10000>; > - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk IMX8MP_CLK_UART2_ROOT>, > - <&clk IMX8MP_CLK_UART2_ROOT>; > - clock-names = "ipg", "per"; > - dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; > - dma-names = "rx", "tx"; > - status = "disabled"; > - }; > + uart3: serial@30880000 { > + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; > + reg = <0x30880000 0x10000>; > + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MP_CLK_UART3_ROOT>, > + <&clk IMX8MP_CLK_UART3_ROOT>; > + clock-names = "ipg", "per"; > + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > > - flexcan1: can@308c0000 { > - compatible = "fsl,imx8mp-flexcan"; > - reg = <0x308c0000 0x10000>; > - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk IMX8MP_CLK_IPG_ROOT>, > - <&clk IMX8MP_CLK_CAN1_ROOT>; > - clock-names = "ipg", "per"; > - assigned-clocks = <&clk IMX8MP_CLK_CAN1>; > - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; > - assigned-clock-rates = <40000000>; > - fsl,clk-source = /bits/ 8 <0>; > - fsl,stop-mode = <&gpr 0x10 4>; > - status = "disabled"; > - }; > + uart2: serial@30890000 { > + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; > + reg = <0x30890000 0x10000>; > + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MP_CLK_UART2_ROOT>, > + <&clk IMX8MP_CLK_UART2_ROOT>; > + clock-names = "ipg", "per"; > + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > > - flexcan2: can@308d0000 { > - compatible = "fsl,imx8mp-flexcan"; > - reg = <0x308d0000 0x10000>; > - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk IMX8MP_CLK_IPG_ROOT>, > - <&clk IMX8MP_CLK_CAN2_ROOT>; > - clock-names = "ipg", "per"; > - assigned-clocks = <&clk IMX8MP_CLK_CAN2>; > - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; > - assigned-clock-rates = <40000000>; > - fsl,clk-source = /bits/ 8 <0>; > - fsl,stop-mode = <&gpr 0x10 5>; > - status = "disabled"; > + flexcan1: can@308c0000 { > + compatible = "fsl,imx8mp-flexcan"; > + reg = <0x308c0000 0x10000>; > + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, > + <&clk IMX8MP_CLK_CAN1_ROOT>; > + clock-names = "ipg", "per"; > + assigned-clocks = <&clk IMX8MP_CLK_CAN1>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; > + assigned-clock-rates = <40000000>; > + fsl,clk-source = /bits/ 8 <0>; > + fsl,stop-mode = <&gpr 0x10 4>; > + status = "disabled"; > + }; > + > + flexcan2: can@308d0000 { > + compatible = "fsl,imx8mp-flexcan"; > + reg = <0x308d0000 0x10000>; > + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, > + <&clk IMX8MP_CLK_CAN2_ROOT>; > + clock-names = "ipg", "per"; > + assigned-clocks = <&clk IMX8MP_CLK_CAN2>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; > + assigned-clock-rates = <40000000>; > + fsl,clk-source = /bits/ 8 <0>; > + fsl,stop-mode = <&gpr 0x10 5>; > + status = "disabled"; > + }; > }; > > crypto: crypto@30900000 { > @@ -1063,11 +1109,11 @@ > noc_opp_table: opp-table { > compatible = "operating-points-v2"; > > - opp-200M { > + opp-200000000 { > opp-hz = /bits/ 64 <200000000>; > }; > > - opp-1000M { > + opp-1000000000 { > opp-hz = /bits/ 64 <1000000000>; > }; > }; > @@ -1080,10 +1126,35 @@ > #size-cells = <1>; > ranges; > > + lcdif2: display-controller@32e90000 { > + compatible = "fsl,imx8mp-lcdif"; > + reg = <0x32e90000 0x10000>; > + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; > + clock-names = "pix", "axi", "disp_axi"; > + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, > + <&clk IMX8MP_VIDEO_PLL1>; > + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, > + <&clk IMX8MP_VIDEO_PLL1_REF_SEL>; > + assigned-clock-rates = <0>, <1039500000>; > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; > + status = "disabled"; > + > + port { > + lcdif2_to_ldb: endpoint { > + remote-endpoint = <&ldb_from_lcdif2>; > + }; > + }; > + }; > + > media_blk_ctrl: blk-ctrl@32ec0000 { > compatible = "fsl,imx8mp-media-blk-ctrl", > - "syscon"; > + "simple-bus", "syscon"; > reg = <0x32ec0000 0x10000>; > + #address-cells = <1>; > + #size-cells = <1>; > power-domains = <&pgc_mediamix>, > <&pgc_mipi_phy1>, > <&pgc_mipi_phy1>, > @@ -1128,6 +1199,44 @@ > assigned-clock-rates = <500000000>, <200000000>; > > #power-domain-cells = <1>; > + > + lvds_bridge: bridge@5c { > + compatible = "fsl,imx8mp-ldb"; > + clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; > + clock-names = "ldb"; > + reg = <0x5c 0x4>, <0x128 0x4>; > + reg-names = "ldb", "lvds"; > + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; > + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + ldb_from_lcdif2: endpoint { > + remote-endpoint = <&lcdif2_to_ldb>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + ldb_lvds_ch0: endpoint { > + }; > + }; > + > + port@2 { > + reg = <2>; > + > + ldb_lvds_ch1: endpoint { > + }; > + }; > + }; > + }; > }; > > pcie_phy: pcie-phy@32f00000 { > @@ -1158,6 +1267,7 @@ > <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; > interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; > #power-domain-cells = <1>; > + #clock-cells = <0>; > }; > }; > > @@ -1165,6 +1275,13 @@ > compatible = "fsl,imx8mp-pcie"; > reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; > reg-names = "dbi", "config"; > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > + <&clk IMX8MP_CLK_HSIO_AXI>, > + <&clk IMX8MP_CLK_PCIE_ROOT>; > + clock-names = "pcie", "pcie_bus", "pcie_aux"; > + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; > + assigned-clock-rates = <10000000>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; > #address-cells = <3>; > #size-cells = <2>; > device_type = "pci"; > @@ -1223,6 +1340,28 @@ > power-domains = <&pgc_gpu2d>; > }; > > + vpu_g1: video-codec@38300000 { > + compatible = "nxp,imx8mm-vpu-g1"; > + reg = <0x38300000 0x10000>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; > + assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; > + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; > + assigned-clock-rates = <600000000>; > + power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; > + }; > + > + vpu_g2: video-codec@38310000 { > + compatible = "nxp,imx8mq-vpu-g2"; > + reg = <0x38310000 0x10000>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; > + assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; > + assigned-clock-rates = <500000000>; > + power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; > + }; > + > vpumix_blk_ctrl: blk-ctrl@38330000 { > compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; > reg = <0x38330000 0x100>; > @@ -1234,6 +1373,9 @@ > <&clk IMX8MP_CLK_VPU_G2_ROOT>, > <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; > clock-names = "g1", "g2", "vc8000e"; > + assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; > + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; > + assigned-clock-rates = <600000000>, <600000000>; > interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, > <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, > <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; > @@ -1279,7 +1421,7 @@ > reg = <0x32f10100 0x8>, > <0x381f0000 0x20>; > clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > - <&clk IMX8MP_CLK_USB_ROOT>; > + <&clk IMX8MP_CLK_USB_SUSP>; > clock-names = "hsio", "suspend"; > interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; > @@ -1292,9 +1434,9 @@ > usb_dwc3_0: usb@38100000 { > compatible = "snps,dwc3"; > reg = <0x38100000 0x10000>; > - clocks = <&clk IMX8MP_CLK_HSIO_AXI>, > + clocks = <&clk IMX8MP_CLK_USB_ROOT>, > <&clk IMX8MP_CLK_USB_CORE_REF>, > - <&clk IMX8MP_CLK_USB_ROOT>; > + <&clk IMX8MP_CLK_USB_SUSP>; > clock-names = "bus_early", "ref", "suspend"; > interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; > phys = <&usb3_phy0>, <&usb3_phy0>; > @@ -1321,7 +1463,7 @@ > reg = <0x32f10108 0x8>, > <0x382f0000 0x20>; > clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > - <&clk IMX8MP_CLK_USB_ROOT>; > + <&clk IMX8MP_CLK_USB_SUSP>; > clock-names = "hsio", "suspend"; > interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; > power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; > @@ -1334,9 +1476,9 @@ > usb_dwc3_1: usb@38200000 { > compatible = "snps,dwc3"; > reg = <0x38200000 0x10000>; > - clocks = <&clk IMX8MP_CLK_HSIO_AXI>, > + clocks = <&clk IMX8MP_CLK_USB_ROOT>, > <&clk IMX8MP_CLK_USB_CORE_REF>, > - <&clk IMX8MP_CLK_USB_ROOT>; > + <&clk IMX8MP_CLK_USB_SUSP>; > clock-names = "bus_early", "ref", "suspend"; > interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > phys = <&usb3_phy1>, <&usb3_phy1>; > diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h > index 9d5cc2ddde89..3f28ce685f41 100644 > --- a/include/dt-bindings/clock/imx8mp-clock.h > +++ b/include/dt-bindings/clock/imx8mp-clock.h > @@ -324,8 +324,18 @@ > #define IMX8MP_CLK_CLKOUT2_SEL 317 > #define IMX8MP_CLK_CLKOUT2_DIV 318 > #define IMX8MP_CLK_CLKOUT2 319 > - > -#define IMX8MP_CLK_END 320 > +#define IMX8MP_CLK_USB_SUSP 320 > +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT > +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 > +#define IMX8MP_CLK_SAI1_ROOT 322 > +#define IMX8MP_CLK_SAI2_ROOT 323 > +#define IMX8MP_CLK_SAI3_ROOT 324 > +#define IMX8MP_CLK_SAI5_ROOT 325 > +#define IMX8MP_CLK_SAI6_ROOT 326 > +#define IMX8MP_CLK_SAI7_ROOT 327 > +#define IMX8MP_CLK_PDM_ROOT 328 > +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 > +#define IMX8MP_CLK_END 330 > > #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 > #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 > -- > 2.34.1 >
Tested-by: Tim Harvey tharvey@gateworks.com #imx8mp-venice-gw74xx
Fabio,
Apparently I didn't do a very good job of testing this. This patch is causing imx8mp-venice-* and imx8mp-evk boards to no longer boot with no SPL banner. The specific change that causes breakage is the one that encapsulates the spi/uart/flexcan children with spba-bus@30800000.
The SPI, UART, and Flexcan are part of the spba-bus.
We'll need to add the spba bus to imx8mp-u-boot.dtsi. Since it had no node name, it'll have to fall under aip3.
Try this:
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index 18d1728e1d..0e6811b129 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -44,6 +44,10 @@
&aips3 { bootph-pre-ram;
spba-bus@30800000 {bootph-pre-ram;};};
&iomuxc {
Adam,
Yup... that's it! Thanks. Want to send a patch or want me to do it?
Actually Fabio I think you should re-submit this patch with the required change to imx8mp-u-boot.dtsi included?
I was just about to say the same thing.
Fabio,
There's more to be done here also. With this patch, and with the spba-bus added to u-boot.dtsi, if you try to enable usb (usb start) you get: starting USB... Bus usb@38200000: Enable clock-controller@30380000 failed probe failed, error -2 No working controllers found
So until we get this figured out please don't apply this.
Best Regards,
Tim
Hi Tim,
On Fri, May 19, 2023 at 8:00 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
There's more to be done here also. With this patch, and with the spba-bus added to u-boot.dtsi, if you try to enable usb (usb start) you get: starting USB... Bus usb@38200000: Enable clock-controller@30380000 failed probe failed, error -2 No working controllers found
So until we get this figured out please don't apply this.
I don't have any imx8mp-based board here to debug this problem, so it would be nice if someone else could investigate this.
Thanks
On Mon, May 22, 2023 at 3:49 PM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Fri, May 19, 2023 at 8:00 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
There's more to be done here also. With this patch, and with the spba-bus added to u-boot.dtsi, if you try to enable usb (usb start) you get: starting USB... Bus usb@38200000: Enable clock-controller@30380000 failed probe failed, error -2 No working controllers found
So until we get this figured out please don't apply this.
I don't have any imx8mp-based board here to debug this problem, so it would be nice if someone else could investigate this.
I can do some testing on the imx8mp-beacon board, but it will likely be a few days before I can get to it.
adam
Thanks
Hi Tim,
On Fri, May 19, 2023 at 8:00 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
There's more to be done here also. With this patch, and with the spba-bus added to u-boot.dtsi, if you try to enable usb (usb start) you get: starting USB... Bus usb@38200000: Enable clock-controller@30380000 failed probe failed, error -2 No working controllers found
Does this help?
--- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -337,8 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); - clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "usb_core_ref", base + 0x44d0, 0)); - clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); + clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "hsio_axi", base + 0x44d0, 0)); + clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate4("usb_suspend_clk", "osc_32k", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
On Wed, May 24, 2023 at 9:02 PM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Fri, May 19, 2023 at 8:00 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
+ Marek I am adding Marek since he did the HSIO power domain driver.
There's more to be done here also. With this patch, and with the spba-bus added to u-boot.dtsi, if you try to enable usb (usb start) you get: starting USB... Bus usb@38200000: Enable clock-controller@30380000 failed probe failed, error -2 No working controllers found
Does this help?
A bit. I finally got some time to try to troubleshoot USB on my 8MP.
--- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -337,8 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk","usb_core_ref", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_PHY_ROOT,
IMX8MP_CLK_USB_PHY_ROOT is also referenced in the device tree, so I don't think we can delete it. I had keep IMX8MP_CLK_USB_ROOT, and IMX8MP_CLK_USB_PHY_ROOT while also adding IMX8MP_CLK_USB_SUSP.
imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk","hsio_axi", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate4("usb_suspend_clk","osc_32k", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
At this point, the missing clock errors go away, but it hangs. I updated my 8MP USB clocks based on the latest Linux kernel so my clocks looks like:
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
The linux kernel uses gate2 for USB_ROOT and USB_SUSP while gate4 is used for IMX8MP_CLK_USB_PHY_ROOT. I didn't verify this against the reference manual.
With some debugging enabled, it looks to me like it might be power-domain related, but I am not 100% certain. When I start the USB, it appears to go through some clocks, and start one power domain, but I think we have a power-domain chain where one power domain starts another. I saw a patch on another thread for enabling parent power-domains, but it didn't seem to help me.
u-boot=> usb start starting USB... Bus usb@38200000: ofnode_read_prop: maximum-speed: <not found> ofnode_read_prop: dr_mode: host dev_power_domain_on usb@32f10108 ofnode_read_prop: assigned-clock-rates: <not found> Looking for clock-controller@30380000 Looking for clock-controller@30380000 - result for clock-controller@30380000: clock-controller@30380000 (ret=0) - result for clock-controller@30380000: clock-controller@30380000 (ret=0) Looking for clock-controller@30380000 Looking for clock-controller@30380000 - result for clock-controller@30380000: clock-controller@30380000 (ret=0) - result for clock-controller@30380000: clock-controller@30380000 (ret=0) ofnode_read_prop: dr_mode: host
<hang>
I added some debug code to the imx8mp_hsiomix_on in HSIOmix power domain driver, and it doesn't appear to be getting called, yet dev_power_domain_on usb@32f10108 should be invoking it.
I am not positive it's a power domain issue, that's my first guess.
Tim - have you had any success?
adam
On Mon, May 29, 2023 at 10:45 AM Adam Ford aford173@gmail.com wrote:
On Wed, May 24, 2023 at 9:02 PM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Fri, May 19, 2023 at 8:00 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
- Marek
I am adding Marek since he did the HSIO power domain driver.
There's more to be done here also. With this patch, and with the spba-bus added to u-boot.dtsi, if you try to enable usb (usb start) you get: starting USB... Bus usb@38200000: Enable clock-controller@30380000 failed probe failed, error -2 No working controllers found
Does this help?
A bit. I finally got some time to try to troubleshoot USB on my 8MP.
--- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -337,8 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk","usb_core_ref", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_PHY_ROOT,IMX8MP_CLK_USB_PHY_ROOT is also referenced in the device tree, so I don't think we can delete it. I had keep IMX8MP_CLK_USB_ROOT, and IMX8MP_CLK_USB_PHY_ROOT while also adding IMX8MP_CLK_USB_SUSP.
imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk","hsio_axi", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate4("usb_suspend_clk","osc_32k", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
At this point, the missing clock errors go away, but it hangs. I updated my 8MP USB clocks based on the latest Linux kernel so my clocks looks like:
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
The linux kernel uses gate2 for USB_ROOT and USB_SUSP while gate4 is used for IMX8MP_CLK_USB_PHY_ROOT. I didn't verify this against the reference manual.
With some debugging enabled, it looks to me like it might be power-domain related, but I am not 100% certain. When I start the USB, it appears to go through some clocks, and start one power domain, but I think we have a power-domain chain where one power domain starts another. I saw a patch on another thread for enabling parent power-domains, but it didn't seem to help me.
u-boot=> usb start starting USB... Bus usb@38200000: ofnode_read_prop: maximum-speed: <not found> ofnode_read_prop: dr_mode: host dev_power_domain_on usb@32f10108 ofnode_read_prop: assigned-clock-rates: <not found> Looking for clock-controller@30380000 Looking for clock-controller@30380000
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
Looking for clock-controller@30380000 Looking for clock-controller@30380000
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
ofnode_read_prop: dr_mode: host
<hang>
I added some debug code to the imx8mp_hsiomix_on in HSIOmix power domain driver, and it doesn't appear to be getting called, yet dev_power_domain_on usb@32f10108 should be invoking it.
I am not positive it's a power domain issue, that's my first guess.
Tim - have you had any success?
Adam,
No success here yet but I don't have any time to work on it for at least another week.
Best Regards,
Tim
On Tue, May 30, 2023 at 12:23 PM Tim Harvey tharvey@gateworks.com wrote:
On Mon, May 29, 2023 at 10:45 AM Adam Ford aford173@gmail.com wrote:
On Wed, May 24, 2023 at 9:02 PM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Fri, May 19, 2023 at 8:00 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
- Marek
I am adding Marek since he did the HSIO power domain driver.
There's more to be done here also. With this patch, and with the spba-bus added to u-boot.dtsi, if you try to enable usb (usb start) you get: starting USB... Bus usb@38200000: Enable clock-controller@30380000 failed probe failed, error -2 No working controllers found
Does this help?
A bit. I finally got some time to try to troubleshoot USB on my 8MP.
--- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -337,8 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk","usb_core_ref", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_PHY_ROOT,IMX8MP_CLK_USB_PHY_ROOT is also referenced in the device tree, so I don't think we can delete it. I had keep IMX8MP_CLK_USB_ROOT, and IMX8MP_CLK_USB_PHY_ROOT while also adding IMX8MP_CLK_USB_SUSP.
imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk","hsio_axi", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate4("usb_suspend_clk","osc_32k", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
At this point, the missing clock errors go away, but it hangs. I updated my 8MP USB clocks based on the latest Linux kernel so my clocks looks like:
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
The linux kernel uses gate2 for USB_ROOT and USB_SUSP while gate4 is used for IMX8MP_CLK_USB_PHY_ROOT. I didn't verify this against the reference manual.
With some debugging enabled, it looks to me like it might be power-domain related, but I am not 100% certain. When I start the USB, it appears to go through some clocks, and start one power domain, but I think we have a power-domain chain where one power domain starts another. I saw a patch on another thread for enabling parent power-domains, but it didn't seem to help me.
u-boot=> usb start starting USB... Bus usb@38200000: ofnode_read_prop: maximum-speed: <not found> ofnode_read_prop: dr_mode: host dev_power_domain_on usb@32f10108 ofnode_read_prop: assigned-clock-rates: <not found> Looking for clock-controller@30380000 Looking for clock-controller@30380000
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
Looking for clock-controller@30380000 Looking for clock-controller@30380000
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
ofnode_read_prop: dr_mode: host
<hang>
I added some debug code to the imx8mp_hsiomix_on in HSIOmix power domain driver, and it doesn't appear to be getting called, yet dev_power_domain_on usb@32f10108 should be invoking it.
I am not positive it's a power domain issue, that's my first guess.
Tim - have you had any success?
Adam,
No success here yet but I don't have any time to work on it for at least another week.
No worries. I'll try to spend some more time this week, and keep you informed of any progress. I'd like to see the USB working too.
adam
Best Regards,
Tim
On Tue, May 30, 2023 at 10:28 AM Adam Ford aford173@gmail.com wrote:
On Tue, May 30, 2023 at 12:23 PM Tim Harvey tharvey@gateworks.com wrote:
On Mon, May 29, 2023 at 10:45 AM Adam Ford aford173@gmail.com wrote:
On Wed, May 24, 2023 at 9:02 PM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Fri, May 19, 2023 at 8:00 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
- Marek
I am adding Marek since he did the HSIO power domain driver.
There's more to be done here also. With this patch, and with the spba-bus added to u-boot.dtsi, if you try to enable usb (usb start) you get: starting USB... Bus usb@38200000: Enable clock-controller@30380000 failed probe failed, error -2 No working controllers found
Does this help?
A bit. I finally got some time to try to troubleshoot USB on my 8MP.
--- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -337,8 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk","usb_core_ref", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_PHY_ROOT,IMX8MP_CLK_USB_PHY_ROOT is also referenced in the device tree, so I don't think we can delete it. I had keep IMX8MP_CLK_USB_ROOT, and IMX8MP_CLK_USB_PHY_ROOT while also adding IMX8MP_CLK_USB_SUSP.
imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk","hsio_axi", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate4("usb_suspend_clk","osc_32k", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
At this point, the missing clock errors go away, but it hangs. I updated my 8MP USB clocks based on the latest Linux kernel so my clocks looks like:
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
The linux kernel uses gate2 for USB_ROOT and USB_SUSP while gate4 is used for IMX8MP_CLK_USB_PHY_ROOT. I didn't verify this against the reference manual.
With some debugging enabled, it looks to me like it might be power-domain related, but I am not 100% certain. When I start the USB, it appears to go through some clocks, and start one power domain, but I think we have a power-domain chain where one power domain starts another. I saw a patch on another thread for enabling parent power-domains, but it didn't seem to help me.
u-boot=> usb start starting USB... Bus usb@38200000: ofnode_read_prop: maximum-speed: <not found> ofnode_read_prop: dr_mode: host dev_power_domain_on usb@32f10108 ofnode_read_prop: assigned-clock-rates: <not found> Looking for clock-controller@30380000 Looking for clock-controller@30380000
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
Looking for clock-controller@30380000 Looking for clock-controller@30380000
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
ofnode_read_prop: dr_mode: host
<hang>
I added some debug code to the imx8mp_hsiomix_on in HSIOmix power domain driver, and it doesn't appear to be getting called, yet dev_power_domain_on usb@32f10108 should be invoking it.
I am not positive it's a power domain issue, that's my first guess.
Tim - have you had any success?
Adam,
No success here yet but I don't have any time to work on it for at least another week.
No worries. I'll try to spend some more time this week, and keep you informed of any progress. I'd like to see the USB working too.
Adam,
Thanks for keeping me in the loop. For my boards I also need to add vbus regulator enable to the dwc controller (which I've worked on a bit but have not submitted anything yet) and eventually gpio dual-role based detect/configure as well (which I have not worked on and currently just force dr-mode to host in a u-boot.dtsi file to deal with).
Best Regards,
Tim
On Tue, May 30, 2023 at 1:40 PM Tim Harvey tharvey@gateworks.com wrote:
On Tue, May 30, 2023 at 10:28 AM Adam Ford aford173@gmail.com wrote:
On Tue, May 30, 2023 at 12:23 PM Tim Harvey tharvey@gateworks.com wrote:
On Mon, May 29, 2023 at 10:45 AM Adam Ford aford173@gmail.com wrote:
On Wed, May 24, 2023 at 9:02 PM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Fri, May 19, 2023 at 8:00 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
- Marek
I am adding Marek since he did the HSIO power domain driver.
There's more to be done here also. With this patch, and with the spba-bus added to u-boot.dtsi, if you try to enable usb (usb start) you get: starting USB... Bus usb@38200000: Enable clock-controller@30380000 failed probe failed, error -2 No working controllers found
Does this help?
A bit. I finally got some time to try to troubleshoot USB on my 8MP.
--- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -337,8 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk","usb_core_ref", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_PHY_ROOT,IMX8MP_CLK_USB_PHY_ROOT is also referenced in the device tree, so I don't think we can delete it. I had keep IMX8MP_CLK_USB_ROOT, and IMX8MP_CLK_USB_PHY_ROOT while also adding IMX8MP_CLK_USB_SUSP.
imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk","hsio_axi", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate4("usb_suspend_clk","osc_32k", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
At this point, the missing clock errors go away, but it hangs. I updated my 8MP USB clocks based on the latest Linux kernel so my clocks looks like:
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
The linux kernel uses gate2 for USB_ROOT and USB_SUSP while gate4 is used for IMX8MP_CLK_USB_PHY_ROOT. I didn't verify this against the reference manual.
With some debugging enabled, it looks to me like it might be power-domain related, but I am not 100% certain. When I start the USB, it appears to go through some clocks, and start one power domain, but I think we have a power-domain chain where one power domain starts another. I saw a patch on another thread for enabling parent power-domains, but it didn't seem to help me.
u-boot=> usb start starting USB... Bus usb@38200000: ofnode_read_prop: maximum-speed: <not found> ofnode_read_prop: dr_mode: host dev_power_domain_on usb@32f10108 ofnode_read_prop: assigned-clock-rates: <not found> Looking for clock-controller@30380000 Looking for clock-controller@30380000
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
Looking for clock-controller@30380000 Looking for clock-controller@30380000
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
- result for clock-controller@30380000: clock-controller@30380000 (ret=0)
ofnode_read_prop: dr_mode: host
<hang>
I added some debug code to the imx8mp_hsiomix_on in HSIOmix power domain driver, and it doesn't appear to be getting called, yet dev_power_domain_on usb@32f10108 should be invoking it.
I am not positive it's a power domain issue, that's my first guess.
Tim - have you had any success?
Adam,
No success here yet but I don't have any time to work on it for at least another week.
No worries. I'll try to spend some more time this week, and keep you informed of any progress. I'd like to see the USB working too.
Adam,
Thanks for keeping me in the loop. For my boards I also need to add vbus regulator enable to the dwc controller (which I've worked on a bit but have not submitted anything yet) and eventually gpio dual-role based detect/configure as well (which I have not worked on and currently just force dr-mode to host in a u-boot.dtsi file to deal with).
I have it working now. I need some time to clean my stuff and re-base the imx8mp.dtsi file, but I can submit a patch which fixes the clocks and re-sync's the device tree with the current stuff from kernel.org. I should be able to get a patch series out tonight.
adam
Best Regards,
Tim
On Tue, May 30, 2023 at 7:35 PM Adam Ford aford173@gmail.com wrote:
I have it working now. I need some time to clean my stuff and re-base the imx8mp.dtsi file, but I can submit a patch which fixes the clocks and re-sync's the device tree with the current stuff from kernel.org. I should be able to get a patch series out tonight.
Great work, Adam!
On 20/05/2023 00.26, Adam Ford wrote:
On Fri, May 19, 2023 at 5:19 PM Tim Harvey tharvey@gateworks.com wrote:
On Wed, May 3, 2023 at 9:11 AM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
Apparently I didn't do a very good job of testing this. This patch is causing imx8mp-venice-* and imx8mp-evk boards to no longer boot with no SPL banner. The specific change that causes breakage is the one that encapsulates the spi/uart/flexcan children with spba-bus@30800000.
The SPI, UART, and Flexcan are part of the spba-bus.
We'll need to add the spba bus to imx8mp-u-boot.dtsi. Since it had no node name, it'll have to fall under aip3.
Try this:
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index 18d1728e1d..0e6811b129 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -44,6 +44,10 @@
&aips3 { bootph-pre-ram;
spba-bus@30800000 {bootph-pre-ram;};};
&iomuxc {
This begs the question: Why don't these tags just implicitly propagate to parent nodes? It's a U-Boot specific tool (fdtgrep) that makes use of them, no? So making the rule be "keep this node if it _or any descendant_ has that tag" should be possible.
This has probably been answered somewhere before.
Rasmus
On Thu, Apr 27, 2023 at 11:08 AM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Sync imx8mm.dtsi with Linux 6.3.
The motivation for doing this sync was a bug when doing "ums 0 mmc 1" on imx8mm-evk. It worked well for the first time, but after doing a CTRL+C and launching the ums again, the command did not work.
Adam Ford suggested to sync imx8mm.dtsi with the Linux dts, as there was a recent USB power domain reorganization there.
After syncing the imx8mm.dtsi with Linux, the ums command works without problem after a CTRL+C.
Suggested-by: Adam Ford aford173@gmail.com Signed-off-by: Fabio Estevam festevam@denx.de
arch/arm/dts/imx8mm.dtsi | 52 +++++++++++++++++++++++++++++----------- 1 file changed, 38 insertions(+), 14 deletions(-)
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index afb90f59c83c..31f4548f85cf 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>;
cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>;@@ -276,6 +277,7 @@ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk";
power-domains = <&pgc_otg1>; }; usbphynop2: usbphynop2 {@@ -285,6 +287,7 @@ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk";
power-domains = <&pgc_otg2>; }; soc: soc@0 {@@ -493,6 +496,8 @@ compatible = "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
nvmem-cells = <&tmu_calib>;nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; };@@ -547,8 +552,8 @@ reg = <0x30330000 0x10000>; };
gpr: iomuxc-gpr@30340000 {compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
gpr: syscon@30340000 {compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };@@ -560,22 +565,40 @@ #address-cells = <1>; #size-cells = <1>;
imx8mm_uid: unique-id@410 {
/** The register address below maps to the MX8M* Fusemap Description Table entries this way.* Assuming* reg = <ADDR SIZE>;* then* Fuse Address = (ADDR * 4) + 0x400* Note that if SIZE is greater than 4, then* each subsequent fuse is located at offset* +0x10 in Fusemap Description Table (e.g.* reg = <0x4 0x8> describes fuses 0x410 and* 0x420).*/imx8mm_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; };
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
fec_mac_address: mac-address@90 {
tmu_calib: calib@3c { /* 0x4f0 */reg = <0x3c 4>;};fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; };
anatop: anatop@30360000 {compatible = "fsl,imx8mm-anatop", "syscon";
anatop: clock-controller@30360000 {compatible = "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>;#clock-cells = <1>; }; snvs: snvs@30370000 {@@ -674,13 +697,11 @@ pgc_otg1: power-domain@2 { #power-domain-cells = <0>; reg = <IMX8MM_POWER_DOMAIN_OTG1>;
power-domains = <&pgc_hsiomix>; }; pgc_otg2: power-domain@3 { #power-domain-cells = <0>; reg = <IMX8MM_POWER_DOMAIN_OTG2>;power-domains = <&pgc_hsiomix>; }; pgc_gpumix: power-domain@4 {@@ -1186,7 +1207,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_otg1>;
power-domains = <&pgc_hsiomix>; status = "disabled"; };@@ -1206,7 +1227,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>;
power-domains = <&pgc_otg2>;
power-domains = <&pgc_hsiomix>; status = "disabled"; };@@ -1238,16 +1259,15 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; };gpmi: nand-controller@33002000{
gpmi: nand-controller@33002000 { compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;@@ -1282,6 +1302,10 @@ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; linux,pci-domain = <0>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,<&clk IMX8MM_CLK_PCIE1_PHY>,<&clk IMX8MM_CLK_PCIE1_AUX>;clock-names = "pcie", "pcie_bus", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;-- 2.34.1
Fabio,
This causes a hang on imx8mm boards when usbotg2 (usb@32e50000) is enabled. You can re-create this on the imx8mm-evk with: diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi index 7d6317d95b13..898639e33d5e 100644 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ b/arch/arm/dts/imx8mm-evk.dtsi @@ -417,6 +417,10 @@ }; };
+&usbotg2 { + status = "okay"; +}; + &usdhc2 { assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; assigned-clock-rates = <200000000>;
Note the imx8mm-evk does have the 2nd host controller but its currently not enabled due to missing bits to deal with the USB 3.0 GPIO controlled mux.
Is there perhaps a corresponding change necessary in the imx8m-power-domain driver?
Best Regards,
Tim
On Thu, Apr 27, 2023 at 3:56 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
This causes a hang on imx8mm boards when usbotg2 (usb@32e50000) is enabled. You can re-create this on the imx8mm-evk with:
I am able to reproduce the hang after enabling usbotg2, but this hang is not caused by the imx8mm.dtsi sync. The hang also happens if I revert the imx8mm.dtsi sync.
The usbotg2 is a different issue.
Note the imx8mm-evk does have the 2nd host controller but its currently not enabled due to missing bits to deal with the USB 3.0 GPIO controlled mux.
Is there perhaps a corresponding change necessary in the imx8m-power-domain driver?
I haven't checked, but yes, it is very likely some imx8m-power-domain changes are needed.
On Thu, Apr 27, 2023 at 12:11 PM Fabio Estevam festevam@gmail.com wrote:
On Thu, Apr 27, 2023 at 3:56 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
This causes a hang on imx8mm boards when usbotg2 (usb@32e50000) is enabled. You can re-create this on the imx8mm-evk with:
I am able to reproduce the hang after enabling usbotg2, but this hang is not caused by the imx8mm.dtsi sync. The hang also happens if I revert the imx8mm.dtsi sync.
The usbotg2 is a different issue.
Note the imx8mm-evk does have the 2nd host controller but its currently not enabled due to missing bits to deal with the USB 3.0 GPIO controlled mux.
Is there perhaps a corresponding change necessary in the imx8m-power-domain driver?
I haven't checked, but yes, it is very likely some imx8m-power-domain changes are needed.
Fabio,
The patch series from Eugen Hristev which implements reference counting for regulators [1] resolves my issue here so I consider this thread closed.
Let's move the discussion regarding your dt sync to those threads.
Best Regards,
Tim [1] https://patchwork.ozlabs.org/project/uboot/list/?series=351536
On Thu, Apr 27, 2023 at 12:14 PM Tim Harvey tharvey@gateworks.com wrote:
On Thu, Apr 27, 2023 at 12:11 PM Fabio Estevam festevam@gmail.com wrote:
On Thu, Apr 27, 2023 at 3:56 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
This causes a hang on imx8mm boards when usbotg2 (usb@32e50000) is enabled. You can re-create this on the imx8mm-evk with:
I am able to reproduce the hang after enabling usbotg2, but this hang is not caused by the imx8mm.dtsi sync. The hang also happens if I revert the imx8mm.dtsi sync.
The usbotg2 is a different issue.
Note the imx8mm-evk does have the 2nd host controller but its currently not enabled due to missing bits to deal with the USB 3.0 GPIO controlled mux.
Is there perhaps a corresponding change necessary in the imx8m-power-domain driver?
I haven't checked, but yes, it is very likely some imx8m-power-domain changes are needed.
Fabio,
The patch series from Eugen Hristev which implements reference counting for regulators [1] resolves my issue here so I consider this thread closed.
Let's move the discussion regarding your dt sync to those threads.
Best Regards,
Tim [1] https://patchwork.ozlabs.org/project/uboot/list/?series=351536
Fabio,
Sorry, responded to the wrong thread here. The thread regarding imx8mm hang on usb_stop is resolved with the regulator reference counting support.
The dt sync here still needs some work apparently.
Best Regards,
Tim
On Thu, Apr 27, 2023 at 4:19 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
Sorry, responded to the wrong thread here. The thread regarding imx8mm hang on usb_stop is resolved with the regulator reference counting support.
The dt sync here still needs some work apparently.
I am confused now.
Which issue exactly does this patch cause you?
On Thu, Apr 27, 2023 at 12:26 PM Fabio Estevam festevam@gmail.com wrote:
On Thu, Apr 27, 2023 at 4:19 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
Sorry, responded to the wrong thread here. The thread regarding imx8mm hang on usb_stop is resolved with the regulator reference counting support.
The dt sync here still needs some work apparently.
I am confused now.
Which issue exactly does this patch cause you?
Fabio,
Sorry for the confusion.
This imx8mm dt sync patch will hang on imx8mm boards that use 'both' usbotg1 and usbotg2. You can reproduce this hang on your imx8mm-evk by enabling usbotg2 in the dt (the board has it but it is not enabled due to the gpio based usb 3.0 mux not being sorted out yet): +&usbotg2 { + dr_mode = "otg"; + status = "okay"; +}; +
u-boot=> usb start && usb tree starting USB... Bus usb@32e40000: Bus usb@32e50000: ^^^ imx8mm-evk hangs
This hang issue is not resolved by the regulator reference counter support and I am assuming that the power domain changes in this patch need to go along with a change in the power domain driver as well.
I don't know yet if the imx8mn/imx8mp dt sync's in your series show issues during testing.
Best Regards,
Tim
On Thu, Apr 27, 2023 at 4:44 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
Sorry for the confusion.
This imx8mm dt sync patch will hang on imx8mm boards that use 'both' usbotg1 and usbotg2. You can reproduce this hang on your imx8mm-evk by enabling usbotg2 in the dt (the board has it but it is not enabled due to the gpio based usb 3.0 mux not being sorted out yet): +&usbotg2 {
dr_mode = "otg";status = "okay";+};
u-boot=> usb start && usb tree starting USB... Bus usb@32e40000: Bus usb@32e50000: ^^^ imx8mm-evk hangs
Yes, I can reproduce the hang, but it happens with or without the imx8mm dt sync.
This hang is a separate issue, not dt related, as far as I understand.
The imx8mm dts sync does solve the issue of running 'ums' after CTRL+C.
On Thu, Apr 27, 2023 at 12:49 PM Fabio Estevam festevam@gmail.com wrote:
On Thu, Apr 27, 2023 at 4:44 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
Sorry for the confusion.
This imx8mm dt sync patch will hang on imx8mm boards that use 'both' usbotg1 and usbotg2. You can reproduce this hang on your imx8mm-evk by enabling usbotg2 in the dt (the board has it but it is not enabled due to the gpio based usb 3.0 mux not being sorted out yet): +&usbotg2 {
dr_mode = "otg";status = "okay";+};
u-boot=> usb start && usb tree starting USB... Bus usb@32e40000: Bus usb@32e50000: ^^^ imx8mm-evk hangs
Yes, I can reproduce the hang, but it happens with or without the imx8mm dt sync.
Fabio,
I do 'not' see a hang on imx8mm-evk on 'usb start && usb tree' on master (my other issue was on a 'usb stop' but only with usb controllers in host mode).
This hang is a separate issue, not dt related, as far as I understand.
The imx8mm dts sync does solve the issue of running 'ums' after CTRL+C.
I don't agree. The hang 'is' related because all my imx8mm-venice-* boards which use 'both' USB controllers hang with this patch on a 'usb start' and don't hang without it. While a basic 'review' of the patch looks good but actual product testing shows issues. As a maintainer for ARM FREESCALE IMX you must have another imx8mm board which uses both usbotg devices to test against and verify you see what I see?
Until we know what other fix is needed to go along with this: Nacked-by: Tim Harvey tharvey@gateworks.com
I've verified that it's the changes from Linux commit 4585c79ff477f ("arm64: dts: imx8mm: correct usb power domains") that causes the hang, but I don't know why yet.
Why are we seeing different behavior on the imx8mm-evk? Are we on different branches? My testing today is on caf0a88d9f31
Best Regards,
Tim
On Thu, Apr 27, 2023 at 5:25 PM Tim Harvey tharvey@gateworks.com wrote:
On Thu, Apr 27, 2023 at 12:49 PM Fabio Estevam festevam@gmail.com wrote:
On Thu, Apr 27, 2023 at 4:44 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
Sorry for the confusion.
This imx8mm dt sync patch will hang on imx8mm boards that use 'both' usbotg1 and usbotg2. You can reproduce this hang on your imx8mm-evk by enabling usbotg2 in the dt (the board has it but it is not enabled due to the gpio based usb 3.0 mux not being sorted out yet): +&usbotg2 {
dr_mode = "otg";status = "okay";+};
u-boot=> usb start && usb tree starting USB... Bus usb@32e40000: Bus usb@32e50000: ^^^ imx8mm-evk hangs
Yes, I can reproduce the hang, but it happens with or without the imx8mm dt sync.
Fabio,
I do 'not' see a hang on imx8mm-evk on 'usb start && usb tree' on master (my other issue was on a 'usb stop' but only with usb controllers in host mode).
This hang is a separate issue, not dt related, as far as I understand.
The imx8mm dts sync does solve the issue of running 'ums' after CTRL+C.
I don't agree. The hang 'is' related because all my imx8mm-venice-* boards which use 'both' USB controllers hang with this patch on a 'usb start' and don't hang without it. While a basic 'review' of the patch looks good but actual product testing shows issues. As a maintainer for ARM FREESCALE IMX you must have another imx8mm board which uses both usbotg devices to test against and verify you see what I see?
Until we know what other fix is needed to go along with this: Nacked-by: Tim Harvey tharvey@gateworks.com
What is the harm is sync'ing the device tree with the kernel? I seemed like you found a solution with the regulator patch. Did I misunderstand that?
adam
I've verified that it's the changes from Linux commit 4585c79ff477f ("arm64: dts: imx8mm: correct usb power domains") that causes the hang, but I don't know why yet.
Why are we seeing different behavior on the imx8mm-evk? Are we on different branches? My testing today is on caf0a88d9f31
Best Regards,
Tim
On Fri, Apr 28, 2023 at 4:57 AM Adam Ford aford173@gmail.com wrote:
On Thu, Apr 27, 2023 at 5:25 PM Tim Harvey tharvey@gateworks.com wrote:
On Thu, Apr 27, 2023 at 12:49 PM Fabio Estevam festevam@gmail.com wrote:
On Thu, Apr 27, 2023 at 4:44 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
Sorry for the confusion.
This imx8mm dt sync patch will hang on imx8mm boards that use 'both' usbotg1 and usbotg2. You can reproduce this hang on your imx8mm-evk by enabling usbotg2 in the dt (the board has it but it is not enabled due to the gpio based usb 3.0 mux not being sorted out yet): +&usbotg2 {
dr_mode = "otg";status = "okay";+};
u-boot=> usb start && usb tree starting USB... Bus usb@32e40000: Bus usb@32e50000: ^^^ imx8mm-evk hangs
Yes, I can reproduce the hang, but it happens with or without the imx8mm dt sync.
Fabio,
I do 'not' see a hang on imx8mm-evk on 'usb start && usb tree' on master (my other issue was on a 'usb stop' but only with usb controllers in host mode).
This hang is a separate issue, not dt related, as far as I understand.
The imx8mm dts sync does solve the issue of running 'ums' after CTRL+C.
I don't agree. The hang 'is' related because all my imx8mm-venice-* boards which use 'both' USB controllers hang with this patch on a 'usb start' and don't hang without it. While a basic 'review' of the patch looks good but actual product testing shows issues. As a maintainer for ARM FREESCALE IMX you must have another imx8mm board which uses both usbotg devices to test against and verify you see what I see?
Until we know what other fix is needed to go along with this: Nacked-by: Tim Harvey tharvey@gateworks.com
What is the harm is sync'ing the device tree with the kernel? I seemed like you found a solution with the regulator patch. Did I misunderstand that?
adam
Adam,
No, the regulator patch did 'not' resolve the issue created by syncing the imx8mm dt (I caused confusion by responding to the wrong thread - the regulator patch resolved a different issue).
Could you please verify my results on a board that uses both usbotg1 and usbotg2? What I see is on master + this imx8mm dt sync (specifically the changes from Linux commit 4585c79ff477f ("arm64: dts: imx8mm: correct usb power domains")) the board hangs on usb start when bringing up usbotg2.
Best Regards,
Tim
On Fri, Apr 28, 2023 at 10:27 AM Tim Harvey tharvey@gateworks.com wrote:
On Fri, Apr 28, 2023 at 4:57 AM Adam Ford aford173@gmail.com wrote:
On Thu, Apr 27, 2023 at 5:25 PM Tim Harvey tharvey@gateworks.com wrote:
On Thu, Apr 27, 2023 at 12:49 PM Fabio Estevam festevam@gmail.com wrote:
On Thu, Apr 27, 2023 at 4:44 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
Sorry for the confusion.
This imx8mm dt sync patch will hang on imx8mm boards that use 'both' usbotg1 and usbotg2. You can reproduce this hang on your imx8mm-evk by enabling usbotg2 in the dt (the board has it but it is not enabled due to the gpio based usb 3.0 mux not being sorted out yet): +&usbotg2 {
dr_mode = "otg";status = "okay";+};
u-boot=> usb start && usb tree starting USB... Bus usb@32e40000: Bus usb@32e50000: ^^^ imx8mm-evk hangs
Yes, I can reproduce the hang, but it happens with or without the imx8mm dt sync.
Fabio,
I do 'not' see a hang on imx8mm-evk on 'usb start && usb tree' on master (my other issue was on a 'usb stop' but only with usb controllers in host mode).
This hang is a separate issue, not dt related, as far as I understand.
The imx8mm dts sync does solve the issue of running 'ums' after CTRL+C.
I don't agree. The hang 'is' related because all my imx8mm-venice-* boards which use 'both' USB controllers hang with this patch on a 'usb start' and don't hang without it. While a basic 'review' of the patch looks good but actual product testing shows issues. As a maintainer for ARM FREESCALE IMX you must have another imx8mm board which uses both usbotg devices to test against and verify you see what I see?
Until we know what other fix is needed to go along with this: Nacked-by: Tim Harvey tharvey@gateworks.com
What is the harm is sync'ing the device tree with the kernel? I seemed like you found a solution with the regulator patch. Did I misunderstand that?
adam
Adam,
No, the regulator patch did 'not' resolve the issue created by syncing the imx8mm dt (I caused confusion by responding to the wrong thread - the regulator patch resolved a different issue).
Ok.
Could you please verify my results on a board that uses both usbotg1 and usbotg2? What I see is on master + this imx8mm dt sync (specifically the changes from Linux commit 4585c79ff477f ("arm64: dts: imx8mm: correct usb power domains")) the board hangs on usb start when bringing up usbotg2.
I can, but I am about to board a plane to go visit some sick family, but I'll try to do it early next week. I have a board with both USB controllers enabled. My OTG2 is host-only, so I think it's similar to your setup.
Should I apply the regulator patch when I test?
adam
Best Regards,
Tim
On Fri, Apr 28, 2023 at 8:32 AM Adam Ford aford173@gmail.com wrote:
On Fri, Apr 28, 2023 at 10:27 AM Tim Harvey tharvey@gateworks.com wrote:
On Fri, Apr 28, 2023 at 4:57 AM Adam Ford aford173@gmail.com wrote:
On Thu, Apr 27, 2023 at 5:25 PM Tim Harvey tharvey@gateworks.com wrote:
On Thu, Apr 27, 2023 at 12:49 PM Fabio Estevam festevam@gmail.com wrote:
On Thu, Apr 27, 2023 at 4:44 PM Tim Harvey tharvey@gateworks.com wrote:
Fabio,
Sorry for the confusion.
This imx8mm dt sync patch will hang on imx8mm boards that use 'both' usbotg1 and usbotg2. You can reproduce this hang on your imx8mm-evk by enabling usbotg2 in the dt (the board has it but it is not enabled due to the gpio based usb 3.0 mux not being sorted out yet): +&usbotg2 {
dr_mode = "otg";status = "okay";+};
u-boot=> usb start && usb tree starting USB... Bus usb@32e40000: Bus usb@32e50000: ^^^ imx8mm-evk hangs
Yes, I can reproduce the hang, but it happens with or without the imx8mm dt sync.
Fabio,
I do 'not' see a hang on imx8mm-evk on 'usb start && usb tree' on master (my other issue was on a 'usb stop' but only with usb controllers in host mode).
This hang is a separate issue, not dt related, as far as I understand.
The imx8mm dts sync does solve the issue of running 'ums' after CTRL+C.
I don't agree. The hang 'is' related because all my imx8mm-venice-* boards which use 'both' USB controllers hang with this patch on a 'usb start' and don't hang without it. While a basic 'review' of the patch looks good but actual product testing shows issues. As a maintainer for ARM FREESCALE IMX you must have another imx8mm board which uses both usbotg devices to test against and verify you see what I see?
Until we know what other fix is needed to go along with this: Nacked-by: Tim Harvey tharvey@gateworks.com
What is the harm is sync'ing the device tree with the kernel? I seemed like you found a solution with the regulator patch. Did I misunderstand that?
adam
Adam,
No, the regulator patch did 'not' resolve the issue created by syncing the imx8mm dt (I caused confusion by responding to the wrong thread - the regulator patch resolved a different issue).
Ok.
Could you please verify my results on a board that uses both usbotg1 and usbotg2? What I see is on master + this imx8mm dt sync (specifically the changes from Linux commit 4585c79ff477f ("arm64: dts: imx8mm: correct usb power domains")) the board hangs on usb start when bringing up usbotg2.
Adam,
Sorry to hear that :(
I can, but I am about to board a plane to go visit some sick family, but I'll try to do it early next week. I have a board with both USB controllers enabled. My OTG2 is host-only, so I think it's similar to your setup.
Yes I think that is similar enough to test. In my experience simply enabling otg2 via dt on imx8mm-evk shows the issue I see here but Fabio says he sees a hang on 'usb start' even before this dt sync and I don't know why my results on an imx8mm-evk differ.
Should I apply the regulator patch when I test?
No, don't apply that as this exposes another issue: Error enabling VBUS supply (ret=-114)
I'm still looking into that. I'm assuming when the regulaor refcnt support gets merged it may expose a lot of issues from unbalanced regulator enable/disable calls. The regulator refcnt series resolved the hang I see on 'usb stop' for boards where otg2 is in host mode (internal usb_hub device powers down the power domain before ehci_shutdown tries to access the registers to disable the ports).
Tim
Hi Tim,
On Fri, Apr 28, 2023 at 12:48 PM Tim Harvey tharvey@gateworks.com wrote:
Yes I think that is similar enough to test. In my experience simply enabling otg2 via dt on imx8mm-evk shows the issue I see here but Fabio says he sees a hang on 'usb start' even before this dt sync and I don't know why my results on an imx8mm-evk differ.
I started from scratch today and now our results match.
Applied the following change against U-Boot master:
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi index 7d6317d95b13..898639e33d5e 100644 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ b/arch/arm/dts/imx8mm-evk.dtsi @@ -417,6 +417,10 @@ }; };
+&usbotg2 { + status = "okay"; +}; + &usdhc2 { assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; assigned-clock-rates = <200000000>; diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index ab9ad41b4548..70c7a21f2d9f 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -119,3 +119,4 @@ CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x40400000 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_USB=y
On Fri, Apr 28, 2023 at 11:26 AM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Fri, Apr 28, 2023 at 12:48 PM Tim Harvey tharvey@gateworks.com wrote:
Yes I think that is similar enough to test. In my experience simply enabling otg2 via dt on imx8mm-evk shows the issue I see here but Fabio says he sees a hang on 'usb start' even before this dt sync and I don't know why my results on an imx8mm-evk differ.
I started from scratch today and now our results match.
Applied the following change against U-Boot master:
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi index 7d6317d95b13..898639e33d5e 100644 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ b/arch/arm/dts/imx8mm-evk.dtsi @@ -417,6 +417,10 @@ }; };
+&usbotg2 {
status = "okay";+};
&usdhc2 { assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; assigned-clock-rates = <200000000>; diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index ab9ad41b4548..70c7a21f2d9f 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -119,3 +119,4 @@ CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x40400000 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y
+CONFIG_CMD_USB=y
2.34.1
Running "usb start" does not hang.
Running "ums 0 mmc 1", CTRL+C and then "ums 0 mmc 1" does not work (SD card is not mounted on PC on the second time).
After applying the imx8mm.dtsi sync with kernel 6.3:
Running "ums 0 mmc 1", CTRL+C and then "ums 0 mmc 1" works fine.
"usb start" hangs.
So, yes, I agree we cannot do the imx8mm.dtsi sync with 6.3 right now as we need to fix the USB hang first.
If anyone has any ideas as to why syncing the commit below:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/ar...
causes issues in U-Boot, please let us know.
I am not in a place to test this as I am traveling, but I thought I'd throw out an idea. The power-domain looks like it moved to the usbphynop2 driver which has the compatible name of "usb-nop-xceiv" Is there a a driver for this? Does it get enabled? If not, maybe we could update the imx8mm-u-u-boot.dtsi to restore the power-domains to a driver that is present.
adam
Thanks
On Fri, Apr 28, 2023 at 9:44 AM Adam Ford aford173@gmail.com wrote:
On Fri, Apr 28, 2023 at 11:26 AM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Fri, Apr 28, 2023 at 12:48 PM Tim Harvey tharvey@gateworks.com wrote:
Yes I think that is similar enough to test. In my experience simply enabling otg2 via dt on imx8mm-evk shows the issue I see here but Fabio says he sees a hang on 'usb start' even before this dt sync and I don't know why my results on an imx8mm-evk differ.
I started from scratch today and now our results match.
Applied the following change against U-Boot master:
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi index 7d6317d95b13..898639e33d5e 100644 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ b/arch/arm/dts/imx8mm-evk.dtsi @@ -417,6 +417,10 @@ }; };
+&usbotg2 {
status = "okay";+};
&usdhc2 { assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; assigned-clock-rates = <200000000>; diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index ab9ad41b4548..70c7a21f2d9f 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -119,3 +119,4 @@ CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x40400000 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y
+CONFIG_CMD_USB=y
2.34.1
Running "usb start" does not hang.
Running "ums 0 mmc 1", CTRL+C and then "ums 0 mmc 1" does not work (SD card is not mounted on PC on the second time).
After applying the imx8mm.dtsi sync with kernel 6.3:
Running "ums 0 mmc 1", CTRL+C and then "ums 0 mmc 1" works fine.
"usb start" hangs.
So, yes, I agree we cannot do the imx8mm.dtsi sync with 6.3 right now as we need to fix the USB hang first.
If anyone has any ideas as to why syncing the commit below:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/ar...
causes issues in U-Boot, please let us know.
I am not in a place to test this as I am traveling, but I thought I'd throw out an idea. The power-domain looks like it moved to the usbphynop2 driver which has the compatible name of "usb-nop-xceiv" Is there a a driver for this? Does it get enabled? If not, maybe we could update the imx8mm-u-u-boot.dtsi to restore the power-domains to a driver that is present.
Adam,
Ya, I think you were on the right track here.
There is a driver (driver/phy/nop-phy.c) which does get enabled but with the dt sync the phy's power domain gets enabled after EHCI registers are accessed.
I believe the fix we need is the following which moves phy setup before the register access (where it should have been along with the case for !defined(CONFIG_PHY): diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 91633f013a55..fae20838c60a 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -703,6 +703,10 @@ static int ehci_usb_probe(struct udevice *dev) usb_internal_phy_clock_gate(priv->phy_addr, 1); usb_phy_enable(ehci, priv->phy_addr); #endif +#else + ret = generic_setup_phy(dev, &priv->phy, 0); + if (ret) + goto err_regulator; #endif
#if CONFIG_IS_ENABLED(DM_REGULATOR) @@ -725,12 +729,6 @@ static int ehci_usb_probe(struct udevice *dev)
mdelay(10);
-#if defined(CONFIG_PHY) - ret = generic_setup_phy(dev, &priv->phy, 0); - if (ret) - goto err_regulator; -#endif - hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength); hcor = (struct ehci_hcor *)((uintptr_t)hccr + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
If everyone agrees here I'll submit a formal patch which should get applied through Marek via the usb tree before the dt sync.
Best Regards,
Tim
Hi Tim,
On Fri, Apr 28, 2023 at 2:59 PM Tim Harvey tharvey@gateworks.com wrote:
I believe the fix we need is the following which moves phy setup before the register access (where it should have been along with the case for !defined(CONFIG_PHY):
...
If everyone agrees here I'll submit a formal patch which should get applied through Marek via the usb tree before the dt sync.
This works for me, thanks.
When you submit it, feel free to add:
Tested-by: Fabio Estevam festevam@denx.de
On Fri, Apr 28, 2023 at 11:19 AM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Fri, Apr 28, 2023 at 2:59 PM Tim Harvey tharvey@gateworks.com wrote:
I believe the fix we need is the following which moves phy setup before the register access (where it should have been along with the case for !defined(CONFIG_PHY):
...
If everyone agrees here I'll submit a formal patch which should get applied through Marek via the usb tree before the dt sync.
This works for me, thanks.
When you submit it, feel free to add:
Tested-by: Fabio Estevam festevam@denx.de
Fabio,
with commit bb6ea0fe9290 ("usb: ehci-mx6: move phy setup before register access") now in imx/master: Tested-by: Tim Harvey tharvey@gateworks.com #imx8mm-venice-gw73xx-0x
Best Regards,
Tim
On Wed, May 3, 2023 at 9:11 AM Tim Harvey tharvey@gateworks.com wrote:
On Fri, Apr 28, 2023 at 11:19 AM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Fri, Apr 28, 2023 at 2:59 PM Tim Harvey tharvey@gateworks.com wrote:
I believe the fix we need is the following which moves phy setup before the register access (where it should have been along with the case for !defined(CONFIG_PHY):
...
If everyone agrees here I'll submit a formal patch which should get applied through Marek via the usb tree before the dt sync.
This works for me, thanks.
When you submit it, feel free to add:
Tested-by: Fabio Estevam festevam@denx.de
Fabio,
with commit bb6ea0fe9290 ("usb: ehci-mx6: move phy setup before register access") now in imx/master: Tested-by: Tim Harvey tharvey@gateworks.com #imx8mm-venice-gw73xx-0x
Stefano,
It doesn't look like this got picked up in your latest tree for some reason.
Best regards,
Tim
Hi Tim, Fabio,
On 14.07.23 02:42, Tim Harvey wrote:
On Wed, May 3, 2023 at 9:11 AM Tim Harvey tharvey@gateworks.com wrote:
On Fri, Apr 28, 2023 at 11:19 AM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Fri, Apr 28, 2023 at 2:59 PM Tim Harvey tharvey@gateworks.com wrote:
I believe the fix we need is the following which moves phy setup before the register access (where it should have been along with the case for !defined(CONFIG_PHY):
...
If everyone agrees here I'll submit a formal patch which should get applied through Marek via the usb tree before the dt sync.
This works for me, thanks.
When you submit it, feel free to add:
Tested-by: Fabio Estevam festevam@denx.de
Fabio,
with commit bb6ea0fe9290 ("usb: ehci-mx6: move phy setup before register access") now in imx/master: Tested-by: Tim Harvey tharvey@gateworks.com #imx8mm-venice-gw73xx-0x
Stefano,
It doesn't look like this got picked up in your latest tree for some reason.
Series disappeared from my list in patchworks, maybe because I erroneously thought that a V2 will be sent. I will pick up the series, thanks for advising.
Best regards, Stefano
Best regards,
Tim
On Thu, Jul 13, 2023 at 10:17 PM Stefano Babic sbabic@denx.de wrote:
Hi Tim, Fabio,
On 14.07.23 02:42, Tim Harvey wrote:
On Wed, May 3, 2023 at 9:11 AM Tim Harvey tharvey@gateworks.com wrote:
On Fri, Apr 28, 2023 at 11:19 AM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Fri, Apr 28, 2023 at 2:59 PM Tim Harvey tharvey@gateworks.com wrote:
I believe the fix we need is the following which moves phy setup before the register access (where it should have been along with the case for !defined(CONFIG_PHY):
...
If everyone agrees here I'll submit a formal patch which should get applied through Marek via the usb tree before the dt sync.
This works for me, thanks.
When you submit it, feel free to add:
Tested-by: Fabio Estevam festevam@denx.de
Fabio,
with commit bb6ea0fe9290 ("usb: ehci-mx6: move phy setup before register access") now in imx/master: Tested-by: Tim Harvey tharvey@gateworks.com #imx8mm-venice-gw73xx-0x
Stefano,
It doesn't look like this got picked up in your latest tree for some reason.
Series disappeared from my list in patchworks, maybe because I erroneously thought that a V2 will be sent. I will pick up the series, thanks for advising.
Best regards, Stefano
Hi Stefano,
This series [1] is still missing - can you pick it up?
[PATCH 1/3] arm: dts: imx8mm: Sync with Linux 6.3 [PATCH 2/3] arm: dts: imx8mn: Sync with Linux 6.3 [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3
Best Regards,
Tim [1] https://patchwork.ozlabs.org/project/uboot/list/?series=352685&state=*
On 17.10.23 21:21, Tim Harvey wrote:
On Thu, Jul 13, 2023 at 10:17 PM Stefano Babic sbabic@denx.de wrote:
Hi Tim, Fabio,
On 14.07.23 02:42, Tim Harvey wrote:
On Wed, May 3, 2023 at 9:11 AM Tim Harvey tharvey@gateworks.com wrote:
On Fri, Apr 28, 2023 at 11:19 AM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Fri, Apr 28, 2023 at 2:59 PM Tim Harvey tharvey@gateworks.com wrote:
I believe the fix we need is the following which moves phy setup before the register access (where it should have been along with the case for !defined(CONFIG_PHY):
...
If everyone agrees here I'll submit a formal patch which should get applied through Marek via the usb tree before the dt sync.
This works for me, thanks.
When you submit it, feel free to add:
Tested-by: Fabio Estevam festevam@denx.de
Fabio,
with commit bb6ea0fe9290 ("usb: ehci-mx6: move phy setup before register access") now in imx/master: Tested-by: Tim Harvey tharvey@gateworks.com #imx8mm-venice-gw73xx-0x
Stefano,
It doesn't look like this got picked up in your latest tree for some reason.
Series disappeared from my list in patchworks, maybe because I erroneously thought that a V2 will be sent. I will pick up the series, thanks for advising.
Best regards, Stefano
Hi Stefano,
This series [1] is still missing - can you pick it up?
[PATCH 1/3] arm: dts: imx8mm: Sync with Linux 6.3 [PATCH 2/3] arm: dts: imx8mn: Sync with Linux 6.3 [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3
Best Regards,
Tim [1] https://patchwork.ozlabs.org/project/uboot/list/?series=352685&state=*
It was set as "Superseeded", that is the reason why it disappeared by my list. Thanks for pointing out, I have added again to be merged.
Regards, Stefano
Hi Fabio, Tim,
On 17.10.23 22:28, Stefano Babic wrote:
On 17.10.23 21:21, Tim Harvey wrote:
On Thu, Jul 13, 2023 at 10:17 PM Stefano Babic sbabic@denx.de wrote:
Hi Tim, Fabio,
On 14.07.23 02:42, Tim Harvey wrote:
On Wed, May 3, 2023 at 9:11 AM Tim Harvey tharvey@gateworks.com wrote:
On Fri, Apr 28, 2023 at 11:19 AM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Fri, Apr 28, 2023 at 2:59 PM Tim Harvey tharvey@gateworks.com wrote:
> I believe the fix we need is the following which moves phy setup > before the register access (where it should have been along with the > case for !defined(CONFIG_PHY): ... > If everyone agrees here I'll submit a formal patch which should get > applied through Marek via the usb tree before the dt sync.
This works for me, thanks.
When you submit it, feel free to add:
Tested-by: Fabio Estevam festevam@denx.de
Fabio,
with commit bb6ea0fe9290 ("usb: ehci-mx6: move phy setup before register access") now in imx/master: Tested-by: Tim Harvey tharvey@gateworks.com #imx8mm-venice-gw73xx-0x
Stefano,
It doesn't look like this got picked up in your latest tree for some reason.
Series disappeared from my list in patchworks, maybe because I erroneously thought that a V2 will be sent. I will pick up the series, thanks for advising.
Best regards, Stefano
Hi Stefano,
This series [1] is still missing - can you pick it up?
[PATCH 1/3] arm: dts: imx8mm: Sync with Linux 6.3 [PATCH 2/3] arm: dts: imx8mn: Sync with Linux 6.3 [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3
Best Regards,
Tim [1] https://patchwork.ozlabs.org/project/uboot/list/?series=352685&state=*
It was set as "Superseeded", that is the reason why it disappeared by my list. Thanks for pointing out, I have added again to be merged.
Rather they were forgotten, and they need a rebase. Can you check ?
Best regards, Stefano
On Thu, Apr 27, 2023 at 1:08 PM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Sync imx8mm.dtsi with Linux 6.3.
The motivation for doing this sync was a bug when doing "ums 0 mmc 1" on imx8mm-evk. It worked well for the first time, but after doing a CTRL+C and launching the ums again, the command did not work.
Adam Ford suggested to sync imx8mm.dtsi with the Linux dts, as there was a recent USB power domain reorganization there.
After syncing the imx8mm.dtsi with Linux, the ums command works without problem after a CTRL+C.
Suggested-by: Adam Ford aford173@gmail.com Signed-off-by: Fabio Estevam festevam@denx.de
Reviewed-by: Adam Ford aford173@gmail.com
arch/arm/dts/imx8mm.dtsi | 52 +++++++++++++++++++++++++++++----------- 1 file changed, 38 insertions(+), 14 deletions(-)
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index afb90f59c83c..31f4548f85cf 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>;
cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>;@@ -276,6 +277,7 @@ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk";
power-domains = <&pgc_otg1>; }; usbphynop2: usbphynop2 {@@ -285,6 +287,7 @@ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk";
power-domains = <&pgc_otg2>; }; soc: soc@0 {@@ -493,6 +496,8 @@ compatible = "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
nvmem-cells = <&tmu_calib>;nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; };@@ -547,8 +552,8 @@ reg = <0x30330000 0x10000>; };
gpr: iomuxc-gpr@30340000 {compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
gpr: syscon@30340000 {compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };@@ -560,22 +565,40 @@ #address-cells = <1>; #size-cells = <1>;
imx8mm_uid: unique-id@410 {
/** The register address below maps to the MX8M* Fusemap Description Table entries this way.* Assuming* reg = <ADDR SIZE>;* then* Fuse Address = (ADDR * 4) + 0x400* Note that if SIZE is greater than 4, then* each subsequent fuse is located at offset* +0x10 in Fusemap Description Table (e.g.* reg = <0x4 0x8> describes fuses 0x410 and* 0x420).*/imx8mm_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; };
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
fec_mac_address: mac-address@90 {
tmu_calib: calib@3c { /* 0x4f0 */reg = <0x3c 4>;};fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; };
anatop: anatop@30360000 {compatible = "fsl,imx8mm-anatop", "syscon";
anatop: clock-controller@30360000 {compatible = "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>;#clock-cells = <1>; }; snvs: snvs@30370000 {@@ -674,13 +697,11 @@ pgc_otg1: power-domain@2 { #power-domain-cells = <0>; reg = <IMX8MM_POWER_DOMAIN_OTG1>;
power-domains = <&pgc_hsiomix>; }; pgc_otg2: power-domain@3 { #power-domain-cells = <0>; reg = <IMX8MM_POWER_DOMAIN_OTG2>;power-domains = <&pgc_hsiomix>; }; pgc_gpumix: power-domain@4 {@@ -1186,7 +1207,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_otg1>;
power-domains = <&pgc_hsiomix>; status = "disabled"; };@@ -1206,7 +1227,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>;
power-domains = <&pgc_otg2>;
power-domains = <&pgc_hsiomix>; status = "disabled"; };@@ -1238,16 +1259,15 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; };gpmi: nand-controller@33002000{
gpmi: nand-controller@33002000 { compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;@@ -1282,6 +1302,10 @@ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; linux,pci-domain = <0>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,<&clk IMX8MM_CLK_PCIE1_PHY>,<&clk IMX8MM_CLK_PCIE1_AUX>;clock-names = "pcie", "pcie_bus", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;-- 2.34.1
participants (5)
-
Adam Ford -
Fabio Estevam -
Rasmus Villemoes -
Stefano Babic -
Tim Harvey