[U-Boot] [PATCH 19/31] i2c, mpc83xx: add CONFIG_SYS_I2C_INIT_BOARD for fsl_i2c
This patch adds the possibility to call a board specific i2c bus reset routine for the fsl_i2c bus driver, and adds this option for the keymile kmeter1 board.
Signed-off-by: Heiko Schocher hs@denx.de --- board/keymile/common/common.c | 14 ++++++++++++++ drivers/i2c/fsl_i2c.c | 6 ++++++ include/configs/kmeter1.h | 1 + 3 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 17312b5..a282421 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -421,6 +421,7 @@ static int get_scl (void)
#endif
+#if !defined(CONFIG_KMETER1) static void writeStartSeq (void) { set_sda (1); @@ -471,6 +472,7 @@ static int i2c_make_abort (void) get_sda (); return ret; } +#endif
/** * i2c_init_board - reset i2c bus. When the board is powercycled during a @@ -478,6 +480,17 @@ static int i2c_make_abort (void) */ void i2c_init_board(void) { +#if defined(CONFIG_KMETER1) + struct fsl_i2c *dev; + dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); + uchar dummy; + + out_8 (&dev->cr, (I2C_CR_MSTA)); + out_8 (&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA)); + dummy = in_8(&dev->dr); + out_8 (&dev->cr, (I2C_CR_MEN)); + +#else #if defined(CONFIG_HARD_I2C) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; @@ -497,6 +510,7 @@ void i2c_init_board(void) /* Set the PortPins back to use for I2C */ setports (0); #endif +#endif } #endif #endif diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 5242884..7ba5ab1 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -176,6 +176,12 @@ i2c_init(int speed, int slaveadd) struct fsl_i2c *dev; unsigned int temp;
+#ifdef CONFIG_SYS_I2C_INIT_BOARD + /* call board specific i2c bus reset routine before accessing the */ + /* environment, which might be in a chip on that bus. For details */ + /* about this problem see doc/I2C_Edge_Conditions. */ + i2c_init_board(); +#endif dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
writeb(0, &dev->cr); /* stop I2C controller */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 17ddcec..31e5cd6 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -316,6 +316,7 @@ #define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_MAX_I2C_BUS 2 +#define CONFIG_SYS_I2C_INIT_BOARD 1 #define CONFIG_I2C_MUX 1
/* EEprom support */
This patch adds the possibility to call a board specific i2c bus reset routine for the fsl_i2c bus driver, and adds this option for the keymile kmeter1 board.
Signed-off-by: Heiko Schocher hs@denx.de
board/keymile/common/common.c | 14 ++++++++++++++ drivers/i2c/fsl_i2c.c | 6 ++++++ include/configs/kmeter1.h | 1 + 3 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/board/keymile/common/common.c
b/board/keymile/common/common.c
index 17312b5..a282421 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -421,6 +421,7 @@ static int get_scl (void)
#endif
+#if !defined(CONFIG_KMETER1) static void writeStartSeq (void) { set_sda (1); @@ -471,6 +472,7 @@ static int i2c_make_abort (void) get_sda (); return ret; } +#endif
/**
- i2c_init_board - reset i2c bus. When the board is powercycled during
a
@@ -478,6 +480,17 @@ static int i2c_make_abort (void) */ void i2c_init_board(void) { +#if defined(CONFIG_KMETER1)
- struct fsl_i2c *dev;
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
- uchar dummy;
- out_8 (&dev->cr, (I2C_CR_MSTA));
- out_8 (&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
- dummy = in_8(&dev->dr);
- out_8 (&dev->cr, (I2C_CR_MEN));
Are you sure this will generate a proper I2C reset sequence? We also use this controller and I tried to do it too but didn't find a way. I then asked Freescale and they could not come up with a solution either.
Jocke
Hello Joakim,
Joakim Tjernlund wrote:
This patch adds the possibility to call a board specific i2c bus reset routine for the fsl_i2c bus driver, and adds this option for the keymile kmeter1 board.
[...]
@@ -478,6 +480,17 @@ static int i2c_make_abort (void) */ void i2c_init_board(void) { +#if defined(CONFIG_KMETER1)
- struct fsl_i2c *dev;
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
- uchar dummy;
- out_8 (&dev->cr, (I2C_CR_MSTA));
- out_8 (&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
- dummy = in_8(&dev->dr);
- out_8 (&dev->cr, (I2C_CR_MEN));
Are you sure this will generate a proper I2C reset sequence? We also use this controller and I tried to do it too but didn't find a way. I then asked Freescale and they could not come up with a solution either.
? This routine is decribed in the MPC8260ERM.pdf §15.5.7 on page 15-23 from Freescale!
15.5.7 Generation of SCLn when SDAn is Negated It is sometimes necessary to force the I2C module to become the I2C bus master out of reset and drive SCLn (even though SDAn may already be driven, which indicates that the bus is busy). This can occur when a system reset does not cause all I2C devices to be reset. Thus, SDAn can be negated low by another I2C device while this I2C module is coming out of reset and will stay low indefinitely. The following procedure can be used to force this I2C module to generate SCLn so that the device driving SDAn can finish its transaction: 1. Disable the I2C module and set the master bit by setting I2CnCR to 0x20. 2. Enable the I2C module by setting I2CnCR to 0xA0. 3. Read I2CnDR. 4. Return the I2C module to slave mode by setting I2CnCR to 0x80.
And this worked fine on our Hardware ...
bye Heiko
Heiko Schocher hs@denx.de wrote on 28/01/2009 11:54:22:
Hello Joakim,
Joakim Tjernlund wrote:
This patch adds the possibility to call a board specific i2c bus reset routine for the fsl_i2c bus driver, and adds this option for the keymile kmeter1 board.
[...]
@@ -478,6 +480,17 @@ static int i2c_make_abort (void) */ void i2c_init_board(void) { +#if defined(CONFIG_KMETER1)
- struct fsl_i2c *dev;
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR +
CONFIG_SYS_I2C_OFFSET);
- uchar dummy;
- out_8 (&dev->cr, (I2C_CR_MSTA));
- out_8 (&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
- dummy = in_8(&dev->dr);
- out_8 (&dev->cr, (I2C_CR_MEN));
Are you sure this will generate a proper I2C reset sequence? We also use this controller and I tried to do it too but didn't find a way. I
then
asked Freescale and they could not come up with a solution either.
? This routine is decribed in the MPC8260ERM.pdf §15.5.7 on page 15-23 from Freescale!
15.5.7 Generation of SCLn when SDAn is Negated It is sometimes necessary to force the I2C module to become the I2C bus
master out of reset and drive
SCLn (even though SDAn may already be driven, which indicates that the
bus is busy). This can occur
when a system reset does not cause all I2C devices to be reset. Thus,
SDAn can be negated low by another
I2C device while this I2C module is coming out of reset and will stay
low indefinitely. The following
procedure can be used to force this I2C module to generate SCLn so that
the device driving SDAn can
finish its transaction:
- Disable the I2C module and set the master bit by setting I2CnCR to
0x20.
- Enable the I2C module by setting I2CnCR to 0xA0.
- Read I2CnDR.
- Return the I2C module to slave mode by setting I2CnCR to 0x80.
And this worked fine on our Hardware ...
Ahh, memory slowly returns. The problem is that this does not generate a reset sequence that will work in all cases. Consider the case when the CPU is reset half-way through writing or reading a byte from the device.
I once researched this(can't remember the exact details now) but the only reset sequence that works in all cases is:
static void send_start(void) { I2C_DELAY; I2C_TRISTATE; I2C_SDA(1); I2C_DELAY; I2C_SCL(1); I2C_DELAY; I2C_SDA(0); I2C_ACTIVE; I2C_DELAY; }
static void send_stop(void) { I2C_SCL(0); I2C_DELAY; I2C_SDA(0); I2C_ACTIVE; I2C_DELAY; I2C_SCL(1); I2C_DELAY; I2C_TRISTATE; I2C_SDA(1); I2C_DELAY; }
/*----------------------------------------------------------------------- * Send a reset sequence consisting of 9 clocks with the data signal high * to clock any confused device back into an idle state. Also send a * <stop> at the end of the sequence for belts & suspenders. */ void tm_i2c_reset(int bus) { int j;
I2C_INIT; I2C_TRISTATE; for(j = 0; j < 9; j++) { if(I2C_READ) send_start(); I2C_SCL(0); I2C_DELAY; I2C_TRISTATE; I2C_SDA(1); I2C_DELAY; I2C_SCL(1); I2C_DELAY; I2C_DELAY; } send_stop(); if(!I2C_READ) printf("I2C SDA is low! I2C bus:%d is stuck!!!\n", bus); }
Hello Joakim,
Joakim Tjernlund wrote:
Heiko Schocher hs@denx.de wrote on 28/01/2009 11:54:22:
Joakim Tjernlund wrote:
This patch adds the possibility to call a board specific i2c bus reset routine for the fsl_i2c bus driver, and adds this option for the keymile kmeter1 board.
[...]
@@ -478,6 +480,17 @@ static int i2c_make_abort (void) */ void i2c_init_board(void) { +#if defined(CONFIG_KMETER1)
- struct fsl_i2c *dev;
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR +
CONFIG_SYS_I2C_OFFSET);
- uchar dummy;
- out_8 (&dev->cr, (I2C_CR_MSTA));
- out_8 (&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
- dummy = in_8(&dev->dr);
- out_8 (&dev->cr, (I2C_CR_MEN));
Are you sure this will generate a proper I2C reset sequence? We also use this controller and I tried to do it too but didn't find a way. I
then
asked Freescale and they could not come up with a solution either.
? This routine is decribed in the MPC8260ERM.pdf §15.5.7 on page 15-23 from Freescale!
15.5.7 Generation of SCLn when SDAn is Negated It is sometimes necessary to force the I2C module to become the I2C bus
master out of reset and drive
SCLn (even though SDAn may already be driven, which indicates that the
bus is busy). This can occur
when a system reset does not cause all I2C devices to be reset. Thus,
SDAn can be negated low by another
I2C device while this I2C module is coming out of reset and will stay
low indefinitely. The following
procedure can be used to force this I2C module to generate SCLn so that
the device driving SDAn can
finish its transaction:
- Disable the I2C module and set the master bit by setting I2CnCR to
0x20.
- Enable the I2C module by setting I2CnCR to 0xA0.
- Read I2CnDR.
- Return the I2C module to slave mode by setting I2CnCR to 0x80.
And this worked fine on our Hardware ...
Ahh, memory slowly returns. The problem is that this does not generate a reset sequence that will work in all cases. Consider the case when the CPU is reset half-way through writing or reading a byte from the device.
I once researched this(can't remember the exact details now) but the only reset sequence that works in all cases is:
static void send_start(void) { I2C_DELAY; I2C_TRISTATE; I2C_SDA(1); I2C_DELAY; I2C_SCL(1); I2C_DELAY; I2C_SDA(0); I2C_ACTIVE; I2C_DELAY; }
static void send_stop(void) { I2C_SCL(0); I2C_DELAY; I2C_SDA(0); I2C_ACTIVE; I2C_DELAY; I2C_SCL(1); I2C_DELAY; I2C_TRISTATE; I2C_SDA(1); I2C_DELAY; }
/*-----------------------------------------------------------------------
- Send a reset sequence consisting of 9 clocks with the data signal high
- to clock any confused device back into an idle state. Also send a
- <stop> at the end of the sequence for belts & suspenders.
*/ void tm_i2c_reset(int bus) { int j;
I2C_INIT; I2C_TRISTATE; for(j = 0; j < 9; j++) { if(I2C_READ) send_start(); I2C_SCL(0); I2C_DELAY; I2C_TRISTATE; I2C_SDA(1); I2C_DELAY; I2C_SCL(1); I2C_DELAY; I2C_DELAY; } send_stop(); if(!I2C_READ) printf("I2C SDA is low! I2C bus:%d is stuck!!!\n", bus);}
I dont know if it is possible to make this with the 8360 ...
Maybe we can do the following: - make the reset Sequence suggested from Freescale - checking the Status Register, if the Bus is now free (MBB Bit = 0) If not, do again the reset Sequence. And this for max. 9 times.
What do you think?
bye Heiko
Hello Joakim,
Joakim Tjernlund wrote:
Heiko Schocher hs@denx.de wrote on 28/01/2009 11:54:22:
Joakim Tjernlund wrote:
This patch adds the possibility to call a board specific i2c bus reset routine for the fsl_i2c bus driver, and adds this option for the keymile kmeter1 board.
[...]
@@ -478,6 +480,17 @@ static int i2c_make_abort (void) */ void i2c_init_board(void) { +#if defined(CONFIG_KMETER1)
- struct fsl_i2c *dev;
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR +
CONFIG_SYS_I2C_OFFSET);
- uchar dummy;
- out_8 (&dev->cr, (I2C_CR_MSTA));
- out_8 (&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
- dummy = in_8(&dev->dr);
- out_8 (&dev->cr, (I2C_CR_MEN));
Are you sure this will generate a proper I2C reset sequence? We also use this controller and I tried to do it too but didn't find a way.
I
then
asked Freescale and they could not come up with a solution either.
? This routine is decribed in the MPC8260ERM.pdf §15.5.7 on page 15-23 from Freescale!
15.5.7 Generation of SCLn when SDAn is Negated It is sometimes necessary to force the I2C module to become the I2C
bus
master out of reset and drive
SCLn (even though SDAn may already be driven, which indicates that
the
bus is busy). This can occur
when a system reset does not cause all I2C devices to be reset. Thus,
SDAn can be negated low by another
I2C device while this I2C module is coming out of reset and will stay
low indefinitely. The following
procedure can be used to force this I2C module to generate SCLn so
that
the device driving SDAn can
finish its transaction:
- Disable the I2C module and set the master bit by setting I2CnCR to
0x20.
- Enable the I2C module by setting I2CnCR to 0xA0.
- Read I2CnDR.
- Return the I2C module to slave mode by setting I2CnCR to 0x80.
And this worked fine on our Hardware ...
Ahh, memory slowly returns. The problem is that this does not generate
a
reset sequence that will work in all cases. Consider the case when the CPU is reset half-way through writing or reading a byte from the
device.
I once researched this(can't remember the exact details now) but the only reset sequence that works in all cases is:
static void send_start(void) { I2C_DELAY; I2C_TRISTATE; I2C_SDA(1); I2C_DELAY; I2C_SCL(1); I2C_DELAY; I2C_SDA(0); I2C_ACTIVE; I2C_DELAY; }
static void send_stop(void) { I2C_SCL(0); I2C_DELAY; I2C_SDA(0); I2C_ACTIVE; I2C_DELAY; I2C_SCL(1); I2C_DELAY; I2C_TRISTATE; I2C_SDA(1); I2C_DELAY; }
/*-----------------------------------------------------------------------
- Send a reset sequence consisting of 9 clocks with the data signal
high
- to clock any confused device back into an idle state. Also send a
- <stop> at the end of the sequence for belts & suspenders.
*/ void tm_i2c_reset(int bus) { int j;
I2C_INIT; I2C_TRISTATE; for(j = 0; j < 9; j++) { if(I2C_READ) send_start(); I2C_SCL(0); I2C_DELAY; I2C_TRISTATE; I2C_SDA(1); I2C_DELAY; I2C_SCL(1); I2C_DELAY; I2C_DELAY; } send_stop(); if(!I2C_READ) printf("I2C SDA is low! I2C bus:%d is stuck!!!\n",
bus);
}
I dont know if it is possible to make this with the 8360 ...
Maybe we can do the following:
- make the reset Sequence suggested from Freescale
- checking the Status Register, if the Bus is now free (MBB Bit = 0) If not, do again the reset Sequence. And this for max. 9 times.
What do you think?
It is better, but not complete I think. Looks similar to our old reset procedure that didn't handle the case when a slave was stuck writing a byte but without the STOP condition: I2C_INIT; I2C_SCL(1); I2C_SDA(1); I2C_INIT; I2C_TRISTATE; for(j = 0; j < 9; j++) { I2C_SCL(0); I2C_DELAY; I2C_DELAY; I2C_SCL(1); I2C_DELAY; I2C_DELAY; } send_stop(); if(!I2C_READ) printf("I2C SDA is low! I2C bus is stuck!!!\n");
You need to experiment and you probably need some help from Freescale.
Jocke
participants (2)
-
Heiko Schocher -
Joakim Tjernlund