[PATCH] arm64: zynqmp: remove Avnet UltraZed-EV Starter Kit

Nobody seems interested and able to keep this board supported, and xilinx_zynqmp_virt_defconfig is supposed to be enough for any zynqmp board.
See the discussion at: https://lore.kernel.org/u-boot/CAPnjgZ3hHbyiFf=_Lp-Wz_XOWBkV-3vK4Q3xp=7bcERw...
Signed-off-by: Luca Ceresoli luca.ceresoli@bootlin.com --- arch/arm/dts/Makefile | 1 - ...ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts | 59 ------------- arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi | 56 ------------- board/xilinx/zynqmp/MAINTAINERS | 6 -- ...edev_cc_v1_0_ultrazedev_som_v1_0_defconfig | 83 ------------------- 5 files changed, 205 deletions(-) delete mode 100644 arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts delete mode 100644 arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi delete mode 100644 configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b3baaf482908..79bec315a2a5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -336,7 +336,6 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zybo-z7.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ avnet-ultra96-rev1.dtb \ - avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \ zynqmp-a2197-revA.dtb \ zynqmp-dlc21-revA.dtb \ zynqmp-e-a2197-00-revA.dtb \ diff --git a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts deleted file mode 100644 index 6d1448e8697a..000000000000 --- a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 - -/* - * UltraZed-EV Carrier Card v1 (based on the UltraZed-EV SoM) - * http://ultrazed.org/product/ultrazed-ev-carrier-card - */ - -/dts-v1/; - -#include "avnet-ultrazedev-som-v1.0.dtsi" - -/ { - model = "Avnet UltraZed EV Carrier Card v1.0"; - compatible = "avnet,ultrazedev-cc-v1.0-ultrazedev-som-v1.0", - "xlnx,zynqmp"; - chosen { - stdout-path = "serial0:115200n8"; - }; - aliases { - ethernet0 = &gem3; - nvmem0 = &eeprom; - serial0 = &uart0; - }; -}; - -&uart0 { - device_type = "serial"; - status = "okay"; -}; - -&i2c_cc { - /* Microchip 24AA025E48T-I/OT: 2K I2C Serial EEPROM with EUI-48 */ - eeprom: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - }; - - /* IDT Versa Clock 5P49V5935B */ - vc5: clock-generator@6a { - compatible = "idt,5p49v5935"; - reg = <0x6a>; - #clock-cells = <1>; - }; -}; - -/* Ethernet RJ-45 */ -&gem3 { - status = "okay"; -}; - -/* microSD card slot */ -&sdhci1 { - status = "okay"; - xlnx,mio-bank = <1>; - clock-frequency = <199998000>; - max-frequency = <50000000>; - no-1-8-v; - disable-wp; -}; diff --git a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi deleted file mode 100644 index cbcb290a5c83..000000000000 --- a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 - -/* - * UltraZed-EV SoM v1 - * http://ultrazed.org/product/ultrazed-ev - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" - -/ { - model = "Avnet UltraZed EV SoM v1.0"; - compatible = "avnet,ultrazedev-som-v1.0", "xlnx,zynqmp"; - memory { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */ - <0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */ - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - i2cswitch@70 { - compatible = "nxp,pca9543"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - /* I2C connected to Carrier Card via JX3A1/JX3C1 */ - i2c_cc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */ -&gem3 { - phy-mode = "rgmii-id"; - phy-handle = <&gem3phy>; - gem3phy: ethernet-phy@0 { - reg = <0>; - }; -}; - -/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */ -&sdhci0 { - status = "okay"; - xlnx,mio-bank = <0>; - clock-frequency = <199998000>; -}; diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index 07b91b81c95b..a4527f8959ab 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -9,9 +9,3 @@ F: board/xilinx/zynqmp/ F: include/configs/xilinx_zynqmp* F: configs/xilinx_zynqmp* F: configs/avnet_ultra96_rev1_defconfig - -ARM ZYNQMP AVNET ULTRAZED EV BOARD -M: Luca Ceresoli luca.ceresoli@bootlin.com -S: Maintained -F: arch/arm/dts/avnet-ultrazedev-* -F: configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig deleted file mode 100644 index 0a3d710a8b1f..000000000000 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ /dev/null @@ -1,83 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_LEN=0x4008000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0" -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y -CONFIG_SYS_LOAD_ADDR=0x8000000 -CONFIG_DEBUG_UART=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x00001000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000000 -CONFIG_REMAKE_ELF=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000 -CONFIG_BOOTDELAY=0 -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_CLOCKS=y -CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0xfffffffc -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20000000 -CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 -CONFIG_SPL_FS_LOAD_KERNEL_NAME="atf-uboot.ub" -CONFIG_SPL_FS_LOAD_ARGS_NAME="u-boot.bin" -CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_SPL_ARGS_ADDR=0x8000000 -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=2073 -CONFIG_SYS_BOOTM_LEN=0x6400000 -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SPI=y -CONFIG_BOOTP_MAY_FAIL=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_CLK_ZYNQMP=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ARM_DCC=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_PANIC_HANG=y -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

On 1/10/23 08:35, Luca Ceresoli wrote:
Nobody seems interested and able to keep this board supported, and xilinx_zynqmp_virt_defconfig is supposed to be enough for any zynqmp board.
Just to make it clear. Config wise yes. But of course you need to have dt file and also psu_init* if you want to use SPL.
See the discussion at: https://lore.kernel.org/u-boot/CAPnjgZ3hHbyiFf=_Lp-Wz_XOWBkV-3vK4Q3xp=7bcERw...
Signed-off-by: Luca Ceresoli luca.ceresoli@bootlin.com
arch/arm/dts/Makefile | 1 - ...ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts | 59 ------------- arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi | 56 ------------- board/xilinx/zynqmp/MAINTAINERS | 6 -- ...edev_cc_v1_0_ultrazedev_som_v1_0_defconfig | 83 ------------------- 5 files changed, 205 deletions(-) delete mode 100644 arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts delete mode 100644 arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi delete mode 100644 configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
You also forget to remove this folder.
board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/
Thanks, Michal
participants (2)
-
Luca Ceresoli
-
Michal Simek