Synchronize the Amlogic ARM64 dts from mainline Linux 4.13.5

In the preparation of the support of the Amlogic P212 board, import the corresponding meson-gxl-s905x-p212.dts file.

Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/meson-gx.dtsi | 13 +- arch/arm/dts/meson-gxbb-odroidc2.dts | 108 ++--- arch/arm/dts/meson-gxbb.dtsi | 220 +++++++---- arch/arm/dts/meson-gxl-mali.dtsi | 43 ++ arch/arm/dts/meson-gxl-s905x-p212.dts | 95 +++++ arch/arm/dts/meson-gxl-s905x-p212.dtsi | 173 ++++++++ arch/arm/dts/meson-gxl-s905x.dtsi | 55 +++ arch/arm/dts/meson-gxl.dtsi | 628 ++++++++++++++++++++++++++++++ include/dt-bindings/gpio/meson-gxl-gpio.h | 131 +++++++ 10 files changed, 1326 insertions(+), 143 deletions(-) create mode 100644 arch/arm/dts/meson-gxl-mali.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905x-p212.dts create mode 100644 arch/arm/dts/meson-gxl-s905x-p212.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905x.dtsi create mode 100644 arch/arm/dts/meson-gxl.dtsi create mode 100644 include/dt-bindings/gpio/meson-gxl-gpio.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5b90280..8a07f53 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -54,7 +54,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3399-puma-ddr1866.dtb \ rv1108-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ - meson-gxbb-odroidc2.dtb + meson-gxbb-odroidc2.dtb \ + meson-gxl-s905x-p212.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi index 436b875..738ed68 100644 --- a/arch/arm/dts/meson-gx.dtsi +++ b/arch/arm/dts/meson-gx.dtsi @@ -200,7 +200,7 @@ };

scpi_sensors: sensors { - compatible = "arm,scpi-sensors"; + compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; #thermal-sensor-cells = <1>; }; }; @@ -304,6 +304,15 @@ status = "disabled"; };

+ spicc: spi@8d80 { + compatible = "amlogic,meson-gx-spicc"; + reg = <0x0 0x08d80 0x0 0x80>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spifc: spi@8c80 { compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc"; reg = <0x0 0x08c80 0x0 0x80>; @@ -391,7 +400,7 @@ };

pwm_AO_ab: pwm@550 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; + compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; reg = <0x0 0x00550 0x0 0x10>; #pwm-cells = <3>; status = "disabled"; diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts index 54a9c6a..d147c85 100644 --- a/arch/arm/dts/meson-gxbb-odroidc2.dts +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts @@ -137,16 +137,6 @@ }; };

-&scpi_clocks { - status = "disabled"; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - &ethmac { status = "okay"; pinctrl-0 = <&eth_rgmii_pins>; @@ -172,6 +162,33 @@ }; };

+&gpio_ao { + /* + * WARNING: The USB Hub on the Odroid-C2 needs a reset signal + * to be turned high in order to be detected by the USB Controller + * This signal should be handled by a USB specific power sequence + * in order to reset the Hub when USB bus is powered down. + */ + usb-hub { + gpio-hog; + gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&i2c_A { + status = "okay"; + pinctrl-0 = <&i2c_a_pins>; + pinctrl-names = "default"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + &pinctrl_aobus { gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En", "USB HUB nRESET", "USB OTG Power En", @@ -223,55 +240,15 @@ ""; };

-&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&gpio_ao { - /* - * WARNING: The USB Hub on the Odroid-C2 needs a reset signal - * to be turned high in order to be detected by the USB Controller - * This signal should be handled by a USB specific power sequence - * in order to reset the Hub when USB bus is powered down. - */ - usb-hub { - gpio-hog; - gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&usb0_phy { - status = "okay"; - phy-supply = <&usb_otg_pwr>; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - &saradc { status = "okay"; vref-supply = <&vcc1v8>; };

+&scpi_clocks { + status = "disabled"; +}; + /* SD */ &sd_emmc_b { status = "okay"; @@ -309,3 +286,26 @@ vmmc-supply = <&vcc3v3>; vqmmc-supply = <&vcc1v8>; }; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb0_phy { + status = "okay"; + phy-supply = <&usb_otg_pwr>; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi index 86105a6..17d3efd 100644 --- a/arch/arm/dts/meson-gxbb.dtsi +++ b/arch/arm/dts/meson-gxbb.dtsi @@ -97,13 +97,6 @@ }; };

-&ethmac { - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; -}; - &aobus { pinctrl_aobus: pinctrl@14 { compatible = "amlogic,meson-gxbb-aobus-pinctrl"; @@ -249,9 +242,119 @@ function = "spdif_out_ao"; }; }; + + ao_cec_pins: ao_cec { + mux { + groups = "ao_cec"; + function = "cec_ao"; + }; + }; + + ee_cec_pins: ee_cec { + mux { + groups = "ee_cec"; + function = "cec_ao"; + }; + }; + }; +}; + +&apb { + mali: gpu@c0000 { + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + reg = <0x0 0xc0000 0x0 0x40000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + + /* + * Mali clocking is provided by two identical clock paths + * MALI_0 and MALI_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + */ + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + <&clkc CLKID_MALI_0>, + <&clkc CLKID_MALI>; /* Glitch free mux */ + assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, /* Do Nothing */ + <&clkc CLKID_MALI_0>; + assigned-clock-rates = <0>, /* Do Nothing */ + <666666666>, + <0>; /* Do Nothing */ + }; +}; + +&cbus { + spifc: spi@8c80 { + compatible = "amlogic,meson-gxbb-spifc"; + reg = <0x0 0x08c80 0x0 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_SPI>; + status = "disabled"; + }; +}; + +&ethmac { + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; +}; + +&hdmi_tx { + compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; + resets = <&reset RESET_HDMITX_CAPB3>, + <&reset RESET_HDMI_SYSTEM_RESET>, + <&reset RESET_HDMI_TX>; + reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; + clocks = <&clkc CLKID_HDMI_PCLK>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_GCLK_VENCI_INT0>; + clock-names = "isfr", "iahb", "venci"; +}; + +&hiubus { + clkc: clock-controller@0 { + compatible = "amlogic,gxbb-clkc"; + #clock-cells = <1>; + reg = <0x0 0x0 0x0 0x3db>; }; };

+&hwrng { + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; +}; + +&i2c_A { + clocks = <&clkc CLKID_I2C>; +}; + +&i2c_AO { + clocks = <&clkc CLKID_AO_I2C>; +}; + +&i2c_B { + clocks = <&clkc CLKID_I2C>; +}; + +&i2c_C { + clocks = <&clkc CLKID_I2C>; +}; + &periphs { pinctrl_periphs: pinctrl@4b0 { compatible = "amlogic,meson-gxbb-periphs-pinctrl"; @@ -262,7 +365,7 @@ gpio: bank@4b0 { reg = <0x0 0x004b0 0x0 0x28>, <0x0 0x004e8 0x0 0x14>, - <0x0 0x00120 0x0 0x14>, + <0x0 0x00520 0x0 0x14>, <0x0 0x00430 0x0 0x40>; reg-names = "mux", "pull", "pull-enable", "gpio"; gpio-controller; @@ -290,6 +393,22 @@ }; };

+ spi_pins: spi { + mux { + groups = "spi_miso", + "spi_mosi", + "spi_sclk"; + function = "spi"; + }; + }; + + spi_ss0_pins: spi-ss0 { + mux { + groups = "spi_ss0"; + function = "spi"; + }; + }; + sdcard_pins: sdcard { mux { groups = "sdcard_d0", @@ -521,67 +640,6 @@ }; };

-&hiubus { - clkc: clock-controller@0 { - compatible = "amlogic,gxbb-clkc"; - #clock-cells = <1>; - reg = <0x0 0x0 0x0 0x3db>; - }; -}; - -&apb { - mali: gpu@c0000 { - compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>; /* Do Nothing */ - }; -}; - -&i2c_A { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_AO { - clocks = <&clkc CLKID_AO_I2C>; -}; - -&i2c_B { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_C { - clocks = <&clkc CLKID_I2C>; -}; - &saradc { compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc"; clocks = <&xtal>, @@ -613,6 +671,13 @@ clock-names = "core", "clkin0", "clkin1"; };

+&spicc { + clocks = <&clkc CLKID_SPICC>; + clock-names = "core"; + resets = <&reset RESET_PERIPHS_SPICC>; + num-cs = <1>; +}; + &spifc { clocks = <&clkc CLKID_SPI>; }; @@ -620,20 +685,3 @@ &vpu { compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; }; - -&hwrng { - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; -}; - -&hdmi_tx { - compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; - resets = <&reset RESET_HDMITX_CAPB3>, - <&reset RESET_HDMI_SYSTEM_RESET>, - <&reset RESET_HDMI_TX>; - reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; - clock-names = "isfr", "iahb", "venci"; -}; diff --git a/arch/arm/dts/meson-gxl-mali.dtsi b/arch/arm/dts/meson-gxl-mali.dtsi new file mode 100644 index 0000000..f06cc23 --- /dev/null +++ b/arch/arm/dts/meson-gxl-mali.dtsi @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2017 BayLibre SAS + * Author: Neil Armstrong narmstrong@baylibre.com + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +&apb { + mali: gpu@c0000 { + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + reg = <0x0 0xc0000 0x0 0x40000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + + /* + * Mali clocking is provided by two identical clock paths + * MALI_0 and MALI_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + */ + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + <&clkc CLKID_MALI_0>, + <&clkc CLKID_MALI>; /* Glitch free mux */ + assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, /* Do Nothing */ + <&clkc CLKID_MALI_0>; + assigned-clock-rates = <0>, /* Do Nothing */ + <666666666>, + <0>; /* Do Nothing */ + }; +}; diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dts b/arch/arm/dts/meson-gxl-s905x-p212.dts new file mode 100644 index 0000000..6ab17c1 --- /dev/null +++ b/arch/arm/dts/meson-gxl-s905x-p212.dts @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione carlo@endlessm.com + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-gxl-s905x-p212.dtsi" + +/ { + compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl"; + model = "Amlogic Meson GXL (S905X) P212 Development Board"; + + cvbs-connector { + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_AO { + status = "okay"; +}; diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi new file mode 100644 index 0000000..f3eea8e --- /dev/null +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2016 Martin Blumenstingl martin.blumenstingl@googlemail.com. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione carlo@endlessm.com + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong narmstrong@baylibre.com + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-gxl-s905x.dtsi" + +/ { + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +&ethmac { + status = "okay"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; + +/* This is connected to the Bluetooth module: */ +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/dts/meson-gxl-s905x.dtsi b/arch/arm/dts/meson-gxl-s905x.dtsi new file mode 100644 index 0000000..3314a0b --- /dev/null +++ b/arch/arm/dts/meson-gxl-s905x.dtsi @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione carlo@endlessm.com + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-gxl.dtsi" +#include "meson-gxl-mali.dtsi" + +/ { + compatible = "amlogic,s905x", "amlogic,meson-gxl"; +}; + +/* S905X only has access to its internal PHY */ +&ethmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +}; diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi new file mode 100644 index 0000000..8d4f316 --- /dev/null +++ b/arch/arm/dts/meson-gxl.dtsi @@ -0,0 +1,628 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione carlo@endlessm.com + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-gx.dtsi" +#include <dt-bindings/clock/gxbb-clkc.h> +#include <dt-bindings/gpio/meson-gxl-gpio.h> +#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> + +/ { + compatible = "amlogic,meson-gxl"; +}; + +&ethmac { + reg = <0x0 0xc9410000 0x0 0x10000 + 0x0 0xc8834540 0x0 0x4>; + + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + +&aobus { + pinctrl_aobus: pinctrl@14 { + compatible = "amlogic,meson-gxl-aobus-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio_ao: bank@14 { + reg = <0x0 0x00014 0x0 0x8>, + <0x0 0x0002c 0x0 0x4>, + <0x0 0x00024 0x0 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aobus 0 0 14>; + }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_tx_ao_a", "uart_rx_ao_a"; + function = "uart_ao"; + }; + }; + + uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { + mux { + groups = "uart_cts_ao_a", + "uart_rts_ao_a"; + function = "uart_ao"; + }; + }; + + uart_ao_b_pins: uart_ao_b { + mux { + groups = "uart_tx_ao_b", "uart_rx_ao_b"; + function = "uart_ao_b"; + }; + }; + + uart_ao_b_0_1_pins: uart_ao_b_0_1 { + mux { + groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1"; + function = "uart_ao_b"; + }; + }; + + uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { + mux { + groups = "uart_cts_ao_b", + "uart_rts_ao_b"; + function = "uart_ao_b"; + }; + }; + + remote_input_ao_pins: remote_input_ao { + mux { + groups = "remote_input_ao"; + function = "remote_input_ao"; + }; + }; + + i2c_ao_pins: i2c_ao { + mux { + groups = "i2c_sck_ao", + "i2c_sda_ao"; + function = "i2c_ao"; + }; + }; + + pwm_ao_a_3_pins: pwm_ao_a_3 { + mux { + groups = "pwm_ao_a_3"; + function = "pwm_ao_a"; + }; + }; + + pwm_ao_a_8_pins: pwm_ao_a_8 { + mux { + groups = "pwm_ao_a_8"; + function = "pwm_ao_a"; + }; + }; + + pwm_ao_b_pins: pwm_ao_b { + mux { + groups = "pwm_ao_b"; + function = "pwm_ao_b"; + }; + }; + + pwm_ao_b_6_pins: pwm_ao_b_6 { + mux { + groups = "pwm_ao_b_6"; + function = "pwm_ao_b"; + }; + }; + + i2s_out_ch23_ao_pins: i2s_out_ch23_ao { + mux { + groups = "i2s_out_ch23_ao"; + function = "i2s_out_ao"; + }; + }; + + i2s_out_ch45_ao_pins: i2s_out_ch45_ao { + mux { + groups = "i2s_out_ch45_ao"; + function = "i2s_out_ao"; + }; + }; + + spdif_out_ao_6_pins: spdif_out_ao_6 { + mux { + groups = "spdif_out_ao_6"; + function = "spdif_out_ao"; + }; + }; + + spdif_out_ao_9_pins: spdif_out_ao_9 { + mux { + groups = "spdif_out_ao_9"; + function = "spdif_out_ao"; + }; + }; + + ao_cec_pins: ao_cec { + mux { + groups = "ao_cec"; + function = "cec_ao"; + }; + }; + + ee_cec_pins: ee_cec { + mux { + groups = "ee_cec"; + function = "cec_ao"; + }; + }; + }; +}; + +&hdmi_tx { + compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; + resets = <&reset RESET_HDMITX_CAPB3>, + <&reset RESET_HDMI_SYSTEM_RESET>, + <&reset RESET_HDMI_TX>; + reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; + clocks = <&clkc CLKID_HDMI_PCLK>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_GCLK_VENCI_INT0>; + clock-names = "isfr", "iahb", "venci"; +}; + +&hiubus { + clkc: clock-controller@0 { + compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc"; + #clock-cells = <1>; + reg = <0x0 0x0 0x0 0x3db>; + }; +}; + +&i2c_A { + clocks = <&clkc CLKID_I2C>; +}; + +&i2c_AO { + clocks = <&clkc CLKID_AO_I2C>; +}; + +&i2c_B { + clocks = <&clkc CLKID_I2C>; +}; + +&i2c_C { + clocks = <&clkc CLKID_I2C>; +}; + +&periphs { + pinctrl_periphs: pinctrl@4b0 { + compatible = "amlogic,meson-gxl-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@4b0 { + reg = <0x0 0x004b0 0x0 0x28>, + <0x0 0x004e8 0x0 0x14>, + <0x0 0x00520 0x0 0x14>, + <0x0 0x00430 0x0 0x40>; + reg-names = "mux", "pull", "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_periphs 0 10 101>; + }; + + emmc_pins: emmc { + mux { + groups = "emmc_nand_d07", + "emmc_cmd", + "emmc_clk", + "emmc_ds"; + function = "emmc"; + }; + }; + + nor_pins: nor { + mux { + groups = "nor_d", + "nor_q", + "nor_c", + "nor_cs"; + function = "nor"; + }; + }; + + spi_pins: spi { + mux { + groups = "spi_miso", + "spi_mosi", + "spi_sclk"; + function = "spi"; + }; + }; + + spi_ss0_pins: spi-ss0 { + mux { + groups = "spi_ss0"; + function = "spi"; + }; + }; + + sdcard_pins: sdcard { + mux { + groups = "sdcard_d0", + "sdcard_d1", + "sdcard_d2", + "sdcard_d3", + "sdcard_cmd", + "sdcard_clk"; + function = "sdcard"; + }; + }; + + sdio_pins: sdio { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_cmd", + "sdio_clk"; + function = "sdio"; + }; + }; + + sdio_irq_pins: sdio_irq { + mux { + groups = "sdio_irq"; + function = "sdio"; + }; + }; + + uart_a_pins: uart_a { + mux { + groups = "uart_tx_a", + "uart_rx_a"; + function = "uart_a"; + }; + }; + + uart_a_cts_rts_pins: uart_a_cts_rts { + mux { + groups = "uart_cts_a", + "uart_rts_a"; + function = "uart_a"; + }; + }; + + uart_b_pins: uart_b { + mux { + groups = "uart_tx_b", + "uart_rx_b"; + function = "uart_b"; + }; + }; + + uart_b_cts_rts_pins: uart_b_cts_rts { + mux { + groups = "uart_cts_b", + "uart_rts_b"; + function = "uart_b"; + }; + }; + + uart_c_pins: uart_c { + mux { + groups = "uart_tx_c", + "uart_rx_c"; + function = "uart_c"; + }; + }; + + uart_c_cts_rts_pins: uart_c_cts_rts { + mux { + groups = "uart_cts_c", + "uart_rts_c"; + function = "uart_c"; + }; + }; + + i2c_a_pins: i2c_a { + mux { + groups = "i2c_sck_a", + "i2c_sda_a"; + function = "i2c_a"; + }; + }; + + i2c_b_pins: i2c_b { + mux { + groups = "i2c_sck_b", + "i2c_sda_b"; + function = "i2c_b"; + }; + }; + + i2c_c_pins: i2c_c { + mux { + groups = "i2c_sck_c", + "i2c_sda_c"; + function = "i2c_c"; + }; + }; + + eth_pins: eth_c { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_clk_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_rxd2", + "eth_rxd3", + "eth_rgmii_tx_clk", + "eth_tx_en", + "eth_txd0", + "eth_txd1", + "eth_txd2", + "eth_txd3"; + function = "eth"; + }; + }; + + eth_link_led_pins: eth_link_led { + mux { + groups = "eth_link_led"; + function = "eth_led"; + }; + }; + + eth_act_led_pins: eth_act_led { + mux { + groups = "eth_act_led"; + function = "eth_led"; + }; + }; + + pwm_a_pins: pwm_a { + mux { + groups = "pwm_a"; + function = "pwm_a"; + }; + }; + + pwm_b_pins: pwm_b { + mux { + groups = "pwm_b"; + function = "pwm_b"; + }; + }; + + pwm_c_pins: pwm_c { + mux { + groups = "pwm_c"; + function = "pwm_c"; + }; + }; + + pwm_d_pins: pwm_d { + mux { + groups = "pwm_d"; + function = "pwm_d"; + }; + }; + + pwm_e_pins: pwm_e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; + + pwm_f_clk_pins: pwm_f_clk { + mux { + groups = "pwm_f_clk"; + function = "pwm_f"; + }; + }; + + pwm_f_x_pins: pwm_f_x { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + }; + }; + + hdmi_hpd_pins: hdmi_hpd { + mux { + groups = "hdmi_hpd"; + function = "hdmi_hpd"; + }; + }; + + hdmi_i2c_pins: hdmi_i2c { + mux { + groups = "hdmi_sda", "hdmi_scl"; + function = "hdmi_i2c"; + }; + }; + + i2s_am_clk_pins: i2s_am_clk { + mux { + groups = "i2s_am_clk"; + function = "i2s_out"; + }; + }; + + i2s_out_ao_clk_pins: i2s_out_ao_clk { + mux { + groups = "i2s_out_ao_clk"; + function = "i2s_out"; + }; + }; + + i2s_out_lr_clk_pins: i2s_out_lr_clk { + mux { + groups = "i2s_out_lr_clk"; + function = "i2s_out"; + }; + }; + + i2s_out_ch01_pins: i2s_out_ch01 { + mux { + groups = "i2s_out_ch01"; + function = "i2s_out"; + }; + }; + i2sout_ch23_z_pins: i2sout_ch23_z { + mux { + groups = "i2sout_ch23_z"; + function = "i2s_out"; + }; + }; + + i2sout_ch45_z_pins: i2sout_ch45_z { + mux { + groups = "i2sout_ch45_z"; + function = "i2s_out"; + }; + }; + + i2sout_ch67_z_pins: i2sout_ch67_z { + mux { + groups = "i2sout_ch67_z"; + function = "i2s_out"; + }; + }; + + spdif_out_h_pins: spdif_out_ao_h { + mux { + groups = "spdif_out_h"; + function = "spdif_out"; + }; + }; + }; + + eth-phy-mux { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x55c 0x0 0x4>; + mux-mask = <0xffffffff>; + mdio-parent-bus = <&mdio0>; + + internal_mdio: mdio@e40908ff { + reg = <0xe40908ff>; + #address-cells = <1>; + #size-cells = <0>; + + internal_phy: ethernet-phy@8 { + compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22"; + reg = <8>; + max-speed = <100>; + }; + }; + + external_mdio: mdio@2009087f { + reg = <0x2009087f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&saradc { + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; + clocks = <&xtal>, + <&clkc CLKID_SAR_ADC>, + <&clkc CLKID_SANA>, + <&clkc CLKID_SAR_ADC_CLK>, + <&clkc CLKID_SAR_ADC_SEL>; + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; +}; + +&sd_emmc_a { + clocks = <&clkc CLKID_SD_EMMC_A>, + <&xtal>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; +}; + +&sd_emmc_b { + clocks = <&clkc CLKID_SD_EMMC_B>, + <&xtal>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; +}; + +&sd_emmc_c { + clocks = <&clkc CLKID_SD_EMMC_C>, + <&xtal>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; +}; + +&spicc { + clocks = <&clkc CLKID_SPICC>; + clock-names = "core"; + resets = <&reset RESET_PERIPHS_SPICC>; + num-cs = <1>; +}; + +&spifc { + clocks = <&clkc CLKID_SPI>; +}; + +&vpu { + compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu"; +}; diff --git a/include/dt-bindings/gpio/meson-gxl-gpio.h b/include/dt-bindings/gpio/meson-gxl-gpio.h new file mode 100644 index 0000000..684d0d7 --- /dev/null +++ b/include/dt-bindings/gpio/meson-gxl-gpio.h @@ -0,0 +1,131 @@ +/* + * GPIO definitions for Amlogic Meson GXL SoCs + * + * Copyright (C) 2016 Endless Mobile, Inc. + * Author: Carlo Caione carlo@endlessm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H +#define _DT_BINDINGS_MESON_GXL_GPIO_H + +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 + +#define GPIOZ_0 0 +#define GPIOZ_1 1 +#define GPIOZ_2 2 +#define GPIOZ_3 3 +#define GPIOZ_4 4 +#define GPIOZ_5 5 +#define GPIOZ_6 6 +#define GPIOZ_7 7 +#define GPIOZ_8 8 +#define GPIOZ_9 9 +#define GPIOZ_10 10 +#define GPIOZ_11 11 +#define GPIOZ_12 12 +#define GPIOZ_13 13 +#define GPIOZ_14 14 +#define GPIOZ_15 15 +#define GPIOH_0 16 +#define GPIOH_1 17 +#define GPIOH_2 18 +#define GPIOH_3 19 +#define GPIOH_4 20 +#define GPIOH_5 21 +#define GPIOH_6 22 +#define GPIOH_7 23 +#define GPIOH_8 24 +#define GPIOH_9 25 +#define BOOT_0 26 +#define BOOT_1 27 +#define BOOT_2 28 +#define BOOT_3 29 +#define BOOT_4 30 +#define BOOT_5 31 +#define BOOT_6 32 +#define BOOT_7 33 +#define BOOT_8 34 +#define BOOT_9 35 +#define BOOT_10 36 +#define BOOT_11 37 +#define BOOT_12 38 +#define BOOT_13 39 +#define BOOT_14 40 +#define BOOT_15 41 +#define CARD_0 42 +#define CARD_1 43 +#define CARD_2 44 +#define CARD_3 45 +#define CARD_4 46 +#define CARD_5 47 +#define CARD_6 48 +#define GPIODV_0 49 +#define GPIODV_1 50 +#define GPIODV_2 51 +#define GPIODV_3 52 +#define GPIODV_4 53 +#define GPIODV_5 54 +#define GPIODV_6 55 +#define GPIODV_7 56 +#define GPIODV_8 57 +#define GPIODV_9 58 +#define GPIODV_10 59 +#define GPIODV_11 60 +#define GPIODV_12 61 +#define GPIODV_13 62 +#define GPIODV_14 63 +#define GPIODV_15 64 +#define GPIODV_16 65 +#define GPIODV_17 66 +#define GPIODV_18 67 +#define GPIODV_19 68 +#define GPIODV_20 69 +#define GPIODV_21 70 +#define GPIODV_22 71 +#define GPIODV_23 72 +#define GPIODV_24 73 +#define GPIODV_25 74 +#define GPIODV_26 75 +#define GPIODV_27 76 +#define GPIODV_28 77 +#define GPIODV_29 78 +#define GPIOX_0 79 +#define GPIOX_1 80 +#define GPIOX_2 81 +#define GPIOX_3 82 +#define GPIOX_4 83 +#define GPIOX_5 84 +#define GPIOX_6 85 +#define GPIOX_7 86 +#define GPIOX_8 87 +#define GPIOX_9 88 +#define GPIOX_10 89 +#define GPIOX_11 90 +#define GPIOX_12 91 +#define GPIOX_13 92 +#define GPIOX_14 93 +#define GPIOX_15 94 +#define GPIOX_16 95 +#define GPIOX_17 96 +#define GPIOX_18 97 +#define GPIOCLK_0 98 +#define GPIOCLK_1 99 +#define GPIO_TEST_N 100 + +#endif

Add the Amlogic Meson GXL pinctrl support based on the GXBB driver and the synchronized DTS from Linux 4.13.5

Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/pinctrl/meson/Kconfig | 4 + drivers/pinctrl/meson/Makefile | 1 + drivers/pinctrl/meson/pinctrl-meson-gxl.c | 736 ++++++++++++++++++++++++++++++ 3 files changed, 741 insertions(+) create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gxl.c

diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index c3e6901..27ba890 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -8,4 +8,8 @@ config PINCTRL_MESON_GXBB bool "Amlogic Meson GXBB SoC pinctrl driver" select PINCTRL_MESON

+config PINCTRL_MESON_GXL + bool "Amlogic Meson GXL SoC pinctrl driver" + select PINCTRL_MESON + endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 6dde4bc..18921e3 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -4,3 +4,4 @@

obj-y += pinctrl-meson.o obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o +obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c new file mode 100644 index 0000000..eebfaa9 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -0,0 +1,736 @@ +/* + * (C) Copyright 2016 - Beniamino Galvani b.galvani@gmail.com + * + * Based on code from Linux kernel: + * Copyright (C) 2016 Endless Mobile, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <dt-bindings/gpio/meson-gxl-gpio.h> + +#include "pinctrl-meson.h" + +#define EE_OFF 10 + +static const unsigned int emmc_nand_d07_pins[] = { + PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF), + PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF), + PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF), +}; +static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) }; +static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) }; +static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) }; + +static const unsigned int nor_d_pins[] = { PIN(BOOT_11, EE_OFF) }; +static const unsigned int nor_q_pins[] = { PIN(BOOT_12, EE_OFF) }; +static const unsigned int nor_c_pins[] = { PIN(BOOT_13, EE_OFF) }; +static const unsigned int nor_cs_pins[] = { PIN(BOOT_15, EE_OFF) }; + +static const unsigned int spi_mosi_pins[] = { PIN(GPIOX_8, EE_OFF) }; +static const unsigned int spi_miso_pins[] = { PIN(GPIOX_9, EE_OFF) }; +static const unsigned int spi_ss0_pins[] = { PIN(GPIOX_10, EE_OFF) }; +static const unsigned int spi_sclk_pins[] = { PIN(GPIOX_11, EE_OFF) }; + +static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) }; +static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) }; +static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) }; +static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) }; +static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) }; +static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) }; + +static const unsigned int sdio_d0_pins[] = { PIN(GPIOX_0, EE_OFF) }; +static const unsigned int sdio_d1_pins[] = { PIN(GPIOX_1, EE_OFF) }; +static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) }; +static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) }; +static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) }; +static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) }; +static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) }; + +static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) }; +static const unsigned int nand_ce1_pins[] = { PIN(BOOT_9, EE_OFF) }; +static const unsigned int nand_rb0_pins[] = { PIN(BOOT_10, EE_OFF) }; +static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, EE_OFF) }; +static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, EE_OFF) }; +static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, EE_OFF) }; +static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_14, EE_OFF) }; +static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, EE_OFF) }; + +static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) }; +static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) }; +static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) }; +static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_15, EE_OFF) }; + +static const unsigned int uart_tx_b_pins[] = { PIN(GPIODV_24, EE_OFF) }; +static const unsigned int uart_rx_b_pins[] = { PIN(GPIODV_25, EE_OFF) }; +static const unsigned int uart_cts_b_pins[] = { PIN(GPIODV_26, EE_OFF) }; +static const unsigned int uart_rts_b_pins[] = { PIN(GPIODV_27, EE_OFF) }; + +static const unsigned int uart_tx_c_pins[] = { PIN(GPIOX_8, EE_OFF) }; +static const unsigned int uart_rx_c_pins[] = { PIN(GPIOX_9, EE_OFF) }; +static const unsigned int uart_cts_c_pins[] = { PIN(GPIOX_10, EE_OFF) }; +static const unsigned int uart_rts_c_pins[] = { PIN(GPIOX_11, EE_OFF) }; + +static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, EE_OFF) }; +static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, EE_OFF) }; + +static const unsigned int i2c_sck_b_pins[] = { PIN(GPIODV_27, EE_OFF) }; +static const unsigned int i2c_sda_b_pins[] = { PIN(GPIODV_26, EE_OFF) }; + +static const unsigned int i2c_sck_c_pins[] = { PIN(GPIODV_29, EE_OFF) }; +static const unsigned int i2c_sda_c_pins[] = { PIN(GPIODV_28, EE_OFF) }; + +static const unsigned int i2c_sck_c_dv19_pins[] = { PIN(GPIODV_19, EE_OFF) }; +static const unsigned int i2c_sda_c_dv18_pins[] = { PIN(GPIODV_18, EE_OFF) }; + +static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) }; +static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) }; +static const unsigned int eth_clk_rx_clk_pins[] = { PIN(GPIOZ_2, EE_OFF) }; +static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_3, EE_OFF) }; +static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_4, EE_OFF) }; +static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_5, EE_OFF) }; +static const unsigned int eth_rxd2_pins[] = { PIN(GPIOZ_6, EE_OFF) }; +static const unsigned int eth_rxd3_pins[] = { PIN(GPIOZ_7, EE_OFF) }; +static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) }; +static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_9, EE_OFF) }; +static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_10, EE_OFF) }; +static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) }; +static const unsigned int eth_txd2_pins[] = { PIN(GPIOZ_12, EE_OFF) }; +static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) }; + +static const unsigned int pwm_a_pins[] = { PIN(GPIOX_6, EE_OFF) }; + +static const unsigned int pwm_b_pins[] = { PIN(GPIODV_29, EE_OFF) }; + +static const unsigned int pwm_c_pins[] = { PIN(GPIOZ_15, EE_OFF) }; + +static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, EE_OFF) }; + +static const unsigned int pwm_e_pins[] = { PIN(GPIOX_16, EE_OFF) }; + +static const unsigned int pwm_f_clk_pins[] = { PIN(GPIOCLK_1, EE_OFF) }; +static const unsigned int pwm_f_x_pins[] = { PIN(GPIOX_7, EE_OFF) }; + +static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, EE_OFF) }; +static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, EE_OFF) }; +static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, EE_OFF) }; + +static const unsigned int i2s_am_clk_pins[] = { PIN(GPIOH_6, EE_OFF) }; +static const unsigned int i2s_out_ao_clk_pins[] = { PIN(GPIOH_7, EE_OFF) }; +static const unsigned int i2s_out_lr_clk_pins[] = { PIN(GPIOH_8, EE_OFF) }; +static const unsigned int i2s_out_ch01_pins[] = { PIN(GPIOH_9, EE_OFF) }; +static const unsigned int i2s_out_ch23_z_pins[] = { PIN(GPIOZ_5, EE_OFF) }; +static const unsigned int i2s_out_ch45_z_pins[] = { PIN(GPIOZ_6, EE_OFF) }; +static const unsigned int i2s_out_ch67_z_pins[] = { PIN(GPIOZ_7, EE_OFF) }; + +static const unsigned int spdif_out_h_pins[] = { PIN(GPIOH_4, EE_OFF) }; + +static const unsigned int eth_link_led_pins[] = { PIN(GPIOZ_14, EE_OFF) }; +static const unsigned int eth_act_led_pins[] = { PIN(GPIOZ_15, EE_OFF) }; + +static const unsigned int tsin_a_d0_pins[] = { PIN(GPIODV_0, EE_OFF) }; +static const unsigned int tsin_a_d0_x_pins[] = { PIN(GPIOX_10, EE_OFF) }; +static const unsigned int tsin_a_clk_pins[] = { PIN(GPIODV_8, EE_OFF) }; +static const unsigned int tsin_a_clk_x_pins[] = { PIN(GPIOX_11, EE_OFF) }; +static const unsigned int tsin_a_sop_pins[] = { PIN(GPIODV_9, EE_OFF) }; +static const unsigned int tsin_a_sop_x_pins[] = { PIN(GPIOX_8, EE_OFF) }; +static const unsigned int tsin_a_d_valid_pins[] = { PIN(GPIODV_10, EE_OFF) }; +static const unsigned int tsin_a_d_valid_x_pins[] = { PIN(GPIOX_9, EE_OFF) }; +static const unsigned int tsin_a_fail_pins[] = { PIN(GPIODV_11, EE_OFF) }; +static const unsigned int tsin_a_dp_pins[] = { + PIN(GPIODV_1, EE_OFF), + PIN(GPIODV_2, EE_OFF), + PIN(GPIODV_3, EE_OFF), + PIN(GPIODV_4, EE_OFF), + PIN(GPIODV_5, EE_OFF), + PIN(GPIODV_6, EE_OFF), + PIN(GPIODV_7, EE_OFF), +}; + +static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, 0) }; +static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, 0) }; +static const unsigned int uart_tx_ao_b_0_pins[] = { PIN(GPIOAO_0, 0) }; +static const unsigned int uart_rx_ao_b_1_pins[] = { PIN(GPIOAO_1, 0) }; +static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) }; +static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) }; +static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_4, 0) }; +static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_5, 0) }; +static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) }; +static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) }; + +static const unsigned int i2c_sck_ao_pins[] = {PIN(GPIOAO_4, 0) }; +static const unsigned int i2c_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; +static const unsigned int i2c_slave_sck_ao_pins[] = {PIN(GPIOAO_4, 0) }; +static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; + +static const unsigned int remote_input_ao_pins[] = {PIN(GPIOAO_7, 0) }; + +static const unsigned int pwm_ao_a_3_pins[] = { PIN(GPIOAO_3, 0) }; +static const unsigned int pwm_ao_a_8_pins[] = { PIN(GPIOAO_8, 0) }; + +static const unsigned int pwm_ao_b_pins[] = { PIN(GPIOAO_9, 0) }; +static const unsigned int pwm_ao_b_6_pins[] = { PIN(GPIOAO_6, 0) }; + +static const unsigned int i2s_out_ch23_ao_pins[] = { PIN(GPIOAO_8, 0) }; +static const unsigned int i2s_out_ch45_ao_pins[] = { PIN(GPIOAO_9, 0) }; + +static const unsigned int spdif_out_ao_6_pins[] = { PIN(GPIOAO_6, 0) }; +static const unsigned int spdif_out_ao_9_pins[] = { PIN(GPIOAO_9, 0) }; + +static const unsigned int ao_cec_pins[] = { PIN(GPIOAO_8, 0) }; +static const unsigned int ee_cec_pins[] = { PIN(GPIOAO_8, 0) }; + +static struct meson_pmx_group meson_gxl_periphs_groups[] = { + GPIO_GROUP(GPIOZ_0, EE_OFF), + GPIO_GROUP(GPIOZ_1, EE_OFF), + GPIO_GROUP(GPIOZ_2, EE_OFF), + GPIO_GROUP(GPIOZ_3, EE_OFF), + GPIO_GROUP(GPIOZ_4, EE_OFF), + GPIO_GROUP(GPIOZ_5, EE_OFF), + GPIO_GROUP(GPIOZ_6, EE_OFF), + GPIO_GROUP(GPIOZ_7, EE_OFF), + GPIO_GROUP(GPIOZ_8, EE_OFF), + GPIO_GROUP(GPIOZ_9, EE_OFF), + GPIO_GROUP(GPIOZ_10, EE_OFF), + GPIO_GROUP(GPIOZ_11, EE_OFF), + GPIO_GROUP(GPIOZ_12, EE_OFF), + GPIO_GROUP(GPIOZ_13, EE_OFF), + GPIO_GROUP(GPIOZ_14, EE_OFF), + GPIO_GROUP(GPIOZ_15, EE_OFF), + + GPIO_GROUP(GPIOH_0, EE_OFF), + GPIO_GROUP(GPIOH_1, EE_OFF), + GPIO_GROUP(GPIOH_2, EE_OFF), + GPIO_GROUP(GPIOH_3, EE_OFF), + GPIO_GROUP(GPIOH_4, EE_OFF), + GPIO_GROUP(GPIOH_5, EE_OFF), + GPIO_GROUP(GPIOH_6, EE_OFF), + GPIO_GROUP(GPIOH_7, EE_OFF), + GPIO_GROUP(GPIOH_8, EE_OFF), + GPIO_GROUP(GPIOH_9, EE_OFF), + + GPIO_GROUP(BOOT_0, EE_OFF), + GPIO_GROUP(BOOT_1, EE_OFF), + GPIO_GROUP(BOOT_2, EE_OFF), + GPIO_GROUP(BOOT_3, EE_OFF), + GPIO_GROUP(BOOT_4, EE_OFF), + GPIO_GROUP(BOOT_5, EE_OFF), + GPIO_GROUP(BOOT_6, EE_OFF), + GPIO_GROUP(BOOT_7, EE_OFF), + GPIO_GROUP(BOOT_8, EE_OFF), + GPIO_GROUP(BOOT_9, EE_OFF), + GPIO_GROUP(BOOT_10, EE_OFF), + GPIO_GROUP(BOOT_11, EE_OFF), + GPIO_GROUP(BOOT_12, EE_OFF), + GPIO_GROUP(BOOT_13, EE_OFF), + GPIO_GROUP(BOOT_14, EE_OFF), + GPIO_GROUP(BOOT_15, EE_OFF), + + GPIO_GROUP(CARD_0, EE_OFF), + GPIO_GROUP(CARD_1, EE_OFF), + GPIO_GROUP(CARD_2, EE_OFF), + GPIO_GROUP(CARD_3, EE_OFF), + GPIO_GROUP(CARD_4, EE_OFF), + GPIO_GROUP(CARD_5, EE_OFF), + GPIO_GROUP(CARD_6, EE_OFF), + + GPIO_GROUP(GPIODV_0, EE_OFF), + GPIO_GROUP(GPIODV_1, EE_OFF), + GPIO_GROUP(GPIODV_2, EE_OFF), + GPIO_GROUP(GPIODV_3, EE_OFF), + GPIO_GROUP(GPIODV_4, EE_OFF), + GPIO_GROUP(GPIODV_5, EE_OFF), + GPIO_GROUP(GPIODV_6, EE_OFF), + GPIO_GROUP(GPIODV_7, EE_OFF), + GPIO_GROUP(GPIODV_8, EE_OFF), + GPIO_GROUP(GPIODV_9, EE_OFF), + GPIO_GROUP(GPIODV_10, EE_OFF), + GPIO_GROUP(GPIODV_11, EE_OFF), + GPIO_GROUP(GPIODV_12, EE_OFF), + GPIO_GROUP(GPIODV_13, EE_OFF), + GPIO_GROUP(GPIODV_14, EE_OFF), + GPIO_GROUP(GPIODV_15, EE_OFF), + GPIO_GROUP(GPIODV_16, EE_OFF), + GPIO_GROUP(GPIODV_17, EE_OFF), + GPIO_GROUP(GPIODV_19, EE_OFF), + GPIO_GROUP(GPIODV_20, EE_OFF), + GPIO_GROUP(GPIODV_21, EE_OFF), + GPIO_GROUP(GPIODV_22, EE_OFF), + GPIO_GROUP(GPIODV_23, EE_OFF), + GPIO_GROUP(GPIODV_24, EE_OFF), + GPIO_GROUP(GPIODV_25, EE_OFF), + GPIO_GROUP(GPIODV_26, EE_OFF), + GPIO_GROUP(GPIODV_27, EE_OFF), + GPIO_GROUP(GPIODV_28, EE_OFF), + GPIO_GROUP(GPIODV_29, EE_OFF), + + GPIO_GROUP(GPIOX_0, EE_OFF), + GPIO_GROUP(GPIOX_1, EE_OFF), + GPIO_GROUP(GPIOX_2, EE_OFF), + GPIO_GROUP(GPIOX_3, EE_OFF), + GPIO_GROUP(GPIOX_4, EE_OFF), + GPIO_GROUP(GPIOX_5, EE_OFF), + GPIO_GROUP(GPIOX_6, EE_OFF), + GPIO_GROUP(GPIOX_7, EE_OFF), + GPIO_GROUP(GPIOX_8, EE_OFF), + GPIO_GROUP(GPIOX_9, EE_OFF), + GPIO_GROUP(GPIOX_10, EE_OFF), + GPIO_GROUP(GPIOX_11, EE_OFF), + GPIO_GROUP(GPIOX_12, EE_OFF), + GPIO_GROUP(GPIOX_13, EE_OFF), + GPIO_GROUP(GPIOX_14, EE_OFF), + GPIO_GROUP(GPIOX_15, EE_OFF), + GPIO_GROUP(GPIOX_16, EE_OFF), + GPIO_GROUP(GPIOX_17, EE_OFF), + GPIO_GROUP(GPIOX_18, EE_OFF), + + GPIO_GROUP(GPIOCLK_0, EE_OFF), + GPIO_GROUP(GPIOCLK_1, EE_OFF), + + GPIO_GROUP(GPIO_TEST_N, EE_OFF), + + /* Bank X */ + GROUP(sdio_d0, 5, 31), + GROUP(sdio_d1, 5, 30), + GROUP(sdio_d2, 5, 29), + GROUP(sdio_d3, 5, 28), + GROUP(sdio_clk, 5, 27), + GROUP(sdio_cmd, 5, 26), + GROUP(sdio_irq, 5, 24), + GROUP(uart_tx_a, 5, 19), + GROUP(uart_rx_a, 5, 18), + GROUP(uart_cts_a, 5, 17), + GROUP(uart_rts_a, 5, 16), + GROUP(uart_tx_c, 5, 13), + GROUP(uart_rx_c, 5, 12), + GROUP(uart_cts_c, 5, 11), + GROUP(uart_rts_c, 5, 10), + GROUP(pwm_a, 5, 25), + GROUP(pwm_e, 5, 15), + GROUP(pwm_f_x, 5, 14), + GROUP(spi_mosi, 5, 3), + GROUP(spi_miso, 5, 2), + GROUP(spi_ss0, 5, 1), + GROUP(spi_sclk, 5, 0), + GROUP(tsin_a_sop_x, 6, 3), + GROUP(tsin_a_d_valid_x, 6, 2), + GROUP(tsin_a_d0_x, 6, 1), + GROUP(tsin_a_clk_x, 6, 0), + + /* Bank Z */ + GROUP(eth_mdio, 4, 23), + GROUP(eth_mdc, 4, 22), + GROUP(eth_clk_rx_clk, 4, 21), + GROUP(eth_rx_dv, 4, 20), + GROUP(eth_rxd0, 4, 19), + GROUP(eth_rxd1, 4, 18), + GROUP(eth_rxd2, 4, 17), + GROUP(eth_rxd3, 4, 16), + GROUP(eth_rgmii_tx_clk, 4, 15), + GROUP(eth_tx_en, 4, 14), + GROUP(eth_txd0, 4, 13), + GROUP(eth_txd1, 4, 12), + GROUP(eth_txd2, 4, 11), + GROUP(eth_txd3, 4, 10), + GROUP(pwm_c, 3, 20), + GROUP(i2s_out_ch23_z, 3, 26), + GROUP(i2s_out_ch45_z, 3, 25), + GROUP(i2s_out_ch67_z, 3, 24), + GROUP(eth_link_led, 4, 25), + GROUP(eth_act_led, 4, 24), + + /* Bank H */ + GROUP(hdmi_hpd, 6, 31), + GROUP(hdmi_sda, 6, 30), + GROUP(hdmi_scl, 6, 29), + GROUP(i2s_am_clk, 6, 26), + GROUP(i2s_out_ao_clk, 6, 25), + GROUP(i2s_out_lr_clk, 6, 24), + GROUP(i2s_out_ch01, 6, 23), + GROUP(spdif_out_h, 6, 28), + + /* Bank DV */ + GROUP(uart_tx_b, 2, 16), + GROUP(uart_rx_b, 2, 15), + GROUP(uart_cts_b, 2, 14), + GROUP(uart_rts_b, 2, 13), + GROUP(i2c_sda_c_dv18, 1, 17), + GROUP(i2c_sck_c_dv19, 1, 16), + GROUP(i2c_sda_a, 1, 15), + GROUP(i2c_sck_a, 1, 14), + GROUP(i2c_sda_b, 1, 13), + GROUP(i2c_sck_b, 1, 12), + GROUP(i2c_sda_c, 1, 11), + GROUP(i2c_sck_c, 1, 10), + GROUP(pwm_b, 2, 11), + GROUP(pwm_d, 2, 12), + GROUP(tsin_a_d0, 2, 4), + GROUP(tsin_a_dp, 2, 3), + GROUP(tsin_a_clk, 2, 2), + GROUP(tsin_a_sop, 2, 1), + GROUP(tsin_a_d_valid, 2, 0), + GROUP(tsin_a_fail, 1, 31), + + /* Bank BOOT */ + GROUP(emmc_nand_d07, 7, 31), + GROUP(emmc_clk, 7, 30), + GROUP(emmc_cmd, 7, 29), + GROUP(emmc_ds, 7, 28), + GROUP(nor_d, 7, 13), + GROUP(nor_q, 7, 12), + GROUP(nor_c, 7, 11), + GROUP(nor_cs, 7, 10), + GROUP(nand_ce0, 7, 7), + GROUP(nand_ce1, 7, 6), + GROUP(nand_rb0, 7, 5), + GROUP(nand_ale, 7, 4), + GROUP(nand_cle, 7, 3), + GROUP(nand_wen_clk, 7, 2), + GROUP(nand_ren_wr, 7, 1), + GROUP(nand_dqs, 7, 0), + + /* Bank CARD */ + GROUP(sdcard_d1, 6, 5), + GROUP(sdcard_d0, 6, 4), + GROUP(sdcard_d3, 6, 1), + GROUP(sdcard_d2, 6, 0), + GROUP(sdcard_cmd, 6, 2), + GROUP(sdcard_clk, 6, 3), + + /* Bank CLK */ + GROUP(pwm_f_clk, 8, 30), +}; + +static struct meson_pmx_group meson_gxl_aobus_groups[] = { + GPIO_GROUP(GPIOAO_0, 0), + GPIO_GROUP(GPIOAO_1, 0), + GPIO_GROUP(GPIOAO_2, 0), + GPIO_GROUP(GPIOAO_3, 0), + GPIO_GROUP(GPIOAO_4, 0), + GPIO_GROUP(GPIOAO_5, 0), + GPIO_GROUP(GPIOAO_6, 0), + GPIO_GROUP(GPIOAO_7, 0), + GPIO_GROUP(GPIOAO_8, 0), + GPIO_GROUP(GPIOAO_9, 0), + + /* bank AO */ + GROUP(uart_tx_ao_b_0, 0, 26), + GROUP(uart_rx_ao_b_1, 0, 25), + GROUP(uart_tx_ao_b, 0, 24), + GROUP(uart_rx_ao_b, 0, 23), + GROUP(uart_tx_ao_a, 0, 12), + GROUP(uart_rx_ao_a, 0, 11), + GROUP(uart_cts_ao_a, 0, 10), + GROUP(uart_rts_ao_a, 0, 9), + GROUP(uart_cts_ao_b, 0, 8), + GROUP(uart_rts_ao_b, 0, 7), + GROUP(i2c_sck_ao, 0, 6), + GROUP(i2c_sda_ao, 0, 5), + GROUP(i2c_slave_sck_ao, 0, 2), + GROUP(i2c_slave_sda_ao, 0, 1), + GROUP(remote_input_ao, 0, 0), + GROUP(pwm_ao_a_3, 0, 22), + GROUP(pwm_ao_b_6, 0, 18), + GROUP(pwm_ao_a_8, 0, 17), + GROUP(pwm_ao_b, 0, 3), + GROUP(i2s_out_ch23_ao, 1, 0), + GROUP(i2s_out_ch45_ao, 1, 1), + GROUP(spdif_out_ao_6, 0, 16), + GROUP(spdif_out_ao_9, 0, 4), + GROUP(ao_cec, 0, 15), + GROUP(ee_cec, 0, 14), +}; + +static const char * const gpio_periphs_groups[] = { + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", + "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14", + "GPIOZ_15", + + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", + "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", + + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", + "BOOT_15", + + "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4", + "CARD_5", "CARD_6", + + "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4", + "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9", + "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14", + "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19", + "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24", + "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29", + + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", + + "GPIO_TEST_N", +}; + +static const char * const emmc_groups[] = { + "emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds", +}; + +static const char * const nor_groups[] = { + "nor_d", "nor_q", "nor_c", "nor_cs", +}; + +static const char * const spi_groups[] = { + "spi_mosi", "spi_miso", "spi_ss0", "spi_sclk", +}; + +static const char * const sdcard_groups[] = { + "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", + "sdcard_cmd", "sdcard_clk", +}; + +static const char * const sdio_groups[] = { + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", + "sdio_cmd", "sdio_clk", "sdio_irq", +}; + +static const char * const nand_groups[] = { + "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle", + "nand_wen_clk", "nand_ren_wr", "nand_dqs", +}; + +static const char * const uart_a_groups[] = { + "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a", +}; + +static const char * const uart_b_groups[] = { + "uart_tx_b", "uart_rx_b", "uart_cts_b", "uart_rts_b", +}; + +static const char * const uart_c_groups[] = { + "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c", +}; + +static const char * const i2c_a_groups[] = { + "i2c_sck_a", "i2c_sda_a", +}; + +static const char * const i2c_b_groups[] = { + "i2c_sck_b", "i2c_sda_b", +}; + +static const char * const i2c_c_groups[] = { + "i2c_sck_c", "i2c_sda_c", "i2c_sda_c_dv18", "i2c_sck_c_dv19", +}; + +static const char * const eth_groups[] = { + "eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv", + "eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3", + "eth_rgmii_tx_clk", "eth_tx_en", + "eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3", +}; + +static const char * const pwm_a_groups[] = { + "pwm_a", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b", +}; + +static const char * const pwm_c_groups[] = { + "pwm_c", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d", +}; + +static const char * const pwm_e_groups[] = { + "pwm_e", +}; + +static const char * const pwm_f_groups[] = { + "pwm_f_clk", "pwm_f_x", +}; + +static const char * const hdmi_hpd_groups[] = { + "hdmi_hpd", +}; + +static const char * const hdmi_i2c_groups[] = { + "hdmi_sda", "hdmi_scl", +}; + +static const char * const i2s_out_groups[] = { + "i2s_am_clk", "i2s_out_ao_clk", "i2s_out_lr_clk", + "i2s_out_ch01", "i2s_out_ch23_z", "i2s_out_ch45_z", "i2s_out_ch67_z", +}; + +static const char * const spdif_out_groups[] = { + "spdif_out_h", +}; + +static const char * const eth_led_groups[] = { + "eth_link_led", "eth_act_led", +}; + +static const char * const tsin_a_groups[] = { + "tsin_a_clk", "tsin_a_clk_x", "tsin_a_sop", "tsin_a_sop_x", + "tsin_a_d_valid", "tsin_a_d_valid_x", "tsin_a_d0", "tsin_a_d0_x", + "tsin_a_dp", "tsin_a_fail", +}; + +static const char * const gpio_aobus_groups[] = { + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", + "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", +}; + +static const char * const uart_ao_groups[] = { + "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a", +}; + +static const char * const uart_ao_b_groups[] = { + "uart_tx_ao_b", "uart_rx_ao_b", "uart_cts_ao_b", "uart_rts_ao_b", + "uart_tx_ao_b_0", "uart_rx_ao_b_1", +}; + +static const char * const i2c_ao_groups[] = { + "i2c_sck_ao", "i2c_sda_ao", +}; + +static const char * const i2c_slave_ao_groups[] = { + "i2c_slave_sck_ao", "i2c_slave_sda_ao", +}; + +static const char * const remote_input_ao_groups[] = { + "remote_input_ao", +}; + +static const char * const pwm_ao_a_groups[] = { + "pwm_ao_a_3", "pwm_ao_a_8", +}; + +static const char * const pwm_ao_b_groups[] = { + "pwm_ao_b", "pwm_ao_b_6", +}; + +static const char * const i2s_out_ao_groups[] = { + "i2s_out_ch23_ao", "i2s_out_ch45_ao", +}; + +static const char * const spdif_out_ao_groups[] = { + "spdif_out_ao_6", "spdif_out_ao_9", +}; + +static const char * const cec_ao_groups[] = { + "ao_cec", "ee_cec", +}; + +static struct meson_pmx_func meson_gxl_periphs_functions[] = { + FUNCTION(gpio_periphs), + FUNCTION(emmc), + FUNCTION(nor), + FUNCTION(spi), + FUNCTION(sdcard), + FUNCTION(sdio), + FUNCTION(nand), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(uart_c), + FUNCTION(i2c_a), + FUNCTION(i2c_b), + FUNCTION(i2c_c), + FUNCTION(eth), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_f), + FUNCTION(hdmi_hpd), + FUNCTION(hdmi_i2c), + FUNCTION(i2s_out), + FUNCTION(spdif_out), + FUNCTION(eth_led), + FUNCTION(tsin_a), +}; + +static struct meson_pmx_func meson_gxl_aobus_functions[] = { + FUNCTION(gpio_aobus), + FUNCTION(uart_ao), + FUNCTION(uart_ao_b), + FUNCTION(i2c_ao), + FUNCTION(i2c_slave_ao), + FUNCTION(remote_input_ao), + FUNCTION(pwm_ao_a), + FUNCTION(pwm_ao_b), + FUNCTION(i2s_out_ao), + FUNCTION(spdif_out_ao), + FUNCTION(cec_ao), +}; + +static struct meson_bank meson_gxl_periphs_banks[] = { + /* name first last pullen pull dir out in */ + BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_18, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), + BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), + BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_9, EE_OFF), 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), + BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), + BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), + BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), + BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_1, EE_OFF), 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), +}; + +static struct meson_bank meson_gxl_aobus_banks[] = { + /* name first last pullen pull dir out in */ + BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_9, 0), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), +}; + +struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = { + .name = "periphs-banks", + .pin_base = 10, + .groups = meson_gxl_periphs_groups, + .funcs = meson_gxl_periphs_functions, + .banks = meson_gxl_periphs_banks, + .num_pins = 101, + .num_groups = ARRAY_SIZE(meson_gxl_periphs_groups), + .num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions), + .num_banks = ARRAY_SIZE(meson_gxl_periphs_banks), +}; + +struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { + .name = "aobus-banks", + .pin_base = 0, + .groups = meson_gxl_aobus_groups, + .funcs = meson_gxl_aobus_functions, + .banks = meson_gxl_aobus_banks, + .num_pins = 10, + .num_groups = ARRAY_SIZE(meson_gxl_aobus_groups), + .num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions), + .num_banks = ARRAY_SIZE(meson_gxl_aobus_banks), +}; + +static const struct udevice_id meson_gxl_pinctrl_match[] = { + { + .compatible = "amlogic,meson-gxl-periphs-pinctrl", + .data = (ulong)&meson_gxl_periphs_pinctrl_data, + }, + { + .compatible = "amlogic,meson-gxl-aobus-pinctrl", + .data = (ulong)&meson_gxl_aobus_pinctrl_data, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(meson_gxl_pinctrl) = { + .name = "meson-gxl-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(meson_gxl_pinctrl_match), + .probe = meson_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct meson_pinctrl), + .ops = &meson_pinctrl_ops, +};

This adds platform code for the Amlogic P212 reference board based on a Meson GXL (S905X) SoC with the Meson GXL configuration.

This initial submission only supports UART and MMC/SDCard, support for the internal Ethernet PHY in Work In Progress.

Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- arch/arm/mach-meson/Kconfig | 22 ++++++++++ board/amlogic/p212/Kconfig | 12 ++++++ board/amlogic/p212/MAINTAINERS | 6 +++ board/amlogic/p212/Makefile | 8 ++++ board/amlogic/p212/README | 96 ++++++++++++++++++++++++++++++++++++++++++ board/amlogic/p212/p212.c | 21 +++++++++ configs/p212_defconfig | 31 ++++++++++++++ include/configs/p212.h | 22 ++++++++++ 8 files changed, 218 insertions(+) create mode 100644 board/amlogic/p212/Kconfig create mode 100644 board/amlogic/p212/MAINTAINERS create mode 100644 board/amlogic/p212/Makefile create mode 100644 board/amlogic/p212/README create mode 100644 board/amlogic/p212/p212.c create mode 100644 configs/p212_defconfig create mode 100644 include/configs/p212.h

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index af3be59..d4bd230 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -9,6 +9,15 @@ config MESON_GXBB The Amlogic Meson GXBaby (S905) is an ARM SoC with a quad-core Cortex-A53 CPU and a Mali-450 GPU.

+config MESON_GXL + bool "Support Meson GXL" + select ARM64 + select DM + select DM_SERIAL + help + The Amlogic Meson GXL (S905X and S905X) is an ARM SoC with a + quad-core Cortex-A53 CPU and a Mali-450 GPU. + if MESON_GXBB

config TARGET_ODROID_C2 @@ -20,6 +29,17 @@ config TARGET_ODROID_C2

endif

+if MESON_GXL + +config TARGET_P212 + bool "P212" + help + P212 is a reference dessign board based on Meson GXL S905X SoC + with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot, + eMMC, IR receiver, CVBS+Audio jack and a SDIO WiFi module. + +endif + config SYS_SOC default "meson"

@@ -28,4 +48,6 @@ config SYS_MALLOC_F_LEN

source "board/amlogic/odroid-c2/Kconfig"

+source "board/amlogic/p212/Kconfig" + endif diff --git a/board/amlogic/p212/Kconfig b/board/amlogic/p212/Kconfig new file mode 100644 index 0000000..720c92b --- /dev/null +++ b/board/amlogic/p212/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P212 + +config SYS_BOARD + default "p212" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "p212" + +endif diff --git a/board/amlogic/p212/MAINTAINERS b/board/amlogic/p212/MAINTAINERS new file mode 100644 index 0000000..6575f17 --- /dev/null +++ b/board/amlogic/p212/MAINTAINERS @@ -0,0 +1,6 @@ +P212 +M: Neil Armstrong narmstrong@baylibre.com +S: Maintained +F: board/amlogic/p212/ +F: include/configs/p212.h +F: configs/p212_defconfig diff --git a/board/amlogic/p212/Makefile b/board/amlogic/p212/Makefile new file mode 100644 index 0000000..960a661 --- /dev/null +++ b/board/amlogic/p212/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2016 BayLibre, SAS +# Author: Neil Armstrong narmstrong@baylibre.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := p212.o diff --git a/board/amlogic/p212/README b/board/amlogic/p212/README new file mode 100644 index 0000000..979502d --- /dev/null +++ b/board/amlogic/p212/README @@ -0,0 +1,96 @@ +U-Boot for Amlogic P212 +======================= + +P212 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - 10/100 Ethernet + - HDMI 2.0 4K/60Hz display + - 2 x USB 2.0 Host + - eMMC, microSD + - Infrared receiver + - SDIO WiFi Module + - CVBS+Stereo Audio Jack + +Schematics are available from Amlogic on demand. + +Currently the u-boot port supports the following devices: + - serial + - eMMC, microSD + +u-boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make p212_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-... + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-... + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot + > cd amlogic-u-boot + > make gxl_p212_v1_defconfig + > make + > export FIPDIR=$PWD/fip + +Go back to mainline U-boot source tree then : + > mkdir fip + + > cp $FIPDIR/gxl/bl2.bin fip/ + > cp $FIPDIR/gxl/acs.bin fip/ + > cp $FIPDIR/gxl/bl21.bin fip/ + > cp $FIPDIR/gxl/bl30.bin fip/ + > cp $FIPDIR/gxl/bl301.bin fip/ + > cp $FIPDIR/gxl/bl31.img fip/ + > cp u-boot.bin fip/bl33.bin + + > $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + > $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c new file mode 100644 index 0000000..1eeb7f2 --- /dev/null +++ b/board/amlogic/p212/p212.c @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong narmstrong@baylibre.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/gxbb.h> + +int board_init(void) +{ + return 0; +} + +int misc_init_r(void) +{ + return 0; +} diff --git a/configs/p212_defconfig b/configs/p212_defconfig new file mode 100644 index 0000000..3c57621 --- /dev/null +++ b/configs/p212_defconfig @@ -0,0 +1,31 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_MESON_GXL=y +CONFIG_TARGET_P212=y +CONFIG_IDENT_STRING=" p212" +CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-p212" +CONFIG_DEBUG_UART=y +CONFIG_ENV_IS_NOWHERE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_MESON_GX=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_GXL=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_BASE=0xc81004c0 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/include/configs/p212.h b/include/configs/p212.h new file mode 100644 index 0000000..0477384 --- /dev/null +++ b/include/configs/p212.h @@ -0,0 +1,22 @@ +/* + * Configuration for Amlogic P212 + * + * Copyright (C) 2017 Baylibre, SAS + * Author: Neil Armstrong narmstrong@baylibre.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MISC_INIT_R + +/* Serial setup */ +#define CONFIG_CONS_INDEX 0 + +#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-p212.dtb\0" + +#include <configs/meson-gxbb-common.h> + +#endif /* __CONFIG_H */