[U-Boot] [PATCH 0/6] ARM: Introduce function to switch to hypervisor mode and enable LPAE
On SoCs like DRA7, OMAP5 one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader.
Patch 1-4 enable LPAE.
Patch 5: Introduces a weak function which can be overridden specific to SoCs to switch to hypervisor mode.
Patch 6: overrides weak function in patch 1 switch cpu to hypervisor mode using the available ROM code hook early in the boot phase before the boot loader checks for hypervisor mode on OMAP5 based SoCs.
Tested on AM57XX-EVM, DRA7XX-EVM.
Keerthy (6): omap: Remove hardcoding of mmu section shift to 20 omap: Set appropriate cache configuration for LPAE and non-LAPE cases configs: am57xx_evm_defconfig: Enable LPAE mode configs: dra7xx_evm_defconfig: Enable LPAE mode ARM: Introduce function to switch to hypervisor mode ARM: OMAP5+: Override switch_to_hypervisor function
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 24 +++++++++++++++++++++ arch/arm/cpu/armv7/omap-common/omap-cache.c | 29 ++++++++++++++++++++++---- arch/arm/cpu/armv7/start.S | 21 +++++++++++++++++++ arch/arm/include/asm/system.h | 4 ++++ configs/am57xx_evm_defconfig | 1 + configs/dra7xx_evm_defconfig | 1 + 6 files changed, 76 insertions(+), 4 deletions(-)
As of now the mmu section shift is hardcoded to 20 but with LPAE coming into picture this can be different. Hence replacing 20 with MMU_SECTION_SHIFT macro.
Signed-off-by: Keerthy j-keerthy@ti.com --- arch/arm/cpu/armv7/omap-common/omap-cache.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c index 579bebf..ee89f1f 100644 --- a/arch/arm/cpu/armv7/omap-common/omap-cache.c +++ b/arch/arm/cpu/armv7/omap-common/omap-cache.c @@ -32,8 +32,8 @@ void dram_bank_mmu_setup(int bank) bd_t *bd = gd->bd; int i;
- u32 start = bd->bi_dram[bank].start >> 20; - u32 size = bd->bi_dram[bank].size >> 20; + u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; + u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; u32 end = start + size;
debug("%s: bank: %d\n", __func__, bank);
On Wed, Sep 14, 2016 at 10:43:28AM +0530, Keerthy wrote:
As of now the mmu section shift is hardcoded to 20 but with LPAE coming into picture this can be different. Hence replacing 20 with MMU_SECTION_SHIFT macro.
Signed-off-by: Keerthy j-keerthy@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, Sep 14, 2016 at 10:43:28AM +0530, Keerthy wrote:
As of now the mmu section shift is hardcoded to 20 but with LPAE coming into picture this can be different. Hence replacing 20 with MMU_SECTION_SHIFT macro.
Signed-off-by: Keerthy j-keerthy@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Cache configuration methods is different for LPAE and non-LPAE cases. Hence the bits and the interpretaion is different for two cases. In case of non-LPAE mode short descriptor format is used and we need to set Cache and Buffer bits.
In the case of LPAE the cache configuration happens via MAIR0 lookup.
Signed-off-by: Keerthy j-keerthy@ti.com --- arch/arm/cpu/armv7/omap-common/omap-cache.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c index ee89f1f..b37163a 100644 --- a/arch/arm/cpu/armv7/omap-common/omap-cache.c +++ b/arch/arm/cpu/armv7/omap-common/omap-cache.c @@ -17,7 +17,28 @@
DECLARE_GLOBAL_DATA_PTR;
-#define ARMV7_DCACHE_WRITEBACK 0xe +/* + * Without LPAE short descriptors are used + * Set C - Cache Bit3 + * Set B - Buffer Bit2 + * The last 2 bits set to 0b10 + * Do Not set XN bit4 + * So value is 0xe + * + * With LPAE cache configuration happens via MAIR0 register + * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF. + * 0xFF maps to Cache writeback with Read and Write Allocate set + * The bits[1:0] should have the value 0b01 for the first level + * descriptor. + * So the value is 0xd + */ + +#ifdef CONFIG_ARMV7_LPAE +#define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC +#else +#define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK +#endif + #define ARMV7_DOMAIN_CLIENT 1 #define ARMV7_DOMAIN_MASK (0x3 << 0)
@@ -38,7 +59,7 @@ void dram_bank_mmu_setup(int bank)
debug("%s: bank: %d\n", __func__, bank); for (i = start; i < end; i++) - set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); + set_section_dcache(i, ARMV7_DCACHE_POLICY); }
void arm_init_domains(void)
On Wed, Sep 14, 2016 at 10:43:29AM +0530, Keerthy wrote:
Cache configuration methods is different for LPAE and non-LPAE cases. Hence the bits and the interpretaion is different for two cases. In case of non-LPAE mode short descriptor format is used and we need to set Cache and Buffer bits.
In the case of LPAE the cache configuration happens via MAIR0 lookup.
Signed-off-by: Keerthy j-keerthy@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, Sep 14, 2016 at 10:43:29AM +0530, Keerthy wrote:
Cache configuration methods is different for LPAE and non-LPAE cases. Hence the bits and the interpretaion is different for two cases. In case of non-LPAE mode short descriptor format is used and we need to set Cache and Buffer bits.
In the case of LPAE the cache configuration happens via MAIR0 lookup.
Signed-off-by: Keerthy j-keerthy@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Enable Linear Physical Address Extension mode which is a prerequisite for hypervisor mode.
Signed-off-by: Keerthy j-keerthy@ti.com --- configs/am57xx_evm_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index d49129d..7021c11 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_OMAP54XX=y CONFIG_TARGET_AM57XX_EVM=y +CONFIG_ARMV7_LPAE=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15" CONFIG_SPL=y
On Wed, Sep 14, 2016 at 10:43:30AM +0530, Keerthy wrote:
Enable Linear Physical Address Extension mode which is a prerequisite for hypervisor mode.
Signed-off-by: Keerthy j-keerthy@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, Sep 14, 2016 at 10:43:30AM +0530, Keerthy wrote:
Enable Linear Physical Address Extension mode which is a prerequisite for hypervisor mode.
Signed-off-by: Keerthy j-keerthy@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Enable Linear Physical Address Extension mode which is a prerequisite for hypervisor mode.
Signed-off-by: Keerthy j-keerthy@ti.com --- configs/dra7xx_evm_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 64184de..2b368c3 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_OMAP54XX=y CONFIG_TARGET_DRA7XX_EVM=y +CONFIG_ARMV7_LPAE=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" CONFIG_SPL=y
On Wed, Sep 14, 2016 at 10:43:31AM +0530, Keerthy wrote:
Enable Linear Physical Address Extension mode which is a prerequisite for hypervisor mode.
Signed-off-by: Keerthy j-keerthy@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, Sep 14, 2016 at 10:43:31AM +0530, Keerthy wrote:
Enable Linear Physical Address Extension mode which is a prerequisite for hypervisor mode.
Signed-off-by: Keerthy j-keerthy@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way.
Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy j-keerthy@ti.com --- arch/arm/cpu/armv7/start.S | 21 +++++++++++++++++++++ arch/arm/include/asm/system.h | 4 ++++ 2 files changed, 25 insertions(+)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 691e5d3..7eee54b 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -17,6 +17,7 @@ #include <config.h> #include <asm/system.h> #include <linux/linkage.h> +#include <asm/armv7.h>
/************************************************************************* * @@ -30,11 +31,24 @@
.globl reset .globl save_boot_params_ret +#ifdef CONFIG_ARMV7_LPAE + .global switch_to_hypervisor_ret +#endif
reset: /* Allow the board to save important registers */ b save_boot_params save_boot_params_ret: +#ifdef CONFIG_ARMV7_LPAE +/* + * check for Hypervisor support + */ + mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 + and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits + cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) + beq switch_to_hypervisor +switch_to_hypervisor_ret: +#endif /* * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, * except if in HYP mode already @@ -103,6 +117,13 @@ ENTRY(save_boot_params) ENDPROC(save_boot_params) .weak save_boot_params
+#ifdef CONFIG_ARMV7_LPAE +ENTRY(switch_to_hypervisor) + b switch_to_hypervisor_ret +ENDPROC(switch_to_hypervisor) + .weak switch_to_hypervisor +#endif + /************************************************************************* * * cpu_init_cp15 diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 7b7b867..c18e1e3 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -223,6 +223,10 @@ void __noreturn psci_system_reset(bool smc); */ void save_boot_params_ret(void);
+#ifdef CONFIG_ARMV7_LPAE +void switch_to_hypervisor_ret(void); +#endif + #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
#ifdef __ARM_ARCH_7A__
On Wed, Sep 14, 2016 at 10:43:32AM +0530, Keerthy wrote:
On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way.
Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy j-keerthy@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, Sep 14, 2016 at 10:43:32AM +0530, Keerthy wrote:
On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way.
Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy j-keerthy@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Override the switch_to_hypervisor function to switch cpu to hypervisor mode using the available ROM code hook early in the boot phase before the boot loader checks for HYP mode.
Based on the work done by Jonathan Bergsagel jbergsagel@ti.com.
Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy j-keerthy@ti.com --- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 66a3b3d..8ce12c8 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -24,6 +24,30 @@ ENTRY(save_boot_params) str r0, [r1] b save_boot_params_ret ENDPROC(save_boot_params) + +#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE) +ENTRY(switch_to_hypervisor) + +/* + * Switch to hypervisor mode + */ + adr r0, save_sp + str sp, [r0] + adr r1, restore_from_hyp + ldr r0, =0x102 + b omap_smc1 +restore_from_hyp: + adr r0, save_sp + ldr sp, [r0] + MRC p15, 4, R0, c1, c0, 0 + ldr r1, =0X1004 @Set cache enable bits for hypervisor mode + orr r0, r0, r1 + MCR p15, 4, R0, c1, c0, 0 + b switch_to_hypervisor_ret +save_sp: + .word 0x0 +ENDPROC(switch_to_hypervisor) +#endif #endif
ENTRY(omap_smc1)
On Wed, Sep 14, 2016 at 10:43:33AM +0530, Keerthy wrote:
Override the switch_to_hypervisor function to switch cpu to hypervisor mode using the available ROM code hook early in the boot phase before the boot loader checks for HYP mode.
Based on the work done by Jonathan Bergsagel jbergsagel@ti.com.
Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy j-keerthy@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, Sep 14, 2016 at 10:43:33AM +0530, Keerthy wrote:
Override the switch_to_hypervisor function to switch cpu to hypervisor mode using the available ROM code hook early in the boot phase before the boot loader checks for HYP mode.
Based on the work done by Jonathan Bergsagel jbergsagel@ti.com.
Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy j-keerthy@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
On Wednesday 14 September 2016 10:43 AM, Keerthy wrote:
On SoCs like DRA7, OMAP5 one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader.
Patch 1-4 enable LPAE.
Patch 5: Introduces a weak function which can be overridden specific to SoCs to switch to hypervisor mode.
Patch 6: overrides weak function in patch 1 switch cpu to hypervisor mode using the available ROM code hook early in the boot phase before the boot loader checks for hypervisor mode on OMAP5 based SoCs.
Tested on AM57XX-EVM, DRA7XX-EVM.
Tom,
Can you pull this series please.
Regards, Keerthy
Keerthy (6): omap: Remove hardcoding of mmu section shift to 20 omap: Set appropriate cache configuration for LPAE and non-LAPE cases configs: am57xx_evm_defconfig: Enable LPAE mode configs: dra7xx_evm_defconfig: Enable LPAE mode ARM: Introduce function to switch to hypervisor mode ARM: OMAP5+: Override switch_to_hypervisor function
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 24 +++++++++++++++++++++ arch/arm/cpu/armv7/omap-common/omap-cache.c | 29 ++++++++++++++++++++++---- arch/arm/cpu/armv7/start.S | 21 +++++++++++++++++++ arch/arm/include/asm/system.h | 4 ++++ configs/am57xx_evm_defconfig | 1 + configs/dra7xx_evm_defconfig | 1 + 6 files changed, 76 insertions(+), 4 deletions(-)
participants (3)
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Keerthy -
Tom Rini