On 01/12/2016 05:59 PM, Daniel Schwierzeck wrote:

2016-01-12 11:18 GMT+01:00 Purna Chandra Mandal purna.mandal@microchip.com:

...

Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com

Changes in v3: None Changes in v2: None

arch/mips/cpu/start.S | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index e95cdca..35d9650 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -185,6 +185,8 @@ reset: PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset sw sp, 0(t0) #endif

•   /* Initialize args to zero */
  

•   move    a0, zero
  

the comment should be on the same line and more precise. That is useful in disassemblies or when debugging. E.g.

move a0, zero # a0 <-- boot_flags = 0

Also add a commit message please explaining why the change is required. Something like that the boot_flags of board_init_f should be set to 0 because $a0 may be utilized in lowlevel_init or mips_cache_reset.

ack. Will add accordingly,

...

    PTR_LA  t9, board_init_f
    jr      t9

-- 1.8.3.1

Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:

PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers and dividers capable of supplying clock to various controllers on or off-chip.

Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com Reviewed-by: Simon Glass sjg@chromium.org

Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com

nits below

---

Changes in v3:

• rename clk-pic32.c to clk_pic32.c
• update clock binding documentation
• replace pic32_ioremap() with ioremap()
• separate MPLL initialization constants

Changes in v2:

• add mpll get clock rate

.../clock/microchip,pic32-clock.txt | 33 ++ drivers/clk/Makefile | 1 + drivers/clk/clk_pic32.c | 433 +++++++++++++++++++++ include/dt-bindings/clock/microchip,clock.h | 29 ++ 4 files changed, 496 insertions(+) create mode 100644 doc/device-tree-bindings/clock/microchip,pic32 -clock.txt create mode 100644 drivers/clk/clk_pic32.c create mode 100644 include/dt-bindings/clock/microchip,clock.h

diff --git a/doc/device-tree-bindings/clock/microchip,pic32-clock.txt b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt new file mode 100644 index 0000000..02e5ce4 --- /dev/null +++ b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt @@ -0,0 +1,33 @@ +* Microchip PIC32 Clock and Oscillator

+Microchip PIC32 clock tree consists of few oscillators, PLLs, +multiplexers and few divider modules capable of supplying clocks +to various controllers within SoC and also to off-chip.

+PIC32 clock controller output is defined by indices as defined +in [0]

+[0] include/dt-bindings/clock/microchip,clock.h

+Required Properties: +- compatible: should be "microchip,pic32mzda_clk" +- reg: physical base address of the controller and length of memory mapped

•   region.
  

+- #clock-cells: should be 1.

+Example: Clock controller node:

• clock: clk@1f801200 {

• compatible = "microchip,pic32mzda_clk";
  

• reg = <0x1f801200 0x1000>;
  

• };

+Example: UART controller node that consumes the clock generated by the clock +controller:

• uart1: serial@1f822000 {

• compatible = "microchip,pic32mzda-uart";
  

• reg = <0xbf822000 0x50>;
  

• interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
  

• clocks = <&clock PB2CLK>;
  

• };

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 4a6a4a8..adda769 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o +obj-$(CONFIG_MACH_PIC32) += clk_pic32.o diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c new file mode 100644 index 0000000..bb0a1cf --- /dev/null +++ b/drivers/clk/clk_pic32.c @@ -0,0 +1,433 @@ +/*

• • Copyright (C) 2015 Purna Chandra Mandal <

purna.mandal@microchip.com>

• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <div64.h> +#include <wait_bit.h> +#include <dm/lists.h> +#include <asm/io.h> +#include <mach/pic32.h> +#include <dt-bindings/clock/microchip,clock.h>

+DECLARE_GLOBAL_DATA_PTR;

+/* Primary oscillator */ +#define SYS_POSC_CLK_HZ 24000000

+/* FRC clk rate */ +#define SYS_FRC_CLK_HZ 8000000

+/* Clock Registers */ +#define OSCCON 0x0000 +#define OSCTUNE 0x0010 +#define SPLLCON 0x0020 +#define REFO1CON 0x0080 +#define REFO1TRIM 0x0090 +#define PB1DIV 0x0140

+/* SPLL */ +#define ICLK_MASK 0x00000080 +#define PLLIDIV_MASK 0x00000007 +#define PLLODIV_MASK 0x00000007 +#define CUROSC_MASK 0x00000007 +#define PLLMUL_MASK 0x0000007F +#define FRCDIV_MASK 0x00000007

+/* PBCLK */ +#define PBDIV_MASK 0x00000007

+/* SYSCLK MUX */ +#define SCLK_SRC_FRC1 0 +#define SCLK_SRC_SPLL 1 +#define SCLK_SRC_POSC 2 +#define SCLK_SRC_FRC2 7

+/* Reference Oscillator Control Reg fields */ +#define REFO_SEL_MASK 0x0f +#define REFO_SEL_SHIFT 0 +#define REFO_ACTIVE BIT(8) +#define REFO_DIVSW_EN BIT(9) +#define REFO_OE BIT(12) +#define REFO_ON BIT(15) +#define REFO_DIV_SHIFT 16 +#define REFO_DIV_MASK 0x7fff

+/* Reference Oscillator Trim Register Fields */ +#define REFO_TRIM_REG 0x10 +#define REFO_TRIM_MASK 0x1ff +#define REFO_TRIM_SHIFT 23 +#define REFO_TRIM_MAX 511

+#define ROCLK_SRC_SCLK 0x0 +#define ROCLK_SRC_SPLL 0x7 +#define ROCLK_SRC_ROCLKI 0x8

+/* Memory PLL */ +#define MPLL_IDIV 0x3f +#define MPLL_MULT 0xff +#define MPLL_ODIV1 0x7 +#define MPLL_ODIV2 0x7 +#define MPLL_VREG_RDY BIT(23) +#define MPLL_RDY BIT(31) +#define MPLL_IDIV_SHIFT 0 +#define MPLL_MULT_SHIFT 8 +#define MPLL_ODIV1_SHIFT 24 +#define MPLL_ODIV2_SHIFT 27 +#define MPLL_IDIV_INIT 0x03 +#define MPLL_MULT_INIT 0x32 +#define MPLL_ODIV1_INIT 0x02 +#define MPLL_ODIV2_INIT 0x01

+struct pic32_clk_priv {

• void __iomem *iobase;
• void __iomem *syscfg_base;

+};

+static ulong pic32_get_pll_rate(struct pic32_clk_priv *priv) +{

• u32 iclk, idiv, odiv, mult;
• ulong plliclk, v;
• v = readl(priv->iobase + SPLLCON);
• iclk = (v & ICLK_MASK);
• idiv = ((v >> 8) & PLLIDIV_MASK) + 1;
• odiv = ((v >> 24) & PLLODIV_MASK);
• mult = ((v >> 16) & PLLMUL_MASK) + 1;
• plliclk = iclk ? SYS_FRC_CLK_HZ : SYS_POSC_CLK_HZ;
• if (odiv < 2)

• odiv = 2;
  

• else if (odiv < 5)

• odiv = (1 << odiv);
  

• else

• odiv = 32;
  

• return ((plliclk / idiv) * mult) / odiv;

+}

+static ulong pic32_get_sysclk(struct pic32_clk_priv *priv) +{

• ulong v;
• ulong hz;
• ulong div, frcdiv;
• ulong curr_osc;
• /* get clk source */
• v = readl(priv->iobase + OSCCON);
• curr_osc = (v >> 12) & CUROSC_MASK;
• switch (curr_osc) {
• case SCLK_SRC_FRC1:
• case SCLK_SRC_FRC2:

• frcdiv = ((v >> 24) & FRCDIV_MASK);
  

• div = ((1 << frcdiv) + 1) + (128 * (frcdiv == 7));
  

• hz = SYS_FRC_CLK_HZ / div;
  

• break;
  

• case SCLK_SRC_SPLL:

• hz = pic32_get_pll_rate(priv);
  

• break;
  

• case SCLK_SRC_POSC:

• hz = SYS_POSC_CLK_HZ;
  

• break;
  

• default:

• hz = 0;
  

• printf("clk: unknown sclk_src.\n");
  

• break;
  

• }
• return hz;

+}

+static ulong pic32_get_pbclk(struct pic32_clk_priv *priv, int periph) +{

• void __iomem *reg;
• ulong div, clk_freq;
• WARN_ON((periph < PB1CLK) || (periph > PB7CLK));
• clk_freq = pic32_get_sysclk(priv);
• reg = priv->iobase + PB1DIV + (periph - PB1CLK) * 0x10;
• div = (readl(reg) & PBDIV_MASK) + 1;
• return clk_freq / div;

+}

+static ulong pic32_get_cpuclk(struct pic32_clk_priv *priv) +{

• return pic32_get_pbclk(priv, PB7CLK);

+}

+static ulong pic32_set_refclk(struct pic32_clk_priv *priv, int periph,

• 	      int parent_rate, int rate, int
  

parent_id) +{

• void __iomem *reg;
• u32 div, trim, v;
• u64 frac;
• WARN_ON((periph < REF1CLK) || (periph > REF5CLK));
• /* calculate dividers,

• *   rate = parent_rate / [2 * (div + (trim / 512))]
  

• */
  

• if (parent_rate <= rate) {

• div = 0;
  

• trim = 0;
  

• } else {

• div = parent_rate / (rate << 1);
  

• frac = parent_rate;
  

• frac <<= 8;
  

• do_div(frac, rate);
  

• frac -= (u64)(div << 9);
  

• trim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX :
  

(u32)frac;

• }
• reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20;
• /* disable clk */
• writel(REFO_ON | REFO_OE, reg + _CLR_OFFSET);
• /* wait till previous src change is active */
• wait_for_bit(__func__, reg, REFO_DIVSW_EN | REFO_ACTIVE,

•      false, CONFIG_SYS_HZ, false);
  

• /* parent_id */
• v = readl(reg);
• v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT);
• v |= (parent_id << REFO_SEL_SHIFT);
• /* apply rodiv */
• v &= ~(REFO_DIV_MASK << REFO_DIV_SHIFT);
• v |= (div << REFO_DIV_SHIFT);
• writel(v, reg);
• /* apply trim */
• v = readl(reg + REFO_TRIM_REG);
• v &= ~(REFO_TRIM_MASK << REFO_TRIM_SHIFT);
• v |= (trim << REFO_TRIM_SHIFT);
• writel(v, reg + REFO_TRIM_REG);
• /* enable clk */
• writel(REFO_ON | REFO_OE, reg + _SET_OFFSET);
• /* switch divider */
• writel(REFO_DIVSW_EN, reg + _SET_OFFSET);
• /* wait for divider switching to complete */
• return wait_for_bit(__func__, reg, REFO_DIVSW_EN, false,

• 	    CONFIG_SYS_HZ, false);
  

+}

+static ulong pic32_get_refclk(struct pic32_clk_priv *priv, int periph) +{

• u32 rodiv, rotrim, rosel, v, parent_rate;
• void __iomem *reg;
• u64 rate64;
• WARN_ON((periph < REF1CLK) || (periph > REF5CLK));
• reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20;
• v = readl(reg);
• /* get rosel */
• rosel = (v >> REFO_SEL_SHIFT) & REFO_SEL_MASK;
• /* get div */
• rodiv = (v >> REFO_DIV_SHIFT) & REFO_DIV_MASK;
• /* get trim */
• v = readl(reg + REFO_TRIM_REG);
• rotrim = (v >> REFO_TRIM_SHIFT) & REFO_TRIM_MASK;
• if (!rodiv)

• return 0;
  

• /* get parent rate */
• switch (rosel) {
• case ROCLK_SRC_SCLK:

• parent_rate = pic32_get_cpuclk(priv);
  

• break;
  

• case ROCLK_SRC_SPLL:

• parent_rate = pic32_get_pll_rate(priv);
  

• break;
  

• default:

• parent_rate = 0;
  

• break;
  

• }
• /* Calculation

• * rate = parent_rate / [2 * (div + (trim / 512))]
  

• */
  

• if (rotrim) {

• rodiv <<= 9;
  

• rodiv += rotrim;
  

• rate64 = parent_rate;
  

• rate64 <<= 8;
  

• do_div(rate64, rodiv);
  

• v = (u32)rate64;
  

• } else {

• v = parent_rate / (rodiv << 1);
  

• }
• return v;

+}

+static ulong pic32_get_mpll_rate(struct pic32_clk_priv *priv) +{

• u32 v, idiv, mul;
• u32 odiv1, odiv2;
• u64 rate;
• v = readl(priv->syscfg_base + CFGMPLL);
• idiv = v & MPLL_IDIV;
• mul = (v >> MPLL_MULT_SHIFT) & MPLL_MULT;
• odiv1 = (v >> MPLL_ODIV1_SHIFT) & MPLL_ODIV1;
• odiv2 = (v >> MPLL_ODIV2_SHIFT) & MPLL_ODIV2;
• rate = (SYS_POSC_CLK_HZ / idiv) * mul;
• do_div(rate, odiv1);
• do_div(rate, odiv2);
• return (ulong)rate;

+}

+static int pic32_mpll_init(struct pic32_clk_priv *priv) +{

• u32 v, mask;
• /* initialize */
• v = (MPLL_IDIV_INIT << MPLL_IDIV_SHIFT) |

•    (MPLL_MULT_INIT << MPLL_MULT_SHIFT) |
  

•    (MPLL_ODIV1_INIT << MPLL_ODIV1_SHIFT) |
  

•    (MPLL_ODIV2_INIT << MPLL_ODIV2_SHIFT);
  

• writel(v, priv->syscfg_base + CFGMPLL);
• /* Wait for ready */
• mask = MPLL_RDY | MPLL_VREG_RDY;
• return wait_for_bit(__func__, priv->syscfg_base + CFGMPLL,

mask,

• 	    true, get_tbclk(), false);
  

+}

+static void pic32_clk_init(struct udevice *dev) +{

• const void *blob = gd->fdt_blob;
• struct pic32_clk_priv *priv;
• ulong rate, pll_hz;
• char propname[50];
• int i;
• priv = dev_get_priv(dev);
• pll_hz = pic32_get_pll_rate(priv);
• /* Initialize REFOs as not initialized and enabled on reset.

*/

• for (i = REF1CLK; i <= REF5CLK; i++) {

• snprintf(propname, sizeof(propname),
  

• 	 "microchip,refo%d-frequency", i - REF1CLK +
  

1);

• rate = fdtdec_get_int(blob, dev->of_offset,
  

propname, 0);

• if (rate)
  

• 	pic32_set_refclk(priv, i, pll_hz, rate,
  

ROCLK_SRC_SPLL);

• }
• /* Memory PLL */
• pic32_mpll_init(priv);

+}

+static ulong pic32_clk_get_rate(struct udevice *dev) +{

• struct pic32_clk_priv *priv = dev_get_priv(dev);
• return pic32_get_cpuclk(priv);

+}

+static ulong pic32_get_periph_rate(struct udevice *dev, int periph) +{

• struct pic32_clk_priv *priv = dev_get_priv(dev);
• ulong rate;
• switch (periph) {
• case PB1CLK ... PB7CLK:

• rate = pic32_get_pbclk(priv, periph);
  

• break;
  

• case REF1CLK ... REF5CLK:

• rate = pic32_get_refclk(priv, periph);
  

• break;
  

• case PLLCLK:

• rate = pic32_get_pll_rate(priv);
  

• break;
  

• case MPLL:

• rate = pic32_get_mpll_rate(priv);
  

• break;
  

• default:

• rate = 0;
  

• break;
  

• }
• return rate;

+}

+static ulong pic32_set_periph_rate(struct udevice *dev, int periph, ulong rate) +{

• struct pic32_clk_priv *priv = dev_get_priv(dev);
• ulong pll_hz;
• switch (periph) {
• case REF1CLK ... REF5CLK:

• pll_hz = pic32_get_pll_rate(priv);
  

• pic32_set_refclk(priv, periph, pll_hz, rate,
  

ROCLK_SRC_SPLL);

• break;
  

• default:

• break;
  

• }
• return rate;

+}

+static struct clk_ops pic32_pic32_clk_ops = {

• .get_rate = pic32_clk_get_rate,
• .set_periph_rate = pic32_set_periph_rate,
• .get_periph_rate = pic32_get_periph_rate,

+};

+static int pic32_clk_probe(struct udevice *dev) +{

• struct pic32_clk_priv *priv = dev_get_priv(dev);
• fdt_addr_t addr;
• fdt_size_t size;
• addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset,

"reg", &size);

• if (addr == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• priv->iobase = ioremap(addr, size);
• if (!priv->iobase)

• return -EINVAL;
  

you can drop this check. ioremap() always returns a mapped address

• priv->syscfg_base = pic32_get_syscfg_base();
• /* initialize clocks */
• pic32_clk_init(dev);
• return 0;

+}

+static const struct udevice_id pic32_clk_ids[] = {

• { .compatible = "microchip,pic32mzda_clk"},
• {}

+};

+U_BOOT_DRIVER(pic32_clk) = {

• .name = "pic32_clk",
• .id = UCLASS_CLK,
• .of_match = pic32_clk_ids,
• .flags = DM_FLAG_PRE_RELOC,
• .ops = &pic32_pic32_clk_ops,
• .probe = pic32_clk_probe,
• .priv_auto_alloc_size = sizeof(struct pic32_clk_priv),

+}; diff --git a/include/dt-bindings/clock/microchip,clock.h b/include/dt -bindings/clock/microchip,clock.h new file mode 100644 index 0000000..93c222d --- /dev/null +++ b/include/dt-bindings/clock/microchip,clock.h @@ -0,0 +1,29 @@ +/*

• • (c) 2015 Purna Chandra Mandal purna.mandal@microchip.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __CLK_MICROCHIP_PIC32 +#define __CLK_MICROCHIP_PIC32

+/* clock output indices */ +#define BASECLK 0 +#define PLLCLK 1 +#define MPLL 2 +#define SYSCLK 3 +#define PB1CLK 4 +#define PB2CLK 5 +#define PB3CLK 6 +#define PB4CLK 7 +#define PB5CLK 8 +#define PB6CLK 9 +#define PB7CLK 10 +#define REF1CLK 11 +#define REF2CLK 12 +#define REF3CLK 13 +#define REF4CLK 14 +#define REF5CLK 15

+#endif /* __CLK_MICROCHIP_PIC32 */

Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:

In PIC32 pin-controller is a combined gpio-controller, pin-mux and pin-config module. Remappable peripherals are assigned pins through per-pin based muxing logic. And pin configuration are performed on specific port registers which are shared along with gpio controller. Note, non-remappable peripherals have default pins assigned thus require no muxing.

Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com

Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com

---

Changes in v3:

• read register base from device-tree
• add/update comments to explain how pinctrl'r works.
• replace pic32_ioremap() with ioremap().

Changes in v2:

• add pinconf routine for configuring pin property

drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl_pic32.c | 363 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 373 insertions(+) create mode 100644 drivers/pinctrl/pinctrl_pic32.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 57e6142..292c4e2 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -131,6 +131,15 @@ config PINCTRL_SANDBOX actually does nothing but print debug messages when pinctrl operations are invoked.

+config PIC32_PINCTRL

• bool "Microchip PIC32 pin-control and pin-mux driver"
• depends on DM && MACH_PIC32
• help

•  Supports individual pin selection and configuration for
  

each remappable

•  peripheral available on Microchip PIC32 SoCs. This driver
  

is controlled

•  by a device tree node which contains both GPIO defintion
  

and pin control

•  functions.
  

endif

source "drivers/pinctrl/uniphier/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 70d25dc..b4f4650 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o

obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/ +obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o diff --git a/drivers/pinctrl/pinctrl_pic32.c b/drivers/pinctrl/pinctrl_pic32.c new file mode 100644 index 0000000..5cf97ec --- /dev/null +++ b/drivers/pinctrl/pinctrl_pic32.c @@ -0,0 +1,363 @@ +/*

• • Pinctrl driver for Microchip PIC32 SoCs
• • Copyright (c) 2015 Microchip Technology Inc.
• • Written by Purna Chandra Mandal purna.mandal@microchip.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <dm/pinctrl.h> +#include <dm/root.h> +#include <mach/pic32.h>

+DECLARE_GLOBAL_DATA_PTR;

+/* PIC32 has 10 peripheral ports with 16 pins each.

• • Ports are marked PORTA-PORTK or PORT0-PORT9.
• */

+enum {

• PIC32_PORT_A = 0,
• PIC32_PORT_B = 1,
• PIC32_PORT_C = 2,
• PIC32_PORT_D = 3,
• PIC32_PORT_E = 4,
• PIC32_PORT_F = 5,
• PIC32_PORT_G = 6,
• PIC32_PORT_H = 7,
• PIC32_PORT_J = 8, /* no PORT_I */
• PIC32_PORT_K = 9,
• PIC32_PINS_PER_PORT = 16,

+};

+#define PIN_CONFIG_PIC32_DIGITAL (PIN_CONFIG_END + 1) +#define PIN_CONFIG_PIC32_ANALOG (PIN_CONFIG_END + 2)

+/* pin configuration descriptor */ +struct pic32_pin_config {

• u16 port; /* port number */
• u16 pin; /* pin number in the port */
• u32 config; /* one of PIN_CONFIG_* */

+}; +#define PIN_CONFIG(_prt, _pin, _cfg) \

• {.port = (_prt), .pin = (_pin), .config = (_cfg), }

+/* In PIC32 muxing is performed at pin-level through two

• • different set of registers - one set for input functions,
• • and other for output functions.
• • Pin configuration is handled through port register.
• */

+/* Port control registers */ +struct pic32_reg_port {

• struct pic32_reg_atomic ansel;
• struct pic32_reg_atomic tris;
• struct pic32_reg_atomic port;
• struct pic32_reg_atomic lat;
• struct pic32_reg_atomic odc;
• struct pic32_reg_atomic cnpu;
• struct pic32_reg_atomic cnpd;
• struct pic32_reg_atomic cncon;
• struct pic32_reg_atomic unused[8];

+};

+/* Input function mux registers */ +struct pic32_reg_in_mux {

• u32 unused0;
• u32 int1[4];
• u32 unused1;
• u32 t2ck[8];
• u32 ic1[9];
• u32 unused2;
• u32 ocfar;
• u32 unused3;
• u32 u1rx;
• u32 u1cts;
• u32 u2rx;
• u32 u2cts;
• u32 u3rx;
• u32 u3cts;
• u32 u4rx;
• u32 u4cts;
• u32 u5rx;
• u32 u5cts;
• u32 u6rx;
• u32 u6cts;
• u32 unused4;
• u32 sdi1;
• u32 ss1;
• u32 unused5;
• u32 sdi2;
• u32 ss2;
• u32 unused6;
• u32 sdi3;
• u32 ss3;
• u32 unused7;
• u32 sdi4;
• u32 ss4;
• u32 unused8;
• u32 sdi5;
• u32 ss5;
• u32 unused9;
• u32 sdi6;
• u32 ss6;
• u32 c1rx;
• u32 c2rx;
• u32 refclki1;
• u32 refclki2;
• u32 refclki3;
• u32 refclki4;

+};

+/* output mux register offset */ +#define PPS_OUT(__port, __pin) \

• (((__port) * PIC32_PINS_PER_PORT + (__pin)) << 2)

+struct pic32_pinctrl_priv {

• struct pic32_reg_in_mux *mux_in; /* mux input function */
• struct pic32_reg_port *pinconf; /* pin configuration*/
• void __iomem *mux_out; /* mux output function */

+};

+enum {

• PERIPH_ID_UART1,
• PERIPH_ID_UART2,
• PERIPH_ID_ETH,
• PERIPH_ID_USB,
• PERIPH_ID_SDHCI,
• PERIPH_ID_I2C1,
• PERIPH_ID_I2C2,
• PERIPH_ID_SPI1,
• PERIPH_ID_SPI2,
• PERIPH_ID_SQI,

+};

+static int pic32_pinconfig_one(struct pic32_pinctrl_priv *priv,

• 	       u32 port_nr, u32 pin, u32 param)
  

+{

• struct pic32_reg_port *port;
• port = &priv->pinconf[port_nr];
• switch (param) {
• case PIN_CONFIG_PIC32_DIGITAL:

• writel(BIT(pin), &port->ansel.clr);
  

• break;
  

• case PIN_CONFIG_PIC32_ANALOG:

• writel(BIT(pin), &port->ansel.set);
  

• break;
  

• case PIN_CONFIG_INPUT_ENABLE:

• writel(BIT(pin), &port->tris.set);
  

• break;
  

• case PIN_CONFIG_OUTPUT:

• writel(BIT(pin), &port->tris.clr);
  

• break;
  

• case PIN_CONFIG_BIAS_PULL_UP:

• writel(BIT(pin), &port->cnpu.set);
  

• break;
  

• case PIN_CONFIG_BIAS_PULL_DOWN:

• writel(BIT(pin), &port->cnpd.set);
  

• break;
  

• case PIN_CONFIG_DRIVE_OPEN_DRAIN:

• writel(BIT(pin), &port->odc.set);
  

• break;
  

• default:

• break;
  

• }
• return 0;

+}

+static int pic32_pinconfig_set(struct pic32_pinctrl_priv *priv,

• 	       const struct pic32_pin_config *list,
  

int count) +{

• int i;
• for (i = 0 ; i < count; i++)

• pic32_pinconfig_one(priv, list[i].port,
  

• 		    list[i].pin, list[i].config);
  

• return 0;

+}

+static void pic32_eth_pin_config(struct udevice *dev) +{

• struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
• const struct pic32_pin_config configs[] = {

• /* EMDC - D11 */
  

• PIN_CONFIG(PIC32_PORT_D, 11,
  

PIN_CONFIG_PIC32_DIGITAL),

• PIN_CONFIG(PIC32_PORT_D, 11, PIN_CONFIG_OUTPUT),
  

• /* ETXEN */
  

• PIN_CONFIG(PIC32_PORT_D, 6,
  

PIN_CONFIG_PIC32_DIGITAL),

• PIN_CONFIG(PIC32_PORT_D, 6, PIN_CONFIG_OUTPUT),
  

• /* ECRSDV */
  

• PIN_CONFIG(PIC32_PORT_H, 13,
  

PIN_CONFIG_PIC32_DIGITAL),

• PIN_CONFIG(PIC32_PORT_H, 13,
  

PIN_CONFIG_INPUT_ENABLE),

• /* ERXD0 */
  

• PIN_CONFIG(PIC32_PORT_H, 8,
  

PIN_CONFIG_PIC32_DIGITAL),

• PIN_CONFIG(PIC32_PORT_H, 8,
  

PIN_CONFIG_INPUT_ENABLE),

• PIN_CONFIG(PIC32_PORT_H, 8,
  

PIN_CONFIG_BIAS_PULL_DOWN),

• /* ERXD1 */
  

• PIN_CONFIG(PIC32_PORT_H, 5,
  

PIN_CONFIG_PIC32_DIGITAL),

• PIN_CONFIG(PIC32_PORT_H, 5,
  

PIN_CONFIG_INPUT_ENABLE),

• PIN_CONFIG(PIC32_PORT_H, 5,
  

PIN_CONFIG_BIAS_PULL_DOWN),

• /* EREFCLK */
  

• PIN_CONFIG(PIC32_PORT_J, 11,
  

PIN_CONFIG_PIC32_DIGITAL),

• PIN_CONFIG(PIC32_PORT_J, 11,
  

PIN_CONFIG_INPUT_ENABLE),

• /* ETXD1 */
  

• PIN_CONFIG(PIC32_PORT_J, 9,
  

PIN_CONFIG_PIC32_DIGITAL),

• PIN_CONFIG(PIC32_PORT_J, 9, PIN_CONFIG_OUTPUT),
  

• /* ETXD0 */
  

• PIN_CONFIG(PIC32_PORT_J, 8,
  

PIN_CONFIG_PIC32_DIGITAL),

• PIN_CONFIG(PIC32_PORT_J, 8, PIN_CONFIG_OUTPUT),
  

• /* EMDIO */
  

• PIN_CONFIG(PIC32_PORT_J, 1,
  

PIN_CONFIG_PIC32_DIGITAL),

• PIN_CONFIG(PIC32_PORT_J, 1,
  

PIN_CONFIG_INPUT_ENABLE),

• /* ERXERR */
  

• PIN_CONFIG(PIC32_PORT_F, 3,
  

PIN_CONFIG_PIC32_DIGITAL),

• PIN_CONFIG(PIC32_PORT_F, 3,
  

PIN_CONFIG_INPUT_ENABLE),

• };
• pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));

+}

+static int pic32_pinctrl_request(struct udevice *dev, int func, int flags) +{

• struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
• switch (func) {
• case PERIPH_ID_UART2:

• /* PPS for U2 RX/TX */
  

• writel(0x02, priv->mux_out + PPS_OUT(PIC32_PORT_G,
  

9));

• writel(0x05, &priv->mux_in->u2rx); /* B0 */
  

• /* set digital mode */
  

• pic32_pinconfig_one(priv, PIC32_PORT_G, 9,
  

• 		    PIN_CONFIG_PIC32_DIGITAL);
  

• pic32_pinconfig_one(priv, PIC32_PORT_B, 0,
  

• 		    PIN_CONFIG_PIC32_DIGITAL);
  

• break;
  

• case PERIPH_ID_ETH:

• pic32_eth_pin_config(dev);
  

• break;
  

• default:

• debug("%s: unknown-unhandled case\n", __func__);
  

• break;
  

• }
• return 0;

+}

+static int pic32_pinctrl_get_periph_id(struct udevice *dev,

• 		       struct udevice *periph)
  

+{

• int ret;
• u32 cell[2];
• ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,

• 		   "interrupts", cell,
  

ARRAY_SIZE(cell));

• if (ret < 0)

• return -EINVAL;
  

• /* interrupt number */
• switch (cell[0]) {
• case 112 ... 114:

• return PERIPH_ID_UART1;
  

• case 145 ... 147:

• return PERIPH_ID_UART2;
  

• case 109 ... 111:

• return PERIPH_ID_SPI1;
  

• case 142 ... 144:

• return PERIPH_ID_SPI2;
  

• case 115 ... 117:

• return PERIPH_ID_I2C1;
  

• case 148 ... 150:

• return PERIPH_ID_I2C2;
  

• case 132 ... 133:

• return PERIPH_ID_USB;
  

• case 169:

• return PERIPH_ID_SQI;
  

• case 191:

• return PERIPH_ID_SDHCI;
  

• case 153:

• return PERIPH_ID_ETH;
  

• default:

• break;
  

• }
• return -ENOENT;

+}

+static int pic32_pinctrl_set_state_simple(struct udevice *dev,

• 			  struct udevice *periph)
  

+{

• int func;
• debug("%s: periph %s\n", __func__, periph->name);
• func = pic32_pinctrl_get_periph_id(dev, periph);
• if (func < 0)

• return func;
  

• return pic32_pinctrl_request(dev, func, 0);

+}

+static struct pinctrl_ops pic32_pinctrl_ops = {

• .set_state_simple = pic32_pinctrl_set_state_simple,
• .request = pic32_pinctrl_request,
• .get_periph_id = pic32_pinctrl_get_periph_id,

+};

+static int pic32_pinctrl_probe(struct udevice *dev) +{

• struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
• struct fdt_resource res;
• void *fdt = (void *)gd->fdt_blob;
• int node = dev->of_offset;
• int ret;
• ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",

• 		     "ppsin", &res);
  

• if (ret < 0) {

• printf("pinctrl: resource \"ppsin\" not found\n");
  

• return ret;
  

• }
• priv->mux_in = ioremap(res.start, fdt_resource_size(&res));
• ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",

• 		     "ppsout", &res);
  

• if (ret < 0) {

• printf("pinctrl: resource \"ppsout\" not found\n");
  

• return ret;
  

• }
• priv->mux_out = ioremap(res.start, fdt_resource_size(&res));
• ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",

• 		     "port", &res);
  

• if (ret < 0) {

• printf("pinctrl: resource \"port\" not found\n");
  

• return ret;
  

• }
• priv->pinconf = ioremap(res.start, fdt_resource_size(&res));
• return 0;

+}

+static int pic32_pinctrl_bind(struct udevice *dev) +{

• /* scan child GPIO banks */
• return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset,

false); +}

+static const struct udevice_id pic32_pinctrl_ids[] = {

• { .compatible = "microchip,pic32mzda-pinctrl" },
• { }

+};

+U_BOOT_DRIVER(pinctrl_pic32) = {

• .name = "pinctrl_pic32",
• .id = UCLASS_PINCTRL,
• .of_match = pic32_pinctrl_ids,
• .ops = &pic32_pinctrl_ops,
• .probe = pic32_pinctrl_probe,
• .bind = pic32_pinctrl_bind,
• .priv_auto_alloc_size = sizeof(struct pic32_pinctrl_priv),

+};

Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:

In PIC32 GPIO controller is part of PIC32 pin controller. PIC32 has ten independently programmable ports and each with multiple pins. Each of these pins can be configured and used as GPIO, provided they are not in use for other peripherals.

Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com

Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com

nits below

---

Changes in v3:

• add check on dev_get_addr()

Changes in v2: None

drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 2 +- drivers/gpio/pic32_gpio.c | 175 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 183 insertions(+), 1 deletion(-) create mode 100644 drivers/gpio/pic32_gpio.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e60e9fd..13e9a6a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -83,4 +83,11 @@ config VYBRID_GPIO help Say yes here to support Vybrid vf610 GPIOs.

+config PIC32_GPIO

• bool "Microchip PIC32 GPIO driver"
• depends on DM_GPIO
• default y if MACH_PIC32
• help

•  Say yes here to support Microchip PIC32 GPIOs.
  

endmenu diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fb4fd25..845a6d4 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o

+obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c new file mode 100644 index 0000000..5b23af4 --- /dev/null +++ b/drivers/gpio/pic32_gpio.c @@ -0,0 +1,175 @@ +/*

• • Copyright (c) 2015 Microchip Technology Inc
• • Purna Chandra Mandal purna.mandal@microchip.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/compat.h> +#include <dt-bindings/gpio/gpio.h> +#include <mach/pic32.h>

+DECLARE_GLOBAL_DATA_PTR;

+/* Peripheral Pin Control */ +struct pic32_reg_port {

• struct pic32_reg_atomic ansel;
• struct pic32_reg_atomic tris;
• struct pic32_reg_atomic port;
• struct pic32_reg_atomic lat;
• struct pic32_reg_atomic open_drain;
• struct pic32_reg_atomic cnpu;
• struct pic32_reg_atomic cnpd;
• struct pic32_reg_atomic cncon;

+};

+enum {

• MICROCHIP_GPIO_DIR_OUT,
• MICROCHIP_GPIO_DIR_IN,
• MICROCHIP_GPIOS_PER_BANK = 16,

+};

+struct pic32_gpio_priv {

• struct pic32_reg_port *regs;
• char name[2];

+};

+static int pic32_gpio_get_value(struct udevice *dev, unsigned offset) +{

• struct pic32_gpio_priv *priv = dev_get_priv(dev);
• return !!(readl(&priv->regs->port.raw) & BIT(offset));

+}

+static int pic32_gpio_set_value(struct udevice *dev, unsigned offset,

• 		int value)
  

+{

• struct pic32_gpio_priv *priv = dev_get_priv(dev);
• int mask = BIT(offset);
• if (value)

• writel(mask, &priv->regs->port.set);
  

• else

• writel(mask, &priv->regs->port.clr);
  

• return 0;

+}

+static int pic32_gpio_direction(struct udevice *dev, unsigned offset) +{

• struct pic32_gpio_priv *priv = dev_get_priv(dev);
• if (readl(&priv->regs->ansel.raw) & BIT(offset))

• return -1;
  

• if (readl(&priv->regs->tris.raw) & BIT(offset))

• return MICROCHIP_GPIO_DIR_IN;
  

• else

• return MICROCHIP_GPIO_DIR_OUT;
  

+}

+static int pic32_gpio_direction_input(struct udevice *dev, unsigned offset) +{

• struct pic32_gpio_priv *priv = dev_get_priv(dev);
• int mask = BIT(offset);
• writel(mask, &priv->regs->ansel.clr);
• writel(mask, &priv->regs->tris.set);
• return 0;

+}

+static int pic32_gpio_direction_output(struct udevice *dev,

• 		       unsigned offset, int value)
  

+{

• struct pic32_gpio_priv *priv = dev_get_priv(dev);
• int mask = BIT(offset);
• writel(mask, &priv->regs->ansel.clr);
• writel(mask, &priv->regs->tris.clr);
• pic32_gpio_set_value(dev, offset, value);
• return 0;

+}

+static int pic32_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,

• 	    struct fdtdec_phandle_args *args)
  

+{

• desc->offset = args->args[0];
• desc->flags = args->args[1] & GPIO_ACTIVE_LOW ?

GPIOD_ACTIVE_LOW : 0;

• return 0;

+}

+static int pic32_gpio_get_function(struct udevice *dev, unsigned offset) +{

• int ret = GPIOF_UNUSED;
• switch (pic32_gpio_direction(dev, offset)) {
• case MICROCHIP_GPIO_DIR_OUT:

• ret = GPIOF_OUTPUT;
  

• break;
  

• case MICROCHIP_GPIO_DIR_IN:

• ret = GPIOF_INPUT;
  

• break;
  

• default:

• ret = GPIOF_UNUSED;
  

• break;
  

• }
• return ret;

+}

+static const struct dm_gpio_ops gpio_pic32_ops = {

• .direction_input = pic32_gpio_direction_input,
• .direction_output = pic32_gpio_direction_output,
• .get_value = pic32_gpio_get_value,
• .set_value = pic32_gpio_set_value,
• .get_function = pic32_gpio_get_function,
• .xlate = pic32_gpio_xlate,

+};

+static int pic32_gpio_probe(struct udevice *dev) +{

• struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
• struct pic32_gpio_priv *priv = dev_get_priv(dev);
• fdt_addr_t addr;
• fdt_size_t size;
• char *end;
• int bank;
• addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset,

"reg", &size);

• if (addr == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• priv->regs = ioremap(addr, size);
• if (!priv->regs)

• return -EINVAL;
  

you can drop this check. ioremap() always returns a mapped address.

• uc_priv->gpio_count = MICROCHIP_GPIOS_PER_BANK;
• end = strrchr(dev->name, '@');
• bank = trailing_strtoln(dev->name, end);
• priv->name[0] = 'A' + bank;
• uc_priv->bank_name = priv->name;
• return 0;

+}

+static const struct udevice_id pic32_gpio_ids[] = {

• { .compatible = "microchip,pic32mzda-gpio" },
• { }

+};

+U_BOOT_DRIVER(gpio_pic32) = {

• .name = "gpio_pic32",
• .id = UCLASS_GPIO,
• .of_match = pic32_gpio_ids,
• .ops = &gpio_pic32_ops,
• .probe = pic32_gpio_probe,
• .priv_auto_alloc_size = sizeof(struct

pic32_gpio_priv), +};

On 01/13/2016 07:38 PM, Daniel Schwierzeck wrote:

Am Mittwoch, den 13.01.2016, 14:46 +0100 schrieb Daniel Schwierzeck:

...

Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:

...

In PIC32 GPIO controller is part of PIC32 pin controller. PIC32 has ten independently programmable ports and each with multiple pins. Each of these pins can be configured and used as GPIO, provided they are not in use for other peripherals.

Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com

Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com

nits below

...

---

Changes in v3:

• add check on dev_get_addr()

Changes in v2: None

drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 2 +- drivers/gpio/pic32_gpio.c | 175 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 183 insertions(+), 1 deletion(-) create mode 100644 drivers/gpio/pic32_gpio.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e60e9fd..13e9a6a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -83,4 +83,11 @@ config VYBRID_GPIO help Say yes here to support Vybrid vf610 GPIOs.

+config PIC32_GPIO

• bool "Microchip PIC32 GPIO driver"
• depends on DM_GPIO
• default y if MACH_PIC32

this should be

depends on DM_GPIO && MACH_PIC32

ack, will add.

...

...

• help

•  Say yes here to support Microchip PIC32 GPIOs.
  

endmenu diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fb4fd25..845a6d4 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o

+obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c new file mode 100644 index 0000000..5b23af4 --- /dev/null +++ b/drivers/gpio/pic32_gpio.c @@ -0,0 +1,175 @@ +/*

• • Copyright (c) 2015 Microchip Technology Inc
• • Purna Chandra Mandal purna.mandal@microchip.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/compat.h> +#include <dt-bindings/gpio/gpio.h> +#include <mach/pic32.h>

+DECLARE_GLOBAL_DATA_PTR;

+/* Peripheral Pin Control */ +struct pic32_reg_port {

• struct pic32_reg_atomic ansel;
• struct pic32_reg_atomic tris;
• struct pic32_reg_atomic port;
• struct pic32_reg_atomic lat;
• struct pic32_reg_atomic open_drain;
• struct pic32_reg_atomic cnpu;
• struct pic32_reg_atomic cnpd;
• struct pic32_reg_atomic cncon;

+};

+enum {

• MICROCHIP_GPIO_DIR_OUT,
• MICROCHIP_GPIO_DIR_IN,
• MICROCHIP_GPIOS_PER_BANK = 16,

+};

+struct pic32_gpio_priv {

• struct pic32_reg_port *regs;
• char name[2];

+};

+static int pic32_gpio_get_value(struct udevice *dev, unsigned offset) +{

• struct pic32_gpio_priv *priv = dev_get_priv(dev);
• return !!(readl(&priv->regs->port.raw) & BIT(offset));

+}

+static int pic32_gpio_set_value(struct udevice *dev, unsigned offset,

• 		int value)
  

+{

• struct pic32_gpio_priv *priv = dev_get_priv(dev);
• int mask = BIT(offset);
• if (value)

• writel(mask, &priv->regs->port.set);
  

• else

• writel(mask, &priv->regs->port.clr);
  

• return 0;

+}

+static int pic32_gpio_direction(struct udevice *dev, unsigned offset) +{

• struct pic32_gpio_priv *priv = dev_get_priv(dev);
• if (readl(&priv->regs->ansel.raw) & BIT(offset))

• return -1;
  

• if (readl(&priv->regs->tris.raw) & BIT(offset))

• return MICROCHIP_GPIO_DIR_IN;
  

• else

• return MICROCHIP_GPIO_DIR_OUT;
  

+}

+static int pic32_gpio_direction_input(struct udevice *dev, unsigned offset) +{

• struct pic32_gpio_priv *priv = dev_get_priv(dev);
• int mask = BIT(offset);
• writel(mask, &priv->regs->ansel.clr);
• writel(mask, &priv->regs->tris.set);
• return 0;

+}

+static int pic32_gpio_direction_output(struct udevice *dev,

• 		       unsigned offset, int value)
  

+{

• struct pic32_gpio_priv *priv = dev_get_priv(dev);
• int mask = BIT(offset);
• writel(mask, &priv->regs->ansel.clr);
• writel(mask, &priv->regs->tris.clr);
• pic32_gpio_set_value(dev, offset, value);
• return 0;

+}

+static int pic32_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,

• 	    struct fdtdec_phandle_args *args)
  

+{

• desc->offset = args->args[0];
• desc->flags = args->args[1] & GPIO_ACTIVE_LOW ?

GPIOD_ACTIVE_LOW : 0;

• return 0;

+}

+static int pic32_gpio_get_function(struct udevice *dev, unsigned offset) +{

• int ret = GPIOF_UNUSED;
• switch (pic32_gpio_direction(dev, offset)) {
• case MICROCHIP_GPIO_DIR_OUT:

• ret = GPIOF_OUTPUT;
  

• break;
  

• case MICROCHIP_GPIO_DIR_IN:

• ret = GPIOF_INPUT;
  

• break;
  

• default:

• ret = GPIOF_UNUSED;
  

• break;
  

• }
• return ret;

+}

+static const struct dm_gpio_ops gpio_pic32_ops = {

• .direction_input = pic32_gpio_direction_input,
• .direction_output = pic32_gpio_direction_output,
• .get_value = pic32_gpio_get_value,
• .set_value = pic32_gpio_set_value,
• .get_function = pic32_gpio_get_function,
• .xlate = pic32_gpio_xlate,

+};

+static int pic32_gpio_probe(struct udevice *dev) +{

• struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
• struct pic32_gpio_priv *priv = dev_get_priv(dev);
• fdt_addr_t addr;
• fdt_size_t size;
• char *end;
• int bank;
• addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset,

"reg", &size);

• if (addr == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• priv->regs = ioremap(addr, size);
• if (!priv->regs)

• return -EINVAL;
  

you can drop this check. ioremap() always returns a mapped address.

ack. will drop.

...

...

• uc_priv->gpio_count = MICROCHIP_GPIOS_PER_BANK;
• end = strrchr(dev->name, '@');
• bank = trailing_strtoln(dev->name, end);
• priv->name[0] = 'A' + bank;
• uc_priv->bank_name = priv->name;
• return 0;

+}

+static const struct udevice_id pic32_gpio_ids[] = {

• { .compatible = "microchip,pic32mzda-gpio" },
• { }

+};

+U_BOOT_DRIVER(gpio_pic32) = {

• .name = "gpio_pic32",
• .id = UCLASS_GPIO,
• .of_match = pic32_gpio_ids,
• .ops = &gpio_pic32_ops,
• .probe = pic32_gpio_probe,
• .priv_auto_alloc_size = sizeof(struct

pic32_gpio_priv), +};

Hi Puma,

On 12 January 2016 at 03:18, Purna Chandra Mandal purna.mandal@microchip.com wrote:

In PIC32 GPIO controller is part of PIC32 pin controller. PIC32 has ten independently programmable ports and each with multiple pins. Each of these pins can be configured and used as GPIO, provided they are not in use for other peripherals.

Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com

---

Changes in v3:

• add check on dev_get_addr()

Changes in v2: None

drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 2 +- drivers/gpio/pic32_gpio.c | 175 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 183 insertions(+), 1 deletion(-) create mode 100644 drivers/gpio/pic32_gpio.c

Reviewed-by: Simon Glass sjg@chromium.org

Just a few nits.

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e60e9fd..13e9a6a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -83,4 +83,11 @@ config VYBRID_GPIO help Say yes here to support Vybrid vf610 GPIOs.

+config PIC32_GPIO

•   bool "Microchip PIC32 GPIO driver"
  

•   depends on DM_GPIO
  

•   default y if MACH_PIC32
  

•   help
  

•     Say yes here to support Microchip PIC32 GPIOs.
  

endmenu diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fb4fd25..845a6d4 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o

+obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c new file mode 100644 index 0000000..5b23af4 --- /dev/null +++ b/drivers/gpio/pic32_gpio.c @@ -0,0 +1,175 @@ +/*

• • Copyright (c) 2015 Microchip Technology Inc
• • Purna Chandra Mandal purna.mandal@microchip.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/compat.h> +#include <dt-bindings/gpio/gpio.h> +#include <mach/pic32.h>

+DECLARE_GLOBAL_DATA_PTR;

+/* Peripheral Pin Control */ +struct pic32_reg_port {

•   struct pic32_reg_atomic ansel;
  

•   struct pic32_reg_atomic tris;
  

•   struct pic32_reg_atomic port;
  

•   struct pic32_reg_atomic lat;
  

•   struct pic32_reg_atomic open_drain;
  

•   struct pic32_reg_atomic cnpu;
  

•   struct pic32_reg_atomic cnpd;
  

•   struct pic32_reg_atomic cncon;
  

+};

+enum {

•   MICROCHIP_GPIO_DIR_OUT,
  

•   MICROCHIP_GPIO_DIR_IN,
  

•   MICROCHIP_GPIOS_PER_BANK = 16,
  

+};

+struct pic32_gpio_priv {

•   struct pic32_reg_port *regs;
  

•   char name[2];
  

+};

+static int pic32_gpio_get_value(struct udevice *dev, unsigned offset) +{

•   struct pic32_gpio_priv *priv = dev_get_priv(dev);
  

•   return !!(readl(&priv->regs->port.raw) & BIT(offset));
  

+}

+static int pic32_gpio_set_value(struct udevice *dev, unsigned offset,

•                           int value)
  

+{

•   struct pic32_gpio_priv *priv = dev_get_priv(dev);
  

•   int mask = BIT(offset);
  

•   if (value)
  

•           writel(mask, &priv->regs->port.set);
  

•   else
  

•           writel(mask, &priv->regs->port.clr);
  

•   return 0;
  

+}

+static int pic32_gpio_direction(struct udevice *dev, unsigned offset) +{

•   struct pic32_gpio_priv *priv = dev_get_priv(dev);
  

•   if (readl(&priv->regs->ansel.raw) & BIT(offset))
  

•           return -1;
  

What does this error mean? Should it be -EPERM? Perhaps add a comment.

•   if (readl(&priv->regs->tris.raw) & BIT(offset))
  

•           return MICROCHIP_GPIO_DIR_IN;
  

•   else
  

•           return MICROCHIP_GPIO_DIR_OUT;
  

+}

+static int pic32_gpio_direction_input(struct udevice *dev, unsigned offset) +{

•   struct pic32_gpio_priv *priv = dev_get_priv(dev);
  

•   int mask = BIT(offset);
  

•   writel(mask, &priv->regs->ansel.clr);
  

•   writel(mask, &priv->regs->tris.set);
  

•   return 0;
  

+}

+static int pic32_gpio_direction_output(struct udevice *dev,

•                                  unsigned offset, int value)
  

+{

•   struct pic32_gpio_priv *priv = dev_get_priv(dev);
  

•   int mask = BIT(offset);
  

•   writel(mask, &priv->regs->ansel.clr);
  

•   writel(mask, &priv->regs->tris.clr);
  

•   pic32_gpio_set_value(dev, offset, value);
  

•   return 0;
  

+}

+static int pic32_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,

•                       struct fdtdec_phandle_args *args)
  

+{

•   desc->offset = args->args[0];
  

This is done automatically in gpio_find_and_xlate(), so you shouldn't need it.

•   desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
  

•   return 0;
  

+}

+static int pic32_gpio_get_function(struct udevice *dev, unsigned offset) +{

•   int ret = GPIOF_UNUSED;
  

•   switch (pic32_gpio_direction(dev, offset)) {
  

•   case MICROCHIP_GPIO_DIR_OUT:
  

•           ret = GPIOF_OUTPUT;
  

•           break;
  

•   case MICROCHIP_GPIO_DIR_IN:
  

•           ret = GPIOF_INPUT;
  

•           break;
  

•   default:
  

•           ret = GPIOF_UNUSED;
  

•           break;
  

•   }
  

•   return ret;
  

+}

+static const struct dm_gpio_ops gpio_pic32_ops = {

•   .direction_input        = pic32_gpio_direction_input,
  

•   .direction_output       = pic32_gpio_direction_output,
  

•   .get_value              = pic32_gpio_get_value,
  

•   .set_value              = pic32_gpio_set_value,
  

•   .get_function           = pic32_gpio_get_function,
  

•   .xlate                  = pic32_gpio_xlate,
  

+};

+static int pic32_gpio_probe(struct udevice *dev) +{

•   struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  

•   struct pic32_gpio_priv *priv = dev_get_priv(dev);
  

•   fdt_addr_t addr;
  

•   fdt_size_t size;
  

•   char *end;
  

•   int bank;
  

•   addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
  

•   if (addr == FDT_ADDR_T_NONE)
  

•           return -EINVAL;
  

•   priv->regs = ioremap(addr, size);
  

•   if (!priv->regs)
  

•           return -EINVAL;
  

•   uc_priv->gpio_count = MICROCHIP_GPIOS_PER_BANK;
  

•   end = strrchr(dev->name, '@');
  

•   bank = trailing_strtoln(dev->name, end);
  

•   priv->name[0] = 'A' + bank;
  

•   uc_priv->bank_name = priv->name;
  

•   return 0;
  

+}

+static const struct udevice_id pic32_gpio_ids[] = {

•   { .compatible = "microchip,pic32mzda-gpio" },
  

•   { }
  

+};

+U_BOOT_DRIVER(gpio_pic32) = {

•   .name           = "gpio_pic32",
  

•   .id             = UCLASS_GPIO,
  

•   .of_match       = pic32_gpio_ids,
  

•   .ops            = &gpio_pic32_ops,
  

•   .probe          = pic32_gpio_probe,
  

•   .priv_auto_alloc_size   = sizeof(struct pic32_gpio_priv),
  

+};

1.8.3.1

Regards, Simon

Am Mittwoch, den 13.01.2016, 14:49 +0100 schrieb Daniel Schwierzeck:

Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:

...

From: Paul Thacker paul.thacker@microchip.com

This adds PIC32 UART controller support based on driver model.

Signed-off-by: Paul Thacker paul.thacker@microchip.com Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com

Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com

nits below

I forgot one thing

...

---

Changes in v3:

• remove ofdata_to_platdata, and replace platdata with priv
• remove special handling of '\r' as being handled by serial-uclass
• remove loop to wait for space in tx buffer before pumping char

Changes in v2:

• fix missing/corrupted chars during baud rate change
• remove loop until any char is avaialbale in getc()

.../serial/microchip,pic32-uart.txt | 5 + drivers/serial/Kconfig | 13 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_pic32.c | 199 +++++++++++++++++++++ 4 files changed, 218 insertions(+) create mode 100644 doc/device-tree-bindings/serial/microchip,pic32 -uart.txt create mode 100644 drivers/serial/serial_pic32.c

diff --git a/doc/device-tree-bindings/serial/microchip,pic32 -uart.txt b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt new file mode 100644 index 0000000..f00e215 --- /dev/null +++ b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt @@ -0,0 +1,5 @@ +* Microchip PIC32 serial UART

+Required properties: +- compatible: must be "microchip,pic32mzda-uart". +- reg: exactly one register range. diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 1fc287e..9763ea1 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -107,6 +107,14 @@ config DEBUG_UART_APBUART will need to provide parameters to make this work. The driver will be available until the real driver model serial is running.

+config DEBUG_UART_PIC32

• bool "Microchip PIC32"
• help

•  Select this to enable a debug UART using the
  

serial_pic32 driver. You

•  will need to provide parameters to make this work. The
  

driver will

•  be available until the real driver model serial is
  

running.

endchoice

config DEBUG_UART_BASE @@ -223,4 +231,9 @@ config UNIPHIER_SERIAL If you have a UniPhier based board and want to use the on -chip serial ports, say Y to this option. If unsure, say N.

+config PIC32_SERIAL

• bool "Support for Microchip PIC32 on-chip UART"

you should add

depends on DM_SERIAL && MACH_PIC32

...

• help

•  Support for the UART found on Microchip PIC32 SoC's.
  

endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dd87147..57cd38b 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o +obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o

ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c new file mode 100644 index 0000000..ee9d056 --- /dev/null +++ b/drivers/serial/serial_pic32.c @@ -0,0 +1,199 @@ +/*

• • (c) 2015 Paul Thacker paul.thacker@microchip.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <serial.h> +#include <wait_bit.h> +#include <mach/pic32.h> +#include <dt-bindings/clock/microchip,clock.h>

+DECLARE_GLOBAL_DATA_PTR;

+/* UART Control Registers */ +#define U_MOD 0x00 +#define U_MODCLR (U_MOD + _CLR_OFFSET) +#define U_MODSET (U_MOD + _SET_OFFSET) +#define U_STA 0x10 +#define U_STACLR (U_STA + _CLR_OFFSET) +#define U_STASET (U_STA + _SET_OFFSET) +#define U_TXR 0x20 +#define U_RXR 0x30 +#define U_BRG 0x40

+/* U_MOD bits */ +#define UART_ENABLE BIT(15)

+/* U_STA bits */ +#define UART_RX_ENABLE BIT(12) +#define UART_TX_BRK BIT(11) +#define UART_TX_ENABLE BIT(10) +#define UART_TX_FULL BIT(9) +#define UART_TX_EMPTY BIT(8) +#define UART_RX_OERR BIT(1) +#define UART_RX_DATA_AVAIL BIT(0)

+struct pic32_uart_priv {

• void __iomem *base;
• ulong uartclk;

+};

+/*

• • Initialize the serial port with the given baudrate.
• • The settings are always 8 data bits, no parity, 1 stop bit, no

start bits.

• */

+static int pic32_serial_init(void __iomem *base, ulong clk, u32 baudrate) +{

• u32 div = DIV_ROUND_CLOSEST(clk, baudrate * 16);
• /* wait for TX FIFO to empty */
• wait_for_bit(__func__, base + U_STA, UART_TX_EMPTY,

•      true, CONFIG_SYS_HZ, false);
  

• /* send break */
• writel(UART_TX_BRK, base + U_STASET);
• /* disable and clear mode */
• writel(0, base + U_MOD);
• writel(0, base + U_STA);
• /* set baud rate generator */
• writel(div - 1, base + U_BRG);
• /* enable the UART for TX and RX */
• writel(UART_TX_ENABLE | UART_RX_ENABLE, base + U_STASET);
• /* enable the UART */
• writel(UART_ENABLE, base + U_MODSET);
• return 0;

+}

+/* Check number of characters ready in RX Fifo */ +static int pic32_uart_pending_input(void __iomem *base) +{

• /* check if rx buffer overrun error has occurred */
• if (readl(base + U_STA) & UART_RX_OERR) {

• readl(base + U_RXR);
  

• /* clear OERR to keep receiving */
  

• writel(UART_RX_OERR, base + U_STACLR);
  

• }
• return readl(base + U_STA) & UART_RX_DATA_AVAIL;

+}

+static int pic32_uart_pending(struct udevice *dev, bool input) +{

• struct pic32_uart_priv *priv = dev_get_priv(dev);
• if (input)

• return pic32_uart_pending_input(priv->base);
  

• return !(readl(priv->base + U_STA) & UART_TX_EMPTY);

+}

+static int pic32_uart_setbrg(struct udevice *dev, int baudrate) +{

• struct pic32_uart_priv *priv = dev_get_priv(dev);
• return pic32_serial_init(priv->base, priv->uartclk,

baudrate); +}

+static int pic32_uart_putc(struct udevice *dev, const char ch) +{

• struct pic32_uart_priv *priv = dev_get_priv(dev);
• /* Check if Tx FIFO is full */
• if (readl(priv->base + U_STA) & UART_TX_FULL)

• return -EAGAIN;
  

• /* pump the char to tx buffer */
• writel(ch, priv->base + U_TXR);
• return 0;

+}

+static int pic32_uart_getc(struct udevice *dev) +{

• struct pic32_uart_priv *priv = dev_get_priv(dev);
• /* return error if RX fifo is empty */
• if (!pic32_uart_pending_input(priv->base))

• return -EAGAIN;
  

• /* read the character from rx buffer */
• return readl(priv->base + U_RXR) & 0xff;

+}

+static int pic32_uart_probe(struct udevice *dev) +{

• struct pic32_uart_priv *priv = dev_get_priv(dev);
• struct udevice *clkdev;
• fdt_addr_t addr;
• fdt_size_t size;
• int ret;
• /* get address */
• addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset,

"reg", &size);

• if (addr == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• priv->base = ioremap(addr, size);
• if (!priv->base)

• return -EINVAL;
  

you can drop this check. ioremap() always returns a mapped address.

...

• /* get clock rate */
• ret = uclass_get_device(UCLASS_CLK, 0, &clkdev);
• if (ret) {

• printf("clk class not found, %d\n", ret);
  

• return ret;
  

• }
• priv->uartclk = clk_get_periph_rate(clkdev, PB2CLK);
• /* initialize serial */
• return pic32_serial_init(priv->base, priv->uartclk,

CONFIG_BAUDRATE); +}

+static const struct dm_serial_ops pic32_uart_ops = {

• .putc = pic32_uart_putc,
• .pending = pic32_uart_pending,
• .getc = pic32_uart_getc,
• .setbrg = pic32_uart_setbrg,

+};

+static const struct udevice_id pic32_uart_ids[] = {

• { .compatible = "microchip,pic32mzda-uart" },
• {}

+};

+U_BOOT_DRIVER(pic32_serial) = {

• .name = "pic32-uart",
• .id = UCLASS_SERIAL,
• .of_match = pic32_uart_ids,
• .probe = pic32_uart_probe,
• .ops = &pic32_uart_ops,
• .flags = DM_FLAG_PRE_RELOC,
• .priv_auto_alloc_size = sizeof(struct pic32_uart_priv),

+};

+#ifdef CONFIG_DEBUG_UART_PIC32 +#include <debug_uart.h>

+static inline void _debug_uart_init(void) +{

• void __iomem *base = (void __iomem

*)CONFIG_DEBUG_UART_BASE;

• pic32_serial_init(base, CONFIG_DEBUG_UART_CLOCK,

CONFIG_BAUDRATE); +}

+static inline void _debug_uart_putc(int ch) +{

• writel(ch, CONFIG_DEBUG_UART_BASE + U_TXR);

+}

+DEBUG_UART_FUNCS +#endif

On 01/14/2016 01:39 AM, Simon Glass wrote:

Hi Purna,

On 12 January 2016 at 03:18, Purna Chandra Mandal purna.mandal@microchip.com wrote:

...

From: Paul Thacker paul.thacker@microchip.com

This adds PIC32 UART controller support based on driver model.

Signed-off-by: Paul Thacker paul.thacker@microchip.com Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com

---

Changes in v3:

• remove ofdata_to_platdata, and replace platdata with priv
• remove special handling of '\r' as being handled by serial-uclass
• remove loop to wait for space in tx buffer before pumping char

Changes in v2:

• fix missing/corrupted chars during baud rate change
• remove loop until any char is avaialbale in getc()

.../serial/microchip,pic32-uart.txt | 5 + drivers/serial/Kconfig | 13 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_pic32.c | 199 +++++++++++++++++++++ 4 files changed, 218 insertions(+) create mode 100644 doc/device-tree-bindings/serial/microchip,pic32-uart.txt create mode 100644 drivers/serial/serial_pic32.c

Reviewed-by: Simon Glass sjg@chromium.org

One nit/question below.

...

diff --git a/doc/device-tree-bindings/serial/microchip,pic32-uart.txt b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt new file mode 100644 index 0000000..f00e215 --- /dev/null +++ b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt @@ -0,0 +1,5 @@ +* Microchip PIC32 serial UART

+Required properties: +- compatible: must be "microchip,pic32mzda-uart". +- reg: exactly one register range. diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 1fc287e..9763ea1 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -107,6 +107,14 @@ config DEBUG_UART_APBUART will need to provide parameters to make this work. The driver will be available until the real driver model serial is running.

+config DEBUG_UART_PIC32

•   bool "Microchip PIC32"
  

•   help
  

•     Select this to enable a debug UART using the serial_pic32 driver. You
  

•     will need to provide parameters to make this work. The driver will
  

•     be available until the real driver model serial is running.
  

endchoice

config DEBUG_UART_BASE @@ -223,4 +231,9 @@ config UNIPHIER_SERIAL If you have a UniPhier based board and want to use the on-chip serial ports, say Y to this option. If unsure, say N.

+config PIC32_SERIAL

•   bool "Support for Microchip PIC32 on-chip UART"
  

•   help
  

•     Support for the UART found on Microchip PIC32 SoC's.
  

endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dd87147..57cd38b 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o +obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o

ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c new file mode 100644 index 0000000..ee9d056 --- /dev/null +++ b/drivers/serial/serial_pic32.c @@ -0,0 +1,199 @@ +/*

• • (c) 2015 Paul Thacker paul.thacker@microchip.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <serial.h> +#include <wait_bit.h> +#include <mach/pic32.h> +#include <dt-bindings/clock/microchip,clock.h>

+DECLARE_GLOBAL_DATA_PTR;

+/* UART Control Registers */ +#define U_MOD 0x00 +#define U_MODCLR (U_MOD + _CLR_OFFSET) +#define U_MODSET (U_MOD + _SET_OFFSET) +#define U_STA 0x10 +#define U_STACLR (U_STA + _CLR_OFFSET) +#define U_STASET (U_STA + _SET_OFFSET) +#define U_TXR 0x20 +#define U_RXR 0x30 +#define U_BRG 0x40

+/* U_MOD bits */ +#define UART_ENABLE BIT(15)

+/* U_STA bits */ +#define UART_RX_ENABLE BIT(12) +#define UART_TX_BRK BIT(11) +#define UART_TX_ENABLE BIT(10) +#define UART_TX_FULL BIT(9) +#define UART_TX_EMPTY BIT(8) +#define UART_RX_OERR BIT(1) +#define UART_RX_DATA_AVAIL BIT(0)

+struct pic32_uart_priv {

•   void __iomem *base;
  

•   ulong uartclk;
  

+};

+/*

• • Initialize the serial port with the given baudrate.
• • The settings are always 8 data bits, no parity, 1 stop bit, no start bits.
• */

+static int pic32_serial_init(void __iomem *base, ulong clk, u32 baudrate) +{

•   u32 div = DIV_ROUND_CLOSEST(clk, baudrate * 16);
  

•   /* wait for TX FIFO to empty */
  

•   wait_for_bit(__func__, base + U_STA, UART_TX_EMPTY,
  

•                true, CONFIG_SYS_HZ, false);
  

•   /* send break */
  

•   writel(UART_TX_BRK, base + U_STASET);
  

•   /* disable and clear mode */
  

•   writel(0, base + U_MOD);
  

•   writel(0, base + U_STA);
  

•   /* set baud rate generator */
  

•   writel(div - 1, base + U_BRG);
  

•   /* enable the UART for TX and RX */
  

•   writel(UART_TX_ENABLE | UART_RX_ENABLE, base + U_STASET);
  

•   /* enable the UART */
  

•   writel(UART_ENABLE, base + U_MODSET);
  

•   return 0;
  

+}

+/* Check number of characters ready in RX Fifo */

But what does it return? The number of available characters? Please make the comment more specific.

Good catch. In PIC32 there is no way to know number of outstanding/pending chars in rx-fifo. Only it can be known whether there is any. I'll update the comment accordingly. Specifically bitwise ANDing with 'UART_RX_DATA_AVAIL' (=BIT(0)) makes result always binary (0, or 1).

...

+static int pic32_uart_pending_input(void __iomem *base) +{

•   /* check if rx buffer overrun error has occurred */
  

•   if (readl(base + U_STA) & UART_RX_OERR) {
  

•           readl(base + U_RXR);
  

•           /* clear OERR to keep receiving */
  

•           writel(UART_RX_OERR, base + U_STACLR);
  

•   }
  

•   return readl(base + U_STA) & UART_RX_DATA_AVAIL;
  

+}

+static int pic32_uart_pending(struct udevice *dev, bool input) +{

•   struct pic32_uart_priv *priv = dev_get_priv(dev);
  

•   if (input)
  

•           return pic32_uart_pending_input(priv->base);
  

Should return the number of characters available. Should this be?

           return pic32_uart_pending_input(priv->base) ? 1 : 0;

Of course I don't quite know what pic32_uart_pending_input() does, so I could be wrong.

It returns in binary (0 or 1) due to short-coming in controller.

...

•   return !(readl(priv->base + U_STA) & UART_TX_EMPTY);
  

+}

+static int pic32_uart_setbrg(struct udevice *dev, int baudrate) +{

•   struct pic32_uart_priv *priv = dev_get_priv(dev);
  

•   return pic32_serial_init(priv->base, priv->uartclk, baudrate);
  

+}

+static int pic32_uart_putc(struct udevice *dev, const char ch) +{

•   struct pic32_uart_priv *priv = dev_get_priv(dev);
  

•   /* Check if Tx FIFO is full */
  

•   if (readl(priv->base + U_STA) & UART_TX_FULL)
  

•           return -EAGAIN;
  

•   /* pump the char to tx buffer */
  

•   writel(ch, priv->base + U_TXR);
  

•   return 0;
  

+}

+static int pic32_uart_getc(struct udevice *dev) +{

•   struct pic32_uart_priv *priv = dev_get_priv(dev);
  

•   /* return error if RX fifo is empty */
  

•   if (!pic32_uart_pending_input(priv->base))
  

•           return -EAGAIN;
  

•   /* read the character from rx buffer */
  

•   return readl(priv->base + U_RXR) & 0xff;
  

+}

+static int pic32_uart_probe(struct udevice *dev) +{

•   struct pic32_uart_priv *priv = dev_get_priv(dev);
  

•   struct udevice *clkdev;
  

•   fdt_addr_t addr;
  

•   fdt_size_t size;
  

•   int ret;
  

•   /* get address */
  

•   addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
  

•   if (addr == FDT_ADDR_T_NONE)
  

•           return -EINVAL;
  

•   priv->base = ioremap(addr, size);
  

•   if (!priv->base)
  

•           return -EINVAL;
  

•   /* get clock rate */
  

•   ret = uclass_get_device(UCLASS_CLK, 0, &clkdev);
  

•   if (ret) {
  

•           printf("clk class not found, %d\n", ret);
  

•           return ret;
  

•   }
  

•   priv->uartclk = clk_get_periph_rate(clkdev, PB2CLK);
  

•   /* initialize serial */
  

•   return pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
  

+}

+static const struct dm_serial_ops pic32_uart_ops = {

•   .putc           = pic32_uart_putc,
  

•   .pending        = pic32_uart_pending,
  

•   .getc           = pic32_uart_getc,
  

•   .setbrg         = pic32_uart_setbrg,
  

+};

+static const struct udevice_id pic32_uart_ids[] = {

•   { .compatible = "microchip,pic32mzda-uart" },
  

•   {}
  

+};

+U_BOOT_DRIVER(pic32_serial) = {

•   .name           = "pic32-uart",
  

•   .id             = UCLASS_SERIAL,
  

•   .of_match       = pic32_uart_ids,
  

•   .probe          = pic32_uart_probe,
  

•   .ops            = &pic32_uart_ops,
  

•   .flags          = DM_FLAG_PRE_RELOC,
  

•   .priv_auto_alloc_size = sizeof(struct pic32_uart_priv),
  

+};

+#ifdef CONFIG_DEBUG_UART_PIC32 +#include <debug_uart.h>

+static inline void _debug_uart_init(void) +{

•   void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
  

•   pic32_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
  

+}

+static inline void _debug_uart_putc(int ch) +{

•   writel(ch, CONFIG_DEBUG_UART_BASE + U_TXR);
  

+}

+DEBUG_UART_FUNCS

+#endif

1.8.3.1

Regards, Simon

Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:

This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker paul.thacker@microchip.com Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com

Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com

---

Changes in v3:

• annotating fixed table with const
• fix camel-case in ddr2 timing parameters
• fix cmd index parameter of host_load_cmd().
• fix compilation warning

Changes in v2:

• move ddr2 initialization from board/microchip/ to

drivers/ddr/microchip

arch/mips/mach-pic32/include/mach/ddr.h | 32 ++++ drivers/Makefile | 1 + drivers/ddr/microchip/Makefile | 6 + drivers/ddr/microchip/ddr2.c | 278 ++++++++++++++++++++++++++++++++ drivers/ddr/microchip/ddr2_regs.h | 148 +++++++++++++++++ drivers/ddr/microchip/ddr2_timing.h | 65 ++++++++ 6 files changed, 530 insertions(+) create mode 100644 arch/mips/mach-pic32/include/mach/ddr.h create mode 100644 drivers/ddr/microchip/Makefile create mode 100644 drivers/ddr/microchip/ddr2.c create mode 100644 drivers/ddr/microchip/ddr2_regs.h create mode 100644 drivers/ddr/microchip/ddr2_timing.h

diff --git a/arch/mips/mach-pic32/include/mach/ddr.h b/arch/mips/mach -pic32/include/mach/ddr.h new file mode 100644 index 0000000..00abfa3 --- /dev/null +++ b/arch/mips/mach-pic32/include/mach/ddr.h @@ -0,0 +1,32 @@ +/*

• • (c) 2015 Purna Chandra Mandal purna.mandal@microchip.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __MICROCHIP_PIC32_DDR_H +#define __MICROCHIP_PIC32_DDR_H

+/* called by initdram() function */ +void ddr2_phy_init(void); +void ddr2_ctrl_init(void); +phys_size_t ddr2_calculate_size(void);

+/* Maximum number of agents */ +#define NUM_AGENTS 5

+/* Board can provide agent specific parameters for arbitration by

• • filling struct ddr2_arbiter_params for all the agents and
• • implementing board_get_ddr_arbiter_params() to return the filled
• • structure.
• */

+struct ddr2_arbiter_params {

• u32 min_limit; /* min bursts to execute per

arbitration */

• u32 req_period; /* request period threshold for accepted

cmds */

• u32 min_cmd_acpt; /* min number of accepted cmds */

+};

+const struct ddr2_arbiter_params *board_get_ddr_arbiter_params(void);

+#endif /* __MICROCHIP_PIC32_DDR_H */ diff --git a/drivers/Makefile b/drivers/Makefile index c9031f2..0ab54d9 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -68,4 +68,5 @@ obj-y += soc/ obj-$(CONFIG_REMOTEPROC) += remoteproc/ obj-y += thermal/

+obj-$(CONFIG_MACH_PIC32) += ddr/microchip/ endif diff --git a/drivers/ddr/microchip/Makefile b/drivers/ddr/microchip/Makefile new file mode 100644 index 0000000..305c48b --- /dev/null +++ b/drivers/ddr/microchip/Makefile @@ -0,0 +1,6 @@ +# +# Copyright (C) 2015 Microchip Technology Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-$(CONFIG_MACH_PIC32) += ddr2.o diff --git a/drivers/ddr/microchip/ddr2.c b/drivers/ddr/microchip/ddr2.c new file mode 100644 index 0000000..6056418 --- /dev/null +++ b/drivers/ddr/microchip/ddr2.c @@ -0,0 +1,278 @@ +/*

• • (c) 2015 Paul Thacker paul.thacker@microchip.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <wait_bit.h> +#include <linux/kernel.h> +#include <linux/bitops.h> +#include <mach/pic32.h> +#include <mach/ddr.h>

+#include "ddr2_regs.h" +#include "ddr2_timing.h"

+/* init DDR2 Phy */ +void ddr2_phy_init(void) +{

• struct ddr2_phy_regs *ddr2_phy;
• u32 pad_ctl;
• ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy));
• /* PHY_DLL_RECALIB */
• writel(DELAY_START_VAL(3) | DISABLE_RECALIB(0) |

•       RECALIB_CNT(0x10), &ddr2_phy->dll_recalib);
  

• /* PHY_PAD_CTRL */
• pad_ctl = ODT_SEL | ODT_EN | DRIVE_SEL(0) |

•   ODT_PULLDOWN(2) | ODT_PULLUP(3) |
  

•   EXTRA_OEN_CLK(0) | NOEXT_DLL |
  

•   DLR_DFT_WRCMD | HALF_RATE |
  

•   DRVSTR_PFET(0xe) | DRVSTR_NFET(0xe) |
  

•   RCVR_EN | PREAMBLE_DLY(2);
  

• writel(pad_ctl, &ddr2_phy->pad_ctrl);
• /* SCL_CONFIG_0 */
• writel(SCL_BURST8 | SCL_DDR_CONNECTED | SCL_RCAS_LAT(RL) |

•       SCL_ODTCSWW, &ddr2_phy->scl_config_1);
  

• /* SCL_CONFIG_1 */
• writel(SCL_CSEN | SCL_WCAS_LAT(WL), &ddr2_phy

->scl_config_2);

• /* SCL_LAT */
• writel(SCL_CAPCLKDLY(3) | SCL_DDRCLKDLY(4), &ddr2_phy

->scl_latency); +}

+/* start phy self calibration logic */ +static int ddr2_phy_calib_start(void) +{

• struct ddr2_phy_regs *ddr2_phy;
• ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy));
• /* DDR Phy SCL Start */
• writel(SCL_START | SCL_EN, &ddr2_phy->scl_start);
• /* Wait for SCL for data byte to pass */
• return wait_for_bit(__func__, &ddr2_phy->scl_start,

SCL_LUBPASS,

• 	    true, CONFIG_SYS_HZ, false);
  

+}

+/* DDR2 Controller initialization */

+/* Target Agent Arbiter */ +static void ddr_set_arbiter(struct ddr2_ctrl_regs *ctrl,

• 	    const struct ddr2_arbiter_params *const
  

param) +{

• int i;
• for (i = 0; i < NUM_AGENTS; i++) {

• /* set min burst size */
  

• writel(i * MIN_LIM_WIDTH, &ctrl->tsel);
  

• writel(param->min_limit, &ctrl->minlim);
  

• /* set request period (4 * req_period clocks) */
  

• writel(i * RQST_PERIOD_WIDTH, &ctrl->tsel);
  

• writel(param->req_period, &ctrl->reqprd);
  

• /* set number of burst accepted */
  

• writel(i * MIN_CMDACPT_WIDTH, &ctrl->tsel);
  

• writel(param->min_cmd_acpt, &ctrl->mincmd);
  

• }

+}

+const struct ddr2_arbiter_params *__weak board_get_ddr_arbiter_params(void) +{

• /* default arbiter parameters */
• static const struct ddr2_arbiter_params arb_params[] = {

• { .min_limit = 0x1f, .req_period = 0xff,
  

.min_cmd_acpt = 0x04,},

• { .min_limit = 0x1f, .req_period = 0xff,
  

.min_cmd_acpt = 0x10,},

• { .min_limit = 0x1f, .req_period = 0xff,
  

.min_cmd_acpt = 0x10,},

• { .min_limit = 0x04, .req_period = 0xff,
  

.min_cmd_acpt = 0x04,},

• { .min_limit = 0x04, .req_period = 0xff,
  

.min_cmd_acpt = 0x04,},

• };
• return &arb_params[0];

+}

+static void host_load_cmd(struct ddr2_ctrl_regs *ctrl, u32 cmd_idx,

• 	  u32 hostcmd2, u32 hostcmd1, u32 delay)
  

+{

• u32 hc_delay;
• hc_delay = max_t(u32, DIV_ROUND_UP(delay, T_CK), 2) - 2;
• writel(hostcmd1, &ctrl->cmd10[cmd_idx]);
• writel((hostcmd2 & 0x7ff) | (hc_delay << 11), &ctrl

->cmd20[cmd_idx]); +}

+/* init DDR2 Controller */ +void ddr2_ctrl_init(void) +{

• u32 wr2prech, rd2prech, wr2rd, wr2rd_cs;
• u32 ras2ras, ras2cas, prech2ras, temp;
• const struct ddr2_arbiter_params *arb_params;
• struct ddr2_ctrl_regs *ctrl;
• ctrl = ioremap(PIC32_DDR2C_BASE, sizeof(*ctrl));
• /* PIC32 DDR2 controller always work in HALF_RATE */
• writel(HALF_RATE_MODE, &ctrl->memwidth);
• /* Set arbiter configuration per target */
• arb_params = board_get_ddr_arbiter_params();
• ddr_set_arbiter(ctrl, arb_params);
• /* Address Configuration, model {CS, ROW, BA, COL} */
• writel((ROW_ADDR_RSHIFT | (BA_RSHFT << 8) | (CS_ADDR_RSHIFT

<< 16) |

•       (COL_HI_RSHFT << 24) | (SB_PRI << 29)  |
  

•       (EN_AUTO_PRECH << 30)), &ctrl->memcfg0);
  

• writel(ROW_ADDR_MASK, &ctrl->memcfg1);
• writel(COL_HI_MASK, &ctrl->memcfg2);
• writel(COL_LO_MASK, &ctrl->memcfg3);
• writel(BA_MASK | (CS_ADDR_MASK << 8), &ctrl->memcfg4);
• /* Refresh Config */
• writel(REFCNT_CLK(DIV_ROUND_UP(T_RFI, T_CK_CTRL) - 2) |

•       REFDLY_CLK(DIV_ROUND_UP(T_RFC_MIN, T_CK_CTRL) - 2) |
  

•       MAX_PEND_REF(7),
  

•       &ctrl->refcfg);
  

• /* Power Config */
• writel(ECC_EN(0) | ERR_CORR_EN(0) | EN_AUTO_PWR_DN(0) |

•       EN_AUTO_SELF_REF(3) | PWR_DN_DLY(8) |
  

•       SELF_REF_DLY(17) | PRECH_PWR_DN_ONLY(0),
  

•       &ctrl->pwrcfg);
  

• /* Delay Config */
• wr2rd = max_t(u32, DIV_ROUND_UP(T_WTR, T_CK_CTRL),

•       DIV_ROUND_UP(T_WTR_TCK, 2)) + WL + BL;
  

• wr2rd_cs = max_t(u32, wr2rd - 1, 3);
• wr2prech = DIV_ROUND_UP(T_WR, T_CK_CTRL) + WL + BL;
• rd2prech = max_t(u32, DIV_ROUND_UP(T_RTP, T_CK_CTRL),

• 	 DIV_ROUND_UP(T_RTP_TCK, 2)) + BL - 2;
  

• ras2ras = max_t(u32, DIV_ROUND_UP(T_RRD, T_CK_CTRL),

• 	DIV_ROUND_UP(T_RRD_TCK, 2)) - 1;
  

• ras2cas = DIV_ROUND_UP(T_RCD, T_CK_CTRL) - 1;
• prech2ras = DIV_ROUND_UP(T_RP, T_CK_CTRL) - 1;
• writel(((wr2rd & 0x0f) |

•       ((wr2rd_cs & 0x0f) << 4) |
  

•       ((BL - 1) << 8) |
  

•       (BL << 12) |
  

•       ((BL - 1) << 16) |
  

•       ((BL - 1) << 20) |
  

•       ((BL + 2) << 24) |
  

•       ((RL - WL + 3) << 28)), &ctrl->dlycfg0);
  

• writel(((T_CKE_TCK - 1) |

•       (((DIV_ROUND_UP(T_DLLK, 2) - 2) & 0xff) << 8) |
  

•       ((T_CKE_TCK - 1) << 16) |
  

•       ((max_t(u32, T_XP_TCK, T_CKE_TCK) - 1) << 20) |
  

•       ((wr2prech >> 4) << 26) |
  

•       ((wr2rd >> 4) << 27) |
  

•       ((wr2rd_cs >> 4) << 28) |
  

•       (((RL + 5) >> 4) << 29) |
  

•       ((DIV_ROUND_UP(T_DLLK, 2) >> 8) << 30)), &ctrl
  

->dlycfg1);

• writel((DIV_ROUND_UP(T_RP, T_CK_CTRL) |

•       (rd2prech << 8) |
  

•       ((wr2prech & 0x0f) << 12) |
  

•       (ras2ras << 16) |
  

•       (ras2cas << 20) |
  

•       (prech2ras << 24) |
  

•       ((RL + 3) << 28)), &ctrl->dlycfg2);
  

• writel(((DIV_ROUND_UP(T_RAS_MIN, T_CK_CTRL) - 1) |

•       ((DIV_ROUND_UP(T_RC, T_CK_CTRL) - 1) << 8) |
  

•       ((DIV_ROUND_UP(T_FAW, T_CK_CTRL) - 1) << 16)),
  

•       &ctrl->dlycfg3);
  

• /* ODT Config */
• writel(0x0, &ctrl->odtcfg);
• writel(BIT(16), &ctrl->odtencfg);
• writel(ODTRDLY(RL - 3) | ODTWDLY(WL - 3) | ODTRLEN(2) |

ODTWLEN(3),

•       &ctrl->odtcfg);
  

• /* Transfer Configuration */
• writel(NXTDATRQDLY(2) | NXDATAVDLY(4) | RDATENDLY(2) |

•       MAX_BURST(3) | (7 << 28) | BIG_ENDIAN(0),
  

•       &ctrl->xfercfg);
  

• /* DRAM Initialization */
• /* CKE high after reset and wait 400 nsec */
• host_load_cmd(ctrl, 0, 0, IDLE_NOP, 400000);
• /* issue precharge all command */
• host_load_cmd(ctrl, 1, 0x04, PRECH_ALL_CMD, T_RP + T_CK);
• /* initialize EMR2 */
• host_load_cmd(ctrl, 2, 0x200, LOAD_MODE_CMD, T_MRD_TCK *

T_CK);

• /* initialize EMR3 */
• host_load_cmd(ctrl, 3, 0x300, LOAD_MODE_CMD, T_MRD_TCK *

T_CK);

• /*

• * RDQS disable, DQSB enable, OCD exit, 150 ohm termination,
  

• * AL=0, DLL enable
  

• */
  

• host_load_cmd(ctrl, 4, 0x100,

•       LOAD_MODE_CMD | (0x40 << 24), T_MRD_TCK *
  

T_CK);

• /*

• * PD fast exit, WR REC = T_WR in clocks -1,
  

• * DLL reset, CAS = RL, burst = 4
  

• */
  

• temp = ((DIV_ROUND_UP(T_WR, T_CK) - 1) << 1) | 1;
• host_load_cmd(ctrl, 5, temp, LOAD_MODE_CMD | (RL << 28) | (2

<< 24),

•       T_MRD_TCK * T_CK);
  

• /* issue precharge all command */
• host_load_cmd(ctrl, 6, 4, PRECH_ALL_CMD, T_RP + T_CK);
• /* issue refresh command */
• host_load_cmd(ctrl, 7, 0, REF_CMD, T_RFC_MIN);
• /* issue refresh command */
• host_load_cmd(ctrl, 8, 0, REF_CMD, T_RFC_MIN);
• /* Mode register programming as before without DLL reset */
• host_load_cmd(ctrl, 9, temp, LOAD_MODE_CMD | (RL << 28) | (3

<< 24),

•       T_MRD_TCK * T_CK);
  

• /* extended mode register same as before with OCD default */
• host_load_cmd(ctrl, 10, 0x103, LOAD_MODE_CMD | (0xc << 24),

•       T_MRD_TCK * T_CK);
  

• /* extended mode register same as before with OCD exit */
• host_load_cmd(ctrl, 11, 0x100, LOAD_MODE_CMD | (0x4 << 28),

•       140 * T_CK);
  

• writel(CMD_VALID | NUMHOSTCMD(11), &ctrl->cmdissue);
• /* start memory initialization */
• writel(INIT_START, &ctrl->memcon);
• /* wait for all host cmds to be transmitted */
• wait_for_bit(__func__, &ctrl->cmdissue, CMD_VALID, false,

•      CONFIG_SYS_HZ, false);
  

• /* inform all cmds issued, ready for normal operation */
• writel(INIT_START | INIT_DONE, &ctrl->memcon);
• /* perform phy caliberation */
• if (ddr2_phy_calib_start())

• printf("ddr2: phy calib failed\n");
  

+}

+phys_size_t ddr2_calculate_size(void) +{

• u32 temp;
• temp = 1 << (COL_BITS + BA_BITS + ROW_BITS);
• /* 16-bit data width between controller and DIMM */
• temp = temp * CS_BITS * (16 / 8);
• return (phys_size_t)temp;

+} diff --git a/drivers/ddr/microchip/ddr2_regs.h b/drivers/ddr/microchip/ddr2_regs.h new file mode 100644 index 0000000..0f4b159 --- /dev/null +++ b/drivers/ddr/microchip/ddr2_regs.h @@ -0,0 +1,148 @@ +/*

• • (c) 2015 Purna Chandra Mandal purna.mandal@microchip.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __MICROCHIP_DDR2_REGS_H +#define __MICROCHIP_DDR2_REGS_H

+#include <linux/bitops.h>

+/* DDR2 Controller */ +struct ddr2_ctrl_regs {

• u32 tsel;
• u32 minlim;
• u32 reqprd;
• u32 mincmd;
• u32 memcon;
• u32 memcfg0;
• u32 memcfg1;
• u32 memcfg2;
• u32 memcfg3;
• u32 memcfg4;
• u32 refcfg;
• u32 pwrcfg;
• u32 dlycfg0;
• u32 dlycfg1;
• u32 dlycfg2;
• u32 dlycfg3;
• u32 odtcfg;
• u32 xfercfg;
• u32 cmdissue;
• u32 odtencfg;
• u32 memwidth;
• u32 unused[11];
• u32 cmd10[16];
• u32 cmd20[16];

+};

+/* Arbiter Config */ +#define MIN_LIM_WIDTH 5 +#define RQST_PERIOD_WIDTH 8 +#define MIN_CMDACPT_WIDTH 8

+/* Refresh Config */ +#define REFCNT_CLK(x) (x) +#define REFDLY_CLK(x) ((x) << 16) +#define MAX_PEND_REF(x) ((x) << 24)

+/* Power Config */ +#define PRECH_PWR_DN_ONLY(x) ((x) << 22) +#define SELF_REF_DLY(x) ((x) << 12) +#define PWR_DN_DLY(x) ((x) << 4) +#define EN_AUTO_SELF_REF(x) ((x) << 3) +#define EN_AUTO_PWR_DN(x) ((x) << 2) +#define ERR_CORR_EN(x) ((x) << 1) +#define ECC_EN(x) (x)

+/* Memory Width */ +#define HALF_RATE_MODE BIT(3)

+/* Delay Config */ +#define ODTWLEN(x) ((x) << 20) +#define ODTRLEN(x) ((x) << 16) +#define ODTWDLY(x) ((x) << 12) +#define ODTRDLY(x) ((x) << 8)

+/* Xfer Config */ +#define BIG_ENDIAN(x) ((x) << 31) +#define MAX_BURST(x) ((x) << 24) +#define RDATENDLY(x) ((x) << 16) +#define NXDATAVDLY(x) ((x) << 4) +#define NXTDATRQDLY(x) ((x) << 0)

+/* Host Commands */ +#define IDLE_NOP 0x00ffffff +#define PRECH_ALL_CMD 0x00fff401 +#define REF_CMD 0x00fff801 +#define LOAD_MODE_CMD 0x00fff001 +#define CKE_LOW 0x00ffeffe

+#define NUM_HOST_CMDS 12

+/* Host CMD Issue */ +#define CMD_VALID BIT(4) +#define NUMHOSTCMD(x) (x)

+/* Memory Control */ +#define INIT_DONE BIT(1) +#define INIT_START BIT(0)

+/* Address Control */ +#define EN_AUTO_PRECH 0 +#define SB_PRI 1

+/* DDR2 Phy Register */ +struct ddr2_phy_regs {

• u32 scl_start;
• u32 unused1[2];
• u32 scl_latency;
• u32 unused2[2];
• u32 scl_config_1;
• u32 scl_config_2;
• u32 pad_ctrl;
• u32 dll_recalib;

+};

+/* PHY PAD CONTROL */ +#define ODT_SEL BIT(0) +#define ODT_EN BIT(1) +#define DRIVE_SEL(x) ((x) << 2) +#define ODT_PULLDOWN(x) ((x) << 4) +#define ODT_PULLUP(x) ((x) << 6) +#define EXTRA_OEN_CLK(x) ((x) << 8) +#define NOEXT_DLL BIT(9) +#define DLR_DFT_WRCMD BIT(13) +#define HALF_RATE BIT(14) +#define DRVSTR_PFET(x) ((x) << 16) +#define DRVSTR_NFET(x) ((x) << 20) +#define RCVR_EN BIT(28) +#define PREAMBLE_DLY(x) ((x) << 29)

+/* PHY DLL RECALIBRATE */ +#define RECALIB_CNT(x) ((x) << 8) +#define DISABLE_RECALIB(x) ((x) << 26) +#define DELAY_START_VAL(x) ((x) << 28)

+/* PHY SCL CONFIG1 */ +#define SCL_BURST8 BIT(0) +#define SCL_DDR_CONNECTED BIT(1) +#define SCL_RCAS_LAT(x) ((x) << 4) +#define SCL_ODTCSWW BIT(24)

+/* PHY SCL CONFIG2 */ +#define SCL_CSEN BIT(0) +#define SCL_WCAS_LAT(x) ((x) << 8)

+/* PHY SCL Latency */ +#define SCL_CAPCLKDLY(x) ((x) << 0) +#define SCL_DDRCLKDLY(x) ((x) << 4)

+/* PHY SCL START */ +#define SCL_START BIT(28) +#define SCL_EN BIT(26) +#define SCL_LUBPASS (BIT(1) | BIT(0))

+#endif /* __MICROCHIP_DDR2_REGS_H */ diff --git a/drivers/ddr/microchip/ddr2_timing.h b/drivers/ddr/microchip/ddr2_timing.h new file mode 100644 index 0000000..5895f9d --- /dev/null +++ b/drivers/ddr/microchip/ddr2_timing.h @@ -0,0 +1,65 @@ +/*

• • (c) 2015 Purna Chandra Mandal purna.mandal@microchip.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __MICROCHIP_DDR2_TIMING_H +#define __MICROCHIP_DDR2_TIMING_H

+/* MPLL freq is 400MHz */ +#define T_CK 2500 /* 2500 psec */ +#define T_CK_CTRL (T_CK * 2)

+/* Burst length in cycles */ +#define BL 2 +/* default CAS latency for all speed grades */ +#define RL 5 +/* default write latency for all speed grades = CL-1 */ +#define WL 4

+/* From Micron MT47H64M16HR-3 data sheet */ +#define T_RFC_MIN 127500 /* psec */ +#define T_WR 15000 /* psec */ +#define T_RP 12500 /* psec */ +#define T_RCD 12500 /* psec */ +#define T_RRD 7500 /* psec */ +/* T_RRD_TCK is minimum of 2 clk periods, regardless of freq */ +#define T_RRD_TCK 2 +#define T_WTR 7500 /* psec */ +/* T_WTR_TCK is minimum of 2 clk periods, regardless of freq */ +#define T_WTR_TCK 2 +#define T_RTP 7500 /* psec */ +#define T_RTP_TCK (BL / 2) +#define T_XP_TCK 2 /* clocks */ +#define T_CKE_TCK 3 /* clocks */ +#define T_XSNR (T_RFC_MIN + 10000) /* psec */ +#define T_DLLK 200 /* clocks */ +#define T_RAS_MIN 45000 /* psec */ +#define T_RC 57500 /* psec */ +#define T_FAW 35000 /* psec */ +#define T_MRD_TCK 2 /* clocks */ +#define T_RFI 7800000 /* psec */

+/* DDR Addressing */ +#define COL_BITS 10 +#define BA_BITS 3 +#define ROW_BITS 13 +#define CS_BITS 1

+/* DDR Addressing scheme: {CS, ROW, BA, COL} */ +#define COL_HI_RSHFT 0 +#define COL_HI_MASK 0 +#define COL_LO_MASK ((1 << COL_BITS) - 1)

+#define BA_RSHFT COL_BITS +#define BA_MASK ((1 << BA_BITS) - 1)

+#define ROW_ADDR_RSHIFT (BA_RSHFT + BA_BITS) +#define ROW_ADDR_MASK ((1 << ROW_BITS) - 1)

+#define CS_ADDR_RSHIFT 0 +#define CS_ADDR_MASK 0

+#endif /* __MICROCHIP_DDR2_TIMING_H */

Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:

Add Microchip PIC32MZ[DA] SoC family support.

Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com

---

Changes in v3:

• drop forcing CONFIG_MIPS_BOOT_* selection in mach-pic32/Kconfig
• indent assembly instructions in delay slot
• made GPIO-nodes child of pinctrl-node in devicetree
• replace pic32_ioremap() with ioremap()

Changes in v2:

• drop board_early_init_f
• use macro LEAF(), END() for lowlevel_init assembly
• move initialization of board_init_f() argument to common start.S
• move initdram() from board/microchip/ to mach-pic32/cpu.c
• remove MIPS virtual address in favor physical one in dts file

arch/mips/dts/pic32mzda.dtsi | 153 ++++++++++++++++++++++++++++++ arch/mips/mach-pic32/Kconfig | 20 +++- arch/mips/mach-pic32/Makefile | 2 +- arch/mips/mach-pic32/cpu.c | 147 ++++++++++++++++++++++++++++ arch/mips/mach-pic32/include/mach/pic32.h | 3 + arch/mips/mach-pic32/lowlevel_init.S | 27 ++++++ arch/mips/mach-pic32/reset.c | 36 +++++++ 7 files changed, 386 insertions(+), 2 deletions(-) create mode 100644 arch/mips/dts/pic32mzda.dtsi create mode 100644 arch/mips/mach-pic32/lowlevel_init.S create mode 100644 arch/mips/mach-pic32/reset.c

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi new file mode 100644 index 0000000..fe8b13a --- /dev/null +++ b/arch/mips/dts/pic32mzda.dtsi @@ -0,0 +1,153 @@ +/*

• • Copyright 2015 Microchip Technology, Inc.
• • Purna Chandra Mandal, purna.mandal@microchip.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/microchip,clock.h> +#include <dt-bindings/gpio/gpio.h> +#include "skeleton.dtsi"

+/ {

• compatible = "microchip,pic32mzda", "microchip,pic32mz";
• aliases {

• gpio0 = &gpioA;
  

• gpio1 = &gpioB;
  

• gpio2 = &gpioC;
  

• gpio3 = &gpioD;
  

• gpio4 = &gpioE;
  

• gpio5 = &gpioF;
  

• gpio6 = &gpioG;
  

• gpio7 = &gpioH;
  

• gpio8 = &gpioJ;
  

• gpio9 = &gpioK;
  

• };
• cpus {

• cpu@0 {
  

• 	compatible = "mips,mips14kc";
  

• };
  

• };
• clock: clk@1f801200 {

• compatible = "microchip,pic32mzda_clk";
  

• reg = <0x1f801200 0x1000>;
  

• clock-cells = <1>;
  

• };
• uart1: serial@1f822000 {

• compatible = "microchip,pic32mzda-uart";
  

• reg = <0x1f822000 0x50>;
  

• interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
  

• status = "disabled";
  

• clocks = <&clock PB2CLK>;
  

• };
• uart2: serial@1f822200 {

• compatible = "microchip,pic32mzda-uart";
  

• reg = <0x1f822200 0x50>;
  

• interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
  

• clocks = <&clock PB2CLK>;
  

• status = "disabled";
  

• };
• uart6: serial@1f822a00 {

• compatible = "microchip,pic32mzda-uart";
  

• reg = <0x1f822a00 0x50>;
  

• interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
  

• clocks = <&clock PB2CLK>;
  

• status = "disabled";
  

• };
• evic: interrupt-controller@1f810000 {

• compatible = "microchip,pic32mzda-evic";
  

• interrupt-controller;
  

• #interrupt-cells = <2>;
  

• reg = <0x1f810000 0x1000>;
  

• };
• pinctrl: pinctrl@1f801400 {

• compatible = "microchip,pic32mzda-pinctrl";
  

• reg = <0x1f801400 0x100>, /* in  */
  

•       <0x1f801500 0x200>, /* out */
  

•       <0x1f860000 0xa00>; /* port */
  

• reg-names = "ppsin","ppsout","port";
  

• status = "disabled";
  

• ranges = <0 0x1f860000 0xa00>;
  

• #address-cells = <1>;
  

• #size-cells = <1>;
  

• gpioA: gpio0@0 {
  

• 	compatible = "microchip,pic32mzda-gpio";
  

• 	reg = <0x000 0x48>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• };
  

• gpioB: gpio1@100 {
  

• 	compatible = "microchip,pic32mzda-gpio";
  

• 	reg = <0x100 0x48>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• };
  

• gpioC: gpio2@200 {
  

• 	compatible = "microchip,pic32mzda-gpio";
  

• 	reg = <0x200 0x48>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• };
  

• gpioD: gpio3@300 {
  

• 	compatible = "microchip,pic32mzda-gpio";
  

• 	reg = <0x300 0x48>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• };
  

• gpioE: gpio4@400 {
  

• 	compatible = "microchip,pic32mzda-gpio";
  

• 	reg = <0x400 0x48>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• };
  

• gpioF: gpio5@500 {
  

• 	compatible = "microchip,pic32mzda-gpio";
  

• 	reg = <0x500 0x48>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• };
  

• gpioG: gpio6@600 {
  

• 	compatible = "microchip,pic32mzda-gpio";
  

• 	reg = <0x600 0x48>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• };
  

• gpioH: gpio7@700 {
  

• 	compatible = "microchip,pic32mzda-gpio";
  

• 	reg = <0x700 0x48>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• };
  

• gpioJ: gpio8@800 {
  

• 	compatible = "microchip,pic32mzda-gpio";
  

• 	reg = <0x800 0x48>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• };
  

• gpioK: gpio9@900 {
  

• 	compatible = "microchip,pic32mzda-gpio";
  

• 	reg = <0x900 0x48>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• };
  

• };

+}; diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach -pic32/Kconfig index c1cc5e3..74be9fb 100644 --- a/arch/mips/mach-pic32/Kconfig +++ b/arch/mips/mach-pic32/Kconfig @@ -2,6 +2,24 @@ menu "Microchip PIC32 platforms" depends on MACH_PIC32

config SYS_SOC

• default "none"

• default "pic32mzda" if SOC_PIC32MZDA

+choice

• prompt "PIC32 SoC select"

+config SOC_PIC32MZDA

• bool "Microchip PIC32MZ[DA] family"
• select SUPPORTS_LITTLE_ENDIAN
• select SUPPORTS_CPU_MIPS32_R1
• select SUPPORTS_CPU_MIPS32_R2
• select MIPS_L1_CACHE_SHIFT_4
• select SYS_MIPS_CACHE_INIT_RAM_LOAD