[U-Boot] [Patch 5/8 Part1/3] add at91 SoC access with c structures
* insert AT91 SoC access using c-stuctures
Signed-off-by: Jens Scharsig js_at_ng@scharsoft.de --- board/atmel/at91sam9263ek/at91sam9263ek.c | 146 +++++++++++++------------- board/atmel/at91sam9263ek/led.c | 9 +- cpu/arm926ejs/at91/at91cap9_devices.c | 88 ++++++++------- cpu/arm926ejs/at91/at91sam9261_devices.c | 48 +++++---- cpu/arm926ejs/at91/at91sam9263_devices.c | 138 +++++++++++++----------- cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 84 ++++++++------- cpu/arm926ejs/at91/at91sam9rl_devices.c | 34 ++++--- cpu/arm926ejs/at91/clock.c | 43 ++++---- cpu/arm926ejs/at91/cpu.c | 4 + cpu/arm926ejs/at91/led.c | 7 ++ cpu/arm926ejs/at91/lowlevel_init.S | 113 +++++++++++--------- cpu/arm926ejs/at91/reset.c | 8 +- cpu/arm926ejs/at91/timer.c | 16 ++- drivers/gpio/Makefile | 1 + drivers/i2c/soft_i2c.c | 11 +- drivers/net/Makefile | 1 + drivers/serial/at91rm9200_usart.c | 8 ++ drivers/serial/atmel_usart.c | 4 + drivers/spi/atmel_dataflash_spi.c | 4 + drivers/usb/host/ohci-at91.c | 5 + drivers/video/bus_vcxk.c | 19 +++- include/asm-arm/arch-at91/at91_pio.h | 107 ++++++++++++++++++ include/asm-arm/arch-at91/at91_pit.h | 15 +++ include/asm-arm/arch-at91/at91_pmc.h | 102 +++++++++++++++++ include/asm-arm/arch-at91/at91_rstc.h | 30 +++++- include/asm-arm/arch-at91/at91_spi.h | 21 ++++ include/asm-arm/arch-at91/at91_wdt.h | 29 +++++ include/asm-arm/arch-at91/at91cap9.h | 9 ++ include/asm-arm/arch-at91/at91sam9260.h | 17 +++ include/asm-arm/arch-at91/at91sam9261.h | 14 +++- include/asm-arm/arch-at91/at91sam9263.h | 22 ++++ include/asm-arm/arch-at91/at91sam9_sdramc.h | 13 +++ include/asm-arm/arch-at91/at91sam9_smc.h | 63 +++++++++++ include/asm-arm/arch-at91/at91sam9g45.h | 15 +++ include/asm-arm/arch-at91/at91sam9rl.h | 14 +++- include/asm-arm/arch-at91/gpio.h | 156 ++------------------------- include/asm-arm/arch-at91/hardware.h | 2 +- include/asm-arm/arch-at91/io.h | 3 + include/i2c.h | 5 + include/netdev.h | 1 + 40 files changed, 936 insertions(+), 493 deletions(-)
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 0b7065b..05764fa 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -25,13 +25,13 @@ #include <common.h> #include <asm/sizes.h> #include <asm/arch/at91sam9263.h> -#include <asm/arch/at91sam9263_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_matrix.h> +#include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> -#include <asm/arch/gpio.h> #include <asm/arch/io.h> #include <asm/arch/hardware.h> #include <lcd.h> @@ -52,33 +52,39 @@ DECLARE_GLOBAL_DATA_PTR; static void at91sam9263ek_nand_hw_init(void) { unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; + at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + /* Enable CS3 */ + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]);
/* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBI0CSA); - at91_sys_write(AT91_MATRIX_EBI0CSA, - csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode);
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | - 1 << AT91SAM9263_ID_PIOCDE); + writel(1 << AT91SAM9263_ID_PIOA | 1 << AT91SAM9263_ID_PIOCDE, + &pmc->pcer);
/* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -91,10 +97,12 @@ static void at91sam9263ek_nand_hw_init(void) #ifdef CONFIG_MACB static void at91sam9263ek_macb_hw_init(void) { - unsigned long rstc; - + unsigned long erstl; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
/* * Disable pull-up on: @@ -104,35 +112,26 @@ static void at91sam9263ek_macb_hw_init(void) * * PHY has internal pull-down */ - writel(pin_to_mask(AT91_PIN_PC25), - pin_to_controller(AT91_PIN_PC0) + PIO_PUDR); - writel(pin_to_mask(AT91_PIN_PE25) | - pin_to_mask(AT91_PIN_PE26), - pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + writel(AT91_PIN_TO_MASK(25), &pio->pioc.pudr); + writel(AT91_PIN_TO_MASK(25) | AT91_PIN_TO_MASK(26), &pio->pioe.pudr);
- /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0D << 8)) | - AT91_RSTC_URSTEN); + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + /* Need to reset PHY -> 500ms reset */ + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | + AT91_RSTC_MR_URSTEN, &rstc->mr);
+ writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL));
/* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (rstc) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
/* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PC25), - pin_to_controller(AT91_PIN_PC0) + PIO_PUER); - writel(pin_to_mask(AT91_PIN_PE25) | - pin_to_mask(AT91_PIN_PE26), - pin_to_controller(AT91_PIN_PE0) + PIO_PUER); + writel(AT91_PIN_TO_MASK(25), &pio->pioc.puer); + writel(AT91_PIN_TO_MASK(25) | AT91_PIN_TO_MASK(26), &pio->pioe.puer);
at91_macb_hw_init(); } @@ -158,41 +157,42 @@ vidinfo_t panel_info = {
void lcd_enable(void) { - at91_set_gpio_value(AT91_PIN_PA30, 1); /* power up */ + at91_set_gpio_value(AT91_PORTPIN(A, 30), 1); /* power up */ }
void lcd_disable(void) { - at91_set_gpio_value(AT91_PIN_PA30, 0); /* power down */ + at91_set_gpio_value(AT91_PORTPIN(A, 30), 0); /* power down */ }
static void at91sam9263ek_lcd_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ - at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ - at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ - at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ - at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ - at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ - at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ - at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ - at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ - at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ - at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ - at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ - at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ - at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */ - at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ - at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ - at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ - at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ - at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ - at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */ - at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ - at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ - - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC); - + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + at91_set_a_periph(AT91_PORTPIN(C, 1), 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PORTPIN(C, 2), 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PORTPIN(C, 3), 0); /* LCDDEN */ + at91_set_b_periph(AT91_PORTPIN(B, 9), 0); /* LCDCC */ + at91_set_a_periph(AT91_PORTPIN(C, 6), 0); /* LCDD2 */ + at91_set_a_periph(AT91_PORTPIN(C, 7), 0); /* LCDD3 */ + at91_set_a_periph(AT91_PORTPIN(C, 8), 0); /* LCDD4 */ + at91_set_a_periph(AT91_PORTPIN(C, 9), 0); /* LCDD5 */ + at91_set_a_periph(AT91_PORTPIN(C, 10), 0); /* LCDD6 */ + at91_set_a_periph(AT91_PORTPIN(C, 11), 0); /* LCDD7 */ + at91_set_a_periph(AT91_PORTPIN(C, 14), 0); /* LCDD10 */ + at91_set_a_periph(AT91_PORTPIN(C, 15), 0); /* LCDD11 */ + at91_set_a_periph(AT91_PORTPIN(C, 16), 0); /* LCDD12 */ + at91_set_b_periph(AT91_PORTPIN(C, 12), 0); /* LCDD13 */ + at91_set_a_periph(AT91_PORTPIN(C, 18), 0); /* LCDD14 */ + at91_set_a_periph(AT91_PORTPIN(C, 19), 0); /* LCDD15 */ + at91_set_a_periph(AT91_PORTPIN(C, 22), 0); /* LCDD18 */ + at91_set_a_periph(AT91_PORTPIN(C, 23), 0); /* LCDD19 */ + at91_set_a_periph(AT91_PORTPIN(C, 24), 0); /* LCDD20 */ + at91_set_b_periph(AT91_PORTPIN(C, 17), 0); /* LCDD21 */ + at91_set_a_periph(AT91_PORTPIN(C, 26), 0); /* LCDD22 */ + at91_set_a_periph(AT91_PORTPIN(C, 27), 0); /* LCDD23 */ + + writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer); gd->fb_base = AT91SAM9263_SRAM0_BASE; }
@@ -258,7 +258,7 @@ int board_init(void) at91sam9263ek_nand_hw_init(); #endif #ifdef CONFIG_HAS_DATAFLASH - at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */ + at91_set_gpio_output(AT91_PORTPIN(E, 20), 1); /* select spi0 clock */ at91_spi0_hw_init(1 << 0); #endif #ifdef CONFIG_MACB @@ -297,7 +297,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *) AT91_EMAC_BASE, 0x00); #endif return rc; } diff --git a/board/atmel/at91sam9263ek/led.c b/board/atmel/at91sam9263ek/led.c index 82c5388..e5817df 100644 --- a/board/atmel/at91sam9263ek/led.c +++ b/board/atmel/at91sam9263ek/led.c @@ -23,16 +23,19 @@ */
#include <common.h> -#include <asm/arch/at91sam9263.h> +#include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h>
void coloured_LED_init(void) { /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB | - 1 << AT91SAM9263_ID_PIOCDE); + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + writel(1 << AT91SAM9263_ID_PIOB | 1 << AT91SAM9263_ID_PIOCDE, + &pmc->pcer);
at91_set_gpio_output(CONFIG_RED_LED, 1); at91_set_gpio_output(CONFIG_GREEN_LED, 1); diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c index 39e405f..f1466d1 100644 --- a/cpu/arm926ejs/at91/at91cap9_devices.c +++ b/cpu/arm926ejs/at91/at91cap9_devices.c @@ -27,6 +27,10 @@ */
#include <common.h> +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> @@ -34,29 +38,29 @@
void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */ + at91_set_a_periph(AT91_PIN_PA22, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIN_PA23, 0); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0); }
void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ + at91_set_a_periph(AT91_PIN_PD0, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIN_PD1, 0); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1); }
void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ + at91_set_a_periph(AT91_PIN_PD2, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIN_PD3, 0); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2); }
void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ + at91_set_a_periph(AT91_PIN_PC30, 0); /* DRXD */ + at91_set_a_periph(AT91_PIN_PC31, 1); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); }
@@ -82,24 +86,24 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ - at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ - at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + at91_set_b_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_b_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_b_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
/* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
if (cs_mask & (1 << 0)) { - at91_set_B_periph(AT91_PIN_PA5, 1); + at91_set_b_periph(AT91_PIN_PA5, 1); } if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PA3, 1); + at91_set_b_periph(AT91_PIN_PA3, 1); } if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PD0, 1); + at91_set_b_periph(AT91_PIN_PD0, 1); } if (cs_mask & (1 << 3)) { - at91_set_B_periph(AT91_PIN_PD1, 1); + at91_set_b_periph(AT91_PIN_PD1, 1); } if (cs_mask & (1 << 4)) { at91_set_gpio_output(AT91_PIN_PA5, 1); @@ -117,24 +121,24 @@ void at91_spi0_hw_init(unsigned long cs_mask)
void at91_spi1_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */ + at91_set_a_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
/* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI1);
if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB15, 1); + at91_set_a_periph(AT91_PIN_PB15, 1); } if (cs_mask & (1 << 1)) { - at91_set_A_periph(AT91_PIN_PB16, 1); + at91_set_a_periph(AT91_PIN_PB16, 1); } if (cs_mask & (1 << 2)) { - at91_set_A_periph(AT91_PIN_PB17, 1); + at91_set_a_periph(AT91_PIN_PB17, 1); } if (cs_mask & (1 << 3)) { - at91_set_A_periph(AT91_PIN_PB18, 1); + at91_set_a_periph(AT91_PIN_PB18, 1); } if (cs_mask & (1 << 4)) { at91_set_gpio_output(AT91_PIN_PB15, 1); @@ -155,26 +159,26 @@ void at91_spi1_hw_init(unsigned long cs_mask) #ifdef CONFIG_MACB void at91_macb_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */ - at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */ - at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */ - at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */ - at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */ - at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */ - at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */ - at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */ - at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */ - at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */ + at91_set_a_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIN_PB22, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIN_PB25, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIN_PB26, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIN_PB27, 0); /* ERXER */ + at91_set_a_periph(AT91_PIN_PB28, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIN_PB23, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIN_PB24, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIN_PB30, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIN_PB29, 0); /* EMDC */
#ifndef CONFIG_RMII - at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */ - at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ - at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ - at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ - at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ - at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ - at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ - at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ + at91_set_b_periph(AT91_PIN_PC25, 0); /* ECRS */ + at91_set_b_periph(AT91_PIN_PC26, 0); /* ECOL */ + at91_set_b_periph(AT91_PIN_PC22, 0); /* ERX2 */ + at91_set_b_periph(AT91_PIN_PC23, 0); /* ERX3 */ + at91_set_b_periph(AT91_PIN_PC27, 0); /* ERXCK */ + at91_set_b_periph(AT91_PIN_PC20, 0); /* ETX2 */ + at91_set_b_periph(AT91_PIN_PC21, 0); /* ETX3 */ + at91_set_b_periph(AT91_PIN_PC24, 0); /* ETXER */ #endif } #endif @@ -182,8 +186,8 @@ void at91_macb_hw_init(void) #ifdef CONFIG_AT91_CAN void at91_can_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA12, 0); /* CAN_TX */ - at91_set_A_periph(AT91_PIN_PA13, 1); /* CAN_RX */ + at91_set_a_periph(AT91_PIN_PA12, 0); /* CAN_TX */ + at91_set_a_periph(AT91_PIN_PA13, 1); /* CAN_RX */
/* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_CAN); diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/cpu/arm926ejs/at91/at91sam9261_devices.c index 16d411f..c20c519 100644 --- a/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -23,6 +23,10 @@ */
#include <common.h> +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> @@ -30,29 +34,29 @@
void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ + at91_set_a_periph(AT91_PIN_PC8, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIN_PC9, 0); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0); }
void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ + at91_set_a_periph(AT91_PIN_PC12, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIN_PC13, 0); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1); }
void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ + at91_set_a_periph(AT91_PIN_PC14, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIN_PC15, 0); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2); }
void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ + at91_set_a_periph(AT91_PIN_PA9, 0); /* DRXD */ + at91_set_a_periph(AT91_PIN_PA10, 1); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); }
@@ -78,24 +82,24 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ - at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ - at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + at91_set_a_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
/* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_a_periph(AT91_PIN_PA3, 1); } if (cs_mask & (1 << 1)) { - at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_a_periph(AT91_PIN_PA4, 1); } if (cs_mask & (1 << 2)) { - at91_set_A_periph(AT91_PIN_PA5, 1); + at91_set_a_periph(AT91_PIN_PA5, 1); } if (cs_mask & (1 << 3)) { - at91_set_A_periph(AT91_PIN_PA6, 1); + at91_set_a_periph(AT91_PIN_PA6, 1); } if (cs_mask & (1 << 4)) { at91_set_gpio_output(AT91_PIN_PA3, 1); @@ -113,24 +117,24 @@ void at91_spi0_hw_init(unsigned long cs_mask)
void at91_spi1_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */ + at91_set_a_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
/* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1);
if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB28, 1); + at91_set_a_periph(AT91_PIN_PB28, 1); } if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PA24, 1); + at91_set_b_periph(AT91_PIN_PA24, 1); } if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PA25, 1); + at91_set_b_periph(AT91_PIN_PA25, 1); } if (cs_mask & (1 << 3)) { - at91_set_A_periph(AT91_PIN_PA26, 1); + at91_set_a_periph(AT91_PIN_PA26, 1); } if (cs_mask & (1 << 4)) { at91_set_gpio_output(AT91_PIN_PB28, 1); diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c index f72efdf..2728aa8 100644 --- a/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -27,37 +27,47 @@ */
#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/arch/at91_pio.h> +//#include <asm/arch/gpio.h>
void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0); + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + at91_set_a_periph(AT91_PORTPIN(A, 26), 1); /* TXD0 */ + at91_set_a_periph(AT91_PORTPIN(A, 27), 0); /* RXD0 */ + writel(1 << AT91SAM9263_ID_US0, &pmc->pcer); }
void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1); + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + at91_set_a_periph(AT91_PORTPIN(D, 0), 1); /* TXD1 */ + at91_set_a_periph(AT91_PORTPIN(D, 1), 0); /* RXD1 */ + writel(1 << AT91SAM9263_ID_US1, &pmc->pcer); }
void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2); + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + at91_set_a_periph(AT91_PORTPIN(D, 2), 1); /* TXD2 */ + at91_set_a_periph(AT91_PORTPIN(D, 3), 0); /* RXD2 */ + writel(1 << AT91SAM9263_ID_US2, &pmc->pcer); }
void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + at91_set_a_periph(AT91_PORTPIN(C, 30), 0); /* DRXD */ + at91_set_a_periph(AT91_PORTPIN(C, 31), 1); /* DTXD */ + writel(1 << AT91_ID_SYS, &pmc->pcer); }
void at91_serial_hw_init(void) @@ -82,71 +92,75 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ - at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ - at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + at91_set_b_periph(AT91_PORTPIN(A, 0), 0); /* SPI0_MISO */ + at91_set_b_periph(AT91_PORTPIN(A, 1), 0); /* SPI0_MOSI */ + at91_set_b_periph(AT91_PORTPIN(A, 2), 0); /* SPI0_SPCK */
/* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0); + writel(1 << AT91SAM9263_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) { - at91_set_B_periph(AT91_PIN_PA5, 1); + at91_set_b_periph(AT91_PORTPIN(A, 5), 1); } if (cs_mask & (1 << 1)) { - at91_set_B_periph(AT91_PIN_PA3, 1); + at91_set_b_periph(AT91_PORTPIN(A, 3), 1); } if (cs_mask & (1 << 2)) { - at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_b_periph(AT91_PORTPIN(A, 4), 1); } if (cs_mask & (1 << 3)) { - at91_set_B_periph(AT91_PIN_PB11, 1); + at91_set_b_periph(AT91_PORTPIN(B, 11), 1); } if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PA5, 1); + at91_set_gpio_output(AT91_PORTPIN(A, 5), 1); } if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PA3, 1); + at91_set_gpio_output(AT91_PORTPIN(A, 3), 1); } if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PA4, 1); + at91_set_gpio_output(AT91_PORTPIN(A, 4), 1); } if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PB11, 1); + at91_set_gpio_output(AT91_PORTPIN(B, 11), 1); } }
void at91_spi1_hw_init(unsigned long cs_mask) { - at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */ - at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */ - at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */ + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + at91_set_a_periph(AT91_PORTPIN(B, 12), 0); /* SPI1_MISO */ + at91_set_a_periph(AT91_PORTPIN(B, 13), 0); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PORTPIN(B, 14), 0); /* SPI1_SPCK */
/* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI1); + writel(1 << AT91SAM9263_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) { - at91_set_A_periph(AT91_PIN_PB15, 1); + at91_set_a_periph(AT91_PORTPIN(B, 15), 1); } if (cs_mask & (1 << 1)) { - at91_set_A_periph(AT91_PIN_PB16, 1); + at91_set_a_periph(AT91_PORTPIN(B, 16), 1); } if (cs_mask & (1 << 2)) { - at91_set_A_periph(AT91_PIN_PB17, 1); + at91_set_a_periph(AT91_PORTPIN(B, 17), 1); } if (cs_mask & (1 << 3)) { - at91_set_A_periph(AT91_PIN_PB18, 1); + at91_set_a_periph(AT91_PORTPIN(B, 18), 1); } if (cs_mask & (1 << 4)) { - at91_set_gpio_output(AT91_PIN_PB15, 1); + at91_set_gpio_output(AT91_PORTPIN(B, 15), 1); } if (cs_mask & (1 << 5)) { - at91_set_gpio_output(AT91_PIN_PB16, 1); + at91_set_gpio_output(AT91_PORTPIN(B, 16), 1); } if (cs_mask & (1 << 6)) { - at91_set_gpio_output(AT91_PIN_PB17, 1); + at91_set_gpio_output(AT91_PORTPIN(B, 17), 1); } if (cs_mask & (1 << 7)) { - at91_set_gpio_output(AT91_PIN_PB18, 1); + at91_set_gpio_output(AT91_PORTPIN(B, 18), 1); } } #endif @@ -154,26 +168,26 @@ void at91_spi1_hw_init(unsigned long cs_mask) #ifdef CONFIG_MACB void at91_macb_hw_init(void) { - at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */ - at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */ - at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */ - at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */ - at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */ - at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */ - at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */ - at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */ - at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */ - at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */ + at91_set_a_periph(AT91_PORTPIN(E, 21), 0); /* ETXCK_EREFCK */ + at91_set_b_periph(AT91_PORTPIN(C, 25), 0); /* ERXDV */ + at91_set_a_periph(AT91_PORTPIN(E, 25), 0); /* ERX0 */ + at91_set_a_periph(AT91_PORTPIN(E, 26), 0); /* ERX1 */ + at91_set_a_periph(AT91_PORTPIN(E, 27), 0); /* ERXER */ + at91_set_a_periph(AT91_PORTPIN(E, 28), 0); /* ETXEN */ + at91_set_a_periph(AT91_PORTPIN(E, 23), 0); /* ETX0 */ + at91_set_a_periph(AT91_PORTPIN(E, 24), 0); /* ETX1 */ + at91_set_a_periph(AT91_PORTPIN(E, 30), 0); /* EMDIO */ + at91_set_a_periph(AT91_PORTPIN(E, 29), 0); /* EMDC */
#ifndef CONFIG_RMII - at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */ - at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ - at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ - at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ - at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ - at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ - at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ - at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ + at91_set_a_periph(AT91_PORTPIN(E, 22), 0); /* ECRS */ + at91_set_b_periph(AT91_PORTPIN(C, 26), 0); /* ECOL */ + at91_set_b_periph(AT91_PORTPIN(C, 22), 0); /* ERX2 */ + at91_set_b_periph(AT91_PORTPIN(C, 23), 0); /* ERX3 */ + at91_set_b_periph(AT91_PORTPIN(C, 27), 0); /* ERXCK */ + at91_set_b_periph(AT91_PORTPIN(C, 20), 0); /* ETX2 */ + at91_set_b_periph(AT91_PORTPIN(C, 21), 0); /* ETX3 */ + at91_set_b_periph(AT91_PORTPIN(C, 24), 0); /* ETXER */ #endif } #endif @@ -182,18 +196,20 @@ void at91_macb_hw_init(void) void at91_uhp_hw_init(void) { /* Enable VBus on UHP ports */ - at91_set_gpio_output(AT91_PIN_PA21, 0); - at91_set_gpio_output(AT91_PIN_PA24, 0); + at91_set_gpio_output(AT91_PORTPIN(A, 21), 0); + at91_set_gpio_output(AT91_PORTPIN(A, 24), 0); } #endif
#ifdef CONFIG_AT91_CAN void at91_can_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA13, 0); /* CAN_TX */ - at91_set_A_periph(AT91_PIN_PA14, 1); /* CAN_RX */ + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + at91_set_a_periph(AT91_PORTPIN(A, 13), 0); /* CAN_TX */ + at91_set_a_periph(AT91_PORTPIN(A, 14), 1); /* CAN_RX */
/* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_CAN); + writel(1 << AT91SAM9263_ID_CAN, &pmc->pcer); } #endif
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Jens Scharsig