Hi Peng,

Some minor questions/remarks below.

On 2016-01-04 21:56, Peng Fan wrote:

From: Peng Fan peng.fan@nxp.com

Introduce Resource Domain Controller support for i.MX. Now i.MX6SX and i.MX7D supports this feature to assign masters and peripherals to different domains.

Signed-off-by: Ye.Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com

---

arch/arm/imx-common/Kconfig | 8 ++ arch/arm/imx-common/Makefile | 1 + arch/arm/imx-common/rdc-sema.c | 184 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/imx-rdc.h | 12 ++ arch/arm/include/asm/imx-common/rdc-sema.h | 117 ++++++++++++++++++ 5 files changed, 322 insertions(+) create mode 100644 arch/arm/imx-common/rdc-sema.c create mode 100644 arch/arm/include/asm/arch-mx6/imx-rdc.h create mode 100644 arch/arm/include/asm/imx-common/rdc-sema.h

diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig index 2296239..c4f48bb 100644 --- a/arch/arm/imx-common/Kconfig +++ b/arch/arm/imx-common/Kconfig @@ -3,3 +3,11 @@ config IMX_CONFIG

config ROM_UNIFIED_SECTIONS bool

+config IMX_RDC

• bool "i.MX Resource domain controller driver"
• depends on ARCH_MX6 || ARCH_MX7
• help

•  i.MX Resource domain controller is used to assign masters
  

•  and peripherals to differet domains. This can be used to
  

•  isolate resources.
  

diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index e7190c3..568f41c 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -27,6 +27,7 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mx7)) obj-y += cache.o init.o obj-$(CONFIG_CMD_SATA) += sata.o obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o +obj-$(CONFIG_IMX_RDC) += rdc-sema.o obj-$(CONFIG_SECURE_BOOT) += hab.o endif ifeq ($(SOC),$(filter $(SOC),vf610)) diff --git a/arch/arm/imx-common/rdc-sema.c b/arch/arm/imx-common/rdc-sema.c new file mode 100644 index 0000000..7db1ec5 --- /dev/null +++ b/arch/arm/imx-common/rdc-sema.c @@ -0,0 +1,184 @@ +/*

• • Copyright (C) 2016 Freescale Semiconductor, Inc.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/rdc-sema.h> +#include <asm/arch/imx-rdc.h> +#include <asm-generic/errno.h>

+/*

• • Check if the RDC Semaphore is required for this peripheral.
• */

+static inline int imx_rdc_check_sema_required(int per_id) +{

• struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
• u32 reg;
• reg = readl(&imx_rdc->pdap[per_id]);
• /*

• * No semaphore:
  

• * Intial value or this peripheral is assigned to only one domain
  

• */
  

• if (!(reg & RDC_PDAP_SREQ_MASK))

• return -ENOENT;
  

• return 0;

+}

+/*

• • Check the peripheral read / write access permission on Domain 0.
• • (Always assume the main CPU is in Domain 0)

Hence you assuming that U-Boot is also always running on main CPU right? I guess this is ok for now.

• */

+int imx_rdc_check_permission(int per_id) +{

• struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
• u32 reg;
• reg = readl(&imx_rdc->pdap[per_id]);
• if (!(reg & (RDC_PDAP_D0W_MASK | RDC_PDAP_D0R_MASK)))

• return -EACCES;  /*No access*/
  

• return 0;

+}

+/*

• • Lock up the RDC semaphore for this peripheral if semaphore is required.
• */

+int imx_rdc_sema_lock(int per_id) +{

• struct rdc_sema_regs *imx_rdc_sema;
• int ret;
• u8 reg;
• ret = imx_rdc_check_sema_required(per_id);
• if (ret)

• return ret;
  

• if (per_id < SEMA_GATES_NUM)

• imx_rdc_sema  = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
  

• else

• imx_rdc_sema  = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
  

• do {

• writeb(RDC_SEMA_PROC_ID,
  

•        &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
  

• reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
  

• if ((reg & RDC_SEMA_GATE_GTFSM_MASK) == RDC_SEMA_PROC_ID)
  

• 	break;  /* Get the Semaphore*/
  

• } while (1);
• return 0;

+}

+/*

• • Unlock the RDC semaphore for this peripheral if main CPU is the
• • semaphore owner.
• */

+int imx_rdc_sema_unlock(int per_id) +{

• struct rdc_sema_regs *imx_rdc_sema;
• int ret;
• u8 reg;
• ret = imx_rdc_check_sema_required(per_id);
• if (ret)

• return ret;
  

• if (per_id < SEMA_GATES_NUM)

• imx_rdc_sema  = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
  

• else

• imx_rdc_sema  = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
  

• reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
• if ((reg & RDC_SEMA_GATE_GTFSM_MASK) != RDC_SEMA_PROC_ID)

• return 1;	/*Not the semaphore owner */
  

• writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
• return 0;

+}

+/*

• • Setup RDC setting for one peripheral
• */

+int imx_rdc_setup_peri(rdc_peri_cfg_t p) +{

• struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
• u32 reg = 0;
• u32 share_count = 0;
• u32 peri_id = p & RDC_PERI_MASK;
• u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
• /* No domain assigned */
• if (domain == 0)

• return -EINVAL;
  

• reg |= domain;
• share_count = (domain & 0x3)

• + ((domain >> 2) & 0x3)
  

• + ((domain >> 4) & 0x3)
  

• + ((domain >> 6) & 0x3);
  

• if (share_count > 0x3)

• reg |= RDC_PDAP_SREQ_MASK;
  

• writel(reg, &imx_rdc->pdap[peri_id]);
• return 0;

+}

+/*

• • Setup RDC settings for multiple peripherals
• */

+int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,

• 		     unsigned count)
  

+{

• rdc_peri_cfg_t const *p = peripherals_list;
• int i, ret;
• for (i = 0; i < count; i++) {

• ret = imx_rdc_setup_peri(*p);
  

• if (ret)
  

• 	return ret;
  

• p++;
  

• }
• return 0;

+}

+/*

• • Setup RDC setting for one master
• */

+int imx_rdc_setup_ma(rdc_ma_cfg_t p) +{

• struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
• u32 master_id = (p & RDC_MASTER_MASK) >> RDC_MASTER_SHIFT;
• u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
• writel((domain & RDC_MDA_DID_MASK), &imx_rdc->mda[master_id]);
• return 0;

+}

+/*

• • Setup RDC settings for multiple masters
• */

+int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count) +{

• rdc_ma_cfg_t const *p = masters_list;
• int i, ret;
• for (i = 0; i < count; i++) {

• ret = imx_rdc_setup_ma(*p);
  

• if (ret)
  

• 	return ret;
  

• p++;
  

• }
• return 0;

+} diff --git a/arch/arm/include/asm/arch-mx6/imx-rdc.h b/arch/arm/include/asm/arch-mx6/imx-rdc.h new file mode 100644 index 0000000..5754f04 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/imx-rdc.h @@ -0,0 +1,12 @@ +/*

• • Copyright (C) 2016 Freescale Semiconductor, Inc.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __IMX_RDC_H__ +#define __IMX_RDC_H__

+#error "Please select cpu"

I don't understand this, wouldn't lead this always to an error?

+#endif /* __IMX_RDC_H__*/ diff --git a/arch/arm/include/asm/imx-common/rdc-sema.h b/arch/arm/include/asm/imx-common/rdc-sema.h new file mode 100644 index 0000000..4470709 --- /dev/null +++ b/arch/arm/include/asm/imx-common/rdc-sema.h @@ -0,0 +1,117 @@ +/*

• • Copyright (C) 2016 Freescale Semiconductor, Inc.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __RDC_SEMA_H__ +#define __RDC_SEMA_H__

+/*

• • [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ]

• •  d3      d2      d1       d0    | master id  |  peri id
    

• • d[x] means domain[x], x can be [3 - 0].
• */

+typedef u32 rdc_peri_cfg_t; +typedef u32 rdc_ma_cfg_t;

+#define RDC_PERI_SHIFT 0 +#define RDC_PERI_MASK 0xFF

+#define RDC_DOMAIN_SHIFT_BASE 16 +#define RDC_DOMAIN_MASK 0xFF0000 +#define RDC_DOMAIN_SHIFT(x) (RDC_DOMAIN_SHIFT_BASE + ((x << 1))) +#define RDC_DOMAIN(x) ((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x)))

+#define RDC_MASTER_SHIFT 8 +#define RDC_MASTER_MASK 0xFF00 +#define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \

• 			(domain_id << RDC_DOMAIN_SHIFT_BASE))
  

+/* The Following macro definitions are common to i.MX6SX and i.MX7D */ +#define SEMA_GATES_NUM 64

+#define RDC_MDA_DID_SHIFT 0 +#define RDC_MDA_DID_MASK (0x3 << RDC_MDA_DID_SHIFT) +#define RDC_MDA_LCK_SHIFT 31 +#define RDC_MDA_LCK_MASK (0x1 << RDC_MDA_LCK_SHIFT)

+#define RDC_PDAP_D0W_SHIFT 0 +#define RDC_PDAP_D0W_MASK (0x1 << RDC_PDAP_D0W_SHIFT) +#define RDC_PDAP_D0R_SHIFT 1 +#define RDC_PDAP_D0R_MASK (0x1 << RDC_PDAP_D0R_SHIFT) +#define RDC_PDAP_D1W_SHIFT 2 +#define RDC_PDAP_D1W_MASK (0x1 << RDC_PDAP_D1W_SHIFT) +#define RDC_PDAP_D1R_SHIFT 3 +#define RDC_PDAP_D1R_MASK (0x1 << RDC_PDAP_D1R_SHIFT) +#define RDC_PDAP_D2W_SHIFT 4 +#define RDC_PDAP_D2W_MASK (0x1 << RDC_PDAP_D2W_SHIFT) +#define RDC_PDAP_D2R_SHIFT 5 +#define RDC_PDAP_D2R_MASK (0x1 << RDC_PDAP_D2R_SHIFT) +#define RDC_PDAP_D3W_SHIFT 6 +#define RDC_PDAP_D3W_MASK (0x1 << RDC_PDAP_D3W_SHIFT) +#define RDC_PDAP_D3R_SHIFT 7 +#define RDC_PDAP_D3R_MASK (0x1 << RDC_PDAP_D3R_SHIFT)

Nit: How about RDC_PDAP_DXW_SHIFT(domain) (2 * domain) style defines?

+#define RDC_PDAP_SREQ_SHIFT 30 +#define RDC_PDAP_SREQ_MASK (0x1 << RDC_PDAP_SREQ_SHIFT) +#define RDC_PDAP_LCK_SHIFT 31 +#define RDC_PDAP_LCK_MASK (0x1 << RDC_PDAP_LCK_SHIFT)

+#define RDC_MRSA_SADR_SHIFT 7 +#define RDC_MRSA_SADR_MASK (0x1ffffff << RDC_MRSA_SADR_SHIFT)

+#define RDC_MREA_EADR_SHIFT 7 +#define RDC_MREA_EADR_MASK (0x1ffffff << RDC_MREA_EADR_SHIFT)

+#define RDC_MRC_D0W_SHIFT 0 +#define RDC_MRC_D0W_MASK (0x1 << RDC_MRC_D0W_SHIFT) +#define RDC_MRC_D0R_SHIFT 1 +#define RDC_MRC_D0R_MASK (0x1 << RDC_MRC_D0R_SHIFT) +#define RDC_MRC_D1W_SHIFT 2 +#define RDC_MRC_D1W_MASK (0x1 << RDC_MRC_D1W_SHIFT) +#define RDC_MRC_D1R_SHIFT 3 +#define RDC_MRC_D1R_MASK (0x1 << RDC_MRC_D1R_SHIFT) +#define RDC_MRC_D2W_SHIFT 4 +#define RDC_MRC_D2W_MASK (0x1 << RDC_MRC_D2W_SHIFT) +#define RDC_MRC_D2R_SHIFT 5 +#define RDC_MRC_D2R_MASK (0x1 << RDC_MRC_D2R_SHIFT) +#define RDC_MRC_D3W_SHIFT 6 +#define RDC_MRC_D3W_MASK (0x1 << RDC_MRC_D3W_SHIFT) +#define RDC_MRC_D3R_SHIFT 7 +#define RDC_MRC_D3R_MASK (0x1 << RDC_MRC_D3R_SHIFT) +#define RDC_MRC_ENA_SHIFT 30 +#define RDC_MRC_ENA_MASK (0x1 << RDC_MRC_ENA_SHIFT) +#define RDC_MRC_LCK_SHIFT 31 +#define RDC_MRC_LCK_MASK (0x1 << RDC_MRC_LCK_SHIFT)

+#define RDC_MRVS_VDID_SHIFT 0 +#define RDC_MRVS_VDID_MASK (0x3 << RDC_MRVS_VDID_SHIFT) +#define RDC_MRVS_AD_SHIFT 4 +#define RDC_MRVS_AD_MASK (0x1 << RDC_MRVS_AD_SHIFT) +#define RDC_MRVS_VADDR_SHIFT 5 +#define RDC_MRVS_VADDR_MASK (0x7ffffff << RDC_MRVS_VADDR_SHIFT)

+#define RDC_SEMA_GATE_GTFSM_SHIFT 0 +#define RDC_SEMA_GATE_GTFSM_MASK (0xf << RDC_SEMA_GATE_GTFSM_SHIFT) +#define RDC_SEMA_GATE_LDOM_SHIFT 5 +#define RDC_SEMA_GATE_LDOM_MASK (0x3 << RDC_SEMA_GATE_LDOM_SHIFT)

+#define RDC_SEMA_RSTGT_RSTGDP_SHIFT 0 +#define RDC_SEMA_RSTGT_RSTGDP_MASK (0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT) +#define RDC_SEMA_RSTGT_RSTGSM_SHIFT 2 +#define RDC_SEMA_RSTGT_RSTGSM_MASK (0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT) +#define RDC_SEMA_RSTGT_RSTGMS_SHIFT 4 +#define RDC_SEMA_RSTGT_RSTGMS_MASK (0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT) +#define RDC_SEMA_RSTGT_RSTGTN_SHIFT 8 +#define RDC_SEMA_RSTGT_RSTGTN_MASK (0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT)

+int imx_rdc_check_permission(int per_id); +int imx_rdc_sema_lock(int per_id); +int imx_rdc_sema_unlock(int per_id); +int imx_rdc_setup_peri(rdc_peri_cfg_t p); +int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,

• 	      unsigned count);
  

+int imx_rdc_setup_ma(rdc_ma_cfg_t p); +int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count);

+#endif /* __RDC_SEMA_H__*/

Hi Stefan, On Wed, Jan 06, 2016 at 10:59:17PM -0800, Stefan Agner wrote:

On 2016-01-04 21:56, Peng Fan wrote:

...

From: Peng Fan peng.fan@nxp.com

To boot a auxiliary core in asymmetric multicore system, introduce the new command "bootaux" to do it. Example of boot auxliary core from 0x70000000 where stores the boot head information that should be parsed by auxiliary core, "bootaux 0x70000000".

This reminds me of a question which was nagging me lately: Is the M4 core of SoloX/MX7 running a boot ROM? Or who/what is "parsing the boot head information"?

There is no bootrom for m4 core. The bootimage for M4 contains stack info and pc info. bootaux command will use the info extracted from bootimage.

See the following code: " int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) { struct src *src_reg; u32 stack, pc;

if (!boot_private_data) return 1;

stack = *(u32 *)boot_private_data; pc = *(u32 *)(boot_private_data + 4);

/* Set the stack and pc to M4 bootROM */ writel(stack, M4_BOOTROM_BASE_ADDR); writel(pc, M4_BOOTROM_BASE_ADDR + 4);

/* Enable M4 */ src_reg = (struct src *)SRC_BASE_ADDR; setbits_le32(&src_reg->scr, 0x00400000); clrbits_le32(&src_reg->scr, 0x00000010);

return 0; }

"

...

Introduce Kconfig option IMX_BOOTAUX.

Signed-off-by: Ye.Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com

---

arch/arm/imx-common/Kconfig | 6 ++++ arch/arm/imx-common/Makefile | 1 + arch/arm/imx-common/imx_bootaux.c | 59 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+) create mode 100644 arch/arm/imx-common/imx_bootaux.c

diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig index c4f48bb..1b7da5a 100644 --- a/arch/arm/imx-common/Kconfig +++ b/arch/arm/imx-common/Kconfig @@ -11,3 +11,9 @@ config IMX_RDC i.MX Resource domain controller is used to assign masters and peripherals to differet domains. This can be used to isolate resources.

+config IMX_BOOTAUX

• bool "Support boot auxiliary core"
• depends on ARCH_MX7 || ARCH_MX6
• help

•  bootaux [addr] to boot auxiliary core.
  

diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 568f41c..30e66ba 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -28,6 +28,7 @@ obj-y += cache.o init.o obj-$(CONFIG_CMD_SATA) += sata.o obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o obj-$(CONFIG_IMX_RDC) += rdc-sema.o +obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o obj-$(CONFIG_SECURE_BOOT) += hab.o endif ifeq ($(SOC),$(filter $(SOC),vf610)) diff --git a/arch/arm/imx-common/imx_bootaux.c b/arch/arm/imx-common/imx_bootaux.c new file mode 100644 index 0000000..da424a7 --- /dev/null +++ b/arch/arm/imx-common/imx_bootaux.c @@ -0,0 +1,59 @@ +/*

• • Copyright (C) 2016 Freescale Semiconductor, Inc.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <command.h>

+/* Allow for arch specific config before we boot */ +static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) +{

• /* please define platform specific arch_auxiliary_core_up() */
• return CMD_RET_FAILURE;

+}

+int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)

• __attribute__((weak, alias("__arch_auxiliary_core_up")));

+/* Allow for arch specific config before we boot */ +static int __arch_auxiliary_core_check_up(u32 core_id) +{

• /* please define platform specific arch_auxiliary_core_check_up() */
• return 0;

+}

+int arch_auxiliary_core_check_up(u32 core_id)

• __attribute__((weak, alias("__arch_auxiliary_core_check_up")));

+int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{

• ulong addr;
• int ret, up;
• if (argc < 2)

• return CMD_RET_USAGE;
  

• up = arch_auxiliary_core_check_up(0);
• if (up) {

• printf("## Auxiliary core is already up\n");
  

• return CMD_RET_SUCCESS;
  

• }
• addr = simple_strtoul(argv[1], NULL, 16);
• printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
• ret = arch_auxiliary_core_up(0, addr);
• if (ret)

• return CMD_RET_FAILURE;
  

• return CMD_RET_SUCCESS;

+}

+U_BOOT_CMD(

• bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
• "Start auxiliary core",

What kind of image are supported by the bootaux command? Afaik, this is some special/binary only format right?

Yeah. I just got the image from our rtos team, I do not have detail info about the format.

Probably another discussion, but before polluting the command namespace: Is that what we generally want?

Hmm, bootaux invokes arch_auxiliary_core_check_up arch_auxiliary_core_u

And arch code takes the responsibility to implement these two functions.

We try to make this common, but not sure whether this is ok for other SoCs. So I move the command to arch/arm/imx-common

Thanks, Peng.

-- Stefan

...

• ""

+);

Hi,

I would like to keep the discussion going and shed some light on the image format introduced here, see below...

On 2016-01-07 00:38, Peng Fan wrote:

Hi Stefan, On Wed, Jan 06, 2016 at 10:59:17PM -0800, Stefan Agner wrote:

...

On 2016-01-04 21:56, Peng Fan wrote:

...

From: Peng Fan peng.fan@nxp.com

To boot a auxiliary core in asymmetric multicore system, introduce the new command "bootaux" to do it. Example of boot auxliary core from 0x70000000 where stores the boot head information that should be parsed by auxiliary core, "bootaux 0x70000000".

This reminds me of a question which was nagging me lately: Is the M4 core of SoloX/MX7 running a boot ROM? Or who/what is "parsing the boot head information"?

There is no bootrom for m4 core. The bootimage for M4 contains stack info and pc info. bootaux command will use the info extracted from bootimage.

So the image expected by bootaux is really a raw binary image, with the only notion that the first two words need to be the stack pointer and the reset handler (firmware entry point).

U-Boot has other commands which work with "raw" images, such as the bootz command. The bootz command also expects a certain "raw" format, hence I guess it is ok to introduce something like that also for the auxiliary core.

Also, since every standard Cortex-M4 vector table begins with SP and reset handler, it is very likely that a firmwares linker file put the vector table also at the beginning of the image. Otherwise, one would need to adopt the linker file to create a "compatible" image. Btw, as Ye Li pointed out, the CPU needs those two words located at 0x0000000000, this is what bootaux is actually doing, coping the information to the right location for the M4 CPU. As an alternative, SCB_VTOR could be used to point to the vector table. However that can only be controlled from the M4 itself, hence is not an option for the bootaux command (as I did it for the libopencm3 Cortex-M4 support for Vybrid, see https://github.com/libopencm3/libopencm3/blob/master/lib/vf6xx/vector_chipse...).

However, IMHO, this patch should at least add this information/restriction to a README and maybe even give a hint in the help text what is expected here....

The other restriction is that the binary needs to be loaded to the location where the firmware has been linked to. Since the firmware is a "raw" image, this information need to be carried along the binary (I need to know that binary xyz.bin is linked to work at memory location 0x7F8000...). This is different to the bootz command: A raw Linux kernel zImage has a position independent loader at the very beginning and hence can be placed anywhere.

I don't really like that this information need to be carried along separately.

In our downstream U-Boot for Vybrid, which has a M4 core too, I introduced a m4boot command which makes use of the FIT image format to carry this information, see: http://git.toradex.com/cgit/u-boot-toradex.git/commit/?h=2015.04-toradex-nex...

It comes with the cost that each firmware need to be packed into a FIT image using mkimage, but then one can just call m4boot <address of image> and the command will make sure that the image is placed at the right location in memory.

Another possible option would be to introduce elf support. I like this approach since the Linux framework remoteproc also supports loading elf firmwares, hence this would align nicely with what has been done in the Linux kernel.

The elf format has all information required to load the firmware: Sections and their location (in M4 terms) as well as the start address. The platform data would only need to have a translation table for the section addresses (0x1fff8000 <=> 0x7F8000) to be able to load the firmware to the correct location. It comes with the cost of coping the firmware to the right location, but it would be much easier to handle elf firmware files.

Other opinions?

One more thing below:

See the following code: " int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) { struct src *src_reg; u32 stack, pc;

if (!boot_private_data) return 1;

stack = *(u32 *)boot_private_data; pc = *(u32 *)(boot_private_data + 4);

/* Set the stack and pc to M4 bootROM */ writel(stack, M4_BOOTROM_BASE_ADDR); writel(pc, M4_BOOTROM_BASE_ADDR + 4);

/* Enable M4 */ src_reg = (struct src *)SRC_BASE_ADDR; setbits_le32(&src_reg->scr, 0x00400000); clrbits_le32(&src_reg->scr, 0x00000010);

return 0; }

"

...

...

Introduce Kconfig option IMX_BOOTAUX.

Signed-off-by: Ye.Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com

---

arch/arm/imx-common/Kconfig | 6 ++++ arch/arm/imx-common/Makefile | 1 + arch/arm/imx-common/imx_bootaux.c | 59 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+) create mode 100644 arch/arm/imx-common/imx_bootaux.c

diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig index c4f48bb..1b7da5a 100644 --- a/arch/arm/imx-common/Kconfig +++ b/arch/arm/imx-common/Kconfig @@ -11,3 +11,9 @@ config IMX_RDC i.MX Resource domain controller is used to assign masters and peripherals to differet domains. This can be used to isolate resources.

+config IMX_BOOTAUX

• bool "Support boot auxiliary core"
• depends on ARCH_MX7 || ARCH_MX6
• help

•  bootaux [addr] to boot auxiliary core.
  

diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 568f41c..30e66ba 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -28,6 +28,7 @@ obj-y += cache.o init.o obj-$(CONFIG_CMD_SATA) += sata.o obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o obj-$(CONFIG_IMX_RDC) += rdc-sema.o +obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o obj-$(CONFIG_SECURE_BOOT) += hab.o endif ifeq ($(SOC),$(filter $(SOC),vf610)) diff --git a/arch/arm/imx-common/imx_bootaux.c b/arch/arm/imx-common/imx_bootaux.c new file mode 100644 index 0000000..da424a7 --- /dev/null +++ b/arch/arm/imx-common/imx_bootaux.c @@ -0,0 +1,59 @@ +/*

• • Copyright (C) 2016 Freescale Semiconductor, Inc.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <command.h>

+/* Allow for arch specific config before we boot */ +static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) +{

• /* please define platform specific arch_auxiliary_core_up() */
• return CMD_RET_FAILURE;

+}

+int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)

• __attribute__((weak, alias("__arch_auxiliary_core_up")));

+/* Allow for arch specific config before we boot */ +static int __arch_auxiliary_core_check_up(u32 core_id) +{

• /* please define platform specific arch_auxiliary_core_check_up() */
• return 0;

+}

+int arch_auxiliary_core_check_up(u32 core_id)

• __attribute__((weak, alias("__arch_auxiliary_core_check_up")));

+int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{

• ulong addr;
• int ret, up;
• if (argc < 2)

• return CMD_RET_USAGE;
  

• up = arch_auxiliary_core_check_up(0);
• if (up) {

• printf("## Auxiliary core is already up\n");
  

• return CMD_RET_SUCCESS;
  

• }
• addr = simple_strtoul(argv[1], NULL, 16);
• printf("## Starting auxiliary core at 0x%08lX ...\n", addr);

A dcache flush is required after loading the firmware. This could be also part of this command e.g. by using flush_dcache_all.

If we would make use of the elf format, then the main CPU would copy the data to the target memory address, and we could explicitly flush only the range required by the auxiliary core.

-- Stefan

...

...

• ret = arch_auxiliary_core_up(0, addr);
• if (ret)

• return CMD_RET_FAILURE;
  

• return CMD_RET_SUCCESS;

+}

+U_BOOT_CMD(

• bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
• "Start auxiliary core",

What kind of image are supported by the bootaux command? Afaik, this is some special/binary only format right?

Yeah. I just got the image from our rtos team, I do not have detail info about the format.

...

Probably another discussion, but before polluting the command namespace: Is that what we generally want?

Hmm, bootaux invokes arch_auxiliary_core_check_up arch_auxiliary_core_u

And arch code takes the responsibility to implement these two functions.

We try to make this common, but not sure whether this is ok for other SoCs. So I move the command to arch/arm/imx-common

Thanks, Peng.

Hi Stefan,

Sorry for this late reply.

On Wed, Jan 13, 2016 at 12:45:05PM -0800, Stefan Agner wrote:

Hi,

I would like to keep the discussion going and shed some light on the image format introduced here, see below...

On 2016-01-07 00:38, Peng Fan wrote:

...

Hi Stefan, On Wed, Jan 06, 2016 at 10:59:17PM -0800, Stefan Agner wrote:

...

On 2016-01-04 21:56, Peng Fan wrote:

...

From: Peng Fan peng.fan@nxp.com

To boot a auxiliary core in asymmetric multicore system, introduce the new command "bootaux" to do it. Example of boot auxliary core from 0x70000000 where stores the boot head information that should be parsed by auxiliary core, "bootaux 0x70000000".

This reminds me of a question which was nagging me lately: Is the M4 core of SoloX/MX7 running a boot ROM? Or who/what is "parsing the boot head information"?

There is no bootrom for m4 core. The bootimage for M4 contains stack info and pc info. bootaux command will use the info extracted from bootimage.

So the image expected by bootaux is really a raw binary image, with the only notion that the first two words need to be the stack pointer and the reset handler (firmware entry point).

Yeah.

U-Boot has other commands which work with "raw" images, such as the bootz command. The bootz command also expects a certain "raw" format, hence I guess it is ok to introduce something like that also for the auxiliary core.

Here bootaux will not let uboot lose control. bootz will let os get the control to soc. But I agree we add a simliar command, I personally think boot[aux] is good :).

Also, since every standard Cortex-M4 vector table begins with SP and reset handler, it is very likely that a firmwares linker file put the vector table also at the beginning of the image. Otherwise, one would need to adopt the linker file to create a "compatible" image. Btw, as Ye Li pointed out, the CPU needs those two words located at 0x0000000000, this is what bootaux is actually doing, coping the information to the right location for the M4 CPU. As an alternative, SCB_VTOR could be used to point to the vector table. However that can only be controlled from the M4 itself, hence is not an option for the bootaux command (as I did it for the libopencm3 Cortex-M4 support for Vybrid, see https://github.com/libopencm3/libopencm3/blob/master/lib/vf6xx/vector_chipse...).

However, IMHO, this patch should at least add this information/restriction to a README and maybe even give a hint in the help text what is expected here....

Add a README for bootaux command? or you mean the image format?

The other restriction is that the binary needs to be loaded to the location where the firmware has been linked to. Since the firmware is a "raw" image, this information need to be carried along the binary (I need to know that binary xyz.bin is linked to work at memory location 0x7F8000...). This is different to the bootz command: A raw Linux kernel zImage has a position independent loader at the very beginning and hence can be placed anywhere.

Good point. How about let bootaux to handle libz compressed M4 image?

I don't really like that this information need to be carried along separately.

In our downstream U-Boot for Vybrid, which has a M4 core too, I introduced a m4boot command which makes use of the FIT image format to carry this information, see: http://git.toradex.com/cgit/u-boot-toradex.git/commit/?h=2015.04-toradex-nex...

It comes with the cost that each firmware need to be packed into a FIT image using mkimage, but then one can just call m4boot <address of image> and the command will make sure that the image is placed at the right location in memory.

Another possible option would be to introduce elf support. I like this approach since the Linux framework remoteproc also supports loading elf firmwares, hence this would align nicely with what has been done in the Linux kernel.

The elf format has all information required to load the firmware: Sections and their location (in M4 terms) as well as the start address. The platform data would only need to have a translation table for the section addresses (0x1fff8000 <=> 0x7F8000) to be able to load the firmware to the correct location. It comes with the cost of coping the firmware to the right location, but it would be much easier to handle elf firmware files.

If we need to let uboot support more functions such as interact with M4 cores, remoteproc maybe a better choice. For simple usage only needs to boot M4, bootaux is enough, I think.

Regards, Peng.

Other opinions?

One more thing below:

...

See the following code: " int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) { struct src *src_reg; u32 stack, pc;

if (!boot_private_data) return 1;

stack = *(u32 *)boot_private_data; pc = *(u32 *)(boot_private_data + 4);

/* Set the stack and pc to M4 bootROM */ writel(stack, M4_BOOTROM_BASE_ADDR); writel(pc, M4_BOOTROM_BASE_ADDR + 4);

/* Enable M4 */ src_reg = (struct src *)SRC_BASE_ADDR; setbits_le32(&src_reg->scr, 0x00400000); clrbits_le32(&src_reg->scr, 0x00000010);

return 0; }

"

...

...

Introduce Kconfig option IMX_BOOTAUX.

Signed-off-by: Ye.Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com

---

arch/arm/imx-common/Kconfig | 6 ++++ arch/arm/imx-common/Makefile | 1 + arch/arm/imx-common/imx_bootaux.c | 59 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+) create mode 100644 arch/arm/imx-common/imx_bootaux.c

diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig index c4f48bb..1b7da5a 100644 --- a/arch/arm/imx-common/Kconfig +++ b/arch/arm/imx-common/Kconfig @@ -11,3 +11,9 @@ config IMX_RDC i.MX Resource domain controller is used to assign masters and peripherals to differet domains. This can be used to isolate resources.

+config IMX_BOOTAUX

• bool "Support boot auxiliary core"
• depends on ARCH_MX7 || ARCH_MX6
• help

•  bootaux [addr] to boot auxiliary core.
  

diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 568f41c..30e66ba 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -28,6 +28,7 @@ obj-y += cache.o init.o obj-$(CONFIG_CMD_SATA) += sata.o obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o obj-$(CONFIG_IMX_RDC) += rdc-sema.o +obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o obj-$(CONFIG_SECURE_BOOT) += hab.o endif ifeq ($(SOC),$(filter $(SOC),vf610)) diff --git a/arch/arm/imx-common/imx_bootaux.c b/arch/arm/imx-common/imx_bootaux.c new file mode 100644 index 0000000..da424a7 --- /dev/null +++ b/arch/arm/imx-common/imx_bootaux.c @@ -0,0 +1,59 @@ +/*

• • Copyright (C) 2016 Freescale Semiconductor, Inc.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <command.h>

+/* Allow for arch specific config before we boot */ +static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) +{

• /* please define platform specific arch_auxiliary_core_up() */
• return CMD_RET_FAILURE;

+}

+int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)

• __attribute__((weak, alias("__arch_auxiliary_core_up")));

+/* Allow for arch specific config before we boot */ +static int __arch_auxiliary_core_check_up(u32 core_id) +{

• /* please define platform specific arch_auxiliary_core_check_up() */
• return 0;

+}

+int arch_auxiliary_core_check_up(u32 core_id)

• __attribute__((weak, alias("__arch_auxiliary_core_check_up")));

+int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{

• ulong addr;
• int ret, up;
• if (argc < 2)

• return CMD_RET_USAGE;
  

• up = arch_auxiliary_core_check_up(0);
• if (up) {

• printf("## Auxiliary core is already up\n");
  

• return CMD_RET_SUCCESS;
  

• }
• addr = simple_strtoul(argv[1], NULL, 16);
• printf("## Starting auxiliary core at 0x%08lX ...\n", addr);

A dcache flush is required after loading the firmware. This could be also part of this command e.g. by using flush_dcache_all.

If we would make use of the elf format, then the main CPU would copy the data to the target memory address, and we could explicitly flush only the range required by the auxiliary core.

-- Stefan

...

...

...

• ret = arch_auxiliary_core_up(0, addr);
• if (ret)

• return CMD_RET_FAILURE;
  

• return CMD_RET_SUCCESS;

+}

+U_BOOT_CMD(

• bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
• "Start auxiliary core",

What kind of image are supported by the bootaux command? Afaik, this is some special/binary only format right?

Yeah. I just got the image from our rtos team, I do not have detail info about the format.

...

...

Probably another discussion, but before polluting the command namespace: Is that what we generally want?

Hmm, bootaux invokes arch_auxiliary_core_check_up arch_auxiliary_core_u

And arch code takes the responsibility to implement these two functions.

We try to make this common, but not sure whether this is ok for other SoCs. So I move the command to arch/arm/imx-common

Thanks, Peng.

On 2016-01-04 21:56, Peng Fan wrote:

From: Peng Fan peng.fan@nxp.com

In current design, if any peripheral was assigned to both A7 and M4, it will receive ipg_stop or ipg_wait when any of the 2 platforms enter low power mode. We will have a risk that, if A7 enter wait, M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait asserted same time. Also if M4 enters stop mode, A7 will have no chance to access the peripheral. There are 26 peripherals impacted by this IC issue:

s/impacted/affected

SIM2(sim2/emvsim2) SIM1(sim1/emvsim1) UART1/UART2/UART3/UART4/UART5/UART6/UART7 SAI1/SAI2/SAI3 WDOG1/WDOG2/WDOG3/WDOG4 GPT1/GPT2/GPT3/GPT4 PWM1/PWM2/PWM3/PWM4 ENET1/ENET2 Software Workaround: The solution is set M4 to a different domain with A core.

Set the M4 core to a different domain using A core? Or merely the peripherals?

So the peripherals are not shared by them. This way requires the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only. M4 image will set the M4 to domain 1 and set peripheral which it will use to domain 1.

Hm, what happens if the M4 image is not doing that? Would that causing problems?

-- Stefan

This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for i.MX7D SABRESD board, and setup the 26 IP resources to domain 0.

Signed-off-by: Ye.Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com

---

arch/arm/cpu/armv7/mx7/soc.c | 64 +++++++++++++++++++++++++++++++++++++++++++ configs/mx7dsabresd_defconfig | 2 ++ 2 files changed, 66 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index 2121ff2..ede7d53 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -12,6 +12,8 @@ #include <asm/imx-common/boot_mode.h> #include <asm/imx-common/dma.h> #include <asm/imx-common/hab.h> +#include <asm/imx-common/rdc-sema.h> +#include <asm/arch/imx-rdc.h> #include <asm/arch/crm_regs.h> #include <dm.h> #include <imx_thermal.h> @@ -29,6 +31,65 @@ U_BOOT_DEVICE(imx7_thermal) = { }; #endif

+#ifdef CONFIG_IMX_RDC +/*

• • In current design, if any peripheral was assigned to both A7 and M4,
• • it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
• • low power mode. So M4 sleep will cause some peripherals fail to work
• • at A7 core side. At default, all resources are in domain 0 - 3.
• • There are 26 peripherals impacted by this IC issue:
• • SIM2(sim2/emvsim2)
• • SIM1(sim1/emvsim1)
• • UART1/UART2/UART3/UART4/UART5/UART6/UART7
• • SAI1/SAI2/SAI3
• • WDOG1/WDOG2/WDOG3/WDOG4
• • GPT1/GPT2/GPT3/GPT4
• • PWM1/PWM2/PWM3/PWM4
• • ENET1/ENET2
• • Software Workaround:
• • Here we setup some resources to domain 0 where M4 codes will move
• • the M4 out of this domain. Then M4 is not able to access them any longer.
• • This is a workaround for ic issue. So the peripherals are not shared
• • by them. This way requires the uboot implemented the RDC driver and
• • set the 26 IPs above to domain 0 only. M4 code will assign resource
• • to its own domain, if it want to use the resource.
• */

+static rdc_peri_cfg_t const resources[] = {

• (RDC_PER_SIM1 | RDC_DOMAIN(0)),
• (RDC_PER_SIM2 | RDC_DOMAIN(0)),
• (RDC_PER_UART1 | RDC_DOMAIN(0)),
• (RDC_PER_UART2 | RDC_DOMAIN(0)),
• (RDC_PER_UART3 | RDC_DOMAIN(0)),
• (RDC_PER_UART4 | RDC_DOMAIN(0)),
• (RDC_PER_UART5 | RDC_DOMAIN(0)),
• (RDC_PER_UART6 | RDC_DOMAIN(0)),
• (RDC_PER_UART7 | RDC_DOMAIN(0)),
• (RDC_PER_SAI1 | RDC_DOMAIN(0)),
• (RDC_PER_SAI2 | RDC_DOMAIN(0)),
• (RDC_PER_SAI3 | RDC_DOMAIN(0)),
• (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
• (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
• (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
• (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
• (RDC_PER_GPT1 | RDC_DOMAIN(0)),
• (RDC_PER_GPT2 | RDC_DOMAIN(0)),
• (RDC_PER_GPT3 | RDC_DOMAIN(0)),
• (RDC_PER_GPT4 | RDC_DOMAIN(0)),
• (RDC_PER_PWM1 | RDC_DOMAIN(0)),
• (RDC_PER_PWM2 | RDC_DOMAIN(0)),
• (RDC_PER_PWM3 | RDC_DOMAIN(0)),
• (RDC_PER_PWM4 | RDC_DOMAIN(0)),
• (RDC_PER_ENET1 | RDC_DOMAIN(0)),
• (RDC_PER_ENET2 | RDC_DOMAIN(0)),

+};

+static void isolate_resource(void) +{

• imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));

+} +#endif

#if defined(CONFIG_SECURE_BOOT) struct imx_sec_config_fuse_t const imx_sec_config_fuse = { .bank = 1, @@ -163,6 +224,9 @@ int arch_cpu_init(void) mxs_dma_init(); #endif

• if (IS_ENABLED(CONFIG_IMX_RDC))

• isolate_resource();
  

• return 0;

}

diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 420d13e..1d262c1 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y CONFIG_TARGET_MX7DSABRESD=y +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y

CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D" # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_IMI is not set